CN111766491A - Test system and test head - Google Patents
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- CN111766491A CN111766491A CN202010205723.0A CN202010205723A CN111766491A CN 111766491 A CN111766491 A CN 111766491A CN 202010205723 A CN202010205723 A CN 202010205723A CN 111766491 A CN111766491 A CN 111766491A
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- 238000012360 testing method Methods 0.000 title claims abstract description 133
- 238000005259 measurement Methods 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims description 33
- 230000003287 optical effect Effects 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- 101100341230 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) isn-1 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000009434 installation Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
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- 102100021257 Beta-secretase 1 Human genes 0.000 description 3
- 101710150192 Beta-secretase 1 Proteins 0.000 description 3
- 102100021277 Beta-secretase 2 Human genes 0.000 description 3
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- 230000002093 peripheral effect Effects 0.000 description 2
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- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a test system and a test head, which realize a test system with less wiring man-hour compared with a conventional test system. The test system (1) includes an integrated controller (18), a measurement circuit (11), drivers (13, 14), an AD converter (15), a cutoff controller (16), and a dynamic characteristic controller (17). A measurement circuit (11) and an AD converter (15) that converts analog signals output from sensors (11p1, 11p2, 11n1, 11n2) included in the measurement circuit (11) into digital signals are built into a test head (10).
Description
Technical Field
The present invention relates to a test system for performing a dynamic characteristic test of a semiconductor device.
Background
Patent document 1 discloses a test system for performing a characteristic test of a power semiconductor device. In the test system described in patent document 1, a dynamic characteristic test of a semiconductor device is performed using a measurement circuit (including a current sensor and a voltage sensor) provided inside a test head.
Documents of the prior art
Patent document
[ patent document 1 ]: japanese laid-open patent publication No. JP-A-2017-67555 "
Disclosure of Invention
Problems to be solved by the invention
However, the test system described in patent document 1 has room for improvement in the following respects.
That is, the test system described in patent document 1 generally adopts the following configuration: the measurement results obtained by the measurement circuit provided inside the test head are transmitted as analog signals to the digitizer and interceptor provided outside the test head. Therefore, strict restrictions are required regarding the wiring between the test head for transmitting analog signals and the digitizer. For example, in order to suppress the skew, it is necessary to perform equal-length wiring for the voltage wiring and the current wiring. Further, in order to suppress variation in the mutual inductance between each wiring and the peripheral conductor (for example, the housing), it is necessary to perform piping wiring or wiring fixation. Therefore, the number of wiring steps is likely to increase, and as a result, the manufacturing cost is likely to increase.
An embodiment of the present invention has been made in view of the above problems, and an object thereof is to realize a test system with less wiring man-hours than a conventional test system.
Means for solving the problems
In order to solve the above-described problems, a test system of one embodiment of the present invention is a test system for performing a dynamic characteristic test of a semiconductor device, the test system including: an integrated controller; a measurement circuit comprising one or more sensors that are current sensors or voltage sensors; a driver that controls a switch included in the measurement circuit; an AD converter that converts an analog signal output from the sensor into a digital signal; a cutoff controller that generates a cutoff signal with reference to the digital signal; and a dynamic characteristic controller that controls the driver with reference to an operation command acquired from the integrated controller and a cutoff signal acquired from the cutoff controller, wherein at least the measurement circuit and the AD converter are built in a test head.
In order to solve the above problems, a test head according to an embodiment of the present invention is a test head included in a test system for performing a dynamic characteristic test of a semiconductor device, the test head including: a measurement circuit including one or more sensors as a current sensor or a voltage sensor, and an AD converter that converts an analog signal output from the sensors into a digital signal.
Effects of the invention
According to an embodiment of the present invention, a test system with less wiring man-hours than a conventional test system can be realized.
Drawings
Fig. 1 is a block diagram showing the structure of a test system according to an embodiment of the present invention.
Fig. 2 is a circuit diagram showing a structure of a measurement circuit provided in the test system shown in fig. 1.
Fig. 3 is a block diagram showing an installation example of the test system shown in fig. 1.
Fig. 4 is a diagram showing the structure of a packet transmitted from a PC to a digitizer board in the installation example of the test system shown in fig. 3.
Detailed Description
(Structure of test head)
A configuration of a test system 1 according to an embodiment of the present invention will be described with reference to fig. 1. Fig. 1 is a block diagram showing the structure of a test system 1.
The test system 1 is a system for performing a dynamic characteristic test of the semiconductor device D. As the semiconductor device D to be subjected to the characteristic test, both a single semiconductor device such as a diode, a transistor, or a thyristor and an IC (Integrated Circuit) in which the single semiconductor device is Integrated are conceivable. In the present embodiment, an IGBT (Insulated Gate Bipolar Transistor) having a P terminal, an N terminal, and an O terminal is particularly assumed.
As shown in fig. 1, the test system 1 includes a measurement circuit 11, a DUT driver 12, a gate driver 13 (an example of a "driver" in the claims), a relay driver 14 (an example of a "driver" in the claims), an AD converter 15, a cutoff controller 16, a dynamic characteristic controller 17, an integrated controller 18, and an optical cable 19. The measurement circuit 11, DUT driver 12, gate driver 13, relay driver 14, AD converter 15, cutoff controller 16, and dynamic characteristics controller 17 are built in the test head 10, and the test head 10 and the integrated controller 18 are connected by an optical cable 19. Here, "built in the test head 10" means being accommodated inside the housing of the test head 10.
The measurement circuit 11 is a circuit for measuring a current flowing through each terminal of the semiconductor device D and/or a voltage of each terminal of the semiconductor device D. The measurement circuit 11 includes a current sensor and/or a voltage sensor connected to each terminal of the semiconductor device D. In the present embodiment, the voltage sensor 11P1 and the current sensor 11P2 connected to the P terminal of the semiconductor device D, and the voltage sensor 11N1 and the current sensor 11N2 connected to the N terminal of the semiconductor device D are included. In addition, the measurement circuit 11 includes a transistor switch and a relay switch for changing measurement conditions of current measurement and/or voltage measurement. An example of the configuration of the measurement circuit 11 will be described later instead of the drawings to be referred to.
The DUT driver 12 is a circuit for applying a gate voltage to the semiconductor device D. The DUT driver 12 refers to a gate voltage setting signal GVS supplied from a dynamic characteristic controller 17 described later, and sets the magnitude of a gate voltage applied to the semiconductor device.
The gate driver 13 is a circuit for controlling (for example, switching from an on state to an off state, or switching from an off state to an on state) the transistor switches included in the measurement circuit 11. The gate driver 13 determines to which state the transistor switch included in the measurement circuit 11 is switched, with reference to a gate drive signal GDS supplied from a dynamic characteristic controller 17 described later.
The relay driver 14 is a circuit for controlling (for example, switching from an on state to an off state, or switching from an off state to an on state) a relay switch included in the measurement circuit 11. The relay driver 14 sets which state the relay switch included in the measurement circuit 11 is switched to with reference to a relay drive signal RDS supplied from a dynamic characteristics controller 17 described later.
The AD converter 15 converts analog signals ASp1, Asn1, ASp2, Asn2 output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 included in the measurement circuit 11 into digital signals DSp1, DSn1, DSp2, DSn2, respectively. The digital signals DSp1, DSn1, DSp2, DSn2 generated by the AD converter 15 are output to the integrated controller 18 as output signals representing the measurement results, and are supplied to the cutoff controller 16.
The cutoff controller 16 generates cutoff signals ISp1, ISn1, ISp2, and ISn2 with reference to the digital signals DSp1, DSn1, DSp2, and DSn2 acquired from the AD converter 15. The cutoff signals ISp1, ISn1 are, for example, digital signals that take a value of 1 when the voltage values indicated by the digital signals DSp1, DSn1 exceed a predetermined threshold value (overvoltage threshold value) and take a value of 0 when the predetermined threshold value (overvoltage threshold value) is not exceeded. The cutoff signals ISp2, ISn2 are digital signals that take a value of 1 when the current values indicated by the digital signals DSp2, DSn2 exceed a predetermined threshold value (overcurrent threshold value) and take a value of 0 when the current values do not exceed the predetermined threshold value (overcurrent threshold value). The cutoff signals ISp1, ISn1, ISp2, ISn2 generated by the cutoff controller 16 are supplied to the dynamic characteristics controller 17.
The dynamic characteristic controller 17 controls the measurement ranges of the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 with reference to the operation command Cmd acquired from the integrated controller 18 and the off signals ISp1, ISn1, ISp2, ISn2 acquired from the off controller 16, and generates the gate voltage setting signal GVS, the gate drive signal GDS, and the relay drive signal RDS. The gate voltage setting signal GVS, the gate drive signal GDS, and the relay drive signal RDS generated by the dynamic characteristic controller 17 are used to control the DUT driver 12, the gate driver 13, and the relay driver 14, respectively.
As described above, the test system 1 of the present embodiment includes (1) the integrated controller 18; (2) a measurement circuit 11 including voltage sensors 11p1, 11n1 and current sensors 11p2, 11n 2; (3) a relay driver 14 that controls a gate driver 13 included in the measurement circuit 11 and a relay switch included in the measurement circuit 11, the gate driver 13 controlling the transistor switch; (4) an AD converter 15 that converts analog signals ASp1, Asn1, ASp2, Asn2 output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 into digital signals DSp1, DSn1, DSp2, DSn 2; (5) a cutoff controller 16 that generates cutoff signals ISp1, ISn1, ISp2, and ISn2 with reference to digital signals DSp1, DSn1, DSp2, and DSn 2; and (6) a dynamic characteristic controller 17 that controls the gate driver 13 and the relay driver 14 with reference to the operation command Cmd acquired from the integrated controller 18 and the off signals ISp1, ISn1, ISp2, ISn2 acquired from the off controller 16.
In the test system 1 according to the present embodiment, the measurement circuit 11 and the AD converter 15 are incorporated in the test head 10. Therefore, the analog signals ASp1, Asn1, ASp2, Asn2 output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 are converted into digital signals DSp1, DSn1, DSp2, DSn2 by the AD converter 15 built in the test head 10 together with the measurement circuit 11. Therefore, as in the test system described in patent document 1, it is not necessary to perform equal-length wiring of the voltage wiring and the current wiring for the wiring between the test head and the digitizer (provided outside the test head) in order to suppress the skew. Further, it is not necessary to perform piping wiring or wiring fixation for suppressing the variation of the mutual inductance with respect to the wiring between the test head and the digitizer. Therefore, a test system with fewer wiring man-hours can be realized as compared with a conventional test system (for example, the test system described in patent document 1).
Furthermore, in the test system 1 according to the present embodiment, the following configuration is also adopted; in addition to the measurement circuit 11 and the AD converter 15, a gate driver 13, a relay driver 14, an off controller 16, and a dynamic characteristics controller 17 are also built in the test head 10. Therefore, it is possible to shorten the wiring from the AD converter 15 that transmits the digital signals DSp1, DSn1, DSp2, DSn2 to the off controller 16 and the wiring from the off controller 16 that transmits the off signal ISp1, ISn1, ISp2, ISn2 to the dynamic characteristics controller 17. In addition, the communication interface that needs to be provided in the test head 10 can be only a communication interface for communicating with the integrated controller 18. Therefore, the structure of the test system 1 can be made more compact.
(example of measuring Circuit configuration)
Referring to fig. 2, a configuration example of the measurement circuit 11 included in the test system 1 will be described. Fig. 2 is a circuit diagram showing a configuration example of the measurement circuit 11.
The measurement circuit 11 is a measurement circuit for performing a dynamic characteristic test of the semiconductor device D, and includes, as shown in fig. 2, a capacitor bank 110, a first selection circuit 111, an overcurrent prevention circuit 112, a high-speed cutoff circuit 113, a second selection circuit 114, voltage sensors 11p1, 11n1, and current sensors 11p2, 11n 2.
The capacitor bank 110 is a circuit as a power source of the measuring circuit 11, and has one end connected to the P terminal of the semiconductor device D and the other end connected to the N terminal of the semiconductor device D. The capacitor bank 110 is composed of a capacitor 1101 and a transistor switch 1102 connected in series with the capacitor 1101. The capacitor 1101 is formed of, for example, a film capacitor. The transistor switch 1102 is composed of, for example, a transistor Qp and a freewheeling diode Dp connected in parallel with the transistor Qp.
The first selection circuit 111 is a circuit for selecting which of the transistors Qdp and Qdn included in the semiconductor device D is to be measured, and is connected in parallel to the capacitor bank 110. The first selection circuit 111 is configured by 2 transistor switches 1111 and 1112 connected in series. The transistor switch 1111 is configured by, for example, a transistor Qhp and a freewheeling diode Dhp connected in parallel to the transistor Qhp. The transistor switch 1112 is configured by, for example, a transistor Qhn and a freewheeling diode Dhn connected in parallel with the transistor Qhn. An intermediate point Cs of the 2 transistor switches 1111 and 1112 is connected to an O terminal of the semiconductor device D via a reactor L as a load in a dynamic characteristic test.
The overcurrent prevention circuit 112 is a circuit for consuming energy stored in the reactor L, and is connected in parallel to the reactor L. The overcurrent prevention circuit 112 is configured by 2 transistor switches 1121, 1122 connected in series. The transistor switch 1121 is configured by, for example, a transistor Qif and a flywheel diode Dif connected in parallel to the transistor Qif. The transistor switch 1122 is composed of, for example, a transistor Qir and a flywheel diode Dir connected in parallel to the transistor Qir.
The high-speed cutoff circuit 113 is a circuit for switching whether or not the overcurrent prevention circuit 112 consumes the energy stored in the reactor L, and is connected in series with the reactor L. The high-speed cutoff circuit 113 is configured by 2 transistor switches 1131, 1132 connected in series. The transistor switch 1131 is configured by, for example, a transistor Qcf and a freewheeling diode Dcf connected in parallel to the transistor Qcf. The transistor switch 1132 is composed of, for example, a transistor Qcr and a flywheel diode Dcr connected in parallel to the transistor Qcr.
The second selection circuit 114 is a circuit for selecting which of the transistors Qdp, Qdn included in the semiconductor device D is to be subjected to short circuit tolerance measurement, and is connected in parallel to the capacitor bank 110. The second selection circuit 114 is constituted by 2 relay switches 1141 and 1142 connected in series. The intermediate point Ct of the 2 relay switches 1141, 1142 included in the second selection circuit 114 is connected to the intermediate point Cs of the 2 transistor switches 1111, 1112 included in the first selection circuit 111 via the reactor L, and is connected to the O terminal of the semiconductor device D.
The voltage sensor 11P1 is a sensor for detecting the voltage of the P terminal of the semiconductor device D, and is connected to the P terminal of the semiconductor device D. The current sensor 11P2 is a sensor for detecting a current flowing into or out of the semiconductor device D via the P terminal, and is provided on a current path of the current.
The voltage sensor 11N1 is a sensor for detecting the voltage of the N terminal of the semiconductor device D, and is connected to the N terminal of the semiconductor device D. The current sensor 11N2 is a sensor for detecting a current flowing into or out of the semiconductor device D via the N terminal, and is provided on a current path of the current.
The transistor switches 1102, 1111, 1112, 1121, 1122, 1131, 1132 included in the measurement circuit 11 are turned on and off by the above-described gate driver 13 with reference to the gate drive signal GDS. In addition, the on and off of the relay switches 1141, 1142 included in the measurement circuit 11 are performed by the above-described relay driver 14 with reference to the relay drive signal RDS. In addition, the measurement ranges of the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 included in the measurement circuit 11 are switched by the above-described dynamic characteristic controller 17 with reference to the operation command Cmd.
The configuration of the measurement circuit 11 is basically the same as that of the measurement circuit included in the test system described in patent document 1. For more details of the measurement circuit 11, reference is made to patent document 1.
(installation example of test System)
An example of mounting the test system 1 will be described with reference to fig. 3. Fig. 3 is a block diagram showing an installation example of the test system 1.
In the example shown in fig. 3, the test head 10 is composed of a digitizer board 10A, a mezzanine card 10B, a measurement circuit 11, a DUT driver 12, a gate driver 13, and a relay driver 14. The AD converter 15 is mounted on the digitizer board 10A as 4 AD converters. The cutoff controller 16 is mounted on the digitizer board 10A as a digital comparator. The dynamic characteristics controller 17 is mounted on the mezzanine card 10B as an FPGA (Field Programmable Gate Array). A PC (Personal Computer) is used as the integrated controller 18.
The integrated controller 18 and the digitizer board 10A include SFP (Small form factor Pluggable) connectors as a kind of optical connectors, which are connected to each other via an optical cable 19. The transmission of (the AD converter 15 of) the digitizer board 10A of the digital signals DSp1, DSn1, DSp2, DSn2 to the integrated controller 18 is performed via the optical cable 19.
In addition, the digitizer board 10A and the mezzanine card 10B have LVDS (Low Voltage differential signaling) connectors, which are connected to each other directly or via a metal cable not shown. The transmission from (the cut-off controller 16 of) the digitizer board 10A of the cut-off signal ISp1, ISn1, ISp2, ISn2 to (the dynamic characteristics controller 17 of) the mezzanine card 10B is performed via the LVDS connector.
In addition, the mezzanine card 10B has an optical driver, and the mezzanine card 10B transmits the gate drive signal GDS as an optical signal to the gate driver 13 and transmits the relay drive signal RDS as an optical signal to the relay driver 14. In addition, mezzanine card 10B has SPI (Serial Peripheral Interface), and mezzanine card 10B is connected to DUT driver 12 via a bus. The transmission from (the dynamic characteristics controller 17 of) the mezzanine card 10B of the gate voltage setting signal GVS to the DUT driver 12 is performed via this bus.
In addition, the transmission of the operation command Cmd from the integrated controller 18 to (the dynamic characteristics controller 17 of) the mezzanine card 10B is performed as follows. First, an operation command Cmd is transmitted from the PC to the digitizer pad 10A via the optical cable 19. Then, the operation command Cmd is transmitted from the digitizer board 10A to the mezzanine card 10B via the LVDS connector.
Thus, as shown in fig. 4, the data packet P transmitted and received between the integrated controller 18 and the digitizer pad 10A includes: (1) a digitizer area storing commands generated by the integrated controller 18 and interpreted by the digitizer pad 10A; (2) a dynamic characteristics controller area that stores commands (operation commands Cmd) generated by the integrated controller 18 and interpreted by the mezzanine card 10B; and (3) a sample data area that stores sample data (digital signals DSp1, DSn1, DSp2, DSn2) generated by the digitizer board 10A and referred to by the integrated controller 18. When receiving the packet P from the integrated controller 18, the digitizer board 10A reads the operation command Cmd from the dynamic characteristics controller area of the packet P, and transmits the read operation command Cmd to the mezzanine card 10B.
As described above, in the test system 1 of the present installation example, the AD converter 15 and the off controller 16 are mounted on the digitizer board 10A built in the test head 10, and the dynamic characteristics controller 17 is mounted on the mezzanine card built in the test head 10 and connected to the digitizer board 10A. Therefore, the internal structure of the test head 10 can be made simple.
(conclusion)
A test system of embodiment 1 of the present invention is a test system for performing a dynamic characteristic test of a semiconductor device, including: an integrated controller; a measurement circuit comprising one or more sensors that are current sensors or voltage sensors; a driver that controls a switch included in the measurement circuit; an AD converter that converts an analog signal output from the sensor into a digital signal; a cutoff controller that generates a cutoff signal with reference to the digital signal; and a dynamic characteristic controller that controls the driver with reference to an operation command acquired from the integrated controller and a cutoff signal acquired from the cutoff controller, wherein at least the measurement circuit and the AD converter are built in a test head. .
According to the above configuration, the analog signal output from the sensor is converted into a digital signal by the AD converter built in the test head together with the measurement circuit. Therefore, as in the test system described in patent document 1, it is not necessary to provide equal-length wirings for the voltage wiring and the current wiring for suppressing skew between the test head and the digitizer (the equal-length wiring is easier to realize in the test head than between the test head and the digitizer). Further, it is not necessary to perform piping wiring or wiring fixation for suppressing the variation of the mutual inductance with respect to the wiring between the test head and the digitizer. Therefore, a test system with fewer wiring man-hours can be realized as compared with a conventional test system (for example, the test system described in patent document 1).
In the test system according to embodiment 2 of the present invention, in addition to the structure of the test system of embodiment 1, the following structure is adopted. Namely, the following structure is adopted: in addition to the measurement circuit and the AD converter, the driver, the cutoff controller, and the dynamic characteristic controller are also built in the test head.
According to the above configuration, the wiring from the AD converter that transmits the digital signal to the off controller and the wiring from the off controller that transmits the off signal to the dynamic characteristic controller can be shortened. In addition, the communication interface that needs to be provided in the test head can be only a communication interface for communicating with the integrated controller. Therefore, the structure of the test system can be more concise.
In the test system according to embodiment 3 of the present invention, the following configuration is adopted in addition to the configuration of the test system of embodiment 2. Namely, the following structure is adopted: the AD converter and the cut-off controller are mounted on a digitizer board built in the test head, and the dynamic characteristic controller is mounted on a mezzanine card connected to the digitizer board built in the test head.
According to the structure, the structure in the test head can be concise.
A test head according to embodiment 4 of the present invention is a test head included in a test system for performing a dynamic characteristic test of a semiconductor device, the test head incorporating: a measurement circuit including one or more sensors as a current sensor or a voltage sensor, and an AD converter converting an analog signal output from the sensors into a digital signal.
According to the above configuration, the analog signal output from the sensor is converted into a digital signal by the AD converter built in the test head together with the measurement circuit. Therefore, in the test system including the test head of the present embodiment, as in the test system described in patent document 1, it is not necessary to perform equal-length wiring of the voltage wiring and the current wiring for suppressing skew with respect to the wiring between the test head and the digitizer (provided outside the test head). In addition, in the test system having the test head according to the present embodiment, it is not necessary to perform piping wiring or wiring fixation for suppressing the variation of the mutual inductance with respect to the wiring between the test head and the digitizer. Therefore, if the test head according to the present embodiment is used, a test system with fewer wiring man-hours can be realized as compared with the test system described in patent document 1.
(Note attached)
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the respective technical means included in the above embodiments are also included in the technical scope of the present invention.
Description of the reference symbols
1: testing the system;
10: a test head;
11: a measurement circuit;
11p1, 11n 1: a voltage sensor;
11p2, 11n 2: a current sensor;
12: a DUT driver;
13: a gate driver;
14: a relay driver;
15: an AD converter;
16: a cut-off controller;
17: a dynamic characteristic controller;
18: an integrated controller;
19: an optical cable;
10A: a digitizing plate;
10B: provided is a sandwich card.
Claims (4)
1. A test system for performing a dynamic characteristic test of a semiconductor device, the test system comprising:
an integrated controller;
a measurement circuit comprising one or more sensors that are current sensors or voltage sensors;
a driver that controls a switch included in the measurement circuit;
an AD converter that converts an analog signal output from the sensor into a digital signal;
a cutoff controller that generates a cutoff signal with reference to the digital signal; and
a dynamic characteristic controller that controls the driver with reference to an operation command acquired from the integrated controller and a cutoff signal acquired from the cutoff controller,
wherein at least the measurement circuit and the AD converter are built in a test head.
2. The test system of claim 1,
in addition to the measurement circuit and the AD converter, the driver, the cutoff controller, and the dynamic characteristic controller are also built in the test head.
3. The test system of claim 2,
the AD converter and the cut-off controller are mounted on a digitizer built in the test head, and the dynamic characteristic controller is mounted on a mezzanine card built in the test head and connected to the digitizer.
4. A test head included in a test system for performing a dynamic characteristic test of a semiconductor device, the test head having built therein:
a measuring circuit comprising one or more sensors as current sensors or voltage sensors, and
an AD converter that converts an analog signal output from the sensor into a digital signal.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2019068627A JP7272061B2 (en) | 2019-03-29 | 2019-03-29 | Test system and test head |
| JP2019-068627 | 2019-03-29 |
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| CN111766491A true CN111766491A (en) | 2020-10-13 |
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| CN202010205723.0A Pending CN111766491A (en) | 2019-03-29 | 2020-03-23 | Test system and test head |
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| JP5461379B2 (en) * | 2010-12-15 | 2014-04-02 | 株式会社アドバンテスト | Test equipment |
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| JP2008157770A (en) * | 2006-12-25 | 2008-07-10 | Yokogawa Electric Corp | Signal selection circuit and semiconductor testing device |
| JP2009092562A (en) * | 2007-10-10 | 2009-04-30 | Yokogawa Electric Corp | Apparatus for testing semiconductor |
| CN101932943A (en) * | 2007-12-10 | 2010-12-29 | 株式会社It&T | Semiconductor device test system |
| CN108139443A (en) * | 2015-09-29 | 2018-06-08 | 新东工业株式会社 | Test system |
| JP2018081948A (en) * | 2016-11-14 | 2018-05-24 | セイコーエプソン株式会社 | Inspection apparatus |
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| JP7272061B2 (en) | 2023-05-12 |
| JP2020165906A (en) | 2020-10-08 |
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