JP2020165906A - Test system and test head - Google Patents

Abstract

To realize a test system which needs less steps of wiring than an existing test system.SOLUTION: A test system (1) includes: an integrated controller (18); a measurement circuit (11); drivers (13, 14); an AD converter (15); a shut-off controller (16); and a dynamic characteristics controller (17). The measurement circuit (11) and the AD converter (15) for converting analog signals output from sensors (11p1, 11p2, 11n1, 11n2) in the measurement circuit (11) to digital signals are contained in a test head (10).SELECTED DRAWING: Figure 1

Description

The present invention relates to a test system for testing dynamic characteristics of a semiconductor device.

Patent Document 1 discloses a test system for performing a characteristic test of a power semiconductor device. In the test system described in Patent Document 1, a dynamic characteristic test of a semiconductor device is performed using a measurement circuit (including a current sensor and a voltage sensor) provided inside the test head.

JP-A-2017-67555

However, in the test system described in Patent Document 1, there is room for improvement in the following points.

That is, in the test system described in Patent Document 1, usually, the measurement result obtained by the measurement circuit provided inside the test head is transmitted as an analog signal to the digitizer and the interceptor provided outside the test head. The configuration is adopted. For this reason, strict constraints are imposed on the wiring between the test head and the digitizer that transmit analog signals. For example, in order to suppress skew, it is necessary to make the voltage wiring and the current wiring equal length wiring. Further, in order to suppress fluctuations in mutual induction between each wiring and a peripheral conductor (for example, a housing), it is necessary to perform duct wiring or wire fixing. For this reason, there is a problem that the wiring man-hours tend to increase, and as a result, the manufacturing cost tends to increase.

One aspect of the present invention has been made in view of the above problems, and an object of the present invention is to realize a test system in which wiring man-hours are less likely to increase than in a conventional test system.

The test system according to the first aspect of the present invention is a test system for performing a dynamic characteristic test of a semiconductor device, and includes an integrated controller, a measurement circuit including one or more sensors which are current sensors or voltage sensors, and the measurement circuit. Acquired from the integrated controller, a driver that controls the switch included in the sensor, an AD converter that converts an analog signal output from the sensor into a digital signal, a cutoff controller that generates a cutoff signal by referring to the digital signal, and an integrated controller. A dynamic characteristic controller that controls the driver with reference to an operation command and the cutoff signal acquired from the cutoff controller is provided, and at least the measurement circuit and the AD converter are built in the test head.

According to the above configuration, the analog signal output from the sensor is converted into a digital signal by the AD converter built in the test head together with the measurement circuit. Therefore, as in the test system described in Patent Document 1, regarding the wiring between the test head and the digitizer (provided outside the test head), the voltage wiring and the current wiring have the same length in order to suppress skew. There is no need for wiring (realizing equal-length wiring within the testhead is easier than achieving equal-length wiring between the testhead and digitizer). Further, regarding the wiring between the test head and the digitizer, it is not necessary to perform duct wiring or wiring fixing in order to suppress fluctuations in mutual induction. Therefore, it is possible to realize a test system in which the wiring man-hours are less complicated than the conventional test system (for example, the test system described in Patent Document 1).

In the test system according to the second aspect of the present invention, the following configurations are adopted in addition to the configuration of the test system according to the first aspect. That is, in addition to the measurement circuit and the AD converter, the driver, the cutoff controller, and the dynamic characteristic controller are built in the test head.

According to the above configuration, the wiring from the AD converter to which the digital signal is transmitted to the cutoff controller and the wiring from the cutoff controller to which the cutoff signal is transmitted to the dynamic characteristic controller can be shortened. Further, the communication interface that needs to be provided in the test head can be only the communication interface for communicating with the integrated controller. Therefore, the configuration of the test system can be simplified.

In the test system according to the third aspect of the present invention, the following configurations are adopted in addition to the configuration of the test system according to the second aspect. That is, the AD converter and the cutoff controller are mounted on the digitizer board built in the test head, and the dynamic characteristic controller is mounted on the mezzanine card built in the test head and connected to the digitizer board. The configuration has been adopted.

According to the above configuration, the configuration inside the test head can be simplified.

The test head according to the fourth aspect of the present invention is a test head included in a test system for performing a dynamic characteristic test of a semiconductor device, and is a measurement circuit including one or a plurality of sensors such as a current sensor or a voltage sensor, and the sensor. It has a built-in AD converter that converts the analog signal output from the sensor into a digital signal.

According to the above configuration, the analog signal output from the sensor is converted into a digital signal by the AD converter built in the test head together with the measurement circuit. Therefore, in the test system provided with the test head according to this aspect, the wiring between the test head and the digitizer (provided outside the test head) is related to the wiring like the test system described in Patent Document 1. It is not necessary to make the voltage wiring and the current wiring equal in length in order to suppress skew. Further, in the test system provided with the test head according to this aspect, it is necessary to perform duct wiring or wire fixing in order to suppress fluctuations in mutual induction regarding the wiring between the test head and the digitizer. Absent. Therefore, by using the test head according to this aspect, it is possible to realize a test system in which the wiring man-hours are less complicated than the test system described in Patent Document 1.

According to one aspect of the present invention, it is possible to realize a test system in which wiring man-hours are less likely to increase than in a conventional test system.

It is a block diagram which shows the structure of the test system which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of the measurement circuit provided in the test system shown in FIG. It is a block which shows the implementation example of the test system shown in FIG. It is a figure which shows the structure of the packet sent from the PC to the digitizer board in the implementation example of the test system shown in FIG.

(Test head configuration)
The configuration of the test system 1 according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the test system 1.

The test system 1 is a system for performing a dynamic characteristic test of the semiconductor device D. As the semiconductor device D to be subjected to the characteristic test, both individual semiconductor devices such as diodes, transistors, and thyristors, and ICs (Integrated Circuits) in which individual semiconductor devices are integrated are assumed. In this embodiment, in particular, an IGBT (Insulated Gate Bipolar Transistor) having a P terminal, an N terminal, and an O terminal is assumed.

As shown in FIG. 1, the test system 1 includes a measurement circuit 11, a DUT driver 12, a gate driver 13 (an example of a “driver” in the claims), and a relay driver 14 (a “driver” in the claims). An example), an AD converter 15, a cutoff controller 16, a dynamic characteristic controller 17, an integrated controller 18, and an optical cable 19. The measurement circuit 11, the DUT driver 12, the gate driver 13, the relay driver 14, the AD converter 15, the cutoff controller 16, and the dynamic characteristic controller 17 are built in the test head 10, and the test head 10 and the integrated controller 18 are It is connected by an optical cable 19. Here, "built into the test head 10" means that it is housed inside the housing of the test head 10.

The measurement circuit 11 is a circuit for measuring the current flowing through each terminal of the semiconductor device D and / or the voltage of each terminal of the semiconductor device D. The measuring circuit 11 includes a current sensor and / or a voltage sensor connected to each terminal of the semiconductor device D. The present embodiment includes a voltage sensor 11p1 and a current sensor 11p2 connected to the P terminal of the semiconductor device D, and a voltage sensor 11n1 and a current sensor 11n2 connected to the N terminal of the semiconductor device D. Further, the measurement circuit 11 includes a transistor switch and a relay switch for changing the measurement conditions of the current measurement and / or the voltage measurement. A configuration example of the measurement circuit 11 will be described later with reference to the drawings.

The DUT driver 12 is a circuit for applying a gate voltage to the semiconductor device D. The DUT driver 12 sets the magnitude of the gate voltage applied to the semiconductor device with reference to the gate voltage setting signal GVS supplied from the dynamic characteristic controller 17 described later.

The gate driver 13 is a circuit for controlling a transistor switch included in the measurement circuit 11 (for example, switching from an on state to an off state or from an off state to an on state). The gate driver 13 determines to which state the transistor switch included in the measurement circuit 11 is switched with reference to the gate drive signal GDS supplied from the dynamic characteristic controller 17, which will be described later.

The relay driver 14 is a circuit for controlling a relay switch included in the measurement circuit 11 (for example, switching from an on state to an off state or from an off state to an on state). The relay driver 14 sets which state the relay switch included in the measurement circuit 11 is switched to by referring to the relay drive signal RDS supplied from the dynamic characteristic controller 17 described later.

The AD converter 15 converts the analog signals ASP1, Asn1, ASp2, Asn2 output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 included in the measurement circuit 11 into digital signals DSp1, DSn1, DSp2, DSn2, respectively. To do. The digital signals DSp1, DSn1, DSp2, DSn2 generated by the AD converter 15 are output to the integrated controller 18 as output signals representing the measurement results, and are also supplied to the cutoff controller 16.

The cutoff controller 16 generates the cutoff signals ISp1, ISn1, ISp2, ISn2 with reference to the digital signals DSp1, DSn1, DSp2, DSn2 acquired from the AD converter 15. The cutoff signals ISp1 and ISn1 are, for example, digital signals that take a value 1 when the voltage values indicated by the digital signals DSp1 and DSn1 exceed a predetermined threshold value (overvoltage threshold value), and take a value 0 otherwise. .. The cutoff signals ISp2 and ISn2 are digital signals that take a value 1 when the current value indicated by the digital signals DSp2 and DSn2 exceeds a predetermined threshold value (overcurrent threshold value), and take a value 0 otherwise. The cutoff signals ISp1, ISn1, ISp2, and ISn2 generated by the cutoff controller 16 are supplied to the dynamic characteristic controller 17.

The dynamic characteristic controller 17 refers to the operation command Cmd acquired from the integrated controller 18 and the interruption signals ISp1, ISn1, ISp2, ISn2 acquired from the interruption controller 16, and the voltage sensor 11p1, 11n1 and the current sensor 11p2, 11n2. While controlling the measurement range, the gate voltage setting signal GVS, the gate drive signal GDS, and the relay drive signal RDS described above are generated. The gate voltage setting signal GVS, the gate drive signal GDS, and the relay drive signal RDS generated by the dynamic characteristic controller 17 are used to control the above-mentioned DUT driver 12, the gate driver 13, and the relay driver 14, respectively. To.

As described above, the test system 1 according to the present embodiment includes (1) an integrated controller 18, (2) a measurement circuit 11 including a voltage sensor 11p1, 11n1 and a current sensor 11p2, 11n2, and (3) a measurement circuit 11. The gate driver 13 that controls the transistor switch included in the above, the relay driver 14 that controls the relay switch included in the measurement circuit 11, and (4) the analog signals ASP1, output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2. An AD converter 15 that converts ASPn1, ASP2, Asn2 into digital signals DSp1, DSpn1, DSp2, DSn2 and (5) a cutoff signal ISp1, ISn1, ISp2, ISn2 are generated by referring to the digital signals DSp1, DSpn1, DSp2, DSn2. The dynamic characteristic controller 17 that controls the gate driver 13 and the relay driver 14 with reference to the shutoff controller 16 and the operation command Cmd obtained from the integrated controller 18 and the cutoff signals ISp1, ISn1, ISp2, ISn2 obtained from the cutoff controller 16. And have.

Then, in the test system 1 according to the present embodiment, a configuration in which the measurement circuit 11 and the AD converter 15 are built in the test head 10 is adopted. Therefore, the analog signals ASP1, ASpn1, ASP2, Asn2 output from the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 are digital signals DSp1, DSpn1, by the AD converter 15 built in the test head 10 together with the measurement circuit 11. It is converted to DSp2 and DSn2. Therefore, as in the test system described in Patent Document 1, regarding the wiring between the test head and the digitizer (provided outside the test head), the voltage wiring and the current wiring have the same length in order to suppress skew. There is no need for wiring. Further, regarding the wiring between the test head and the digitizer, it is not necessary to perform duct wiring or wiring fixing in order to suppress fluctuations in mutual induction. Therefore, it is possible to realize a test system in which the wiring man-hours are less complicated than the conventional test system (for example, the test system described in Patent Document 1).

Further, in the test system 1 according to the present embodiment, in addition to the measurement circuit 11 and the AD converter 15, the gate driver 13, the relay driver 14, the cutoff controller 16, and the dynamic characteristic controller 17 are incorporated in the test head 10. Has been done. Therefore, the wiring from the AD converter 15 to the cutoff controller 16 through which the digital signals DSp1, DSpn1, DSp2, DSn2 are transmitted, and the dynamic characteristic controller 17 from the cutoff controller 16 through which the cutoff signals ISp1, ISn1, ISp2, ISn2 are transmitted. Wiring to can be shortened. Further, the communication interface that needs to be provided in the test head 10 can be only the communication interface for communicating with the integrated controller 18. Therefore, the configuration of the test system 1 can be made simpler.

(Example of measurement circuit configuration)
A configuration example of the measurement circuit 11 included in the test system 1 will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration example of the measurement circuit 11.

The measurement circuit 11 is a measurement circuit for performing a dynamic characteristic test of the semiconductor device D, and as shown in FIG. 2, a capacitor bank 110, a first selection circuit 111, an overcurrent prevention circuit 112, and a high-speed cutoff circuit. It includes 113, a second selection circuit 114, voltage sensors 11p1, 11n1, and current sensors 11p2, 11n2.

The capacitor bank 110 is a circuit that serves as a power source for the measurement circuit 11, one end of which is connected to the P terminal of the semiconductor device D, and the other end of which is connected to the N terminal of the semiconductor device D. The capacitor bank 110 is composed of a capacitor 1101 and a transistor switch 1102 connected in series with the capacitor 1101. The capacitor 1101 is composed of, for example, a film capacitor. The transistor switch 1102 is composed of, for example, a transistor Qp and a freewheeling diode Dp connected in parallel to the transistor Qp.

The first selection circuit 111 is a circuit for selecting which of the transistors Qdp and Qdn included in the semiconductor device D is to be measured, and is connected in parallel to the capacitor bank 110. The first selection circuit 111 is composed of two transistor switches 1111, 1112 connected in series. The transistor switch 1111 is composed of, for example, a transistor Qhp and a freewheeling diode Dhp connected in parallel with the transistor Qhp. The transistor switch 1112 is composed of, for example, a transistor Qhn and a freewheeling diode Dnp connected in parallel to the transistor Qhn. The intermediate points Cs of the two transistor switches 1111, 1112 are connected to the O terminal of the semiconductor device D via the reactor L which is a load in the dynamic characteristic test.

The overcurrent prevention circuit 112 is a circuit for consuming the energy stored in the reactor L, and is connected in parallel to the reactor L. The overcurrent protection circuit 112 is composed of two transistor switches 1121 and 1122 connected in series. The transistor switch 1121 is composed of, for example, a transistor Qif and a freewheeling diode Dir connected in parallel with the transistor Qif. The transistor switch 1122 is composed of, for example, a transistor Qir and a freewheeling diode Dir connected in parallel with the transistor Qir.

The high-speed cutoff circuit 113 is a circuit for switching whether or not the energy stored in the reactor L is consumed by the overcurrent prevention circuit 112, and is connected in series with the reactor L. The high-speed cutoff circuit 113 is composed of two transistor switches 1131, 1132 connected in series. The transistor switch 1131 is composed of, for example, a transistor Qcf and a freewheeling diode Dcr connected in parallel with the transistor Qcf. The transistor switch 1132 is composed of, for example, a transistor Qcr and a freewheeling diode Dcr connected in parallel with the transistor Qcr.

The second selection circuit 114 is a circuit for selecting which of the transistors Qdp and Qdn included in the semiconductor device D is to be measured for short-circuit withstand capability, and is connected in parallel to the capacitor bank. The second selection circuit 114 is composed of two relay switches 1141 and 1142 connected in series. The midpoint Ct of the two relay switches 1141, 1142 included in the second selection circuit 114 is connected to the midpoint Cs of the two transistor switches 1111, 1112 included in the first selection circuit 111 via the reactor L. , It is connected to the O terminal of the semiconductor device D.

The voltage sensor 11p1 is a sensor for detecting the voltage of the P terminal of the semiconductor device D, and is connected to the P terminal of the semiconductor device. The current sensor 11p2 is a sensor for detecting the current flowing into the semiconductor device D or flowing out from the semiconductor device D via the P terminal, and is provided on the current path of the current.

The voltage sensor 11n1 is a sensor for detecting the voltage of the N terminal of the semiconductor device D, and is connected to the N terminal of the semiconductor device. The current sensor 11n2 is a sensor for detecting a current that flows into or flows out of the semiconductor device D via the N terminal, and is provided on the current path of the current.

The gate driver 13 described above opens and closes the transistor switches 1102, 1111, 1112, 1121, 1122, 1131, and 1132 included in the measurement circuit 11 with reference to the gate drive signal GDS. Further, the relay driver 14 described above opens and closes the relay switches 1141 and 1142 included in the measurement circuit 11 with reference to the relay drive signal RDS. Further, the measurement ranges of the voltage sensors 11p1, 11n1 and the current sensors 11p2, 11n2 included in the measurement circuit 11 are switched by the above-mentioned dynamic characteristic controller with reference to the operation command Cmd.

The configuration of the measurement circuit 11 is basically the same as the configuration of the measurement circuit included in the test system described in Patent Document 1. For further details of the measuring circuit 11, refer to Patent Document 1.

(Example of test system implementation)
An implementation example of the test system 1 will be described with reference to FIG. FIG. 3 is a block diagram showing an implementation example of the test system 1.

In the mounting example shown in FIG. 3, the test head 10 is composed of a digitizer board 10A, a mezzanine card 10B, a measurement circuit 11, a DUT driver 12, a gate driver 13, and a relay driver 14. The AD converter 15 is mounted on the digitizer board 10A as four AD converters. The cutoff controller 16 is mounted on the digitizer board 10A as a digital comparator. The dynamic characteristic controller 17 is mounted on the mezzanine card 10B as an FPGA (Field Programmable Gate Array). A PC (Personal Computer) is used as the integrated controller 18.

The integrated controller 18 and the digitizer board 10A include an SFP (Small Form Factor Pluggable) connector which is a kind of optical connector, and are connected to each other via an optical cable 19. Transmission of the digital signals DSp1, DSn1, DSp2, DSn2 from the digitizer board 10A (AD converter 15) to the integrated controller 18 is performed via the optical cable 19.

Further, the digitizer board 10A and the mezzanine card 10B are provided with an LVDS (Low Voltage Differential Signaling) connector, and are connected to each other directly or via a metal cable (not shown). Transmission of the cutoff signals ISp1, ISn1, ISp2, and ISn2 from the digitizer board 10A (cutoff controller 16) to the mezzanine card 10B (dynamic characteristic controller 17) is performed via this LVDS connector.

Further, the mezzanine card 10B includes an optical driver, and sends a gate drive signal GDS as an optical signal to the gate driver 13 and a relay drive signal RDS as an optical signal to the relay driver 14. Further, the mezzanine card 10B is provided with an SPI (Serial Peripheral Interface) and is connected to the DUT driver 12 via a bus. The transmission of the gate voltage setting signal GVS from the mezzanine card 10B (dynamic characteristic controller 17) to the DUT driver 12 is performed via this bus.

The operation command Cmd is transmitted from the integrated controller 18 to the mezzanine card 10B (dynamic characteristic controller 17) as follows. First, the operation command Cmd is transmitted from the PC to the digitizer board 10A via the optical cable 19. Next, the operation command Cmd is transmitted from the digitizer board 10A to the mezzanine card 10B via the LVDS connector.

Therefore, as shown in FIG. 4, the packet P transmitted / received between the integrated controller 18 and the digitizer board 10A is (1) a digitizer that stores instructions generated by the integrated controller 18 and interpreted by the digitizer board 10A. The region, (2) the dynamic characteristic controller region that stores the instruction (operation command Cmd) generated by the integrated controller 18 and interpreted by the mezzanine card 10B, and (3) the dynamic characteristic controller region generated by the digitizer board 10A and referenced by the integrated controller 18. A sampling data area for storing the sampling data (digital signals DSp1, DSn1, DSp2, DSn2) to be generated is included. When the digitizer board 10A receives the packet P from the integrated controller 18, it reads the operation command Cmd from the dynamic characteristic controller area of the packet P and sends the read operation command Cmd to the mezzanine card 10B.

As described above, in the test system 1 according to this mounting example, the AD converter 15 and the cutoff controller 16 are mounted on the digitizer board 10A built in the test head 10, and the dynamic characteristic controller 17 is the test head 10. It is mounted on a mezzanine card built into the digitizer board 10A and connected to the digitizer board 10A. Therefore, the internal configuration of the test head 10 can be simplified.

(Additional notes)
The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the individual technical means included in the above-described embodiments are also included in the technical scope of the present invention.

1 Test system 10 Test head 11 Measuring circuit 11p1, 11n1 Voltage sensor 11p2, 11n2 Current sensor 12 DUT driver 13 Gate driver 14 Relay driver 15 AD converter 16 Breaking controller 17 Dynamic characteristic controller 18 Integrated controller 19 Optical cable 10A Digitizer board 10B Mezzanine card

Claims (4)

It is a test system that tests the dynamic characteristics of semiconductor devices.
With integrated controller
A measurement circuit that includes one or more sensors that are current or voltage sensors,
A driver that controls the switch included in the measurement circuit,
An AD converter that converts an analog signal output from the sensor into a digital signal,
A cutoff controller that generates a cutoff signal with reference to the digital signal,
A dynamic characteristic controller that controls the driver by referring to the operation command acquired from the integrated controller and the interruption signal acquired from the interruption controller is provided.
At least the measurement circuit and the AD converter are built in the test head.
A test system that features that. In addition to the measurement circuit and the AD converter, the driver, the cutoff controller, and the dynamic characteristic controller are built in the test head.
The test system according to claim 1. The AD converter and the cutoff controller are mounted on a digitizer board built in the test head, and the dynamic characteristic controller is mounted on a mezzanine card built in the test head and connected to the digitizer board. Yes,
2. The test system according to claim 2. A test head included in a test system that tests the dynamic characteristics of semiconductor devices.
A measurement circuit that includes one or more sensors that are current or voltage sensors,
It has a built-in AD converter that converts the analog signal output from the sensor into a digital signal.
A test head that features that.

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