JP6273877B2 - Driving circuit for semiconductor switch element parallel connection circuit - Google Patents

Description

  The present invention relates to a drive circuit for a circuit in which a plurality of semiconductor switch elements are connected in parallel, and more particularly to an overcurrent detection circuit and a protection method when an overcurrent flows through any of the semiconductor switch elements connected in parallel.

  FIG. 10 shows a conventional example described in Patent Document 1. This is a conventional example of overcurrent detection in a circuit connected between a positive electrode P and a negative electrode N of a DC power source using a switch circuit in which two semiconductor switch elements are connected in parallel to upper and lower arms. In the inverter circuit and the converter circuit, a plurality of upper and lower arms are connected in parallel, and the connection point of the upper and lower arms is an AC terminal. In the example using an IGBT as the semiconductor switch element, the upper arm is connected to IGBTs 2 and 3, and the lower arm is connected to IGBTs 6 and 7 in parallel. 4 is the inductance of the negative conductor connected to the emitter of IGBT 2, 5 is the inductance of the negative conductor connected to the emitter of IGBT 3, 8 is the inductance of the negative conductor connected to the emitter of IGBT 6, and 9 is connected to the emitter of IGBT 7. The inductance of the negative conductor. There are conductors that connect the positive electrodes of the IGBTs, but they are omitted because they are not affected by the present invention. Since the overcurrent detection circuit has the same circuit configuration for both the upper arm and the lower arm, only the upper arm will be described.

  Reference numeral 11 denotes a gate drive circuit, from the g terminal of the gate drive circuit to the gate (control pole terminal) of the IGBT 2 via the gate resistance Rg1, to the gate (control pole terminal) of the IGBT 3 via the gate resistance Rg2, and from the e terminal. Wired individually to the emitter of IGBT 2 (control terminal having the same potential as the negative terminal) and the emitter of IGBT 3 (control terminal having the same potential as the negative terminal). The primary winding of the current detector 12 is connected to the wiring connecting the e terminal and the IGBT 2 emitter (control terminal having the same potential as the negative terminal), and the e terminal and the emitter of IGBT 3 (control terminal having the same potential as the negative terminal). The primary winding of the current detector 13 is connected to the wiring to be connected. The polarity detector 21 and the overcurrent detector 31 are connected to the detection winding of the current detector 12, and the polarity detector 22 and the overcurrent detector 32 are connected to the detection winding of the current detector 13, respectively. . The outputs of the polarity detectors 21 and 22 are respectively input to the exclusive OR element 23, the outputs of the overcurrent detectors 31 and 32 are respectively input to the OR element 33, and the output of the exclusive OR element 23 and the OR. The output of the element 33 is connected to the input of the AND element 34, respectively, and the output of the AND element 34 becomes an overcurrent detection signal.

  In such a configuration, when ON signals are simultaneously input to the IGBTs of the upper and lower arms for some reason, the upper and lower arm short-circuit current flows, and the IGBT is destroyed by overcurrent. In the present circuit configuration, an overcurrent detection operation when an overcurrent flows through the IGBT 3 of the upper arm will be described with reference to FIGS. When an overcurrent flows through the upper arm IGBT 3, a voltage Eo is induced in the wiring inductance 5. The voltage Eo is Eo = L × di / dt, where L is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the induced voltage of the wiring inductance 5 becomes a power source, and a current flows through the path of the wiring inductance 5 → the current detector 13 → the current detector 12 → the wiring inductance 4 → the wiring inductance 5.

  In a steady state where no overcurrent flows, as shown in FIG. 12, when the gate voltage is raised by an ON signal command, the current direction of the current detector 12 is the direction from the emitter of the IGBT 2 to the e terminal of the gate drive circuit. The current direction of the current detector 13 is the direction from the emitter of the IGBT 3 to the e terminal of the gate drive circuit, and the polarity of the current is the same direction. Further, when the gate voltage is lowered by the off signal command, the current direction of the current detector 12 is the direction from the e terminal of the gate drive circuit to the emitter of the IGBT 2, and the current direction of the current detector 13 is the e terminal of the gate drive circuit. To the emitter of the IGBT 3 and the polarity of the current is the same direction.

  When an overcurrent flows, as shown in FIG. 11, the induced voltage Eo of the wiring inductance 5 becomes a power source, and the current direction of the current detector 12 is the direction from the e terminal of the gate drive circuit toward the emitter of the IGBT 2. The current direction of the detector 13 is a direction from the emitter of the IGBT 3 toward the e terminal of the gate drive circuit. FIG. 11 shows the detection current of the current detector when an overcurrent occurs. Assuming that the current directions in the steady state of the current detectors 12 and 13 are the same direction, when the overcurrent flows, the directions are opposite to each other. Therefore, this can be detected by the exclusive OR element 23. Further, by detecting the magnitude of the overcurrent with the overcurrent detector 31 or 32, a difference in the magnitude of the current from the steady-state current is determined, and erroneous determination is prevented.

  Even when an overcurrent flows through the IGBT 2 of the upper arm, it can be detected by the same principle. When an overcurrent flows through the upper arm IGBT 2, a voltage is induced in the wiring inductance 4. When this voltage is induced, the induced voltage of the wiring inductance 4 becomes a power source, and a current flows through the path of the wiring inductance 4 → the current detector 12 → the current detector 13 → the wiring inductance 5 → the wiring inductance 4. In a steady state in which no overcurrent flows, the current direction of the current detector 13 is a direction from the emitter of the IGBT 3 to the e terminal of the gate drive circuit, and the current direction of the current detector 12 is the e of the gate drive circuit from the emitter of the IGBT 2. The direction is toward the terminal. When an overcurrent flows, the current direction of the current detector 12 is from the emitter of the IGBT 2 to the e terminal of the gate drive circuit, and the current direction of the current detector 13 is from the e terminal of the gate drive circuit to the emitter of the IGBT 3. It is the direction to go. Therefore, assuming that the current direction in the steady state is the same direction, when the overcurrent flows, the directions are opposite to each other, and this can be detected by the exclusive OR element 23. Further, by detecting the magnitude of the overcurrent with the overcurrent detector 31 or 32, a difference in the magnitude of the current from the steady-state current is determined, and erroneous determination is prevented.

Japanese Patent Laid-Open No. 10-42546

  As described above, the current flowing through the current detectors 12 and 13 during the steady state where no overcurrent flows through the IGBT is directed in the direction from the emitter of the IGBT toward the e terminal of the gate drive circuit 11 during the ON signal command. When an OFF signal is commanded, a current flows in a direction from the e terminal of the gate drive circuit 11 toward the emitter of the IGBT. Therefore, when a current transformer (CT) using a magnetic core is used as the current detector, the magnetic core is excited at the rise and fall of the ON signal. As a result, in the high-frequency switching operation, a large excitation loss occurs in the magnetic core, and it is necessary to use a large magnetic core that takes into account the temperature rise of the magnetic core. The power supply capacity is increased, and the apparatus is large and expensive. In addition, the power supply capacity of the gate drive circuit is increased, which causes a reduction in power conversion efficiency of the power conversion device.

  Therefore, an object of the present invention is to reduce the power loss in the steady state in the high-frequency switching operation, and to reliably detect the overcurrent of the switching elements connected in parallel when the overcurrent occurs, and capable of overcurrent protection Is to provide.

  In order to solve the above-mentioned problem, in the first invention, there is provided a drive circuit for a circuit in which N (N is an integer of 2 or more) voltage-driven semiconductor switch elements connected in parallel, each of the semiconductor switches A drive circuit for outputting a common drive signal to the drive terminals of the elements, a positive conductor connecting the positive terminals of the semiconductor switch elements, and a negative conductor connecting the negative terminals of the semiconductor switch elements And N first wirings individually connected from the drive circuit to the respective control electrode terminals of the respective semiconductor switch elements, and respective controls having the same potential as the negative electrode terminals of the respective semiconductor switch elements from the drive circuit. In the drive circuit of the semiconductor switch element parallel connection circuit comprising N second wirings individually connected to the terminals, any two of the N second wirings are mutually connected during steady operation. Electric Each is connected via (N-1) current detection current transformers, each of which has two primary windings connected so that the directions are opposite to each other and one secondary winding for current detection. The overcurrent of each semiconductor switch element connected in parallel is detected.

  According to a second aspect of the invention, in the drive circuit of the semiconductor switch element parallel connection circuit according to the first aspect of the invention, the two primary windings penetrate one of the two second wires through the magnetic core one or more times. The structure to be made.

  In the third invention, in the drive circuit of the semiconductor switch element parallel connection circuit in the first or second invention, the current of the secondary winding of the current detection current transformer is rectified and converted into a voltage signal, When the voltage value of the voltage signal exceeds a predetermined value, it is determined as an overcurrent, and the on signal to all the semiconductor switch elements is changed to the off signal.

  According to a fourth aspect of the invention, in the drive circuit of the semiconductor switch element parallel connection circuit according to the third aspect of the invention, the off signal is a signal that makes the voltage between the control pole terminal and the control terminal of the semiconductor switch element zero. .

  In a fifth aspect of the present invention, there is provided a drive circuit for a circuit in which N (N is an integer of 2 or more) voltage-driven semiconductor switch elements are connected in parallel, and a drive signal common to the drive terminals of the respective semiconductor switch elements. A drive circuit that outputs each of the semiconductor switch elements, a positive conductor that connects the positive terminals of the semiconductor switch elements, a negative conductor that connects the negative terminals of the semiconductor switch elements, and N first wirings individually connected to each control electrode terminal of the semiconductor switch element, and N pieces of individually connected from the drive circuit to each control terminal having the same potential as the negative electrode terminal of each semiconductor switch element And a second wiring, wherein the first wiring and the second wiring connected to each of the semiconductor switching elements are in a steady operation. Each of which is connected via a current detection current transformer having two primary windings and one secondary winding for current detection that are connected so that their current directions are opposite to each other. The overcurrent of each semiconductor switch element is detected.

  According to a sixth aspect of the invention, in the drive circuit of the semiconductor switch element parallel connection circuit according to the fifth aspect of the invention, the two primary windings are connected to the magnetic core one or more times with the first wiring and the second wiring. Use a structure that penetrates.

  In the seventh invention, in the drive circuit of the semiconductor switch element parallel connection circuit in the fifth or sixth invention, the current of the secondary winding of the current detection current transformer is rectified and converted into a voltage signal, When the voltage value of the voltage signal exceeds a predetermined value, it is determined as an overcurrent, and the on signal to all the semiconductor switch elements is changed to the off signal.

  According to an eighth aspect of the invention, in the drive circuit of the semiconductor switch element parallel connection circuit according to the seventh aspect of the invention, the off signal is a signal that makes the voltage between the control pole terminal and the control terminal of the semiconductor switch element zero. .

In the present invention, the current direction at the time of steady state is reversed with the two wires connecting the control terminal having the same potential as the negative terminal of the switching elements connected in parallel and the gate drive circuit as the primary winding of the magnetic core for current detection When an overcurrent occurs, the overcurrent is detected by the detection winding of the current detection magnetic core. Also, the connection line between the control pole terminal of the switching element connected in parallel and the gate drive circuit and the connection line between the control terminal and the gate drive circuit having the same potential as the negative terminal of the parallel connected switching element are connected to the primary winding of the magnetic core. It is wired as a line, and when an overcurrent occurs, the overcurrent is detected by a detection winding of a magnetic core for current detection.
As a result, there is no exciting operation of the magnetic core in a steady state, and there is no loss due to the excitation even in the high-frequency switching operation, and it is possible to detect the overcurrent with the detection winding when the overcurrent is generated.

It is a circuit diagram which shows the Example at the time of 2 parallel connection using the (N-1) current detector of this invention. It is an example of an operation waveform at the time of steady operation of the example of FIG. It is operation | movement explanatory drawing at the time of the overcurrent of the Example of FIG. It is a modified circuit diagram of the embodiment of FIG. It is a circuit diagram which shows the Example at the time of 3 parallel connection using the (N-1) current detector of this invention. It is a circuit diagram which shows the Example at the time of 2 parallel connection using N electric current detectors of this invention. It is an example of an operation waveform at the time of the steady state of the Example of FIG. It is operation | movement explanatory drawing at the time of the overcurrent of the Example of FIG. It is a circuit diagram which shows the Example at the time of 3 parallel connection using N electric current detectors of this invention. It is a circuit diagram which shows the conventional Example. The example of a waveform of each part at the time of the overcurrent detection of FIG. 10 is shown. FIG. 11 shows an example of operation waveforms in the steady state of FIG.

  The gist of the present invention is a wiring for connecting a gate driving circuit and a driving terminal of each semiconductor switching element in a driving circuit of a circuit in which N (N is an integer of 2 or more) voltage-driven semiconductor switching elements are connected in parallel. This is because a current detector using a magnetic core is connected to the magnetic core so that the magnetic core is not excited in a steady state, and an overcurrent can be detected by a current detection winding when an overcurrent occurs. The basic configuration uses (N-1) current detectors having two primary windings and one detection winding, and each of the gate drive circuit and the two semiconductor switching elements in a steady state. A configuration in which the wiring connected to the negative terminal and the control terminal having the same potential is wired so that the driving current in the reverse direction flows through the two primary windings of the current detector, and the two primary windings and one detection Two primary windings of the current detector are connected to the gate driving circuit and the control terminal of each switching element and the control terminal having the same potential as the negative terminal using N current detectors having windings. There are two proposals: a configuration in which a driving current in the opposite direction flows through the line.

  FIG. 1 shows a first embodiment of the present invention. This is an example in which the number N of parallel connections of switching elements is 2, and one ((N−1)) current transformers are used as current detectors. This is an embodiment in an upper arm in which IGBTTT1 and T2 are connected in parallel as switching elements. Since the lower arm can be similarly configured, the upper arm will be described. In the claims, the collector of the IGBT as the switching element is called a positive terminal, the emitter is a negative terminal, the gate is a control electrode terminal, and a terminal having the same potential as the emitter connected to the gate drive circuit is called a control terminal. The wiring inductance L1 connected to the emitter of the IGBTTT1 and the wiring inductance L2 connected to the emitter of the IGBTTT2 are inductances of conductors connecting the emitters. There are conductors that connect the positive electrodes of the IGBTs, but in the present invention, they are not affected by the operation, and are omitted.

  The GDU is a gate drive circuit, and has a function of converting an on / off signal from a control circuit not described into a signal for on / off control between the gate and emitter of the IGBT. A positive / negative voltage according to an on / off signal from the gate driving power supply GPS having the positive electrode PG, the negative electrode GN and the zero electrode M to the g terminal via the resistors R1, R2 and transistors Qf, Qr with reference to the zero voltage of the e terminal. Is output. The output terminal g of the gate drive circuit GDU is connected to the gate (control pole terminal) of the IGBTTT1 via the gate resistance Rg1, to the gate (control pole terminal) of the IGBTTT3 via the gate resistance Rg2, and the e terminal is the emitter of the IGBTTT1 (control terminal). A control terminal having the same potential as the negative terminal and an emitter of the IGBTTT 2 (control terminal having the same potential as the negative terminal) are individually wired. In the wiring connecting the e terminal and the IGBTTT1 emitter (control terminal having the same potential as the negative electrode terminal), the terminals L1 and K1 of the first primary winding of the current detector CT are in this order, and the e terminal and the emitter of the IGBTTT2 ( The terminals K2 and L2 of the second primary winding of the current detector CT are connected in this order to the wiring connecting the control terminal having the same potential as the negative terminal. Here, the current direction that passes through the first primary windings (K1, L1) of the current detector CT and the current direction that passes through the second primary windings (K2, L2) are balanced with each IGBT. In a steady state that flows, the connection is made in the opposite direction.

  In addition, a current detection circuit Idt including a rectifier circuit and a resistor is provided in the detection windings (terminals a and b) of the current detector CT, and a plus terminal (+) of the voltage comparator CP is provided in the output of the current detection circuit Idt. The clock terminal of the D flip-flop DF is connected to the output of the voltage comparator CP, and the amplifier AM is connected to the Q output terminal of the D flip-flop DF. The reference voltage Vref is connected to the negative terminal (−) of the voltage comparator CP, and the positive power supply Vc (H level voltage) of the control circuit is connected to the D terminal of the D flip-flop DF.

  In such a configuration, when ON signals are simultaneously input to the IGBTs of the upper and lower arms for some reason, the upper and lower arm short-circuit current flows, and the IGBT is destroyed by overcurrent. In the present circuit configuration, an overcurrent detection operation when an overcurrent flows through the IGBTTT1 of the upper arm will be described with reference to FIG. When overcurrent flows through the IGBTTT1 of the upper arm, a voltage VL1 is induced in the wiring inductance L1. The voltage VL1 is VL1 = L11 × di / dt, where L11 is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the voltage of the wiring inductance L1 becomes a power source, and the wiring inductance L1 → the first primary winding (terminals K1, L1) of the current detector CT → the second primary winding of the current detector CT. Current flows through a path of (terminals K2, L2) → wiring inductance L2 → wiring inductance L1. As a result, a current flows in the same direction in the first primary winding (K1, L1) and the second primary winding (K2, L2) of the current detector CT, exciting the magnetic core of the current detector CT. In the detection windings (terminals a and b), a current determined by the turn ratio of the primary winding and the detection winding flows.

  This current is converted by the current detection circuit Idt into a voltage corresponding to the current value via a rectified resistor. This voltage is compared with the reference value Vref by the voltage comparator CP to determine that an overcurrent has flowed. When an overcurrent flows, the output of the voltage comparator CP becomes a high (H) signal and is input to the clock terminal of the D flip-flop. In the D flip-flop, the H level voltage of the control power supply voltage is connected to the D terminal, and the Q output terminal becomes a high (H) level by the input signal to the clock terminal. This signal is amplified by the amplifier circuit AM, the transistor Q1 of the gate drive circuit is operated, the voltage of the output terminal g of the gate drive circuit is lowered to zero (the voltage at the M point), and the IGBTs T1 and T2 are turned off. At this time, since the IGBTTT1 cuts off the overcurrent, the gate voltage at the off time is not a negative voltage at the time of normal operation, but can be reduced to zero voltage, thereby suppressing a surge voltage at the time of the cut off. .

  Even when an overcurrent flows through the IGBTTT2 of the upper arm, it can be detected by the same principle. When an overcurrent flows through the upper arm IGBTTT2, a voltage is induced in the wiring inductance L2. When this voltage is induced, the induced voltage of the wiring inductance L2 becomes a power source, and the wiring inductance L2 → the second primary winding (terminals L2, K2) of the current detector CT → the first primary winding of the current detector CT. A current flows through a path of lines (terminals L1, K1) → wiring inductance L1 → wiring inductance L2. As a result, the current directions of the two primary windings of the current detector CT are the same, and the overcurrent can be detected in the same manner as when an overcurrent flows through the IGBTTT1. The direction of the current flowing through the two primary windings of the current detector CT is the same, but the direction is opposite to that when an overcurrent flows through the IGBTTT1. For this reason, the current detection circuit Idt has a circuit configuration using a rectifier circuit and a resistor in order to detect in the same way even if the current direction is different.

  Although the primary winding of the current detector CT is described as having a first winding having terminals K1 and L1 and a second winding having terminals K2 and L2, the primary winding of the gate drive circuit is described. What can be realized by passing the wiring connecting the e terminal and the emitter of the IGBTTT1 and the wiring connecting the e terminal of the gate drive circuit and the emitter of the IGBTTT2 as a primary winding of the current detector one or more times through the magnetic core. Needless to say.

  In a steady state in which no overcurrent flows, as shown in FIG. 2, when the gate voltage is raised by the ON signal command, the current direction of the first winding (terminals K1, L1) of the current detector CT is the IGBTTT1. In the direction from the emitter toward the e terminal of the gate drive circuit, the current direction of the second primary winding (terminals K2, L2) of the current detector CT is from the emitter of the IGBTTT2 toward the e terminal of the gate drive circuit. The polarities of the currents in the two primary windings of the detector CT are in opposite directions, and the magnetic core of the current detector CT is not excited. Further, when the gate voltage is lowered by the off signal command, the current direction of the first primary winding (terminals K1, L1) of the current detector CT is the direction from the e terminal of the gate drive circuit toward the emitter of the IGBTTT1, The current direction of the second primary winding of the detector CT is the direction from the e terminal of the gate drive circuit to the emitter of the IGBTTT2, and the current polarity of the two primary windings of the current detector CT is in the opposite direction. The magnetic core of the CT is not excited. Therefore, in this configuration, in a steady state, the magnetic core of the current detector is not excited, and it is possible to reduce the excitation loss and the gate drive power supply capacity.

  FIG. 4 shows a second embodiment of the present invention. The difference from the first embodiment is the connection method of the current detector CT inserted between the e terminal of the gate drive circuit GDU and the control terminals (terminals having the same potential as the emitter) of the IGBTs T1 and T2. In the first embodiment, the first primary winding (terminals L1 and K1) of the current detector CT is connected to the wiring connecting the e terminal and the emitter of IGBTTT1 (control terminal having the same potential as the negative electrode terminal), the e terminal and IGBTTT2. The second primary windings (terminals K2 and L2) of the current detector CT are connected to the wiring connecting the emitters (control terminals having the same potential as the negative terminal), but in the second embodiment, The first primary windings (terminals K1, L1) of the current detector CT are connected in this order to the wiring connecting the e terminal and the emitter of the IGBTTT1 (control terminal having the same potential as the negative terminal) in this order. The second primary windings (terminals L2, K2) of the current detector CT are connected in this order to the wiring connecting the emitter (control terminal having the same potential as the negative terminal).

  The current direction of the primary winding at the time of overcurrent is opposite to that of the first embodiment, but a current detection circuit Idt comprising a rectifier circuit and a resistor is used for the output of the detection winding (terminals a and b). Therefore, the overcurrent can be detected and the semiconductor switching element can be turned off as in the first embodiment. In a steady state, the magnetic core of the current detector is not excited, and it is possible to reduce excitation loss and gate drive power supply capacity.

  FIG. 5 shows a third embodiment of the present invention. This is an example in which the number N of parallel connections of switching elements is 3, and two ((N-1)) current transformers are used as current detectors. The wiring inductance L1 connected to the emitter of the IGBTTT1, the wiring inductance L2 connected to the emitter of the IGBTTT2, and the wiring inductance L3 connected to the emitter of the IGBTTT3 are inductances of conductors connecting the emitters to each other. There are conductors that connect the positive electrodes of the IGBTs, but in the present invention, they are not affected by the operation, and are omitted.

  The difference from the first and second embodiments is the wiring method of the current detector inserted between the gate drive circuit and the switching element due to the difference in the number of switching elements. The output terminal g of the gate drive circuit GDU is connected to the gate (control pole terminal) of the IGBTTT1 via the gate resistance Rg1, to the gate (control pole terminal) of the IGBTTT3 via the gate resistance Rg2, and to the gate (control pole terminal) of the IGBTTT3 via the gate resistance Rg3. Each gate is wired to a gate (control electrode terminal). Further, the e terminal is respectively connected to the emitter of IGBTTT1 (control terminal having the same potential as the negative electrode terminal), the emitter of IGBTTT2 (control terminal having the same potential as the negative electrode terminal), and the emitter of IGBTTT3 (control terminal having the same potential as the negative electrode terminal). Wired individually.

  The wiring connecting the e terminal and the IGBTTT1 emitter (the control terminal having the same potential as the negative electrode terminal) has the terminals L1 and K1 of the first primary winding of the current detector CT1 in this order, and the eterminal and the IGBTTT2 emitter ( The wiring connecting the negative electrode terminal and the control terminal having the same potential) has terminals K2, L2 of the second primary winding of the current detector CT1 and terminals L1, K1 of the first primary winding of the current detector CT2. In this order, the terminals K2 and L2 of the second primary winding of the current detector CT2 are connected to the wiring connecting the e terminal and the emitter of the IGBT TT3 (control terminal having the same potential as the negative terminal).

  Here, the current direction passing through the first primary winding (K1, L1) of the current detector CT1, the current direction passing through the second primary winding (K2, L2), and the first direction of the current detector CT2. The direction of current passing through the primary windings (K1, L1) and the direction of current passing through the second primary windings (K2, L2) are opposite in a steady state in which current flows through each IGBT in a balanced manner. Connect as follows. In addition, a current detection circuit Idt1 including a rectifier circuit and a resistor is provided in the detection winding (terminals a and b) of the current detector CT1, and a rectification circuit and a resistor are provided in the detection winding (terminals a and b) of the current detector CT2. Is connected to a current detection circuit Idt2. The output of the current detection circuit Idt1 and the output of the current detection circuit Idt2 are respectively connected to the plus terminal (+) of the voltage comparator CP via the diodes D1 and D2, and the output of the voltage comparator CP is the clock terminal of the D flip-flop DF. However, the amplifier AM is connected to each Q output terminal of the D flip-flop DF. The reference voltage Vref is connected to the negative terminal (−) of the voltage comparator CP, and the positive power supply Vc (H level voltage) of the control circuit is connected to the D terminal of the D flip-flop DF.

  In such a configuration, when ON signals are simultaneously input to the IGBTs of the upper and lower arms for some reason, the upper and lower arm short-circuit current flows, and the IGBT is destroyed by overcurrent. In the present circuit configuration, an overcurrent detection operation when an overcurrent flows through the IGBTTT1 of the upper arm will be described. When overcurrent flows through the IGBTTT1 of the upper arm, a voltage VL1 is induced in the wiring inductance L1. The voltage VL1 is VL1 = L11 × di / dt, where L11 is the inductance of the wiring and di / dt is the temporal change in current.

  When this voltage is induced, the voltage of the wiring inductance L1 becomes a power source, and the wiring inductance L1 → the first primary winding (terminals K1, L1) of the current detector CT1 → the second primary winding of the current detector CT1. (Terminals K2, L2) → first primary winding of current detector CT2 (terminals L1, K1) → wiring inductance L2 → path of wiring inductance L1 and wiring inductance L1 → first primary winding of current detector CT1 A current flows in the path of the line (terminals K1, L1) → the second primary winding (terminals K2, L2) of the current detector CT2 → the wiring inductance L3 → the wiring inductance L1. As a result, current flows in the same direction in the first primary windings (K1, L1) and the second primary windings (K2, L2) of the current detector CT1, thereby exciting the magnetic core of the current detector CT1. In the detection windings (terminals a and b), a current determined by the turn ratio of the primary winding and the detection winding flows.

  Further, when an overcurrent flows through the IGBTTT2, a voltage VL2 is induced in the wiring inductance L2. The voltage VL2 is VL2 = L12 × di / dt, where L12 is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the induced voltage of the wiring inductance L2 becomes the power source, and the wiring inductance L2 → the first primary winding (terminals K1, L1) of the current detector CT2 → the second primary winding of the current detector CT1. Line (terminals L2, K2) → first primary winding of current detector CT1 (terminals L1, K1) → wiring inductance L1 → path of wiring inductance L2 and wiring inductance L2 → first primary of current detector CT2 Winding (terminals K1, L1) → second primary winding (terminals L2, K2) of current detector CT1 → second primary winding (terminals K2, L2) of current detector CT2 → wiring inductance L3 → wiring A current flows through the path of the inductance L2.

  As a result, the second primary windings (L2, K2) and the first primary windings (L1, K1) of the current detector CT1 and the first primary windings (K1, L1) of the current detector CT2 and the first primary windings (L1, K1). Current flows in the same direction in the primary windings (K2, L2) of 2 to excite the magnetic cores of the current detectors CT1 and CT2, and the primary winding and the detection winding are connected to the detection windings (terminals a, b). A current determined by the turn ratio of the wire flows.

  Further, when an overcurrent flows through the IGBTTT3, a voltage VL3 is induced in the wiring inductance L3. The voltage VL3 is VL3 = L13 × di / dt, where L13 is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the voltage of the wiring inductance L3 becomes the power source, and the wiring inductance L3 → the second primary winding (terminals L2, K2) of the current detector CT2 → the first primary winding of the current detector CT1. (Terminals L1, K1) → wiring inductance L1 → wiring inductance L3 path and wiring inductance L3 → second primary winding of current detector CT2 (terminals L2, K2) → second primary winding of current detector CT1 A current flows through the path of the line (terminals K2, L2) → the first primary winding (terminals L1, K1) of the current detector CT2 → the wiring inductance L2 → the wiring inductance L3. As a result, current flows in the same direction in the first primary windings (L1, K1) and the second primary windings (L2, K2) of the current detector CT2, thereby exciting the magnetic core of the current detector CT2. In the detection windings (terminals a and b), a current determined by the turn ratio of the primary winding and the detection winding flows.

  These currents are converted into a voltage corresponding to the current value via the resistance after rectification by the current detection circuits Idt1 and Idt2. This voltage is input to the positive terminal of the voltage comparator CP through the diodes D1 and D2, and is compared with the reference value Vref to determine that an overcurrent has flowed. When an overcurrent flows, the output of the voltage comparator CP becomes a high (H) signal and is input to the clock terminal of the D flip-flop. In the D flip-flop, the H level voltage of the control power supply voltage is connected to the D terminal, and the Q output terminal becomes a high (H) level by the input signal to the clock terminal. This signal is amplified by the amplifier circuit AM, the transistor Q1 of the gate drive circuit is operated, the voltage of the output terminal g of the gate drive circuit is lowered to zero (the voltage at the M point), and the IGBTs T1 and T2 are turned off. At this time, since the IGBTTT1 cuts off the overcurrent, the gate voltage at the off time is not a negative voltage at the time of normal operation, but can be reduced to zero voltage, thereby suppressing a surge voltage at the time of the cut off. . The connection method of the current detector is that the connection line connecting the emitter (control terminal) of any two elements of the switching element (IGBT) and the e terminal of the gate drive circuit is respectively connected to the two primary windings of the current detector. It may be connected via

  In a steady state in which no overcurrent flows, the first current detectors CT1 and CT2 are both used when the gate voltage is raised by an on signal command and when the gate voltage is lowered by an off signal command, as in the first and second embodiments. The current direction of the primary winding is opposite to the current direction of the second primary winding, and the magnetic cores of the current detectors CT1 and CT2 are not excited. Therefore, in this configuration, in a steady state, the magnetic core of the current detector is not excited, and it is possible to reduce the excitation loss and the gate drive power supply capacity.

FIG. 6 shows a fourth embodiment of the present invention. In the configuration when two switching elements (IGBTs) are connected in parallel, the number of current detectors used and the number of switching elements used are the same.
The wiring inductance L1 connected to the emitter of the IGBTTT1 and the wiring inductance L2 connected to the emitter of the IGBTTT2 are inductances of conductors connecting the emitters. There are conductors that connect the positive electrodes of the IGBTs, but in the present invention, they are not affected by the operation, and are omitted.

  The GDU is a gate drive circuit, and has a function of converting an on / off signal from a control circuit not described into a signal for on / off control between the gate and emitter of the IGBT. A positive / negative voltage corresponding to an on / off signal with zero e terminal voltage is output to the g terminal via the resistors R1 and R2 and the transistors Qf and Qr from the gate driving power supply GPS having the positive electrode PG, the negative electrode GN, and the zero electrode M. To do. The output terminal g of the gate drive circuit GDU is connected to the gate (control pole terminal) of the IGBTTT1 via the gate resistance Rg1, to the gate (control pole terminal) of the IGBTTT2 via the gate resistance Rg2, and the e terminal is the emitter of the IGBTTT1 (control pole terminal). A control terminal having the same potential as the negative terminal and an emitter of the IGBTTT 2 (control terminal having the same potential as the negative terminal) are individually wired.

  The wiring connecting the g terminal and the gate of IGBTTT1 connects the e terminal and the emitter of IGBTTT1 (control terminal having the same potential as the negative electrode terminal) via the first primary winding terminal (L1, K1) of the current detector CT1. The wiring to be connected is connected via terminals L2 and K2 of the second primary winding of the current detector CT1. Further, the wiring connecting the g terminal and the gate of the IGBTTT2 is connected to the e terminal and the emitter of the IGBTTT1 (control terminal having the same potential as the negative electrode terminal) via the first primary winding terminals (L1, K1) of the current detector CT2. Are connected via the terminals L2 and K2 of the second primary winding of the current detector CT2, respectively.

  Here, the current direction passing through the first primary windings (K1, L1) of the current detectors CT1, CT2 and the current direction passing through the second primary windings (K2, L2) are determined as follows. In a steady state that flows in equilibrium, the connections are made in the opposite direction. In addition, current detection circuits Idt1 and Idt2 including a rectifier circuit and a resistor are connected to the detection windings (terminals a and b) of the current detectors CT1 and CT2, and outputs of the current detection circuits Idt1 and Idt2 are connected via diodes D1 and D2. The positive terminal (+) of the voltage comparator CP is connected, the clock terminal of the D flip-flop DF is connected to the output of the voltage comparator CP, and the amplifier AM is connected to the Q output terminal of the D flip-flop DF. The reference voltage Vref is connected to the negative terminal (−) of the voltage comparator CP, and the positive power supply Vc (H level voltage) of the control circuit is connected to the D terminal of the D flip-flop DF.

  In such a configuration, when ON signals are simultaneously input to the IGBTs of the upper and lower arms for some reason, the upper and lower arm short-circuit current flows, and the IGBT is destroyed by overcurrent.

  In the present circuit configuration, an overcurrent detection operation when an overcurrent flows through the IGBTTT1 of the upper arm will be described with reference to FIG. When overcurrent flows through the IGBTTT1 of the upper arm, a voltage VL1 is induced in the wiring inductance L1. The voltage VL1 is VL1 = L11 × di / dt, where L11 is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the voltage of the wiring inductance L1 becomes the power source, and the wiring inductance L1 → the second primary winding (terminals K2, L2) of the current detector CT1 → the second primary winding of the current detector CT2. Current flows through a path of (terminals L2, K2) → wiring inductance L2 → wiring inductance L1.

  As a result, the magnetic cores of the current detectors CT1 and CT2 are excited, and a current determined by the turn ratio of the primary winding and the detection winding flows through the detection windings (terminals a and b). This current is converted into a voltage according to the current value via the resistance after rectification by the current detection circuits Idt1 and Idt2. This voltage is compared with the reference value Vref by the voltage comparator CP to determine that an overcurrent has flowed. When an overcurrent flows, the output of the voltage comparator CP becomes a high (H) signal and is input to the clock terminal of the D flip-flop. In the D flip-flop, the H level voltage of the control power supply voltage is connected to the D terminal, and the Q output terminal becomes a high (H) level by the input signal to the clock terminal. This signal is amplified by the amplifier circuit AM, the transistor Q1 of the gate drive circuit is operated, the voltage of the output terminal g of the gate drive circuit is lowered to zero (the voltage at the M point), and the IGBTs T1 and T2 are turned off. At this time, since the IGBTTT1 cuts off the overcurrent, the gate voltage at the off time is not a negative voltage at the time of normal operation, but can be reduced to zero voltage, thereby suppressing a surge voltage at the time of the cut off. .

  When an overcurrent flows through the IGBTTT2, a voltage VL2 is induced in the wiring inductance L2. The voltage VL2 is VL1 = L12 × di / dt, where L12 is the inductance of the wiring and di / dt is the temporal change in current. When this voltage is induced, the voltage of the wiring inductance L2 becomes a power source, and the wiring inductance L2 → the second primary winding of the current detector CT2 (terminals K2, L2) → the second primary winding of the current detector CT1. Current flows through a path of (terminals L2, K2) → wiring inductance L1 → wiring inductance L2. As a result, the magnetic cores of the current detectors CT1 and CT2 are excited, and a current determined by the turn ratio of the primary winding and the detection winding flows through the detection windings (terminals a and b). The subsequent operation is the same as when an overcurrent flows through the IGBTTT1.

  In a steady state in which no overcurrent flows, as shown in FIG. 7, the first primary of the current detectors CT1 and CT2 is used both when the gate voltage is raised by an on signal command and when the gate voltage is lowered by an off signal command. The current direction of the winding and the current direction of the second primary winding are opposite, and the magnetic cores of the current detectors CT1 and CT2 are not excited. Therefore, in this configuration, in a steady state, the magnetic core of the current detector is not excited, and it is possible to reduce the excitation loss and the gate drive power supply capacity.

FIG. 9 shows a fifth embodiment of the present invention. In the fourth embodiment, when three switching elements (IGBTs) are connected in parallel, the number of current detectors used and the number of switching elements used are the same.
The wiring inductance L1 connected to the emitter of the IGBTTT1, the wiring inductance L2 connected to the emitter of the IGBTTT2, and the wiring inductance L3 connected to the emitter of the IGBTTT3 are inductances of conductors connecting the emitters. There are conductors that connect the positive electrodes of the IGBTs, but in the present invention, they are not affected by the operation, and are omitted.

In the configuration in which three switching elements (IGBTs) are connected in parallel, a gate resistor Rg3, a current detector CT3, a current detection circuit Idt3, and a diode D3 are added to the fourth embodiment. Other configurations are the same as those in the fourth embodiment. The operation is the same as in the fourth embodiment. When an overcurrent flows through any of the IGBTs, this is detected, and the gate drive circuit switches the on signal to the off signal to turn off all the IGBTs. Further, since each current detector is not excited in a steady state in which no overcurrent flows, it is possible to reduce excitation loss and gate drive power supply capacity.
In the above embodiment, the overcurrent is detected and the on signal is switched to the off signal in the gate drive circuit. However, the overcurrent detection signal is sent to the external control circuit, and the entire system is stopped from the control circuit. It is also possible to do so.

  The present invention relates to overcurrent protection when semiconductor switching elements are connected in parallel, and can be applied to a DC power supply, an AC power supply, an inverter, an uninterruptible power supply (UPS), and the like.

T1 to T3, 2, 3, 6, 7 ... IGBT (switching element)
L1 to L3, 4, 5, 8, 9 ... wiring inductance GDU, 11 ... gate drive circuit 21, 22 ... polarity detector 31, 32 ... overcurrent detector 23 ... exclusive OR element 12, 13, CT, CT1 to CT3 ... current detector 33 ... OR element 34 ... AND element Rg1-Rg3 ... gate resistance R1-R3 ... resistance Idt, Idt1 ~ Idt3 ... Current detection circuit D1 ~ D3 ... Diode CP ... Voltage comparator DF ... D flip-flop AM ... Amplifier GPS ... Gate drive power supply Qf, Qr, Q1 ... Transistor

Claims (8)

A drive circuit of a circuit in which N (N is an integer of 2 or more) voltage-driven semiconductor switch elements are connected in parallel, and outputs a common drive signal to the drive terminals of each of the semiconductor switch elements; A positive electrode conductor connecting each positive electrode terminal of each semiconductor switch element; a negative electrode conductor connecting each negative electrode terminal of each semiconductor switch element; and each control extreme of each semiconductor switch element from the drive circuit N first wirings individually connected to the child, and N second wirings individually connected from the driving circuit to each control terminal having the same potential as the negative terminal of each of the semiconductor switch elements, In the drive circuit of the semiconductor switch element parallel connection circuit provided,
Any two of the N second wirings are connected to each other so that their current directions are opposite to each other during normal operation, and one secondary winding for current detection. A drive circuit for a semiconductor switch element parallel connection circuit, wherein each of the current detection current transformers is connected via (N-1) current detection current transformers.   2. The drive circuit of the semiconductor switch element parallel connection circuit according to claim 1, wherein the two primary windings have a structure in which one of the two second wirings penetrates the magnetic core one or more times. A drive circuit for a semiconductor switch element parallel connection circuit.   The drive circuit of the semiconductor switch element parallel connection circuit according to claim 1 or 2, wherein the current of the secondary winding of the current detection current transformer is rectified and converted into a voltage signal, and the voltage value of the voltage signal is A drive circuit for a semiconductor switch element parallel connection circuit, wherein an overcurrent is determined when a predetermined value is exceeded, and an on signal to all the semiconductor switch elements is changed to an off signal.   4. The drive circuit of the semiconductor switch element parallel connection circuit according to claim 3, wherein the off signal is a signal that makes a voltage between a control pole terminal and a control terminal of the semiconductor switch element zero. Drive circuit for switch element parallel connection circuit. A drive circuit of a circuit in which N (N is an integer of 2 or more) voltage-driven semiconductor switch elements are connected in parallel, and outputs a common drive signal to the drive terminals of each of the semiconductor switch elements; A positive electrode conductor connecting each positive electrode terminal of each semiconductor switch element; a negative electrode conductor connecting each negative electrode terminal of each semiconductor switch element; and each control extreme of each semiconductor switch element from the drive circuit N first wirings individually connected to the child, and N second wirings individually connected from the driving circuit to each control terminal having the same potential as the negative terminal of each of the semiconductor switch elements, In the drive circuit of the semiconductor switch element parallel connection circuit provided,
The first wiring and the second wiring connected to each of the semiconductor switching elements are two primary windings that are connected so that their current directions are opposite to each other during steady operation, and one current detection A drive circuit for a semiconductor switch element parallel connection circuit, wherein each of the drive circuits is connected via a current detection current transformer having a secondary winding.   6. The drive circuit of the semiconductor switch element parallel connection circuit according to claim 5, wherein the two primary windings have a structure in which the first wiring and the second wiring are passed through the magnetic core one or more times. A drive circuit for a semiconductor switch element parallel connection circuit. The drive circuit of the semiconductor switch element parallel connection circuit according to claim 5 or 6, wherein the current of the secondary winding of the current detection current transformer is rectified and converted into a voltage signal, and the voltage value of the voltage signal is A drive circuit for a semiconductor switch element parallel connection circuit, wherein an overcurrent is determined when a predetermined value is exceeded, and an on signal to all the semiconductor switch elements is changed to an off signal. 8. The drive circuit of a semiconductor switch element parallel connection circuit according to claim 7, wherein the off signal is a signal that makes a voltage between a control pole terminal and a control terminal of the semiconductor switch element zero. Drive circuit for switch element parallel connection circuit.

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