JPH1042546A - Overcurrent detector for parallel semiconductor switching devices - Google Patents

Overcurrent detector for parallel semiconductor switching devices

Info

Publication number
JPH1042546A
JPH1042546A JP18795896A JP18795896A JPH1042546A JP H1042546 A JPH1042546 A JP H1042546A JP 18795896 A JP18795896 A JP 18795896A JP 18795896 A JP18795896 A JP 18795896A JP H1042546 A JPH1042546 A JP H1042546A
Authority
JP
Japan
Prior art keywords
circuit
current
semiconductor switch
overcurrent
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18795896A
Other languages
Japanese (ja)
Inventor
Naoto Yoshinori
直人 義則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP18795896A priority Critical patent/JPH1042546A/en
Publication of JPH1042546A publication Critical patent/JPH1042546A/en
Pending legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Power Conversion In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect an overcurrent in one of a plurality of semiconductor switching devices which are connected in parallel to each other and are operated simultaneously by operation signals from a common driving circuit with a simple detection circuit. SOLUTION: When common operation signals are supplied by a gate-drive circuit 11 to IGBTs (insulated gate bipolar transistors) 2 and 3 which are connected in parallel to each other, gate current detectors 12 and 13 are inserted into respective wirings between the gate-drive circuit 11 and the IGBTs 2 and 3. If an overcurrent flows in one of the IGBTs, the difference in polarities of the detected currents of the gate current detectors 12 and 13 is detected by polarity detectors 21 and 22, and an exclusive OR device 23, and an arm short-circuit current is detected. Or a circuit which detects that one of the currents detected by the gate current detectors 12 and 13 exceeds a predetermined value by overcurrent detectors 31 and 32 and an OR device 33 is added, and the AND of the output of the OR device 33 and the output of the exclusive OR device 23 is calculated by an AND device 34, to detect the arm short-circuit current.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、並列に接続して
運転中の半導体スイッチ素子のいずれかに過電流を生じ
たことを検出する並列半導体スイッチ素子の過電流検出
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent detection device for a parallel semiconductor switch element for detecting that an overcurrent has occurred in any of the operating semiconductor switch elements connected in parallel.

【0002】[0002]

【従来の技術】半導体スイッチ素子として、例えば絶縁
ゲートバイポーラトランジスタ(以下ではIGBTと略
記する)の2つを直列にして、この直列回路を直流電源
の正負極間に接続する。このとき正極側に接続したアー
ムを構成するIGBTと、負極側に接続したアームを構
成するIGBTとを交互にオン・オフさせることによ
り、両アームの結合点からは変換された交流を取り出す
ことができる。そこで、このような動作をするIGBT
直列回路の複数組を並列接続して直流電源に接続すれ
ば、直流を交流に変換し、あるいは交流を直流に変換す
る電力変換装置を得ることができる。
2. Description of the Related Art As a semiconductor switch element, for example, two insulated gate bipolar transistors (hereinafter abbreviated as IGBTs) are connected in series, and this series circuit is connected between the positive and negative electrodes of a DC power supply. At this time, by turning on and off the IGBT constituting the arm connected to the positive electrode side and the IGBT constituting the arm connected to the negative electrode side alternately, it is possible to extract the converted alternating current from the connection point of both arms. it can. Therefore, an IGBT that performs such an operation
If a plurality of sets of series circuits are connected in parallel and connected to a DC power supply, a power converter that converts DC to AC or converts AC to DC can be obtained.

【0003】ところで、正極側アーム及び負極側アーム
を構成する両IGBTは、本来は同時にオンとはならな
いのであるが、なんらかの原因で両者が同時にオンとな
る期間があると、そのときに直流電源は短絡状態にな
る。これがアーム短絡である。アーム短絡によりIGB
Tには過大な電流が流れてこれを破損する恐れがあるの
で、この過電流を検出して素早く遮断する必要がある。
By the way, both IGBTs constituting the positive arm and the negative arm are not originally turned on at the same time, but if there is a period during which both are turned on at the same time for some reason, the DC power supply is then turned off. A short circuit occurs. This is an arm short circuit. IGB due to arm short circuit
Since an excessive current flows through T and may be damaged, it is necessary to detect this overcurrent and quickly shut off.

【0004】図5はゲート電圧をパラメータにしてIG
BTのコレクタ電圧とコレクタ電流との関係を示した特
性図であって、横軸はコレクタ電圧,縦軸はコレクタ電
流である。アーム短絡などによりコレクタ電流が過電流
になると、図5に図示のコレクタ電圧−電流特性により
コレクタ電圧が上昇する。そこで、コレクタ電圧がある
値を越えればコレクタ電流が過大であると判断して、こ
のコレクタ電流を減少させたのち遮断することで、当該
IGBTを保護する。
FIG. 5 is a graph showing an IG using a gate voltage as a parameter.
FIG. 6 is a characteristic diagram showing a relationship between a collector voltage and a collector current of the BT, wherein a horizontal axis represents a collector voltage and a vertical axis represents a collector current. When the collector current becomes overcurrent due to an arm short circuit or the like, the collector voltage increases due to the collector voltage-current characteristic shown in FIG. Therefore, if the collector voltage exceeds a certain value, it is determined that the collector current is excessive, and the IGBT is protected by reducing and then shutting off the collector current.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前述し
た従来の過電流検出方法はコレクタ電圧が所定値を越え
たときに過電流発生と判断しているので、例えばIGB
Tがターンオンする際の過渡電圧を過電流発生と判断す
るような誤検出を避けるために、一定時間は過電圧を検
出しないようにマスクをしている。そのために検出回路
が複雑になるし、一定時間のマスクは検出遅れの原因に
なるので、過電流がIGBTの許容時間を越えて流れ、
当該IGBTを破壊してしまう恐れを生じる欠点があ
る。
However, in the above-described conventional overcurrent detection method, it is determined that an overcurrent has occurred when the collector voltage exceeds a predetermined value.
In order to avoid erroneous detection such as judging that a transient voltage when T turns on is determined to be an occurrence of an overcurrent, masking is performed so that the overvoltage is not detected for a certain period of time. As a result, the detection circuit becomes complicated, and a mask for a certain period of time causes a detection delay, so that an overcurrent flows beyond the allowable time of the IGBT,
There is a disadvantage that the IGBT may be destroyed.

【0006】ところで電力変換装置は、その容量がます
ます増大しつつあるが、半導体スイッチ素子の定格電
圧,定格電流には限界があるので、複数のIGBTの並
列接続でアームを構成することで容量の増大を図ること
になる。IGBTを並列接続してアームを構成する場合
は、これら複数のIGBTの中のいずれかがノイズなど
により誤オンすると、対抗したアームがオン状態ならば
アーム短絡を生じる。そこでアーム短絡に備えて、並列
接続した各IGBTのそれぞれにコレクタ電圧の過大を
検出する前述の回路を別個に備えることになる。よって
装置全体の過電流検出回路が複雑化する欠点がある。更
に、一定時間のマスクによる過電流の検出遅れは依然と
して存在するので、IGBTが破壊されてしまう恐れは
解消されない。
Although the capacity of the power converter is increasing, the rated voltage and the rated current of the semiconductor switch element are limited. Therefore, the capacity is increased by configuring an arm by connecting a plurality of IGBTs in parallel. Will be increased. When an arm is configured by connecting IGBTs in parallel, if any of the plurality of IGBTs is erroneously turned on due to noise or the like, an arm short circuit occurs if the opposing arm is on. Therefore, in preparation for an arm short-circuit, each of the parallel-connected IGBTs is separately provided with the above-described circuit for detecting an excessive collector voltage. Therefore, there is a disadvantage that the overcurrent detection circuit of the entire device is complicated. Furthermore, since the detection of overcurrent by the mask for a certain period of time still exists, the risk of the IGBT being destroyed is not eliminated.

【0007】そこでこの発明の目的は、並列接続した複
数の半導体スイッチ素子を共通の駆動回路からの動作信
号で同時に動作させる構成の装置で、いずれかの半導体
スイッチ素子に過電流を生じたことを、簡単な回路で確
実に検出できるようにすることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus having a configuration in which a plurality of semiconductor switch elements connected in parallel are simultaneously operated by an operation signal from a common drive circuit, and an overcurrent is generated in any one of the semiconductor switch elements. It is to ensure that the detection can be performed with a simple circuit.

【0008】[0008]

【課題を解決するための手段】前記の目的を達成するた
めに、この発明の並列半導体スイッチ素子の過電流検出
装置は、複数の半導体スイッチ素子に共通の駆動信号を
出力する駆動回路と、これら複数の半導体スイッチ素子
の各正極端子同士を相互に接続する導体と、各負極端子
同士を相互に接続する導体と、前記駆動回路から各制御
極端子へ別個に接続する配線と、前記駆動回路から各負
極端子と同電位の制御端子へ別個に接続する配線とを備
えてなる並列半導体スイッチ素子において、前記駆動回
路と各半導体スイッチ素子との間に駆動信号を流す前記
各配線に別個の電流検出回路を設置し、この電流検出回
路が検出する各電流の極性を極性検出回路で別個に検出
する。この検出電流極性が不一致のときに、前記並列半
導体スイッチ素子のいずれかに過電流が生じたと判定す
るものとする。
In order to achieve the above object, an overcurrent detecting device for a parallel semiconductor switching device according to the present invention comprises a driving circuit for outputting a driving signal common to a plurality of semiconductor switching devices; A conductor connecting the respective positive terminals of the plurality of semiconductor switch elements to each other, a conductor connecting the respective negative terminals to each other, a wiring separately connecting from the drive circuit to each control electrode terminal, In a parallel semiconductor switch element including each negative electrode terminal and a wiring separately connected to a control terminal having the same potential, a separate current detection is performed on each of the wirings that passes a drive signal between the drive circuit and each semiconductor switch element. A circuit is installed, and the polarity of each current detected by the current detection circuit is separately detected by the polarity detection circuit. When the detected current polarities do not match, it is determined that an overcurrent has occurred in any of the parallel semiconductor switch elements.

【0009】または、前記駆動回路と各半導体スイッチ
素子との間に駆動信号を流す前記各配線に別個の電流検
出回路を設け、この電流検出回路が検出する各電流の極
性を極性検出回路で別個に検出し、且つ、前記各検出電
流が所定値を越えたことを過電流検出回路で別個に検出
する。各検出電流のいずれかが前記所定値を越え且つ各
電流の検出極性が不一致のときに、前記並列半導体スイ
ッチ素子のいずれかに過電流が生じたと判定するものと
する。
Alternatively, a separate current detection circuit is provided on each of the wirings through which a drive signal flows between the drive circuit and each semiconductor switch element, and the polarity of each current detected by the current detection circuit is separately determined by the polarity detection circuit. And the overcurrent detection circuit separately detects that each of the detected currents exceeds a predetermined value. When any of the detection currents exceeds the predetermined value and the detection polarities of the currents do not match, it is determined that an overcurrent has occurred in any of the parallel semiconductor switch elements.

【0010】[0010]

【発明の実施の形態】図6は2つのIGBTを並列にし
て同時にゲートオンさせたときのゲート電流の変化を示
した動作波形図であって、図6は一方のIGBTのゲ
ート電流の変化、図6は他方のIGBTのゲート電流
の変化を示しており、t1 はゲートオン信号入力時点で
ある。また、図7は2つのIGBTを並列にして同時に
ゲートオフさせたときのゲート電流の変化を示した動作
波形図であって、図7は一方のIGBTのゲート電流
の変化、図7は他方のIGBTのゲート電流の変化を
示しており、t2 はゲートオフ信号入力時点である。こ
の図6,図7で明らかなように、並列接続しているIG
BTを同時にオン・オフさせるときの各ゲート電流の極
性は同じである。
FIG. 6 is an operation waveform diagram showing a change in gate current when two IGBTs are turned on in parallel with two IGBTs in parallel. FIG. 6 is a diagram showing a change in gate current of one IGBT. 6 shows a change in the gate current of the other IGBT, and t 1 is the time when the gate-on signal is input. FIG. 7 is an operation waveform diagram showing a change in gate current when two IGBTs are turned off in parallel in parallel with each other. FIG. 7 shows a change in gate current of one IGBT, and FIG. 7 shows another IGBT. , And t 2 is the point in time when the gate-off signal is input. As apparent from FIGS. 6 and 7, the IGs connected in parallel
The polarity of each gate current when the BT is turned on and off simultaneously is the same.

【0011】図1は本発明の第1実施例を表した回路図
であって、2つの半導体スイッチ素子を並列接続した場
合の電力変換装置の部分を図示している。即ち、半導体
スイッチ素子としてのIGBT2とIGBT3とを並列
に接続して正極側アームを構成し、そのコレクタ側を直
流電源の正極Pに接続する。このときIGBT2には配
線インダクタンス4が直列に存在し、IGBT3には配
線インダクタンス5が直列に存在する。負極側アームは
IGBT6とIGBT7との並列接続で構成されるが、
IGBT6には配線インダクタンス8が直列に存在し、
IGBT7には配線インダクタンス9が直列に存在す
る。これら正極側アームと負極側アームとは直列に接続
され、負極側アームのエミッタ側は直流電源の負極Nに
接続される。正極側アームの両IGBT2,3はゲート
駆動回路11からの駆動信号で同時にオン・オフする。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and shows a portion of a power conversion device when two semiconductor switch elements are connected in parallel. In other words, IGBT2 and IGBT3 as semiconductor switch elements are connected in parallel to form a positive arm, and the collector side is connected to the positive electrode P of the DC power supply. At this time, the IGBT 2 has the wiring inductance 4 in series, and the IGBT 3 has the wiring inductance 5 in series. The negative arm is configured by connecting IGBT6 and IGBT7 in parallel,
The IGBT 6 has a wiring inductance 8 in series,
The IGBT 7 has a wiring inductance 9 in series. The positive arm and the negative arm are connected in series, and the emitter of the negative arm is connected to the negative electrode N of the DC power supply. Both IGBTs 2 and 3 of the positive side arm are simultaneously turned on / off by a drive signal from the gate drive circuit 11.

【0012】負極側アームを構成しているIGBT6と
IGBT7とがオンしているときには、ゲート駆動回路
11はオン信号を出力しないから、IGBT2とIGB
T3とはオフ状態である。このときに、例えばIGBT
3のゲート回路にノイズが侵入してこれを誤ってターン
オンさせたとすると、アーム短絡電流IC は2点鎖線で
図示しているように、正極P→IGBT3→配線インダ
クタンス5→IGBT6,7→配線インダクタンス8,
9→負極Nの経路で流れる。
When the IGBT 6 and the IGBT 7 constituting the negative arm are turned on, the gate drive circuit 11 does not output an on signal, so that the IGBT 2 and the IGB
T3 is an off state. At this time, for example, IGBT
When noise third gate circuit is that turns on erroneously which penetrates the arm short-circuit current I C is as shown by the two-dot chain line, the positive electrode P → IGBT 3 → wiring inductance 5 → IGBT6,7 → wiring Inductance 8,
9 → flow on the negative electrode N path.

【0013】このアーム短絡電流IC により配線インダ
クタンス5に誘起電圧E0 を生じ、配線インダクタンス
5→ゲート電流検出器13→ゲート電流検出器12→配
線インダクタンス4→配線インダクタンス5の経路で、
破線で図示しているゲート回路誘導電流I0 が流れる
が、このゲート回路誘導電流I0 が流れる方向はゲート
電流検出器12とゲート電流検出器13とでは逆であ
る。そこで、過電流検出回路20を構成している極性検
出器21と極性検出器22とがこの電流方向を検出し、
両者の方向が相反しているときに排他的論理和素子23
が過電流の発生を検出する。
The arm short-circuit current I C causes an induced voltage E 0 in the wiring inductance 5, and the wiring inductance 5 → the gate current detector 13 → the gate current detector 12 → the wiring inductance 4 → the wiring inductance 5,
Although the gate circuit induction current I 0 shown by the broken line flows, the direction in which the gate circuit induction current I 0 flows is opposite between the gate current detector 12 and the gate current detector 13. Therefore, the polarity detector 21 and the polarity detector 22 constituting the overcurrent detection circuit 20 detect this current direction,
When the directions are opposite to each other, the exclusive OR element 23 is used.
Detects the occurrence of overcurrent.

【0014】図2は本発明の第2実施例を表した回路図
であって、前述した図1の第1実施例回路と同様に2つ
の半導体スイッチ素子を並列接続した場合の電力変換装
置の部分を図示しているが、図2の第2実施例回路に図
示のIGBT2と3,配線インダクタンス4と5,IG
BT6と7,配線インダクタンス8と9,ゲート駆動回
路11,ゲート電流検出器12とと13,極性検出器2
1と22,および排他的論理和素子23の名称・用途・
機能は図1で既述の第1実施例回路の場合と同じである
から、これらの説明は省略する。
FIG. 2 is a circuit diagram showing a second embodiment of the present invention. Similar to the circuit of the first embodiment shown in FIG. 1, an electric power converter in which two semiconductor switch elements are connected in parallel is shown. Although the IGBTs 2 and 3, the wiring inductances 4 and 5, and the IG
BTs 6 and 7, wiring inductances 8 and 9, gate drive circuit 11, gate current detectors 12 and 13, polarity detector 2
1 and 22 and the exclusive OR element 23
The function is the same as that of the circuit of the first embodiment described above with reference to FIG.

【0015】この第2実施例回路では、ゲート電流検出
器12と13の検出電流を入力する過電流検出器31と
32、これらの出力信号の論理和を演算する論理和素子
33、この論理和素子33の出力信号と前記の排他的論
理和素子23の出力信号との論理積を演算する論理積素
子34とを付加して構成した過電流検出回路30を備え
ている点が、前述した第1実施例回路とは異なってい
る。即ち、ゲート回路誘導電流I0 の極性が異なってい
ることを排他的論理和素子23で検出すると共に、ゲー
ト電流検出器12と13で検出するゲート回路誘導電流
0 のうちのいずれかが過電流設定値を越えていると、
論理和素子33を介して過電流状態が検出される。論理
積素子34はゲート回路誘導電流I0 のいずれかが過電
流で、且つ極性不一致であることを検出して、アーム短
絡電流IC の発生を検知する。
In the circuit of the second embodiment, overcurrent detectors 31 and 32 for inputting the detection currents of the gate current detectors 12 and 13, an OR element 33 for calculating the OR of these output signals, and the OR The point that the overcurrent detection circuit 30 includes an AND element 34 for calculating the AND of the output signal of the element 33 and the output signal of the exclusive OR element 23 is provided. This is different from the circuit of the first embodiment. That is, the possible detected by the exclusive OR element 23 a polarity of the gate circuit an induced current I 0 are different, one of the gate circuit induction current I 0 to be detected by the gate current detector 12 and 13 is excessive If the current setting is exceeded,
An overcurrent state is detected via the OR element 33. The AND element 34 detects the occurrence of the arm short-circuit current I C by detecting that any one of the gate circuit induced currents I 0 is an overcurrent and the polarities do not match.

【0016】図3は図1に図示の第1実施例回路の動作
を表した動作波形図であって、図3はアーム短絡電流
C の変化、図3はアーム短絡電流IC に伴って配線
インダクタンス5に現れる誘起電圧E0 の変化、図3
はゲート電流検出器13が検出するゲート回路誘導電流
0 の変化、図3はゲート電流検出器12が検出する
ゲート回路誘導電流I0 の変化をそれぞれが表してい
る。t0 はアーム短絡電流IC の発生時点であって、こ
のアーム短絡電流IC で生じる誘起電圧E0 により流れ
るゲート回路誘導電流I0 をゲート電流検出器12,1
3で検出するが、検出した各電流の極性が異なっている
ことから、アーム短絡電流IC の発生を検出できる。
[0016] Figure 3 is a waveform diagram showing the operation of the first embodiment circuit shown in Figure 1, Figure 3 is the change in the arm short-circuit current I C, 3 with the arm short-circuit current I C 3. Change in induced voltage E 0 appearing in wiring inductance 5, FIG.
3 shows a change in the gate circuit induction current I 0 detected by the gate current detector 13, and FIG. 3 shows a change in the gate circuit induction current I 0 detected by the gate current detector 12. t 0 is a time point of generation of the arm short-circuit current I C, the gate current detector gate circuit induction current I 0 flowing through the induced voltage E 0 that occurs in the arm short-circuit current I C 12,1
Detected in 3 but, since the polarities of the current detected is different, it can detect the occurrence of the arm short-circuit current I C.

【0017】図4は図2に図示の第2実施例回路の動作
を表した動作波形図であって、図4はアーム短絡電流
C の変化、図4はアーム短絡電流IC に伴って配線
インダクタンス5に現れる誘起電圧E0 の変化、図4
はゲート電流検出器13が検出するゲート回路誘導電流
0 の変化、図4はゲート電流検出器12が検出する
ゲート回路誘導電流I0 の変化をそれぞれが表してい
る。t0 はアーム短絡電流IC の発生時点であって、こ
のアーム短絡電流IC が誘起電圧E0 を生じ、ゲート電
流検出器12とゲート電流検出器13は、誘起電圧E0
により流れるゲート回路誘導電流I0 の大きさと極性と
を検出する。アーム短絡電流IC の大きさのいずれかが
過電流設定値を越え、且つ電流極性が異なっていれば、
アーム短絡電流IC が発生したことが検出できる。
[0017] Figure 4 is a waveform diagram showing the operation of the second embodiment circuit shown in FIG. 2, FIG. 4 is a change in the arm short-circuit current I C, 4 with the arm short-circuit current I C 4. Change in induced voltage E 0 appearing in wiring inductance 5, FIG.
4 shows a change in the gate circuit induction current I 0 detected by the gate current detector 13, and FIG. 4 shows a change in the gate circuit induction current I 0 detected by the gate current detector 12. t 0 is a point in time when the arm short-circuit current I C is generated, and this arm short-circuit current I C generates an induced voltage E 0 , and the gate current detector 12 and the gate current detector 13 cause the induced voltage E 0
Detecting the magnitude and polarity of the gate circuit induction current I 0 flowing through. If one of the magnitudes of the arm short-circuit current I C exceeds the overcurrent set value and the current polarities are different,
Arm short circuit current I C can be detected that has occurred.

【0018】[0018]

【発明の効果】この発明によれば、並列接続した半導体
スイッチ素子を同時オン・オフさせる構成のアームを直
列接続して得られる電力変換装置において、並列接続し
た各半導体スイッチ素子の中のいずれかが誤オンしてア
ーム短絡電流が流れた場合に、各半導体スイッチ素子の
ゲート回路に誘導されるゲート回路誘導電流の極性を検
出してその極性が異なっているとき、或いはこのゲート
回路誘導電流の大きさと極性とを検出して、その大きさ
のいずれかが設定値以上で且つ極性が異なっているとき
に、アーム短絡電流発生と判断することにより、従来に
比べてアーム短絡電流検出装置の構成が簡素化できる効
果が得られる。更に、アーム短絡電流の検出を時間遅れ
無しで素早く確実に行えるので、半導体スイッチ素子が
過電流で破壊される恐れを回避できる効果も得られる。
According to the present invention, in a power converter obtained by connecting in series an arm configured to simultaneously turn on and off semiconductor switch elements connected in parallel, any one of the semiconductor switch elements connected in parallel is used. Erroneously turns on and the arm short-circuit current flows, detects the polarity of the gate circuit induced current induced in the gate circuit of each semiconductor switch element and detects that the polarity is different, or By detecting the magnitude and polarity and determining that an arm short-circuit current has occurred when one of the magnitudes is equal to or greater than a set value and the polarity is different, the configuration of the arm short-circuit current detection device is compared to the conventional device. Can be simplified. Furthermore, since the detection of the arm short-circuit current can be performed quickly and reliably without a time delay, the effect of avoiding the possibility that the semiconductor switch element is destroyed by an overcurrent can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例を表した回路図FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図2】本発明の第2実施例を表した回路図FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

【図3】図1に図示の第1実施例回路の動作を表した動
作波形図
FIG. 3 is an operation waveform diagram showing the operation of the circuit of the first embodiment shown in FIG. 1;

【図4】図2に図示の第2実施例回路の動作を表した動
作波形図
4 is an operation waveform diagram showing the operation of the circuit of the second embodiment shown in FIG.

【図5】ゲート電圧をパラメータにしてIGBTのコレ
クタ電圧とコレクタ電流との関係を示した特性図
FIG. 5 is a characteristic diagram showing a relationship between a collector voltage and a collector current of an IGBT using a gate voltage as a parameter.

【図6】2つのIGBTを並列にして同時にゲートオン
させたときのゲート電流の変化を示した動作波形図
FIG. 6 is an operation waveform diagram showing a change in gate current when two IGBTs are placed in parallel and gates are turned on simultaneously.

【図7】2つのIGBTを並列にして同時にゲートオフ
させたときのゲート電流の変化を示した動作波形図
FIG. 7 is an operation waveform diagram showing a change in gate current when two IGBTs are placed in parallel and gates are turned off simultaneously.

【符号の説明】[Explanation of symbols]

2,3,6,7 IGBT 4,5,8,9 配線インダクタンス 11 ゲート駆動回路 12,13 ゲート電流検出器 20,30 過電流検出回路 21,22 極性検出器 23 排他的論理和素子 31,32 過電流検出器 33 論理和素子 34 論理積素子 2,3,6,7 IGBT 4,5,8,9 Wiring inductance 11 Gate drive circuit 12,13 Gate current detector 20,30 Overcurrent detection circuit 21,22 Polarity detector 23 Exclusive OR element 31,32 Overcurrent detector 33 OR element 34 AND element

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H02M 1/08 341 H02M 1/08 341B ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical display location H02M 1/08 341 H02M 1/08 341B

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】複数の半導体スイッチ素子に共通の駆動信
号を出力する駆動回路と、これら複数の半導体スイッチ
素子の各正極端子同士を相互に接続する導体と、各負極
端子同士を相互に接続する導体と、前記駆動回路から各
制御極端子へ別個に接続する配線と、前記駆動回路から
各負極端子と同電位の制御端子へ別個に接続する配線と
を備えてなる並列半導体スイッチ素子において、 前記駆動回路と各半導体スイッチ素子との間に駆動信号
を流す前記各配線に別個に設置する電流検出回路と、こ
の電流検出回路が検出する各電流の極性を別個に検出す
る極性検出回路と、各電流の検出極性が不一致のときに
前記並列半導体スイッチ素子のいずれかに過電流が生じ
たと判定する過電流判定回路と、を備えていることを特
徴とする並列半導体スイッチ素子の過電流検出装置。
1. A drive circuit for outputting a common drive signal to a plurality of semiconductor switch elements, a conductor connecting the respective positive terminals of the plurality of semiconductor switch elements to each other, and connecting the respective negative terminals to each other. A parallel semiconductor switch element comprising: a conductor, a wiring separately connected from the drive circuit to each control electrode terminal, and a wiring separately connected from the drive circuit to a control terminal having the same potential as each negative electrode terminal. A current detection circuit separately provided on each of the wirings for flowing a drive signal between the drive circuit and each semiconductor switch element; a polarity detection circuit for separately detecting the polarity of each current detected by the current detection circuit; An overcurrent determination circuit that determines that an overcurrent has occurred in any of the parallel semiconductor switch elements when the detected polarities of the currents do not match. Overcurrent detection device for switch elements.
【請求項2】複数の半導体スイッチ素子の各正極側同士
を相互に接続する回路と、各負極側同士を相互に接続す
る回路と、各制御極と駆動回路とを別個に接続する配線
と、各負極側に設けた前記制御端子と前記駆動回路とを
別個に接続する配線とを備えて、複数の前記半導体スイ
ッチ素子に共通の駆動信号を与える構成の並列半導体ス
イッチ素子において、 前記駆動回路と各半導体スイッチ素子との間に駆動信号
を流す前記各配線に別個に設置する電流検出回路と、こ
の電流検出回路が検出する各電流の極性を別個に検出す
る極性検出回路と、前記各検出電流が所定値を越えたこ
とを別個に検出する過電流検出回路と、いずれかの電流
が前記所定値を越え且つ各電流の検出極性が不一致のと
きに、前記並列半導体スイッチ素子のいずれかに過電流
が生じたと判定する過電流判定回路と、を備えているこ
とを特徴とする並列半導体スイッチ素子の過電流検出装
置。
2. A circuit for connecting the respective positive electrode sides of a plurality of semiconductor switch elements to each other, a circuit for connecting the respective negative electrode sides to each other, and a wiring for separately connecting each control electrode and the drive circuit; A parallel semiconductor switch element having a configuration for providing a common drive signal to a plurality of the semiconductor switch elements, the wiring including a wiring for separately connecting the control terminal and the drive circuit provided on each negative electrode side; A current detection circuit separately provided on each of the wirings for flowing a drive signal between each semiconductor switch element; a polarity detection circuit for separately detecting the polarity of each current detected by the current detection circuit; And an overcurrent detection circuit for separately detecting that the current has exceeded a predetermined value, and an overcurrent detection circuit for detecting whether any of the currents exceeds the predetermined value and the detection polarities of the respective currents do not match each other. An overcurrent detection device for a parallel semiconductor switch element, comprising: an overcurrent determination circuit that determines that a current has occurred.
JP18795896A 1996-07-18 1996-07-18 Overcurrent detector for parallel semiconductor switching devices Pending JPH1042546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18795896A JPH1042546A (en) 1996-07-18 1996-07-18 Overcurrent detector for parallel semiconductor switching devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18795896A JPH1042546A (en) 1996-07-18 1996-07-18 Overcurrent detector for parallel semiconductor switching devices

Publications (1)

Publication Number Publication Date
JPH1042546A true JPH1042546A (en) 1998-02-13

Family

ID=16215149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18795896A Pending JPH1042546A (en) 1996-07-18 1996-07-18 Overcurrent detector for parallel semiconductor switching devices

Country Status (1)

Country Link
JP (1) JPH1042546A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014529239A (en) * 2011-08-26 2014-10-30 ゼネラル・エレクトリック・カンパニイ Reverse conduction mode self-turn-off gate driver
JP2015149828A (en) * 2014-02-06 2015-08-20 富士電機株式会社 Drive circuit of semiconductor switch element parallel connection circuit
JP2015216839A (en) * 2014-05-08 2015-12-03 ゼネラル・エレクトリック・カンパニイ Gate drive unit and method for short circuit protection for power switch
WO2021024432A1 (en) 2019-08-07 2021-02-11 オムロン株式会社 Imbalance failure detection circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014529239A (en) * 2011-08-26 2014-10-30 ゼネラル・エレクトリック・カンパニイ Reverse conduction mode self-turn-off gate driver
JP2015149828A (en) * 2014-02-06 2015-08-20 富士電機株式会社 Drive circuit of semiconductor switch element parallel connection circuit
JP2015216839A (en) * 2014-05-08 2015-12-03 ゼネラル・エレクトリック・カンパニイ Gate drive unit and method for short circuit protection for power switch
WO2021024432A1 (en) 2019-08-07 2021-02-11 オムロン株式会社 Imbalance failure detection circuit
JPWO2021024432A1 (en) * 2019-08-07 2021-02-11
EP4012925A4 (en) * 2019-08-07 2023-04-19 OMRON Corporation Imbalance failure detection circuit
US11984880B2 (en) 2019-08-07 2024-05-14 Omron Corporation Unbalanced failure detector circuit for detecting unbalanced failure of electronic device apparatus including electronic devices

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