JP2005102443A - Output voltage detecting method of power converter - Google Patents

Output voltage detecting method of power converter Download PDF

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JP2005102443A
JP2005102443A JP2003335096A JP2003335096A JP2005102443A JP 2005102443 A JP2005102443 A JP 2005102443A JP 2003335096 A JP2003335096 A JP 2003335096A JP 2003335096 A JP2003335096 A JP 2003335096A JP 2005102443 A JP2005102443 A JP 2005102443A
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output voltage
current
power converter
resistors
common line
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Takeaki Tabata
壮章 田畑
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To detect, as quick as possible, an output voltage of a power converter such as an inverter, while maintaining insulation performance. <P>SOLUTION: Resistors R11-R23 are connected parallel to, for example, semiconductor switch elements Q11-Q23 of IGBT or the like constituting a power converter (inverter) Conv of three-phase bridge configuration. Detectors CT1-CT3 are provided to a common line that connects the semiconductor switch elements and the resistors, for detecting a current. An output voltage is indirectly acquired from the current value, for the high-speed detection of a voltage with no delay in detection while easily attaining insulation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、半導体素子で構成された電力変換装置の出力電圧検出方法、特に素子故障をその部位とともに検出し得る出力電圧検出方法に関する。   The present invention relates to an output voltage detection method for a power conversion device constituted by semiconductor elements, and more particularly to an output voltage detection method capable of detecting an element failure together with its part.

図13にこの種の従来例を示す。これは、半導体素子を任意に直列または並列に構成して直流電源Edに接続することで、出力端子に接続された負荷Lに任意の交流電力を供給する電力変換装置、すなわちインバータを示すものである。
図13において、電力変換装置の出力電圧を検出する手段として、図示のように各相ごとに電圧検出回路Vsenを設け、制御装置から出力されるオン,オフ信号より推定されるインバータの出力電圧指令値と、電圧検出回路Vsenにより検出される出力電圧実際値とを比較し、出力電圧量を制御装置で補正するのが一般的である。
このような電圧検出回路の例が特許文献1,2などに示されている。特許文献1に示すものは図14のように、抵抗およびコンデンサなどのフィルタにより、インバータの出力電圧の高周波成分を除去し、絶縁アンプなどを介して入力するものである。
FIG. 13 shows this type of conventional example. This shows a power converter that supplies arbitrary AC power to a load L connected to an output terminal by configuring a semiconductor element arbitrarily in series or parallel and connecting it to a DC power supply Ed, that is, an inverter. is there.
In FIG. 13, as a means for detecting the output voltage of the power converter, a voltage detection circuit Vsen is provided for each phase as shown, and an inverter output voltage command estimated from an on / off signal output from the control device. In general, the value is compared with the actual output voltage value detected by the voltage detection circuit Vsen, and the output voltage amount is corrected by the control device.
Examples of such a voltage detection circuit are shown in Patent Documents 1 and 2 and the like. As shown in Patent Document 1, as shown in FIG. 14, a high frequency component of an output voltage of an inverter is removed by a filter such as a resistor and a capacitor, and input through an insulation amplifier or the like.

ところで、図13に示す制御装置からの図15(a)に示すようなオン,オフ信号により、インバータから例えばそのU相出力電圧が図15(b)のように出力されるのが理想の状態である。しかし、実際には図16(d)に示すように、オン,オフ信号が半導体素子としてのIGBT(絶縁ゲート形バイポーラトランジスタ)を駆動するゲート駆動回路GAに入力され、このGAからIGBTのゲートに信号が伝達された後、IGBTが動作するまでにオンとオフでそれぞれ図16(c)に示すように、td1,td2の遅れが生じる。この遅れにより、制御装置からの出力電圧指令と、実際のインバータ出力電圧との間にずれが生じる。それゆえ、実際の出力電圧値を検出することが、負荷に高精度の電力を供給するために必要とされる。   By the way, it is ideal that, for example, the U-phase output voltage is output from the inverter as shown in FIG. 15B by the ON / OFF signal as shown in FIG. 15A from the control device shown in FIG. It is. However, actually, as shown in FIG. 16D, on / off signals are input to a gate drive circuit GA that drives an IGBT (insulated gate bipolar transistor) as a semiconductor element, and from this GA to the gate of the IGBT. After the signal is transmitted, there is a delay of td1 and td2, as shown in FIG. Due to this delay, a deviation occurs between the output voltage command from the control device and the actual inverter output voltage. Therefore, it is necessary to detect the actual output voltage value in order to supply the load with high accuracy.

また、特許文献2では、交流出力電圧VacをコンパレータCPに入力するが、このコンパレータCPを駆動するための検出電源E1,E2を必要とする。つまり、検出電源E1,E2を新たに設けなければならず、これらを主回路と絶縁する必要がある。さらには、コンパレータCPの出力をフォトカプラPCで絶縁し、制御装置に伝達する手段を要するだけでなく、高速に検出するためには、上記コンパレータおよびフォトカプラの高速応答が要求される。   In Patent Document 2, the AC output voltage Vac is input to the comparator CP. However, detection power sources E1 and E2 for driving the comparator CP are required. That is, the detection power supplies E1 and E2 must be newly provided, and these must be insulated from the main circuit. Furthermore, not only a means for isolating the output of the comparator CP by the photocoupler PC and transmitting it to the control device is required, but also a high-speed response of the comparator and the photocoupler is required for high-speed detection.

特開平08−107700号公報(第3頁、図1)Japanese Patent Laid-Open No. 08-107700 (page 3, FIG. 1) 特開平06−121544号公報(第3頁、図1)Japanese Patent Laid-Open No. 06-121544 (page 3, FIG. 1)

上記特許文献1では、インバータの交流出力電圧から高周波成分除去のために、抵抗やコンデンサなどで構成されたフィルタが必要となり、フィルタの時定数を大きくすると、ノイズに強くなる反面検出遅れが生じ、フィルタの時定数を小さくすると、検出が高速になる反面ノイズに弱くなるというトレードオフの関係がある。
したがって、この発明の課題は、インバータの出力電圧を絶縁して高速に検出できるようにすることにある。
In the above-mentioned Patent Document 1, a filter composed of a resistor, a capacitor or the like is required to remove a high frequency component from the AC output voltage of the inverter. When the time constant of the filter is reduced, there is a trade-off relationship that the detection becomes faster but the noise becomes weaker.
Therefore, an object of the present invention is to insulate the output voltage of the inverter so that it can be detected at high speed.

このような課題を解決するために、請求項1の発明では、ブリッジ構成のアーム当たり1つ以上設けられ、オン,オフ信号により駆動される半導体素子からなる電力変換装置において、前記各半導体素子と並列にそれぞれ抵抗を接続し、前記各抵抗間と各半導体素子間とを接続する共通線に流れる電流値とその方向を検出する検出手段を設け、この検出手段により電力変換装置の交流出力電圧を検出することを特徴とする。   In order to solve such a problem, in the invention of claim 1, in a power conversion device including one or more semiconductor elements driven by an on / off signal provided per bridge-structured arm, A resistor is connected in parallel to each other, and a detecting means for detecting a current value and a direction flowing through a common line connecting the resistors and the semiconductor elements is provided, and the detecting device can detect an AC output voltage of the power converter. It is characterized by detecting.

請求項1の発明においては、前記共通線に流れる電流値とその方向に、前記オン,オフ信号を組み合わせることにより、半導体素子の故障をその部位とともに検出することができ(請求項2の発明)、請求項1または2の発明においては、前記共通線に流れる電流が所定値よりも小さいときは、前記オン,オフ信号をすべてオフとして電力変換装置の運転を停止することができる(請求項3の発明)。   According to the first aspect of the present invention, the failure of the semiconductor element can be detected together with the portion thereof by combining the on / off signal in the direction and the direction of the current flowing through the common line (the second aspect of the invention). In the invention of claim 1 or 2, when the current flowing through the common line is smaller than a predetermined value, the on / off signal can be turned off to stop the operation of the power converter. Invention).

この発明によれば、電流を検出して間接的に交流出力電圧を検出するようにしたので、検出遅れをなくすことができる。また、電流検出器として例えば変流器のように電線に挿入するタイプのものを用いることで、容易に絶縁を図ることができ、しかも電力変換装置の主電流と別部位に配置されるため、電流の測定可能範囲を微小電流範囲に抑えることができ、小型,低コスト化が可能となる。   According to the present invention, since the AC output voltage is detected indirectly by detecting the current, the detection delay can be eliminated. In addition, by using a type of current detector that is inserted into an electric wire, such as a current transformer, it is possible to easily insulate, and because it is arranged in a separate part from the main current of the power converter, The current measurable range can be limited to a very small current range, and the size and cost can be reduced.

図1はこの発明の第1の実施の形態を示す回路図であり、その1相分を図2,図3に示す。図2は素子IGBTQ1n,Q2nにそれぞれ抵抗R1n,R2nを並列接続する例を示し、これらの抵抗R1n,R2nを素子IGBTQ1n,Q2nの接続点Vacに接続する場合、図3に示す共通の線(太線参照)で接続するとともに、この共通の太線に電流検出器CTnを挿入すると、図1のようになる。   FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and one phase portion is shown in FIGS. FIG. 2 shows an example in which resistors R1n and R2n are connected in parallel to the devices IGBTQ1n and Q2n, respectively. When these resistors R1n and R2n are connected to the connection point Vac of the devices IGBTQ1n and Q2n, the common line (thick line) shown in FIG. 1), and when the current detector CTn is inserted into the common thick line, the result is as shown in FIG.

図3に示す1相分の回路により、図1の動作について図4,5を参照して説明する。図4(a)〜(d)は電力変換装置が動作中の回路状態を示しており、図4(a)はIGBTQ1nに電流が通流、図4(b)はIGBTQ1nに逆並列に接続されているFWD(フライホイールダイオード)に通流、図4(c)はIGBTQ2nに電流が通流、図4(d)はIGBTQ2nに逆並列に接続されているFWDに通流している状態を、それぞれ示す。   The operation of FIG. 1 will be described with reference to FIGS. 4 and 5 using the circuit for one phase shown in FIG. 4A to 4D show circuit states when the power converter is operating. FIG. 4A shows a current flow through the IGBT Q1n, and FIG. 4B shows an antiparallel connection to the IGBT Q1n. 4 (c) shows the current flowing through the IGBT Q2n, and FIG. 4 (d) shows the current flowing through the FWD connected in reverse parallel to the IGBT Q2n. Show.

つまり、電力変換装置が運転中のときは、図4(a)〜(d)のいずれかの状態をとり、交流出力端子はそれぞれEd,Ed,0,0の電圧を出力する。すなわち、電流検出器CTnではそれぞれEd/R2n,Ed/R2n,Ed/R1n,Ed/R1nの電流が検出されることになる。これらの動作を示すのが図5で、図示のように電力変換装置の出力電圧と電流検出器CTnで検出される値とは比例し、このことから電流検出器CTnで電力変換装置の出力電圧を検出できることになる。   That is, when the power converter is in operation, one of the states shown in FIGS. 4A to 4D is taken, and the AC output terminals output voltages of Ed, Ed, 0, 0, respectively. That is, the current detector CTn detects currents of Ed / R2n, Ed / R2n, Ed / R1n, and Ed / R1n, respectively. FIG. 5 shows these operations. As shown in the figure, the output voltage of the power converter is proportional to the value detected by the current detector CTn. From this, the output voltage of the power converter is detected by the current detector CTn. Can be detected.

このとき、電流検出器CTnは電力変換装置の主電流ではなく、抵抗に流れる電流を検出すれば良いため、小型の電流検出器とすることができる。さらに、電流検出器CTnは電力変換装置とは絶縁されているため、電流検出器CTnの出力信号を、制御装置に直接取り込むことが可能である。   At this time, since the current detector CTn only needs to detect the current flowing through the resistor, not the main current of the power conversion device, the current detector CTn can be a small current detector. Furthermore, since the current detector CTn is insulated from the power converter, the output signal of the current detector CTn can be directly taken into the control device.

図6はこの発明の第2の実施の形態を説明するための説明図で、回路図としては図3と同じである。
いま、図6(a)において、IGBTQ2nが何らかの故障で破壊したとする。この状態において、IGBTQ1nにオン信号が入力されてオンすると、短絡が生じる。このとき、IGBTQ1nおよびIGBTQ2nは、それぞれ直流電圧Edを分圧することとなる。そして、IGBTQ1nとIGBTQ2nが均等に直流電圧Edを分圧した場合、出力端子にはEd/2の電圧が発生する。抵抗R1nとR2nの接続点もEd/2となるため、CTnには電流が流れなくなる。
FIG. 6 is an explanatory diagram for explaining a second embodiment of the present invention, and a circuit diagram thereof is the same as FIG.
In FIG. 6A, it is assumed that the IGBT Q2n is destroyed due to some failure. In this state, when an on signal is input to the IGBT Q1n and turned on, a short circuit occurs. At this time, IGBTQ1n and IGBTQ2n each divide DC voltage Ed. When IGBTQ1n and IGBTQ2n equally divide DC voltage Ed, a voltage of Ed / 2 is generated at the output terminal. Since the connection point between the resistors R1n and R2n is also Ed / 2, no current flows through CTn.

また、IGBTQ1nとIGBTQ2nで均等に電圧を分圧しない場合でも、抵抗R1n,R2nの抵抗値を、
R1n=R2n=R
とすれば、電流検出器CTnに流れる電流Isは、
−Ed/R<Is<Ed/R
の範囲にあるので、この範囲の電流値を故障と設定することで、素子故障を検出することが可能となる。また、素子故障を検出したときは、素子へのオン,オフ信号をすべてオフ状態とし、電力変換装置の運転を停止することが望ましい。
Further, even when the voltage is not equally divided between the IGBT Q1n and the IGBT Q2n, the resistance values of the resistors R1n and R2n are
R1n = R2n = R
Then, the current Is flowing through the current detector CTn is
-Ed / R <Is <Ed / R
Therefore, it is possible to detect an element failure by setting the current value in this range as a failure. Moreover, when an element failure is detected, it is desirable to turn off all on / off signals to the element and stop the operation of the power converter.

さらに、素子Q1nが直流電圧Edを全電圧を持った場合においても、電流検出器CTnに流れる電流の方向(電流極性)とオン,オフ信号との関係から、素子故障を検出することができる。例えば、図7で素子Q2nにオン信号ON2を与えたとき、CTnに流れる電流の方向が図8(a)ならば正常とし、図8(b)の場合は異常と判定する。
また、図6(b)に示すように、素子Q1nが破壊したときも同様で、この場合に素子Q2nがオン信号によりオンすると短絡が発生するが交流出力電圧により、CTnに流れる電流値(大きさ)Isを検出することで、素子Q1nの破壊を同様にして検出することができる。
Further, even when the element Q1n has the full DC voltage Ed, the element failure can be detected from the relationship between the direction of the current (current polarity) flowing through the current detector CTn and the on / off signal. For example, when the ON signal ON2 is given to the element Q2n in FIG. 7, it is determined that the direction of the current flowing in CTn is normal if it is FIG. 8 (a), and abnormal if it is FIG. 8 (b).
As shown in FIG. 6B, the same applies when the element Q1n is destroyed. In this case, when the element Q2n is turned on by an ON signal, a short circuit occurs. A) By detecting Is, the destruction of the element Q1n can be detected in the same manner.

図9はこの発明の第2の実施の形態を説明するための説明図である。これは、スイッチング素子を複数個直列に接続する例として、2個の例を示している。つまり、各IGBTQ11n,Q12n,Q21n,Q22nには、それぞれ並列に抵抗R11n,R12n,R21n,R22nが接続されている。各IGBTと並列に接続されている抵抗のそれぞれに共通する線に、電流検出器CT1n,CT2n,CT12nが挿入されている。図9の動作原理を図10〜12に示す。   FIG. 9 is an explanatory diagram for explaining a second embodiment of the present invention. This shows two examples as an example of connecting a plurality of switching elements in series. That is, the resistors R11n, R12n, R21n, and R22n are connected in parallel to the IGBTs Q11n, Q12n, Q21n, and Q22n, respectively. Current detectors CT1n, CT2n, and CT12n are inserted into lines common to the resistors connected in parallel to the IGBTs. The operation principle of FIG. 9 is shown in FIGS.

図9,10は先の図4,5にそれぞれ対応しており、したがって電流検出器CT12nで検出される電流値Isは図4,5の場合と同様に、
Is=2Ed/(R21n+R22n)…図9(a),(b)の場合
=2Ed/(R11n+R12n)…図9(c),(d)の場合
となる。ここで、計算を簡単にするため、
R11n,R12n,R21n,R22n=R
とすれば、Is=2Ed/(2R)=Ed/R
となり、
図5の場合とまったく同様にして検出が可能なことは明らかである。
9 and 10 correspond to FIGS. 4 and 5, respectively. Therefore, the current value Is detected by the current detector CT12n is the same as in FIGS.
Is = 2Ed / (R21n + R22n) in the case of FIGS. 9A and 9B = 2Ed / (R11n + R12n) In the case of FIGS. 9C and 9D. Here, to simplify the calculation,
R11n, R12n, R21n, R22n = R
Then, Is = 2Ed / (2R) = Ed / R
And
It is clear that detection can be performed in exactly the same manner as in FIG.

図11に故障の場合の例を示す。
図9(a),(b),(c),(d)の状態では、電流検出器CT1n,CT2nで検出される電流は、いずれも「0」である。図11で、例えばQ22nが破壊したとすると、CT2nに2Ed/Rの電流が検出される。これにより、素子故障をその部位とともに検出することが可能となる。各部位の故障時における電流検出器の電流(大きさ)と向き(極性)との関係を、図12に示す。これは図9(a)の場合であるが、図9(b),(c),(d)の各場合についても同様にして、電流検出器の電流と向きから、素子故障をその部位とともに検出することが可能となる。
FIG. 11 shows an example in the case of a failure.
In the states of FIGS. 9A, 9B, 9C, and 9D, the currents detected by the current detectors CT1n and CT2n are all “0”. In FIG. 11, for example, if Q22n is destroyed, a current of 2 Ed / R is detected in CT2n. Thereby, it becomes possible to detect an element failure together with the part. FIG. 12 shows the relationship between the current (magnitude) and direction (polarity) of the current detector when each part fails. This is the case of FIG. 9 (a). Similarly, in each of the cases of FIGS. 9 (b), (c), and (d), an element failure is detected together with its location from the current and direction of the current detector. It becomes possible to detect.

この発明の実施の形態を示す回路図Circuit diagram showing an embodiment of the present invention 図1の1相分の半導体素子に並列接続される抵抗の接続態様説明図1 is an explanatory diagram of a connection mode of resistors connected in parallel to the semiconductor element for one phase in FIG. 図2で電流検出器を接続した場合を示す回路図Circuit diagram showing the case where the current detector is connected in FIG. 図3の動作状態の遷移説明図Transition diagram of the operation state of FIG. 図1の動作説明図FIG. 1 is an explanatory diagram of the operation. 図3の短絡電流経路説明図Short-circuit current path explanatory diagram of FIG. 図1の故障時の動作説明図Operation explanatory diagram at the time of failure of FIG. 図3の素子故障時の動作説明図Operational explanation diagram at the time of device failure of FIG. 各アームが複数素子からなる場合の動作状態の遷移説明図Transition diagram of operating state when each arm is composed of multiple elements 各アームが複数素子からなる場合の動作説明図Operation explanatory diagram when each arm is composed of multiple elements 1相分が故障した場合の動作説明図Explanation of operation when one phase has failed 故障素子と検出値との関係説明図Explanatory diagram of relationship between faulty element and detected value 電力変換装置の従来例を示す構成図Configuration diagram showing a conventional example of a power converter 従来の電圧検出回路の具体例を示す回路図Circuit diagram showing a specific example of a conventional voltage detection circuit 図13の動作説明図FIG. 13 is a diagram for explaining the operation. 従来例の課題を説明する説明図Explanatory drawing explaining the subject of a prior art example

符号の説明Explanation of symbols

Q11,Q12,Q13,Q21,Q22,Q23,Q1n,Q2n…IGBT(絶縁ゲート型バイポーラトランジスタ)、CT1,CT2,CT3,CTn,CT1n,CT2n,CT12n…電流検出器、R11,R12,R21,R22,R13,R23,R1n,R2n,R11n,R12n,R21n,R22n…抵抗、Ed…直流電源。
Q11, Q12, Q13, Q21, Q22, Q23, Q1n, Q2n ... IGBT (insulated gate bipolar transistor), CT1, CT2, CT3, CTn, CT1n, CT2n, CT12n ... current detector, R11, R12, R21, R22 , R13, R23, R1n, R2n, R11n, R12n, R21n, R22n ... resistors, Ed ... DC power supply.

Claims (3)

ブリッジ構成のアーム当たり1つ以上設けられ、オン,オフ信号により駆動される半導体素子からなる電力変換装置において、
前記各半導体素子と並列にそれぞれ抵抗を接続し、前記各抵抗間と各半導体素子間とを接続する共通線に流れる電流値とその方向を検出する検出手段を設け、この検出手段により電力変換装置の交流出力電圧を検出することを特徴とする電力変換装置の出力電圧検出方法。
In the power conversion device comprising one or more semiconductor elements driven by an on / off signal, provided at least one arm in a bridge configuration,
A resistor is connected in parallel with each of the semiconductor elements, and a detecting means for detecting a current value flowing in a common line connecting the resistors and between the semiconductor elements and a direction thereof are provided, and a power conversion device is provided by the detecting means. The output voltage detection method of the power converter device which detects the alternating current output voltage of this.
前記共通線に流れる電流値とその方向に、前記オン,オフ信号を組み合わせることにより、半導体素子の故障をその部位とともに検出することを特徴とする請求項1に記載の電力変換装置の出力電圧検出方法。   2. The output voltage detection of the power converter according to claim 1, wherein a failure of the semiconductor element is detected together with a portion thereof by combining the on / off signal in the direction and the current value flowing through the common line. Method. 前記共通線に流れる電流値が所定値よりも小さいときは、前記オン,オフ信号をすべてオフとして電力変換装置の運転を停止することを特徴とする請求項1または2に記載の電力変換装置の出力電圧検出方法。
3. The power conversion device according to claim 1, wherein when the value of a current flowing through the common line is smaller than a predetermined value, the operation of the power conversion device is stopped by turning off all of the on / off signals. Output voltage detection method.
JP2003335096A 2003-09-26 2003-09-26 Output voltage detecting method of power converter Pending JP2005102443A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026676A1 (en) * 2008-09-02 2010-03-11 パナソニック株式会社 Output buffer circuit and output buffer system
US8045301B2 (en) 2006-06-30 2011-10-25 Toyota Jidosha Kabushiki Kaisha Motor drive device
FR2993059A1 (en) * 2012-07-04 2014-01-10 Bosch Gmbh Robert POWER STAGE AND METHOD OF MANAGING THE SAME

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045301B2 (en) 2006-06-30 2011-10-25 Toyota Jidosha Kabushiki Kaisha Motor drive device
WO2010026676A1 (en) * 2008-09-02 2010-03-11 パナソニック株式会社 Output buffer circuit and output buffer system
FR2993059A1 (en) * 2012-07-04 2014-01-10 Bosch Gmbh Robert POWER STAGE AND METHOD OF MANAGING THE SAME

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