CN109164377B - Fault testing device and method for high-speed AD/DA hybrid chip - Google Patents

Abstract

The invention discloses a fault testing device and a fault testing method for a high-speed AD/DA hybrid chip, which are used for diagnosing high-speed ADC and DAC devices on a circuit board; for the diagnosis of the ADC, a given voltage value is input into a PC upper computer, the PC upper computer generates an analog voltage through an AD/DA integrated module and loads the analog voltage to the ADC to be tested to generate a test instruction and a test vector, the test instruction and the test vector act on an AD test module through an IEEE1149.1 controller, the AD test module quickly serially shifts out an acquired voltage quantization value to the IEEE1149.1 controller, then the IEEE1149.1 controller sends data to the PC upper computer, and the data are compared with an expected response, so that the fault condition of the ADC can be judged; for the diagnosis of the DAC, a given voltage value is input into a PC upper computer, the PC upper computer converts the voltage value into a test vector and generates a test instruction, the test vector is decoded by an IEEE1149.1 controller, then the test vector is shifted into a DA test module through TDI, and is further loaded to the DAC to be tested, the analog voltage output by the DAC to be tested and collected by the AD/DA integrated module is received, and the analog voltage is compared with an expected response, so that the fault condition of the DAC can be judged.

Description

Fault testing device and method for high-speed AD/DA hybrid chip

Technical Field

The invention belongs to the technical field of integrated circuit fault testing, and particularly relates to a fault testing device and method of a high-speed AD/DA hybrid chip.

Background

In 1986 and 1988, Joint Test Action Group (JTAG) mainly based on european and north american members has pioneered the research of boundary scan Test technology to solve the Test problem of vlsi (very Large Scale integration) and other novel electronic devices. The organization developed the IEEE1149.1 standard for digital boundary scan testing techniques in 1990, and was then continually supplemented and modified. In 1999, the IEEE organization released the IEEE1149.4 boundary scan standard, which was dedicated to the standardization of testability designs for analog circuits. However, currently, there are few integrated circuits supporting the IEEE1149.4 standard, which mainly include the KLIC (hybrid signal boundary scan test experimental Chip) provided by the dual-alternative analog switch STA400EP of the TI (Texas Instruments ) company and the IEEE1149.4 working group, and for the digital-analog hybrid chips such as the commonly used high-speed ADC, DAC, SoC (System on Chip), etc., IEEE1149.4 is rarely supported, so the test technology based on the IEEE1149.4 standard has not been applied to a relatively mature technology, and the boundary scan test of the hybrid integrated circuit is difficult to perform.

The invention overcomes the application obstruction, and realizes the fault diagnosis test of the high-speed AD/DA hybrid chip by means of the IEEE1149.1 boundary scan test technology aiming at the AD/DA of the classical hybrid chip in the digital-analog hybrid circuit. Because the testing technology based on the IEEE1149.1 standard is mature, the application is wide, and devices supporting the standard are abundant, the scheme of the invention has higher operability and practicability.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a fault testing device of a high-speed AD/DA hybrid chip, which utilizes a digital boundary scanning technology and uses a device supporting the IEEE1149.1 standard to carry out fault diagnosis on the AD/DA hybrid chip, thereby solving the problem of fault testing of the functional failure of a hybrid circuit mainly based on the AD/DA hybrid chip.

To achieve the above object, the present invention provides a fault testing apparatus for a high-speed AD/DA hybrid chip, comprising:

the PC upper computer is mainly used for generating boundary scanning test vectors and operation instructions required by the test, receiving test response vectors and voltage test data of the tested circuit, and analyzing and processing the received data by using a built-in algorithm to obtain a fault diagnosis report;

the operation of the whole device is controlled through a PC upper computer interface, and then according to the operation state of the device, the PC upper computer is connected and communicated with the AD/DA integrated module through a serial interface, and manually input voltage test data are input into the AD/DA integrated module or voltage test data output by the AD/DA integrated module are received; meanwhile, the PC upper computer communicates with the IEEE1149.1 controller through a USB interface, and loads the test vector and the test instruction to the IEEE1149.1 controller or receives a test response vector output by the IEEE1149.1 controller; the built-in algorithm of the PC upper computer can generate a corresponding expected response according to the current test instruction, and the fault condition can be judged by comparing the expected response with the received data;

the IEEE1149.1 controller is connected with the AD test module through a JTAG1 interface and is connected with the DA test module through a JTAG2 interface; the IEEE1149.1 controller loads a test vector through TDI, recovers a response vector through TDO, controls the state of a TAP (test access port) controller in the boundary scanning chip through TMS (TMS) and TCK (TCK) signals and further controls the test mode of the boundary scanning chip; the IEEE1149.1 controller is also responsible for decoding test vectors and test instructions transmitted by the PC upper computer, generating different JTAG signals and loading the different JTAG signals to a tested circuit, waiting for receiving test response vectors generated by the tested circuit and then forwarding the test response vectors to the PC upper computer;

the AD test module is provided with a plurality of I/O ports and is used for shifting out the quantized voltage value generated by the ADC in the tested circuit; the AD test module is connected with the ADC in the tested circuit in parallel through the I/O port and is connected with a JTAG1 interface of an IEEE1149.1 controller; all devices in the AD test module are connected in a daisy chain mode, namely the TDO of the previous device is connected with the TDI of the next device; after voltage quantization data output by an ADC (analog to digital converter) in a tested circuit is loaded to an I/O (input/output) port of an AD test module, the AD test module serially shifts out the voltage quantization data to an IEEE1149.1 controller through TDO (time difference of arrival) according to test vectors and test instructions sent by the IEEE1149.1 controller;

the DA test module is provided with a plurality of I/O ports and is used for loading the quantized voltage values to a DAC (digital-to-analog converter) in the tested circuit; the DA test module is connected with the DAC in the tested circuit in parallel through an I/O port and is connected with a JTAG2 interface of an IEEE1149.1 controller, and all devices in the DA test module are connected in a daisy chain mode, namely the TDO of the previous device is connected with the TDI of the next device; when the DAC in the tested circuit is tested, voltage data generated by a PC upper computer is shifted into an I/O port of a DA test module through an IEEE1149.1 controller, and then is loaded to a data input end of the DAC in the tested circuit;

the voltage output end of the AD/DA integrated module is connected with an ADC (analog-to-digital converter) in the tested circuit in parallel and used for loading analog voltage, and the voltage input end of the AD/DA integrated module is connected with a DAC (digital-to-analog converter) in the tested circuit in parallel and used for collecting analog voltage and outputting the analog voltage; the AD/DA integrated module collects analog voltage according to the requirement of the PC upper computer or sends the received analog voltage to the PC upper computer.

Meanwhile, the invention also provides a method for carrying out fault test by using the device, which is characterized by comprising the following steps:

(1) the initialization device comprises an initialization PC upper computer interface, an IEEE1149.1 controller and an AD/DA integrated module;

(2) loading a netlist file of a tested circuit and a BSDL file of an onboard boundary scanning device to a PC upper computer, and generating a test vector and a test instruction;

(3) selecting a test type on an upper computer interface of the PC, and manually inputting a test voltage; if the selected test class is 'ADC test' operation, entering step (4), and if the selected test class is 'DAC test' operation, entering step (5);

(4) ADC fault testing

(4.1) the AD/DA integrated module generates corresponding analog voltage and supplies the analog voltage to an ADC (analog-to-digital converter) in the tested circuit, and the IEEE1149.1 controller collects the output of the ADC in the tested circuit which is serially shifted out by the AD testing module;

(4.2) uploading the acquired output data to a PC upper computer by the IEEE1149.1 controller, and comparing the processed output data with an expected response to judge the fault condition;

(4.3) automatically generating a fault diagnosis report by the PC according to the fault condition, visually explaining to a tester, ending the test, and waiting for the start of the next test;

(5) DAC failure testing

(5.1) the IEEE1149.1 controller loads the test vector after voltage conversion to a DAC input port in the tested circuit through a DA test module, and collects analog voltage output of a DAC in the tested circuit through an AD/DA integrated module;

(5.2) comparing the acquired analog output voltage with an expected response after being processed, and judging the fault condition;

and (5.3) automatically generating a fault diagnosis report by the PC upper computer according to the fault condition, visually explaining to a tester, finishing the test, and waiting for the start of the next test.

The invention aims to realize the following steps:

the invention relates to a fault testing device and a fault testing method for a high-speed AD/DA hybrid chip, which are used for diagnosing high-speed ADC and DAC devices on a circuit board; for the diagnosis of the ADC, a given voltage value is input into a PC upper computer, the PC upper computer generates analog voltage through an AD/DA integrated module and loads the analog voltage to the ADC in a tested circuit to generate a test instruction and a test vector, the test instruction and the test vector act on an AD test module through an IEEE1149.1 controller, the AD test module quickly serially shifts out an acquired voltage quantization value to the IEEE1149.1 controller, then the IEEE1149.1 controller sends data to the PC upper computer, and the data is compared with an expected response, so that the fault condition of the ADC can be judged; for the diagnosis of the DAC, a given voltage value is input into a PC upper computer, the PC upper computer converts the voltage value into a test vector and generates a test instruction, the test vector is decoded by an IEEE1149.1 controller, then the test vector is shifted into a DA test module through TDI, and is further loaded to the DAC in a tested circuit, and then the analog voltage output by the tested DAC and collected by the AD/DA integrated module is received and compared with an expected response, so that the fault condition of the DAC can be judged.

Drawings

FIG. 1 is a block diagram of an embodiment of a high-speed AD/DA hybrid chip failure testing apparatus according to the present invention;

FIG. 2 is a flow chart of the test of the AD/DA hybrid chip provided by the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Examples

For convenience of description, the related terms appearing in the detailed description are explained:

AD/DA (Analog Digital/Digital Analog): modulus/digifax;

pc (personal computer): a personal computer;

IEEE (institute of Electrical and Electronic Engineers): the institute of electrical and electronics engineers;

adc (analog to Digital converter): an analog-to-digital converter;

DAC (digital to Analog converter): a digital-to-analog converter;

bsdl (boundary Scan Description language): a boundary scan description language;

usb (universal Serial bus): a universal serial bus;

JTAG (Joint Test Action group): a joint test action group;

TDI (test Data input): inputting test data;

TDO (test Data output): outputting test data;

TCK (test clock): testing a clock;

tms (test Mode select): selecting a test mode;

tap (test Access port): a test access port;

I/O (Input/Output): an input/output;

TI (Texas instruments): texas instruments;

FIG. 1 is a block diagram of an embodiment of a high-speed AD/DA hybrid chip failure testing apparatus according to the present invention.

In this embodiment, as shown in fig. 1, the fault testing apparatus for a high-speed AD/DA hybrid chip of the present invention mainly includes: PC host computer 1, IEEE1149.1 controller 2, AD test module 3, DA test module 4, AD/DA integrative module 5.

The PC upper computer 1 is used as a control center of the whole device, is mainly used for generating boundary scanning test vectors and operation instructions required by the test, simultaneously receives test response vectors and voltage test data of a tested circuit, analyzes and processes the received data by using a built-in algorithm and completes a fault diagnosis report;

the PC upper computer 1 can control the operation of the whole device through an interface, the interface mainly comprises an ADC test area, a DAC test area and a fault information display area, test data can be manually input, a netlist file and a BSDL file are imported, and a test report is exported; the PC upper computer 1 is connected with and communicates with the AD/DA integrated module 5 through a serial interface, and manually input voltage test data are input into the AD/DA integrated module 5 or voltage test data output by the AD/DA integrated module 5 are received; meanwhile, the PC upper computer 1 communicates with the IEEE1149.1 controller 2 through a USB interface, and loads a test vector and a test instruction to the IEEE1149.1 controller 2 or receives a test response vector output by the IEEE1149.1 controller 2; the built-in algorithm of the PC upper computer 1 can generate a corresponding expected response according to the current test instruction, and the fault condition of functional failure can be judged by comparing the expected response with the received test data;

the IEEE1149.1 controller 2, and in this embodiment, as shown in fig. 1, the IEEE1149.1 controller 2 employs a dual JTAG interface. Because the test methods for the ADC and the DAC are different, the circuit can be simplified by processing the ADC and the DAC through different JTAG interfaces, and the test efficiency is improved.

In the embodiment, the test device is connected with the AD test module 3 through a JTAG1 interface and is connected with the DA test module 4 through a JTAG2 interface; the IEEE1149.1 controller 2 can load a test vector through TDI, recover a response vector through TDO, and control the state of a TAP controller in the boundary scan chip through selecting input TMS and inputting TCK signals through a test mode so as to control the test mode of the boundary scan chip; the controller is mainly used for decoding the test vector and the test instruction transmitted by the PC upper computer 1, generating different JTAG signals to be loaded to a tested circuit board, waiting for receiving a test response vector generated by the tested circuit board and then forwarding the test response vector to the PC upper computer 1;

the AD test module 3 is provided with a plurality of I/O ports and is used for shifting out the quantized voltage value generated by the ADC in the tested circuit; the AD test module 3 is connected with an ADC in a tested circuit in parallel through an I/O port and is connected with a JTAG1 interface of an IEEE1149.1 controller 2; the devices in the AD test module 3 are connected in a daisy chain manner, namely the test data output TDO of the previous device is connected with the test data input TDI of the next device; after voltage quantization data output by an ADC in a tested circuit is loaded to an I/O port of an AD test module 3, the AD test module 3 serially shifts out the voltage quantization data to an IEEE1149.1 controller 2 through TDO according to a test vector and a test instruction sent by the IEEE1149.1 controller 2;

the DA test module 4 is provided with a plurality of I/O ports and is used for loading the quantized voltage values to a DAC (digital-to-analog converter) in the tested circuit; the DA test module 4 is connected with the DAC to be tested in parallel through an I/O port and is connected with a JTAG2 interface of the IEEE1149.1 controller 2, and all devices in the DA test module 4 are connected in a daisy chain mode, namely the TDO of the previous device is connected with the TDI of the next device; when the DAC is tested, voltage data generated by the PC upper computer 1 is shifted into an I/O port of the DA test module 4 through the IEEE1149.1 controller 2, and then is loaded to a data input end of the DAC in a tested circuit;

in the present embodiment, as shown in fig. 1, the device supporting the IEEE1149.1 standard used by both the AD test module 3 and the DA test module 4 is an SN74BCT8244A chip. The SN74BCT8244A chip is an eight-way buffer which supports the IEEE1149.1-1990 boundary scan standard and is produced by TI company, and an I/O port of the chip can quickly capture the voltage quantization value output by an ADC (analog-to-digital converter) or quickly load a test vector to a DAC (digital-to-analog converter), so that the test is efficiently completed.

The voltage output end of the AD/DA integrated module 5 is connected with an ADC (analog-to-digital converter) in the tested circuit in parallel and used for loading analog voltage, and the voltage input end of the AD/DA integrated module is connected with a DAC (digital-to-analog converter) in the tested circuit in parallel and used for collecting analog voltage and outputting the analog voltage; the AD/DA integrated module 5 collects analog voltage according to the requirement of the PC upper computer 1, or sends the received analog voltage to the PC upper computer 1.

In this embodiment, the AD/DA integrated module is a small-scale functional circuit integrating devices such as an ADC, a DAC, a single chip, and an amplifier, where the ADC and the DAC use high-speed, high-precision, and high-stability devices, and errors brought to the test result by the module are reduced as much as possible.

FIG. 2 is a flow chart of the test of the AD/DA hybrid chip provided by the present invention.

As shown in fig. 2, a method for testing the failure of a high-speed AD/DA hybrid chip includes the following steps:

s1, initializing device, which includes initializing PC upper computer interface, IEEE1149.1 controller and AD/DA integrated module;

s2, loading a netlist file (NET) of a tested circuit and a BSDL file of an onboard boundary scanning device to a PC upper computer in a manual mode, and generating a test vector and a test instruction; meanwhile, the PC upper computer generates a corresponding expected response through a built-in algorithm according to the current test instruction;

s3, selecting a test type on the PC upper computer interface, and manually inputting a test voltage, wherein the test type is divided into an ADC test and a DAC test; if the selected test class is the "ADC test" operation, proceeding to step S4, and if the selected test class is the "DAC test" operation, proceeding to step S5;

s4 ADC fault test

S4.1, the AD/DA integrated module generates corresponding analog voltage and provides the analog voltage for an ADC (analog to digital converter) in the tested circuit, and the IEEE1149.1 controller collects the output of the ADC in the tested circuit serially shifted out by the AD testing module;

s4.2, uploading the acquired output data to a PC upper computer by the IEEE1149.1 controller, comparing the processed output data with an expected response, and judging a fault condition;

s4.3, automatically generating a fault diagnosis report by the PC according to the fault condition, visually explaining to a tester, ending the test, and waiting for the start of the next test;

s5 DAC fault test

S5.1, the IEEE1149.1 controller loads the test vector after voltage conversion to a DAC input port in the tested circuit through a DA test module, and the analog voltage output of the DAC in the tested circuit is collected through an AD/DA integrated module;

s5.2, comparing the acquired analog output voltage with an expected response after being processed, and judging a fault condition;

and S5.3, automatically generating a fault diagnosis report by the PC upper computer according to the fault condition, visually explaining to a tester, finishing the test, and waiting for the start of the next test.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (3)

1. A fault testing device of a high-speed AD/DA hybrid chip is characterized by comprising:

the PC upper computer is mainly used for generating boundary scanning test vectors and operation instructions required by the test, receiving test response vectors and voltage test data of the tested circuit at the same time, and analyzing and processing the received data by using a built-in algorithm to obtain a fault diagnosis report;

the PC upper computer controls the operation of the whole device through an interface, the interface mainly comprises an ADC test area, a DAC test area and a fault information display area, test data can be manually input, a netlist file and a BSDL file are imported, and a test report is exported; the PC upper computer is connected and communicated with the AD/DA integrated module through a serial interface, and manually input voltage test data are input into the AD/DA integrated module or voltage test data output by the AD/DA integrated module are received; meanwhile, the PC upper computer communicates with the IEEE1149.1 controller through a USB interface, and loads the test vector and the test instruction to the IEEE1149.1 controller or receives a test response vector output by the IEEE1149.1 controller; the built-in algorithm of the PC upper computer can generate a corresponding expected response according to the current test instruction, and the fault condition of functional failure can be judged by comparing the expected response with the received test data;

the IEEE1149.1 controller adopts double JTAG interfaces and carries out test processing on the ADC and the DAC through different JTAG interfaces; the method specifically comprises the following steps: the test system is connected with the AD test module through a JTAG1 interface and is connected with the DA test module through a JTAG2 interface; the IEEE1149.1 controller loads a test vector through TDI, recovers a response vector through TDO, and controls the state of a TAP (test access port) controller in the boundary scanning chip through TMS (TMS) and TCK (TCK) signals so as to control the test mode of the boundary scanning chip; the IEEE1149.1 controller is also responsible for decoding test vectors and test instructions transmitted by the PC upper computer, generating different JTAG signals and loading the different JTAG signals to a tested circuit, waiting for receiving test response vectors generated by the tested circuit and then forwarding the test response vectors to the PC upper computer;

the AD test module is provided with a plurality of I/O ports and is used for shifting out the quantized voltage value generated by the ADC in the tested circuit; the AD test module is connected with the ADC in the tested circuit in parallel through the I/O port and is connected with a JTAG1 interface of an IEEE1149.1 controller; all devices in the AD test module are connected in a daisy chain mode, namely the TDO of the previous device is connected with the TDI of the next device; after voltage quantization data output by an ADC (analog to digital converter) in a tested circuit is loaded to an I/O (input/output) port of an AD test module, the AD test module serially shifts out the voltage quantization data to an IEEE1149.1 controller through TDO (time difference of arrival) according to test vectors and test instructions sent by the IEEE1149.1 controller;

the DA test module is provided with a plurality of I/O ports and is used for loading the quantized voltage values to a DAC (digital-to-analog converter) in the tested circuit; the DA test module is connected with the DAC in the tested circuit in parallel through an I/O port and is connected with a JTAG2 interface of an IEEE1149.1 controller, and all devices in the DA test module are connected in a daisy chain mode, namely the TDO of the previous device is connected with the TDI of the next device; when the DAC in the tested circuit is tested, voltage data generated by a PC upper computer is shifted into an I/O port of a DA test module through an IEEE1149.1 controller, and then is loaded to a data input end of the DAC in the tested circuit;

the voltage output end of the AD/DA integrated module is connected with an ADC (analog-to-digital converter) in the tested circuit in parallel and used for loading analog voltage, and the voltage input end of the AD/DA integrated module is connected with a DAC (digital-to-analog converter) in the tested circuit in parallel and used for collecting analog voltage and outputting the analog voltage; the AD/DA integrated module collects analog voltage according to the requirement of the PC upper computer or sends the received analog voltage to the PC upper computer.

2. The device for testing the fault of the high-speed AD/DA hybrid chip of claim 1, wherein the device supporting the IEEE1149.1 standard used by the AD test module and the DA test module is an SN74BCT8244A chip; the SN74BCT8244A chip supports the eight-way buffer of IEEE1149.1-1990 boundary scan standard, and the I/O port thereof can rapidly capture the voltage quantization value output by the ADC or rapidly load the test vector to the DAC.

3. A method for performing fault testing using the apparatus of claim 1, comprising the steps of:

(1) the initialization device comprises an initialization PC upper computer interface, an IEEE1149.1 controller and an AD/DA integrated module;

(2) loading a netlist file of a tested circuit and a BSDL file of an onboard boundary scanning device to a PC upper computer, and generating a test vector and a test instruction;

(3) selecting a test type on an upper computer interface of the PC, and manually inputting a test voltage; if the selected test class is 'ADC test' operation, entering step (4), and if the selected test class is 'DAC test' operation, entering step (5);

(4) ADC fault testing

(4.1) the AD/DA integrated module generates corresponding analog voltage and supplies the analog voltage to an ADC (analog-to-digital converter) in the tested circuit, and the IEEE1149.1 controller collects the output of the ADC in the tested circuit which is serially shifted out by the AD testing module;

(4.2) uploading the acquired output data to a PC upper computer by the IEEE1149.1 controller, and comparing the processed output data with an expected response to judge the fault condition;

(4.3) automatically generating a fault diagnosis report by the PC according to the fault condition, visually explaining to a tester, ending the test, and waiting for the start of the next test;

(5) DAC failure testing

(5.1) the IEEE1149.1 controller loads the test vector after voltage conversion to a DAC input port in the tested circuit through a DA test module, and collects analog voltage output of a DAC in the tested circuit through an AD/DA integrated module;

(5.2) comparing the acquired analog output voltage with an expected response after being processed, and judging the fault condition;

and (5.3) automatically generating a fault diagnosis report by the PC upper computer according to the fault condition, visually explaining to a tester, finishing the test, and waiting for the start of the next test.

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