JP2008147228A - Wiring board and its manufacturing method - Google Patents

Wiring board and its manufacturing method Download PDF

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JP2008147228A
JP2008147228A JP2006329256A JP2006329256A JP2008147228A JP 2008147228 A JP2008147228 A JP 2008147228A JP 2006329256 A JP2006329256 A JP 2006329256A JP 2006329256 A JP2006329256 A JP 2006329256A JP 2008147228 A JP2008147228 A JP 2008147228A
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wiring board
film carrier
electronic component
electronic components
manufacturing
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JP5098313B2 (en
Inventor
Hidekatsu Sekine
秀克 関根
Kenji Kawamoto
憲治 河本
Jin Sato
尽 佐藤
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To realize downsizing by improving positioning accuracy between the respective layers of a wiring board and electronic parts and to reduce manufacturing time and costs by incorporating electronic parts such as semiconductor element, capacitor, resistor, inductor or the like in the wiring board at the same time. <P>SOLUTION: Electronic parts such as semiconductor element, capacitor, resistor and inductor are built in the wiring board. When stacking the layers, they are positioned by sprocket holes or the like of a film carrier wherein the electronic parts are mounted, so as to improve the positioning accuracy between the respective layers of the wiring board and the electronic parts. Furthermore, an ILB connection technology that is technologically established is used to cope with narrower pitches of semiconductor elements, stable reliability of connection and shortest wiring to the upper layer for downsizing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、各種電子機器の配線基板の製造方法に係わり、さらに詳しくは半導体素子、キャパシタ、抵抗、インダクタ等の電子部品が内蔵される配線基板において、配線基板の各層と内蔵電子部品との位置精度を向上させることにより小型化を可能とし、さらに、製造時間及びコストを低減させることのできる配線基板及びその製造方法に関する。   The present invention relates to a method for manufacturing a wiring board of various electronic devices, and more specifically, in a wiring board in which electronic components such as a semiconductor element, a capacitor, a resistor, and an inductor are built, positions of each layer of the wiring board and the built-in electronic components. The present invention relates to a wiring board that can be miniaturized by improving accuracy, and that can reduce manufacturing time and cost, and a manufacturing method thereof.

近年の配線基板については、以下に示す第１〜第３の従来例が知られている。
まず、第１の従来例は、例えば図９に示すように、配線基板内の電極５上に半導体素子１、キャパシタ（図示せず）、抵抗３、及びインダクタ（図示せず）等の電子部品を一つずつ実装した例である（例えば特許文献１参照）。
この配線基板は、複数層の絶縁樹脂１７を重ね合わせて基板本体が成形され、下側の絶縁樹脂１７上に電極５が形成されている。そして、半導体素子１の場合は、半導体素子の電極５（図示せず）上に金等のバンプ６を形成し、非導電性接着剤（NCF（Non-conductive Film））２３等を介して、フェイスダウン方式により、基板上の金めっき等が施された電極５に実装されている。また、その他の部品は、基板（絶縁樹脂１７）上の半田２７等が施された電極５に実装されている。そして、このような電子部品上に上層の絶縁樹脂１７が積層される。また、このような配線基板の上下両面に配線１４が設けられている。 Regarding recent wiring boards, the following first to third conventional examples are known.
First, as shown in FIG. 9, for example, a first conventional example is an electronic component such as a semiconductor element 1, a capacitor (not shown), a resistor 3, and an inductor (not shown) on an electrode 5 in a wiring board. Are mounted one by one (see, for example, Patent Document 1).
In this wiring board, a plurality of layers of insulating resin 17 are stacked to form a substrate body, and the electrode 5 is formed on the lower insulating resin 17. In the case of the semiconductor element 1, a bump 6 such as gold is formed on the electrode 5 (not shown) of the semiconductor element, and a non-conductive adhesive (NCF (Non-conductive Film)) 23 or the like is used. It is mounted on the electrode 5 on which gold plating or the like is applied on the substrate by a face-down method. Other components are mounted on the electrode 5 on which solder 27 or the like is applied on a substrate (insulating resin 17). And the upper layer insulating resin 17 is laminated | stacked on such an electronic component. Moreover, the wiring 14 is provided on both upper and lower surfaces of such a wiring board.

また、第２の従来例は、例えば図１０に示すように、配線基板上に半導体素子１、キャパシタ（図示せず）、抵抗３、及びインダクタ（図示せず）等の電子部品が一つずつ接地され、直接、電子部品の電極５と上層配線１４とが最短で接続された例である（例えば特許文献２参照）。
この配線基板においては、半導体素子１の場合は、電極５上に金等のバンプ６を形成し、フェイスアップ方式で基板（絶縁樹脂１７）上のダイパッド２４上に銀ペーストを介して接地し、その他の電子部品は、絶縁樹脂１７上に絶縁接着剤を介して接地し、上層の絶縁樹脂１７を積層した後、炭酸ガスレーザー等でバンプ６及び電極５上に穴を開け、無電解めっきや電解めっきにて上層との接続を行う。なお、その他は図９に示す構成と同様であり、共通する部材には同一符号を付して説明は省略する。 Further, in the second conventional example, as shown in FIG. 10, for example, one electronic component such as a semiconductor element 1, a capacitor (not shown), a resistor 3, and an inductor (not shown) is provided on the wiring board. This is an example in which the electrode 5 of the electronic component and the upper wiring 14 are directly connected in the shortest time (see, for example, Patent Document 2).
In this wiring board, in the case of the semiconductor element 1, bumps 6 such as gold are formed on the electrodes 5, and are grounded via a silver paste on the die pad 24 on the board (insulating resin 17) in a face-up manner, Other electronic components are grounded on the insulating resin 17 via an insulating adhesive, and after the upper insulating resin 17 is laminated, holes are made on the bumps 6 and the electrodes 5 with a carbon dioxide laser or the like, and electroless plating or The upper layer is connected by electrolytic plating. The rest of the configuration is the same as that shown in FIG. 9, and the same reference numerals are given to common members, and descriptions thereof are omitted.

また、第３の従来例は、例えば図１１、図１２に示すように、フィルムキャリア４に半導体素子１のみが実装されたパッケージを一つずつ配線基板内に埋め込んだ例である（例えば特許文献３参照）。
以下、この第３の従来例の製造工程を順次説明する。まず、パッケージはＴＣＰ（図１１（ａ））と呼ばれ、ＴＡＢ（フィルムキャリヤ）の実装方式を採用したパッケージであり、リードピッチの縮小化、パッケージの薄型化小型化に適している。
代表的な製造方法としては、長尺の樹脂フィルム２６にシート状接着剤（図示せず）を貼り合わせた後、金型等でパンチングし、所定の開口部２６Ａを設ける。
次に、シート状接着剤を介して樹脂フィルム２６に銅箔１３を貼りあわせ、フォトリソグラフィ及びエッチングプロセスを用いて、樹脂フィルム２６の開口部２６Ａにリード１７が張り出した銅配線１４を形成する。なお、この一連のプロセスは樹脂フィルム２６の両端に形成されたスプロケットホール１２と呼ばれる穴で位置合わせ及び搬送が行われる（図１２参照）。
次いで、例えば錫めっきが施されたリード７と半導体素子１（半導体チップ）の電極５上に形成されたバンプ６（例えば金バンプ）とを所定の治具でボンディングする。
次に、ポッティング樹脂１０により半導体素子１（半導体チップ）及び所望周辺部を樹脂封止し、所定の金型等でパンチングし、ＴＣＰ（図１１（ａ））を作製する。
そして、この従来例は、パッケージを配線基板に内蔵する形態であり、ＴＣＰが接着剤を介して基板（絶縁樹脂１７）の開口部に接地され、アウターリード２５といわれる外へ張り出したリードがＡＣＦといわれる異方性導電フィルム（図示せず）を介して基板上の配線１４に接続される（図１１（ｂ）参照）。
特開平６−４５７６３号公報 特開２００２−１８５１４５号公報 特開２００２−９２３６号公報 In addition, the third conventional example is an example in which, as shown in FIGS. 11 and 12, for example, packages in which only the semiconductor element 1 is mounted on a film carrier 4 are embedded in a wiring board one by one (for example, Patent Documents). 3).
Hereinafter, the manufacturing process of the third conventional example will be sequentially described. First, the package is called TCP (FIG. 11 (a)) and adopts a TAB (film carrier) mounting method, and is suitable for reducing the lead pitch and making the package thinner and smaller.
As a typical manufacturing method, a sheet-like adhesive (not shown) is bonded to a long resin film 26, and then punched with a mold or the like to provide a predetermined opening 26A.
Next, the copper foil 13 is bonded to the resin film 26 via a sheet-like adhesive, and the copper wiring 14 in which the leads 17 protrude from the opening 26A of the resin film 26 is formed using photolithography and an etching process. In this series of processes, alignment and conveyance are performed in holes called sprocket holes 12 formed at both ends of the resin film 26 (see FIG. 12).
Next, for example, the lead 7 plated with tin and the bump 6 (for example, gold bump) formed on the electrode 5 of the semiconductor element 1 (semiconductor chip) are bonded with a predetermined jig.
Next, the semiconductor element 1 (semiconductor chip) and a desired peripheral portion are resin-sealed with a potting resin 10 and punched with a predetermined mold or the like to produce a TCP (FIG. 11A).
In this conventional example, the package is built in the wiring board, and the TCP is grounded to the opening of the board (insulating resin 17) via an adhesive, and the lead extending outwardly called the outer lead 25 is the ACF. It connects to the wiring 14 on a board | substrate via the anisotropic conductive film (not shown) said (refer FIG.11 (b)).
JP-A-6-45763 JP 2002-185145 A JP 2002-9236 A

しかしながら、上記第１の従来例の場合、電子部品の周辺に配線１４を引き出し、上層の回路へ接続するため、配線基板の小型化が不可能となり、また、特に半導体素子１の場合は、半導体素子１上の電極５も狭ピッチ化が進んでいるため、従来の配線基板上の配線技術では、それに対応する配線の形成が困難であるといった問題があった。また、電子部品の種類毎に、基板上の電極の表面処理を変える必要があり、コスト高といった問題があった。
また、第２の従来例の場合、配線基板上へ接着剤等を介して電子部品を接着するため、配線基板の回路パターンと電子部品の位置精度が悪くなり、特に、半導体素子の場合は、上層回路パターンを形成する際、上層回路パターンと電子部品の電極位置ズレが発生すると、狭ピッチなため接続不良が発生するといった問題があった。
また、第３の従来例の場合、第２の従来例の問題を解決する方法の一つではあるが、電子部品の外周での接続となるため、第１の従来例の問題を解決できないといった問題があった。また、さらには、半導体素子とそれ以外の電子部品の実装方法が異なるため、コスト高といった問題があった。
また、第１、２及び３の従来例とも、一つずつ電子部品を配線基板内に内蔵するため、製造時間が長く、コストが高いといた問題があった。 However, in the case of the first conventional example, since the wiring 14 is drawn out to the periphery of the electronic component and connected to the upper layer circuit, it is impossible to reduce the size of the wiring board. Since the pitch of the electrodes 5 on the element 1 has also been reduced, there has been a problem that it is difficult to form the corresponding wiring by the conventional wiring technology on the wiring board. In addition, it is necessary to change the surface treatment of the electrodes on the substrate for each type of electronic component, resulting in a problem of high cost.
In the case of the second conventional example, since the electronic component is bonded onto the wiring board via an adhesive or the like, the position accuracy of the circuit pattern of the wiring board and the electronic component is deteriorated. When forming the upper layer circuit pattern, if the upper layer circuit pattern and the electrode position deviation of the electronic component occur, there is a problem that connection failure occurs due to the narrow pitch.
Further, in the case of the third conventional example, although it is one of the methods for solving the problem of the second conventional example, since the connection is made on the outer periphery of the electronic component, the problem of the first conventional example cannot be solved. There was a problem. Furthermore, since the mounting method of the semiconductor element and other electronic components is different, there is a problem of high cost.
Further, both the first, second, and third conventional examples have the problem that the manufacturing time is long and the cost is high because the electronic components are built in the wiring board one by one.

そこで本発明の目的は、配線基板の各層と電子部品との位置精度を向上させることにより、小型化を可能とし、さらに、一括で半導体素子、キャパシタ、抵抗体、及びインダクタ等の電子部品を配線基板内に内蔵させることより、製造時間及びコストを低減させることのできる配線基板及びその製造方法を提供することにある。   Accordingly, an object of the present invention is to enable miniaturization by improving the positional accuracy between each layer of the wiring board and the electronic component, and also to wire electronic components such as a semiconductor element, a capacitor, a resistor, and an inductor all together. It is an object of the present invention to provide a wiring board and a method for manufacturing the wiring board that can reduce manufacturing time and cost by being incorporated in the board.

上述の目的を達成するため、本発明の配線基板は、複数種類の電子部品が搭載される配線基板であって、少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有することを特徴とする。また、前記位置決め用の孔が搬送孔兼用のスプロケットホールであることを特徴とする。また、前記複数種類の電子部品は、半導体素子、キャパシタ、抵抗体、及びインダクタの少なくとも一種類を含むことを特徴とする。
また、前記電子部品の少なくとも一種類がフィルムキャリアの製造工程内で作り込まれていることを特徴とする。また、前記フィルムキャリアと電子部品とを電気的に接続するためのバンプがフィルムキャリアに形成されていることを特徴とする。また、前記フィルムキャリアと電子部品とを電気的に接続するためのバンプが電子部品に形成されていることを特徴とする。また、前記フィルムキャリアと電子部品を電気的に接続するためのリードが１つの接続に対して２つ以上フィルムキャリアに形成されていることを特徴とする。また、前記フィルムキャリアと電子部品を電気的に接続するためのバンプが１つの接続に対して２つ以上電子部品に形成されていることを特徴とする。 In order to achieve the above-described object, a wiring board of the present invention is a wiring board on which a plurality of types of electronic components are mounted, and at least one type of electronic component is mounted and a plurality of film carriers having positioning holes. It is characterized by having at least one layer arranged in a band shape including the module. Further, the positioning hole is a sprocket hole also serving as a transport hole. The plural types of electronic components include at least one of a semiconductor element, a capacitor, a resistor, and an inductor.
In addition, at least one of the electronic components is built in a film carrier manufacturing process. Further, the film carrier is formed with bumps for electrically connecting the film carrier and the electronic component. The electronic component may further include a bump for electrically connecting the film carrier and the electronic component. In addition, two or more leads for electrically connecting the film carrier and the electronic component are formed on the film carrier for one connection. Also, two or more bumps for electrically connecting the film carrier and the electronic component are formed on the electronic component for one connection.

また本発明は、複数種類の電子部品が搭載される配線基板の製造方法であって、位置決め用の孔が設けられた長尺フィルムキャリアを作製する工程と、前記長尺フィルムキャリアに電子部品をＴＡＢ実装する工程と、前記電子部品がＴＡＢ実装された長尺フィルムキャリアの両面にプリプレグを介して配線用の金属箔を張り合わせる工程とを有し、少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成することを特徴とする。また、前記長尺フィルムキャリアを複数並べた状態で、並列に前記プリプレグを介して金属箔を張り合わせる工程を含むことを特徴とする。   The present invention is also a method of manufacturing a wiring board on which a plurality of types of electronic components are mounted, the step of producing a long film carrier provided with positioning holes, and the electronic component on the long film carrier. A TAB mounting step, and a step of attaching a metal foil for wiring to both sides of the long film carrier on which the electronic component is TAB mounted via a prepreg, and at least one type of electronic component is mounted and positioned A film carrier having a hole for forming a wiring board having at least one layer arranged in a band shape including a plurality of modules. Further, the method includes a step of bonding metal foils in parallel through the prepreg in a state where a plurality of the long film carriers are arranged.

また本発明は、複数種類の電子部品が搭載される配線基板の製造方法であって、長尺金属板の両面に、ポジ型フォトレジストをロールコートし、露光現像を行うフォトリソグラフィ法、及び金属を腐食させるエッチング法により、前記電子部品が実装される部分だけのリードと位置決め用の孔が設けられた長尺フィルムキャリアを作製する工程と、前記長尺フィルムキャリアに電子部品をＴＡＢ実装する工程と、前記電子部品がＴＡＢ実装された長尺フィルムキャリアの実装側にプリプレグを介して基板を張り合わせる工程とを有し、少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成することを特徴とする。   The present invention also relates to a method of manufacturing a wiring board on which a plurality of types of electronic components are mounted, and a photolithography method in which a positive photoresist is roll-coated on both sides of a long metal plate, and exposure development is performed, and a metal A step of producing a long film carrier provided with a lead and a positioning hole only for a portion where the electronic component is mounted, and a step of mounting the electronic component on the long film carrier by TAB etching And a step of attaching a substrate via a prepreg to the mounting side of the long film carrier on which the electronic component is TAB mounted, and a film carrier on which at least one kind of electronic component is mounted and having a positioning hole A wiring board having at least one layer arranged in a band shape including a plurality of modules is formed.

また本発明は、複数種類の電子部品が搭載される配線基板の製造方法であって、第１面に金属箔を張り付けた樹脂基板よりなるフィルムキャリアの第２面に接着剤を塗布する工程と、前記フィルムキャリアの所望の位置に電子部品が実装される開口部、及び位置決め用の孔を形成する工程と、前記フィルムキャリアの第２面に接着剤を介して金属箔を接着する工程と、前記フィルムキャリアの金属箔を用いて配線を形成する工程と、前記フィルムキャリアに電子部品をＴＡＢ実装する工程と、前記フィルムキャリアに上層膜の積層を行う工程とを有し、少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成することを特徴とする。   The present invention is also a method of manufacturing a wiring board on which a plurality of types of electronic components are mounted, the step of applying an adhesive to a second surface of a film carrier made of a resin substrate having a metal foil attached to the first surface; A step of forming an opening for mounting an electronic component at a desired position of the film carrier and a positioning hole; a step of bonding a metal foil to the second surface of the film carrier via an adhesive; A step of forming wiring using the metal foil of the film carrier, a step of TAB mounting an electronic component on the film carrier, and a step of laminating an upper film on the film carrier, and at least one kind of electronic A film carrier having components mounted thereon and a film carrier having positioning holes is formed to form a wiring board having at least one layer arranged in a strip shape including a plurality of modules. That.

本発明の配線基板及びその製造方法によれば、半導体素子、キャパシタ、抵抗、及びインダクタ等の電子部品が内蔵される配線基板において、各層の積層の際に、電子部品が実装されているフィルムキャリアのスプロケットホール等により位置合せを行うことで、配線基板の各層と電子部品との位置精度を向上させることにより、また、技術的に確立されたＩＬＢ接続技術を用いることにより、半導体素子の狭ピッチ化への対応、接続の信頼性確保、さらには、上層に最短距離で配線を引き出しが可能となり、小型化を実現することができる効果がある。さらに、一括で半導体素子、キャパシタ、抵抗、及びインダクタ等の電子部品を配線基板内に内蔵させることより、製造時間及びコストを低減させることが可能となる。   According to the wiring board and the manufacturing method thereof of the present invention, in the wiring board in which electronic components such as a semiconductor element, a capacitor, a resistor, and an inductor are built, the film carrier on which the electronic components are mounted when each layer is laminated By aligning with sprocket holes, etc., it is possible to improve the positional accuracy between each layer of the wiring board and the electronic components, and by using the technically established ILB connection technology, the narrow pitch of the semiconductor element As a result, it is possible to reduce the size of the upper layer by ensuring the reliability of connection, securing the connection reliability, and drawing out the wiring to the upper layer at the shortest distance. Furthermore, since electronic components such as a semiconductor element, a capacitor, a resistor, and an inductor are integrated in the wiring board in a lump, manufacturing time and cost can be reduced.

以下、本発明を実施するための最良の形態を詳細に説明する。
図１〜図８は本発明の実施の形態による配線基板の各具体例を示す断面図及び平面図である。
本実施の形態による配線基板は、まず、半導体素子１、キャパシタ２、抵抗３、及びインダクタ等の少なくとも一種類がフィルムキャリア４（図１（ａ）参照）に実装されており、そのフィルムキャリアが少なくとも１層含まれた配線基板（図１（ｂ）参照）である。
なお、フィルムキャリア４と電子部品との接合方法は、電子部品の電極５上に金等のバンプ６を形成して接合する方法（図２（ａ）参照）とフィルムキャリアのリード７上に金等のバンプ６を形成し接合する方法（図２（ｂ）参照）がある。
また、キャパシタ、抵抗、及びインダクタ等の電子部品にバンプ６を形成する際、バンプ６を複数形成し、接合することでリード７との接着強度が上がり、接続信頼性が向上する。リード７には、接合のため、金、銀、錫等のめっきを施し、バンプ６としては、一般に金が用いられるが、接合用の金属種には様々な組み合わせを取ることができることは公知である。 Hereinafter, the best mode for carrying out the present invention will be described in detail.
1 to 8 are a sectional view and a plan view showing specific examples of the wiring board according to the embodiment of the present invention.
In the wiring board according to the present embodiment, first, at least one kind of semiconductor element 1, capacitor 2, resistor 3, inductor, and the like is mounted on a film carrier 4 (see FIG. 1A). A wiring board (see FIG. 1B) including at least one layer.
The film carrier 4 and the electronic component are joined by forming a bump 6 such as gold on the electrode 5 of the electronic component (see FIG. 2A) and gold on the lead 7 of the film carrier. There is a method (see FIG. 2B) for forming and bonding the bumps 6 and the like.
Further, when the bumps 6 are formed on the electronic components such as capacitors, resistors, and inductors, a plurality of bumps 6 are formed and bonded to increase the bonding strength with the leads 7 and improve the connection reliability. The lead 7 is plated with gold, silver, tin or the like for bonding, and gold is generally used as the bump 6, but it is known that various combinations can be used for the metal species for bonding. is there.

また、本実施の形態による配線基板は、半導体素子１、キャパシタ２、抵抗３、及びインダクタ等の電子部品が内蔵される配線基板において、キャパシタ２、抵抗３、及びインダクタ等の少なくとも一種類がフィルムキャリア４（図３参照）の製造工程内で作り込まれている配線基板である。なお、キャパシタ２及び抵抗３は、印刷や薄膜フォトリソグラフィプロセス等で形成され、インダクタはフィルムキャリア４上の配線にて渦上の所謂スパイダルコイルを形成するのが一般的であるが、本発明では、その構成は問わないものとする。
また、本実施の形態による配線基板は、半導体素子１、キャパシタ２、抵抗３、及びインダクタ等の電子部品が内蔵される配線基板において、キャパシタ２、抵抗３、及びインダクタ等の少なくとも一種類の電子部品がフィルムキャリア４の製造工程内で作り込まれたものとフィルムキャリアに実装されたものであり、要求精度が低いものは造り込み、要求精度が高いものはチップ部品をフィルムキャリア４に実装することが望ましい（図４参照）。 In addition, the wiring board according to the present embodiment is a wiring board in which electronic components such as the semiconductor element 1, the capacitor 2, the resistor 3, and the inductor are incorporated, and at least one of the capacitor 2, the resistor 3, the inductor, and the like is a film. This is a wiring board built in the manufacturing process of the carrier 4 (see FIG. 3). Note that the capacitor 2 and the resistor 3 are formed by printing, a thin film photolithography process, or the like, and the inductor generally forms a so-called spider coil on a vortex by wiring on the film carrier 4, but in the present invention, The configuration is not limited.
Further, the wiring board according to the present embodiment is a wiring board in which electronic components such as the semiconductor element 1, the capacitor 2, the resistor 3, and the inductor are built, and at least one kind of electrons such as the capacitor 2, the resistor 3, and the inductor. The parts are built in the manufacturing process of the film carrier 4 and are mounted on the film carrier. The parts with low required accuracy are built in, and those with high required precision are mounted on the film carrier 4 with chip parts. It is desirable (see FIG. 4).

また、本実施の形態による配線基板に用いられるフィルムキャリア４の構成としては、金属の１層タイプ、金属と樹脂フィルムとの２層タイプ（接着剤を介して貼り合わされているものでも良い）、樹脂フィルムの両面に金属がある両面タイプ、金属と樹脂フィルムとが交互に複数積層された多層タイプ（図８参照）がある。金属としては、一般に銅が使用され、樹脂フィルムとしては、ＰＥＴ、ポリイミド等のフレキシブルタイプやガラスクロス入りエポキシ樹脂等のリジッドタイプを用いることができ、厚さは電子部品の構成や回路設計により決定されるが、２５μｍから３００μｍ程度が用いられる。
また、フィルムキャリア４における電子部品の実装部は、図２（ａ）及び図５(ａ)、（ｂ）に示すように、張り出した形のリードでも、接続部９以外が樹脂１０で覆われた構造でも良く、各電子部品に対して様々な構成が簡単に適用できる。さらに、フィルムキャリア以外の配線基板の絶縁材に用いられる材料はフレキシブル及びリジッドタイプの材料が自由に選択できる。 Moreover, as a structure of the film carrier 4 used for the wiring board by this Embodiment, the 1 layer type of a metal, the 2 layer type of a metal and a resin film (may be bonded together with an adhesive), There are a double-sided type with metal on both sides of the resin film and a multi-layer type in which a plurality of metals and resin films are alternately laminated (see FIG. 8). As the metal, copper is generally used, and as the resin film, a flexible type such as PET or polyimide, or a rigid type such as epoxy resin with glass cloth can be used, and the thickness is determined by the configuration of electronic components and circuit design. However, about 25 μm to 300 μm is used.
Further, as shown in FIGS. 2A, 5A, and 5B, the mounting part of the electronic component in the film carrier 4 is covered with the resin 10 except for the connecting part 9 even in the protruding lead. Various structures can be easily applied to each electronic component. Furthermore, a flexible or rigid type material can be freely selected as the material used for the insulating material of the wiring board other than the film carrier.

以下、図６を参照して本発明の実施例１を具体的に説明する。なお、図６において、（ａ）はフィルムキャリアの断面図、（ｂ）は電子部品を実装した後の断面図、（ｃ）は上層積層前の断面図、（ｄ）は上層積層後の断面図である。
まず、１５０ｍｍ幅、２５μｍ厚の熱硬化性長尺ポリイミドフィルム１１上に２μｍ厚の熱可塑性ポリイミド接着剤（図示せず）を所定温度でラミネートした後、所望の金型で電子部品が実装される部分及び位置決め孔や搬送孔となるスプロケットホール１２（スプロケットホールでなく、位置決めになる孔だけでも良い）をパンチング加工する。
次いで、１２μｍ厚の銅箔１３を熱可塑性ポリイミド接着剤（図示せず）を介して熱硬化性長尺ポリイミドフィルム１１に所定温度でラミネートし、部材を作製する。
次いで、部材両面にフォトレジストをロールコートし、露光現像を行うフォトリソグラフィ及び銅を腐食させるエッチング法により、所望の配線１４を形成する（図６（ａ）参照）。 Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to FIG. 6A is a cross-sectional view of the film carrier, FIG. 6B is a cross-sectional view after mounting the electronic component, FIG. 6C is a cross-sectional view before the upper layer lamination, and FIG. 6D is a cross-section after the upper layer lamination. FIG.
First, a thermoplastic polyimide adhesive (not shown) having a thickness of 2 μm is laminated on a thermosetting long polyimide film 11 having a width of 150 mm and a thickness of 25 μm at a predetermined temperature, and then an electronic component is mounted with a desired mold. A sprocket hole 12 (not a sprocket hole but only a positioning hole) may be punched to be a part, a positioning hole or a transport hole.
Next, a copper foil 13 having a thickness of 12 μm is laminated on the thermosetting long polyimide film 11 at a predetermined temperature via a thermoplastic polyimide adhesive (not shown) to produce a member.
Next, a photoresist is roll-coated on both surfaces of the member, and a desired wiring 14 is formed by photolithography for exposure and development and an etching method for corroding copper (see FIG. 6A).

次いで、フォトレジストを剥離後、配線１４の表面に無電解錫めっきを行う。なお、錫めっき厚は１μｍ程度とする。ここで、錫めっきを行ったのは、電子部品との接合性を確保するためであり、錫めっき以外には、金めっき、銀めっき、ニッケルめっき等が挙げられる。また、めっきを行う前後に、配線１４の一部に積層材と同種類の保護膜、例えば、エポキシ系樹脂を設けても良い。
次いで、半導体素子１、キャパシタ２、抵抗３、及びインダクタ等のチップ部品の電極５上にボールボンディング装置を用いて金バンプ６を形成する。なお、リード７と電極５を直接接続すると半導体素子表面にリードが接触し、ショートが発生したり、回路を破壊してしまう可能性があるため、通常、突起状のバンプ６を設ける。バンプ６の種類は、リード７に施されためっきの種類により、選択されるが、一般的には金が好ましい。また、バンプ６の形成方法には、ボールボンディング装置を用いる他に、めっきによる形成方法等もある。また、リード７にバンプ６を形成し、電子部品との接続を図る方法もある。 Next, after removing the photoresist, electroless tin plating is performed on the surface of the wiring 14. The tin plating thickness is about 1 μm. Here, the tin plating was performed in order to ensure the bondability with the electronic component, and other than the tin plating, gold plating, silver plating, nickel plating, and the like can be given. Further, a protective film of the same type as the laminated material, for example, an epoxy resin may be provided on a part of the wiring 14 before and after plating.
Next, a gold bump 6 is formed on the electrode 5 of the chip component such as the semiconductor element 1, the capacitor 2, the resistor 3, and the inductor by using a ball bonding apparatus. Note that when the lead 7 and the electrode 5 are directly connected, the lead comes into contact with the surface of the semiconductor element, which may cause a short circuit or break the circuit. Therefore, the protruding bump 6 is usually provided. The type of bump 6 is selected depending on the type of plating applied to the lead 7, but gold is generally preferable. In addition to using a ball bonding apparatus, bump 6 may be formed by plating or the like. There is also a method in which bumps 6 are formed on the leads 7 for connection to electronic components.

次いで、一般に用いられているＩＬＢ（インナーリードボンディング）装置のボンディングステージ上に設置した電子部品の電極５上のバンプ６に対し、フィルムキャリヤ４の所望のリード７をボンディングツールを用いて、加熱加圧することで、電子部品の電極５とリード７の接続を行う（図６（ｂ）参照）。
ここで、シングルボンディングと言われるバンプ６とリード７とを一つずつ接続する方法もある。 Next, the desired lead 7 of the film carrier 4 is heated with a bonding tool against the bump 6 on the electrode 5 of the electronic component placed on the bonding stage of a generally used ILB (inner lead bonding) apparatus. By applying pressure, the electrode 5 of the electronic component and the lead 7 are connected (see FIG. 6B).
Here, there is also a method of connecting the bump 6 and the lead 7 one by one, which is called single bonding.

次いで、電子部品（特に半導体素子）やリードを湿気や汚染から保護したり、接続の信頼性を確保するため、一般にポッティングと言われる液状エポキシ系樹脂１０を所望部に滴下し、熱硬化させることで封止する。ここでの封止は、工程中での信頼性を十分得るためであり、場合によっては封止無しでも良い。
次いで、プリント配線基板の途中工程で得られた基板であり、電子部品が内蔵される溝１５が形成された基板上に、例えば、電子部品が内蔵される部分を開口したガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、電子部品が実装されたフィルムキャリア４を位置させ、その上に、ガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、銅箔１３を位置させ（図６（ｃ）参照）、最高加熱温度１７５°Ｃ、２時間程度で加熱プレスする（図６（ｄ）参照））。 Next, in order to protect electronic components (especially semiconductor elements) and leads from moisture and contamination, and to ensure connection reliability, a liquid epoxy resin 10 generally called potting is dropped onto a desired portion and thermally cured. Seal with. The sealing here is for obtaining sufficient reliability in the process, and in some cases, the sealing may be omitted.
Next, a glass cloth-containing epoxy resin, for example, in which a portion in which an electronic component is incorporated is opened on a substrate in which a groove 15 in which an electronic component is incorporated is formed, which is a substrate obtained in an intermediate process of a printed wiring board. The film carrier 4 on which electronic components are mounted is positioned through the prepreg 16, and the copper foil 13 is positioned on the film carrier 4 via the prepreg 16, which is an epoxy resin containing glass cloth (see FIG. 6C). ), And heat-pressed at a maximum heating temperature of 175 ° C. for about 2 hours (see FIG. 6D)).

次いで、残された一連の配線基板の製造工程を行うことで、本実施の形態による配線基板を完成する。なお、上下層配線とフィルムキャリア上の配線との接続は、一般的な接続が利用でき、例えば、ＹＡＧレーザーや炭酸ガスレーザー等により穴を形成し、めっきによる接続や導電性ペーストを印刷する接続等の方法を用いることができる。一例として、図１（ｂ）に、めっきにより接続を行った配線基板を示す。また、上記において、プリント配線基板の途中工程で得られた基板は、３４０×４１０ｍｍのサイズであり、電子部品が実装されたフィルムキャリアのサイズを１５０×４１０ｍｍに切り出し、フィルムキャリアを２列並べ、位置合せ孔を用い位置合せを行い、積層する。   Next, the wiring board according to the present embodiment is completed by performing a series of remaining wiring board manufacturing steps. The connection between the upper and lower layer wiring and the wiring on the film carrier can be a general connection. For example, a hole is formed by a YAG laser, a carbon dioxide gas laser, etc., and a connection by plating or a conductive paste is printed. Etc. can be used. As an example, FIG. 1B shows a wiring board connected by plating. In the above, the substrate obtained in the intermediate process of the printed wiring board is 340 × 410 mm in size, cut out the size of the film carrier on which the electronic component is mounted to 150 × 410 mm, and arrange the film carriers in two rows, Alignment is performed using alignment holes, and lamination is performed.

以下、図７を参照して本発明の実施例２を具体的に説明する。
まず、１５０ｍｍ幅、２５μｍ厚の熱硬化性長尺ポリイミドフィルム１１Ａの両面に２μｍ厚の熱可塑性ポリイミド接着剤（図示せず）を所定温度でラミネートした後、１８μｍ厚の銅箔１３を熱可塑性ポリイミド接着剤を介して熱硬化性長尺ポリイミドフィルム１１Ａの片側に所定温度でラミネートし、次いで、所望の金型で電子部品が実装される部分及び位置決め孔や搬送孔となるスプロケットホール１２（スプロケットホールでなく、位置決めになる孔だけでも良い）のパンチング加工を行い、第１の部材を作製する。
次いで、１４２ｍｍ幅、２５μｍ厚の熱硬化性長尺ポリイミドフィルム１１Ｂの上に２μｍ厚の熱可塑性ポリイミド接着剤（図示せず）を所定温度でラミネートした後、１２μｍ厚の銅箔１３を熱可塑性ポリイミド接着剤を介して熱硬化性長尺ポリイミドフィルム１１Ｂに所定温度でラミネートし、第２の部材を作製する。
次いで、第１の部材に第２の部材を所定温度でラミネートすることで第３の部材を作製する。次いで、第１の部材側から、炭酸ガスレーザーにより、電子部品の電極５上のバンプ６が接続される部分のポリイミドを除去し、銅を露出させた。次いで、第２の部材側から、ＹＡＧレーザーにより、両面の接続となるビア１８穴を開け、第１部材側の銅を露出させた。次に、第１の部材側にレジスト（図示せず）をロールコートし、無電解銅めっき及び電解銅めっきにより、ビア１８を形成し、両面を電気的に接続する（図７（ａ）参照）。 Hereinafter, the second embodiment of the present invention will be described in detail with reference to FIG.
First, a 2 μm-thick thermoplastic polyimide adhesive (not shown) is laminated on both sides of a 150 mm wide, 25 μm-thick thermosetting long polyimide film 11A, and then 18 μm-thick copper foil 13 is thermoplastic polyimide. Lamination is performed at a predetermined temperature on one side of the thermosetting long polyimide film 11A through an adhesive, and then a sprocket hole 12 (sprocket hole 12 serving as a part where electronic components are mounted in a desired mold and a positioning hole or a conveyance hole. The first member is manufactured by performing punching processing of only the hole to be positioned.
Next, a thermoplastic polyimide adhesive (not shown) having a thickness of 2 μm is laminated at a predetermined temperature on a thermosetting long polyimide film 11B having a width of 142 mm and a thickness of 25 μm, and then a copper foil 13 having a thickness of 12 μm is thermoplastic polyimide. A second member is produced by laminating the thermosetting long polyimide film 11B through an adhesive at a predetermined temperature.
Next, a third member is produced by laminating the second member on the first member at a predetermined temperature. Next, from the first member side, the portion of the polyimide to which the bump 6 on the electrode 5 of the electronic component was connected was removed by a carbon dioxide laser to expose copper. Next, vias 18 for connecting both sides were opened from the second member side by a YAG laser to expose the copper on the first member side. Next, a resist (not shown) is roll-coated on the first member side, vias 18 are formed by electroless copper plating and electrolytic copper plating, and both surfaces are electrically connected (see FIG. 7A). ).

次いで、第２の部材側にフォトレジストをロールコートし、露光現像を行うフォトリソグラフィ及び銅を腐食させるエッチング法により、所望の配線１４を形成する。次いで、レジスト及びフォトレジストを剥離後、配線１４の表面に無電解錫めっきを行った。錫めっき厚は１μｍ程度である。次いで、半導体素子１、キャパシタ２、抵抗（図示せず）及びインダクタ（図示せず）等のチップ部品の電極５上にボールボンディング装置を用い、金バンプ６を形成する。
次いで、一般に用いられているＩＬＢ（インナーリードボンディング）装置のボンディングステージ上に設置した電子部品の電極５上のバンプ６に対して、非導電性接着剤２３（NCF（Non-conductive Film）やNCP（Non-conductive Paste））を介して、フィルムキャリヤ４の所望のリード７をボンディングツールを用いて、加熱加圧することで、電子部品の電極５とリード７の接続を行う。なお、ＮＣＰの場合は、実装後でも良い（図７（ｂ）参照）。
次いで、電子部品が実装されたフィルムキャリア４の両面に、例えば、ガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、銅箔１３を位置させ、最高加熱温度１７５°Ｃ、２時間程度で加熱プレスする（図７（ｃ）参照）。
次いで、残された一連の配線基板の製造工程を行うことで、本実施の形態による配線基板を作製する。 Next, a photoresist is roll-coated on the second member side, and a desired wiring 14 is formed by photolithography for exposure and development and an etching method for corroding copper. Next, after removing the resist and the photoresist, electroless tin plating was performed on the surface of the wiring 14. The tin plating thickness is about 1 μm. Next, a gold bump 6 is formed on the electrode 5 of a chip component such as the semiconductor element 1, the capacitor 2, a resistor (not shown), and an inductor (not shown) using a ball bonding apparatus.
Next, a non-conductive adhesive 23 (NCF (Non-conductive Film) or NCP is applied to the bumps 6 on the electrode 5 of the electronic component installed on the bonding stage of a generally used ILB (inner lead bonding) apparatus. The desired lead 7 of the film carrier 4 is heated and pressurized using a bonding tool via (Non-conductive Paste)), thereby connecting the electrode 5 of the electronic component and the lead 7. In the case of NCP, it may be after mounting (see FIG. 7B).
Next, the copper foil 13 is positioned on both surfaces of the film carrier 4 on which the electronic components are mounted, for example, via a prepreg 16 that is an epoxy resin containing glass cloth, and is heated and pressed at a maximum heating temperature of 175 ° C. for about 2 hours. (See FIG. 7C).
Next, the wiring board according to the present embodiment is manufactured by performing a series of remaining wiring board manufacturing steps.

以下、図４を参照して本発明の実施例３を具体的に説明する。
まず、１５０ｍｍ幅、２５μｍ厚の熱硬化性長尺ポリイミドフィルム１１上に２μｍ厚の熱可塑性ポリイミド接着剤を所定温度でラミネートした後、所望の金型で電子部品が実装される部分及び位置決め孔や搬送孔となるスプロケットホール１２（スプロケットホールでなく、位置決めになる孔だけでも良い）をパンチング加工する。
次いで、１２μｍ厚の銅箔１３を熱可塑性ポリイミド接着剤を介して熱硬化性長尺ポリイミドフィルム１１に所定温度でラミネートし、部材を作製する。次いで、部材両面にフォトレジストをロールコートし、露光現像を行うフォトリソグラフィ及び銅を腐食させるエッチング法により、所望の配線１４及び印刷キャパシタ８の下電極１９を形成し、次いで、フォトレジストを剥離する。次いで、エポキシ系樹脂にチタン酸バリウム粒子を混入した誘電体ペーストをスクリーン印刷により、下電極１９上に印刷し、所定の温度で硬化させた。
次いで、誘電体２０及び引き出し電極２１上に、銅ペーストを用い、同じくスクリーン印刷により、上電極２２を印刷し、所定の温度で硬化させることで、印刷キャパシタ８を形成する。なお、ここで、要求精度の低いキャパシタに対して印刷キャパシタ８を適用する。次いで、配線の表面に無電解錫めっきを行った。錫めっき厚は１μｍ程度である。次いで、半導体素子、キャパシタ（要求精度の高いキャパシタ）、抵抗、及びインダクタ等のチップ部品の電極５上にボールボンディング装置を用い、金バンプ６を形成する。 Hereinafter, Example 3 of the present invention will be described in detail with reference to FIG.
First, after laminating a 2 μm-thick thermoplastic polyimide adhesive on a thermosetting long polyimide film 11 having a width of 150 mm and a thickness of 25 μm at a predetermined temperature, a part where electronic parts are mounted with a desired mold, positioning holes, A punching process is performed on a sprocket hole 12 (not only a sprocket hole but also a positioning hole) that becomes a transport hole.
Next, a copper foil 13 having a thickness of 12 μm is laminated on the thermosetting long polyimide film 11 at a predetermined temperature via a thermoplastic polyimide adhesive to produce a member. Next, a photoresist is roll-coated on both surfaces of the member, and the desired wiring 14 and the lower electrode 19 of the printed capacitor 8 are formed by photolithography for exposure and development and an etching method for corroding copper, and then the photoresist is peeled off. . Next, a dielectric paste in which barium titanate particles were mixed in an epoxy resin was printed on the lower electrode 19 by screen printing and cured at a predetermined temperature.
Next, the upper electrode 22 is printed on the dielectric 20 and the extraction electrode 21 by using a copper paste and also by screen printing, and is cured at a predetermined temperature, thereby forming the printed capacitor 8. Here, the printed capacitor 8 is applied to a capacitor with low required accuracy. Next, electroless tin plating was performed on the surface of the wiring. The tin plating thickness is about 1 μm. Next, a gold bump 6 is formed on the electrode 5 of a chip component such as a semiconductor element, a capacitor (capacitor with high required accuracy), a resistor, and an inductor using a ball bonding apparatus.

次いで、一般に用いられているＩＬＢ（インナーリードボンディング）装置のボンディングステージ上に設置した電子部品の電極５上のバンプ６に対して、フィルムキャリヤ４所望のリード７をボンディングツールを用いて、加熱加圧することで、電子部品の電極５とリード７の接続を行った。次いで、電子部品（特に半導体素子）やリードを湿気や汚染から保護や接続信頼性を確保するため、一般にポッティングと言われる液状エポキシ系樹脂１０を所望部に滴下し、熱硬化させることで封止する。
次いで、プリント配線基板の途中工程で得られた基板であり、電子部品が内蔵される溝が形成された基板上に、例えば、電子部品が内蔵される部分を開口したガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、電子部品が実装されたフィルムキャリアを位置させ、その上に、ガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、銅箔を位置させ、最高加熱温度１７５°Ｃ、２時間程度で加熱プレスする。
次いで、残された一連の配線基板の製造工程を行う事で、本発明の配線基板を作製する。 Next, the desired lead 7 of the film carrier 4 is heated with a bonding tool against the bump 6 on the electrode 5 of the electronic component placed on the bonding stage of a generally used ILB (inner lead bonding) apparatus. The electrode 5 of the electronic component and the lead 7 were connected by pressing. Next, in order to protect electronic components (especially semiconductor elements) and leads from moisture and contamination and to ensure connection reliability, a liquid epoxy resin 10 generally referred to as potting is dropped onto a desired portion and sealed by thermosetting. To do.
Next, it is a substrate obtained in the middle of the printed wiring board, and on the substrate in which the groove in which the electronic component is incorporated is formed, for example, with an epoxy resin containing glass cloth having an opening in which the electronic component is incorporated A film carrier on which electronic components are mounted is positioned through a certain prepreg 16, and a copper foil is positioned on the prepreg 16, which is an epoxy resin containing glass cloth, at a maximum heating temperature of 175 ° C. for 2 hours. Heat-press at a degree.
Next, the wiring board of the present invention is manufactured by performing a series of remaining wiring board manufacturing steps.

以下、本発明の実施例４を具体的に説明する。
まず、１５０ｍｍ幅、３５μｍ厚の長尺銅箔の両面に、ポジ型フォトレジストをロールコートし、露光現像を行うフォトリソグラフィ及び銅を腐食させるエッチング法により、電子部品が実装される部分だけのリード７と位置決め孔や搬送孔となるスプロケットホール１２（スプロケットホールでなく、位置決めになる孔だけでも良い）を形成する。
次いで、リード７の部分だけに光を照射し、現像を行い、リード７の表面に無電解錫めっきを行った。錫めっき厚は１μｍ程度である。次いで、フォトレジストを剥離する。次いで、半導体素子１、キャパシタ２、抵抗３、及びインダクタ等のチップ部品の電極５上にボールボンディング装置を用い、金バンプ６を形成する。
次いで、一般に用いられているＩＬＢ（インナーリードボンディング）装置のボンディングステージ上に設置した電子部品の電極５上のバンプ６に対して、フィルムキャリヤ４所望のリード７をボンディングツールを用いて、加熱加圧することで、電子部品の電極５とリード７の接続を行う。 Example 4 of the present invention will be specifically described below.
First, a positive photoresist is roll-coated on both sides of a long copper foil with a width of 150 mm and a thickness of 35 μm, and the lead only on the portion where the electronic component is mounted by photolithography for exposure and development and an etching method for corroding copper 7 and a sprocket hole 12 (not only a sprocket hole but also a hole for positioning) to be a positioning hole and a transport hole are formed.
Subsequently, only the lead 7 portion was irradiated with light, developed, and electroless tin plating was performed on the surface of the lead 7. The tin plating thickness is about 1 μm. Next, the photoresist is peeled off. Next, a gold bump 6 is formed on the electrode 5 of the chip component such as the semiconductor element 1, the capacitor 2, the resistor 3, and the inductor by using a ball bonding apparatus.
Next, the desired lead 7 of the film carrier 4 is heated with a bonding tool against the bump 6 on the electrode 5 of the electronic component placed on the bonding stage of a generally used ILB (inner lead bonding) apparatus. By applying pressure, the electrode 5 of the electronic component and the lead 7 are connected.

次いで、電子部品（特に半導体素子）やリードを湿気や汚染から保護や接続信頼性を確保するため、一般にポッティングと言われる液状エポキシ系樹脂を所望部に滴下し、熱硬化させることで封止する。
次いで、プリント配線基板の途中工程で得られた基板であり、電子部品が内蔵される溝１５が形成された基板上に、例えば、電子部品が内蔵される部分を開口したガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、電子部品が実装されたフィルムキャリア４を位置させ、基板の他方面には、ガラスクロス入りエポキシ系樹脂であるプリプレグ１６を介し、銅箔を位置させ、最高加熱温度１７５°Ｃ、２時間程度で加熱プレスする。ここで、一般的なガラス不織布出なければ、電子部品が内蔵される溝１５が形成されていない基板でも良く、開口されていないプリプレグ１６でも良い。
次いで、残された一連の配線基板の製造工程を行うことで、本実施の形態の配線基板を作製する。 Next, in order to protect electronic components (especially semiconductor elements) and leads from moisture and contamination and to ensure connection reliability, a liquid epoxy resin generally referred to as potting is dropped onto a desired portion and sealed by thermosetting. .
Next, a glass cloth-containing epoxy resin, for example, in which a portion in which an electronic component is incorporated is opened on a substrate in which a groove 15 in which an electronic component is incorporated is formed, which is a substrate obtained in an intermediate process of a printed wiring board. The film carrier 4 on which electronic components are mounted is positioned via the prepreg 16, and the copper foil is positioned on the other surface of the substrate via the prepreg 16, which is an epoxy resin containing glass cloth, and the maximum heating temperature 175 C. Heat press in about 2 hours. Here, as long as a general glass nonwoven fabric does not come out, a substrate in which the groove 15 in which the electronic component is incorporated is not formed or a prepreg 16 that is not opened may be used.
Next, the wiring substrate of this embodiment is manufactured by performing a series of manufacturing steps of the remaining wiring substrate.

以下、本発明の実施例５を具体的に説明する。
まず、配線基板の製造時に用いられる例えば、リジッド基板である、基板厚０.２ｍｍのエポキシ系片面銅張り基板を用い、樹脂表面に例えば、エポキシ系熱硬化型接着剤を形成する。ここで、両面銅張り基板を用いるときは、片側の銅箔をエッチング等で除去する。
次いで、所望の位置に電子部品が実装される開口部、及び位置決め孔や搬送孔となるスプロケットホールや位置決めになる孔を形成した後、接着剤を介して、銅箔を接着する。次いで、所望の位置に、ドリルやレーザー等で穴を開け、無電解銅めっき及び電解銅めっき等を行い、スルーホールまたはビアを形成する。
次いで、基板表面にフォトレジストを形成し、露光現像を行った後、塩化第２銅液等でエッチングを行い、配線を形成する。次いで、配線に例えば無電解Ｓｎめっきを施し、リジッド基板からなるフィルムキャリアを作製する。
次いで、フィルムキャリアに、例えば、金バンプ等が形成された半導体素子やキャパシタ等の電子部品をＴＡＢ実装する。ここで、金バンプは、フィルムキャリアのリード側に形成しても良い。
次いで、上層積層等、残された一連の配線基板の製造工程を行う事で、本発明の配線基板を作製する。 Example 5 of the present invention will be specifically described below.
First, for example, an epoxy-based thermosetting adhesive is formed on the resin surface using, for example, a rigid substrate, an epoxy-based single-sided copper-clad substrate having a substrate thickness of 0.2 mm. Here, when using a double-sided copper-clad substrate, the copper foil on one side is removed by etching or the like.
Next, after forming an opening where an electronic component is mounted at a desired position, a sprocket hole serving as a positioning hole or a transport hole, and a hole serving as a positioning hole, a copper foil is bonded via an adhesive. Next, a hole is drilled at a desired position with a drill or a laser, and electroless copper plating and electrolytic copper plating are performed to form a through hole or a via.
Next, a photoresist is formed on the substrate surface, and after exposure and development, etching is performed with a cupric chloride solution or the like to form wiring. Next, for example, electroless Sn plating is applied to the wiring to produce a film carrier made of a rigid substrate.
Next, on the film carrier, for example, electronic components such as semiconductor elements and capacitors on which gold bumps are formed are TAB-mounted. Here, the gold bumps may be formed on the lead side of the film carrier.
Next, the wiring board of the present invention is manufactured by performing a series of remaining wiring board manufacturing processes such as upper layer lamination.

以上のような本発明の配線基板の製造方法は、特に、携帯機器等の配線基板の小型化させ、電気的特性を向上させるといった、受動素子を内蔵する配線基板の製造に利用でき、特に、積層の際、電子部品が実装されているフィルムキャリアのスプロケットホール等により位置合せを行うことで、配線基板の各層と電子部品との位置精度を向上させる事により、また、上層に最短距離で配線を引き出せるので、より小型化を可能とし、さらに、一括で半導体素子、キャパシタ、抵抗体及びインダクタ等の電子部品を配線基板内に内蔵させることより、製造時間及びコストを低減させることが可能となる。   The method for manufacturing a wiring board of the present invention as described above can be used for manufacturing a wiring board with a built-in passive element, in particular, reducing the size of the wiring board of a portable device or the like and improving the electrical characteristics. When stacking, alignment is performed by sprocket holes on the film carrier on which electronic components are mounted, improving the positional accuracy between each layer of the wiring board and the electronic components, and wiring to the upper layer at the shortest distance Therefore, it is possible to further reduce the size, and further, it is possible to reduce manufacturing time and cost by incorporating electronic components such as semiconductor elements, capacitors, resistors, and inductors in the wiring board in a lump. .

本発明の実施の形態によるフィルムキャリア及び配線基板を示す断面図である。It is sectional drawing which shows the film carrier and wiring board by embodiment of this invention. 図１に示す配線基板において、キャパシタチップ部品の電極部にバンプを設けた部分と、リード先端にバンプを設けた部分を示す断面図である。FIG. 2 is a cross-sectional view showing a portion where bumps are provided on electrode portions of capacitor chip components and a portion where bumps are provided on the tips of leads in the wiring board shown in FIG. 図１に示す配線基板における電子部品が実装されたフィルムキャリアに印刷抵抗を造り込み、半導体素子を実装した後の状態を示す断面図である。It is sectional drawing which shows the state after building a printing resistance in the film carrier with which the electronic component in the wiring board shown in FIG. 1 was mounted, and mounting the semiconductor element. 図１に示す配線基板における電子部品が実装されたフィルムキャリアに印刷キャパシタを造り込み、チップキャパシタを実装した状態を示す断面図である。It is sectional drawing which shows the state which built the printing capacitor in the film carrier with which the electronic component in the wiring board shown in FIG. 1 was mounted, and mounted the chip capacitor. 図１に示す配線基板のフィルムキャリアにおける半導体素子の接続部の状態を上方向及び下方向から示す平面図である。It is a top view which shows the state of the connection part of the semiconductor element in the film carrier of the wiring board shown in FIG. 1 from an upper direction and a downward direction. 本発明の実施例１における配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board in Example 1 of this invention. 本発明の実施例２における配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board in Example 2 of this invention. 多層構造のフィルムキャリアの例を示す断面図である。It is sectional drawing which shows the example of the film carrier of a multilayer structure. 従来例１の電子部品が内蔵された配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board in which the electronic component of the prior art example 1 was incorporated. 従来例２の電子部品が内蔵された配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board in which the electronic component of the prior art example 2 was incorporated. 従来例３の電子部品が内蔵された配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board in which the electronic component of the prior art example 3 was incorporated. 従来例３の電子部品が内蔵された配線基板のフィルムキャリアを示す平面図である。It is a top view which shows the film carrier of the wiring board in which the electronic component of the prior art example 3 was incorporated.

符号の説明Explanation of symbols

１……半導体素子、２……キャパシタ、３……抵抗、４……フィルムキャリア、５……電極、６……バンプ、７……リード、８……印刷キャパシタ、９……接続部、１０……樹脂、１１……熱硬化性長尺ポリイミドフィルム、１２……スプロケットホール、１３……銅箔、１４……配線、１５……溝、１６……プリプレグ、１７……絶縁樹脂、１８……ビア、１９……下電極、２０……誘電体、２１……引き出し電極、２２……上電極、２３……非導電性接着剤、２４……ダイパッド、 ２５……アウターリード、２６……フィルム、２７……半田。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Capacitor, 3 ... Resistance, 4 ... Film carrier, 5 ... Electrode, 6 ... Bump, 7 ... Lead, 8 ... Print capacitor, 9 ... Connection part, 10 ...... Resin, 11 ... Thermosetting long polyimide film, 12 ... Sprocket hole, 13 ... Copper foil, 14 ... Wiring, 15 ... Groove, 16 ... Pre-preg, 17 ... Insulating resin, 18 ... ... via, 19 ... lower electrode, 20 ... dielectric, 21 ... extraction electrode, 22 ... upper electrode, 23 ... non-conductive adhesive, 24 ... die pad, 25 ... outer lead, 26 ... Film, 27 ... solder.

Claims (14)

複数種類の電子部品が搭載される配線基板であって、少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有することを特徴とする配線基板。   A wiring board on which a plurality of types of electronic components are mounted, wherein at least one type of electronic components is mounted, and a film carrier having a positioning hole has at least one layer arranged in a band shape including a plurality of modules A wiring board characterized by that. 前記位置決め用の孔が搬送孔兼用のスプロケットホールであることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the positioning hole is a sprocket hole also serving as a transport hole. 前記複数種類の電子部品は、半導体素子、キャパシタ、抵抗体、及びインダクタの少なくとも一種類を含むことを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the plurality of types of electronic components include at least one of a semiconductor element, a capacitor, a resistor, and an inductor. 前記電子部品の少なくとも一種類がフィルムキャリアの製造工程内で作り込まれていることを特徴とする請求項１〜３のいずれか１項記載の配線基板。   The wiring board according to claim 1, wherein at least one of the electronic components is built in a film carrier manufacturing process. 前記フィルムキャリアと電子部品とを電気的に接続するためのバンプがフィルムキャリアに形成されていることを特徴とする請求項１〜４のいずれか１項記載の配線基板。   The wiring board according to claim 1, wherein bumps for electrically connecting the film carrier and the electronic component are formed on the film carrier. 前記フィルムキャリアと電子部品とを電気的に接続するためのバンプが電子部品に形成されていることを特徴とする請求項１〜４のいずれか１項記載の配線基板。   The wiring substrate according to claim 1, wherein bumps for electrically connecting the film carrier and the electronic component are formed on the electronic component. 前記フィルムキャリアと電子部品を電気的に接続するためのリードが１つの接続に対して２つ以上フィルムキャリアに形成されていることを特徴とする請求項６記載の配線基板。   7. The wiring board according to claim 6, wherein two or more leads for electrically connecting the film carrier and the electronic component are formed on the film carrier for one connection. 前記フィルムキャリアと電子部品を電気的に接続するためのバンプが１つの接続に対して２つ以上電子部品に形成されていることを特徴とする請求項７記載の配線基板。   The wiring board according to claim 7, wherein two or more bumps for electrically connecting the film carrier and the electronic component are formed on the electronic component for one connection. 複数種類の電子部品が搭載される配線基板の製造方法であって、
位置決め用の孔が設けられた長尺フィルムキャリアを作製する工程と、
前記長尺フィルムキャリアに電子部品をＴＡＢ実装する工程と、
前記電子部品がＴＡＢ実装された長尺フィルムキャリアの両面にプリプレグを介して配線用の金属箔を張り合わせる工程とを有し、
少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成する、
ことを特徴とする配線基板の製造方法。 A method of manufacturing a wiring board on which a plurality of types of electronic components are mounted,
Producing a long film carrier provided with a positioning hole; and
TAB mounting electronic components on the long film carrier;
Bonding the metal foil for wiring to both sides of the long film carrier on which the electronic component is TAB-mounted via a prepreg,
At least one kind of electronic component is mounted, and a film carrier having a positioning hole forms a wiring board having at least one layer arranged in a band shape including a plurality of modules.
A method for manufacturing a wiring board. 前記長尺フィルムキャリアを複数並べた状態で、並列に前記プリプレグを介して金属箔を張り合わせる工程を含むことを特徴とする請求項９記載の配線基板の製造方法。   10. The method for manufacturing a wiring board according to claim 9, further comprising a step of bonding metal foils in parallel through the prepreg in a state where a plurality of the long film carriers are arranged. 複数種類の電子部品が搭載される配線基板の製造方法であって、
長尺金属板の両面に、ポジ型フォトレジストをロールコートし、露光現像を行うフォトリソグラフィ法、及び金属を腐食させるエッチング法により、前記電子部品が実装される部分だけのリードと位置決め用の孔が設けられた長尺フィルムキャリアを作製する工程と、
前記長尺フィルムキャリアに電子部品をＴＡＢ実装する工程と、
前記電子部品がＴＡＢ実装された長尺フィルムキャリアの実装側にプリプレグを介して基板を張り合わせる工程とを有し、
少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成する、
ことを特徴とする配線基板の製造方法。 A method of manufacturing a wiring board on which a plurality of types of electronic components are mounted,
Leads and positioning holes only on the part where the electronic parts are mounted by photolithography method that rolls positive photoresist on both sides of long metal plate, exposure and development, and etching method that corrodes metal Producing a long film carrier provided with,
TAB mounting electronic components on the long film carrier;
Bonding the substrate to the mounting side of the long film carrier on which the electronic component is TAB mounted via a prepreg,
At least one kind of electronic component is mounted, and a film carrier having a positioning hole forms a wiring board having at least one layer arranged in a band shape including a plurality of modules.
A method for manufacturing a wiring board. 複数種類の電子部品が搭載される配線基板の製造方法であって、
第１面に金属箔を張り付けた樹脂基板よりなるフィルムキャリアの第２面に接着剤を塗布する工程と、
前記フィルムキャリアの所望の位置に電子部品が実装される開口部、及び位置決め用の孔を形成する工程と、
前記フィルムキャリアの第２面に接着剤を介して金属箔を接着する工程と、
前記フィルムキャリアの金属箔を用いて配線を形成する工程と、
前記フィルムキャリアに電子部品をＴＡＢ実装する工程と、
前記フィルムキャリアに上層膜の積層を行う工程とを有し、
少なくとも一種類の電子部品が実装され、位置決め用の孔を有するフィルムキャリアが複数のモジュールを含む帯状で配置される層を少なくとも１層有する配線基板を形成する、
ことを特徴とする配線基板の製造方法。 A method of manufacturing a wiring board on which a plurality of types of electronic components are mounted,
Applying an adhesive to the second surface of the film carrier comprising a resin substrate with a metal foil attached to the first surface;
Forming an opening for mounting an electronic component at a desired position of the film carrier, and a positioning hole;
Bonding a metal foil to the second surface of the film carrier via an adhesive;
Forming a wiring using the metal foil of the film carrier;
TAB mounting electronic components on the film carrier;
And laminating an upper film on the film carrier,
At least one kind of electronic component is mounted, and a film carrier having a positioning hole forms a wiring board having at least one layer arranged in a band shape including a plurality of modules.
A method for manufacturing a wiring board. 前記位置決め用の孔が搬送孔兼用のスプロケットホールであることを特徴とする請求項９〜１２のいずれか１項記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 9, wherein the positioning hole is a sprocket hole that also serves as a transport hole. 前記複数種類の電子部品は、半導体素子、キャパシタ、抵抗体、及びインダクタの少なくとも一種類を含むことを特徴とする請求項９〜１２のいずれか１項記載の配線基板の製造方法。   The method of manufacturing a wiring board according to claim 9, wherein the plurality of types of electronic components include at least one of a semiconductor element, a capacitor, a resistor, and an inductor.
JP2006329256A 2006-12-06 2006-12-06 Wiring board Expired - Fee Related JP5098313B2 (en)

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JP2010199191A (en) * 2009-02-24 2010-09-09 Oki Semiconductor Co Ltd Semiconductor package and method of manufacturing semiconductor package
JP2011243897A (en) * 2010-05-21 2011-12-01 Fujitsu Ltd Multilayer printed board and method of manufacturing the same

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