JP2008034856A - 微細ビアホールの形成方法及びこのビアホールの形成方法を用いた多層印刷回路基板 - Google Patents

微細ビアホールの形成方法及びこのビアホールの形成方法を用いた多層印刷回路基板 Download PDF

Info

Publication number
JP2008034856A
JP2008034856A JP2007199200A JP2007199200A JP2008034856A JP 2008034856 A JP2008034856 A JP 2008034856A JP 2007199200 A JP2007199200 A JP 2007199200A JP 2007199200 A JP2007199200 A JP 2007199200A JP 2008034856 A JP2008034856 A JP 2008034856A
Authority
JP
Japan
Prior art keywords
via hole
ink
forming
conductive
thermosetting substance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007199200A
Other languages
English (en)
Japanese (ja)
Inventor
Kyung Tae Kang
ギョン デ カン
Kyeong Kyun Lee
ギョン キュン リ
Young Joon Cho
ヨン ジュン チョ
Kwon Yong Sin
クォン ヨン シン
Min Su Lee
ミン ス リ
Joong Ho Song
ジュン ホ ソン
Young Seok Park
ヨン セ パク
Hyung Kun Kim
ヒョン クン キム
Byung Jik Lee
ビョン ジク リ
Chang Keun Seo
チャン グン セオ
Seung Min Oh
スン ミン オ
Dae Sub Song
デ ソプ ソン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Korea Institute of Industrial Technology KITECH
Original Assignee
Korea Institute of Industrial Technology KITECH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Institute of Industrial Technology KITECH filed Critical Korea Institute of Industrial Technology KITECH
Publication of JP2008034856A publication Critical patent/JP2008034856A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2007199200A 2006-07-31 2007-07-31 微細ビアホールの形成方法及びこのビアホールの形成方法を用いた多層印刷回路基板 Pending JP2008034856A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060072012A KR100777021B1 (ko) 2006-07-31 2006-07-31 미세 비아홀 형성 방법 및 이 비아홀 형성방법을 이용한다층 인쇄회로기판

Publications (1)

Publication Number Publication Date
JP2008034856A true JP2008034856A (ja) 2008-02-14

Family

ID=39079919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007199200A Pending JP2008034856A (ja) 2006-07-31 2007-07-31 微細ビアホールの形成方法及びこのビアホールの形成方法を用いた多層印刷回路基板

Country Status (2)

Country Link
JP (1) JP2008034856A (ko)
KR (1) KR100777021B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009272575A (ja) * 2008-05-12 2009-11-19 Panasonic Corp 半導体貫通電極形成方法
CN106793535A (zh) * 2015-11-20 2017-05-31 富泰华工业（深圳）有限公司 电路板丝网印刷方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109395790B (zh) * 2018-12-11 2024-03-29 福州大学 一种纸基复合三维微/纳电路及其加工方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307930A (ja) 1998-04-24 1999-11-05 Namics Corp 基板およびその製造方法
JP2002329974A (ja) * 2001-05-01 2002-11-15 Nitto Denko Corp 配線基板及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009272575A (ja) * 2008-05-12 2009-11-19 Panasonic Corp 半導体貫通電極形成方法
CN106793535A (zh) * 2015-11-20 2017-05-31 富泰华工业（深圳）有限公司 电路板丝网印刷方法

Also Published As

Publication number Publication date
KR100777021B1 (ko) 2007-11-16

Similar Documents

Publication Publication Date Title
JP4682294B2 (ja) 電気接続パッド金属保護層を備える半導体パッケージ基板構造及びその製法
US7592706B2 (en) Multi-layer circuit board with fine pitches and fabricating method thereof
TWI569699B (zh) 印刷電路板及其製造方法
US7754598B2 (en) Method for manufacturing coreless packaging substrate
US9674967B2 (en) Via in a printed circuit board
US20090288873A1 (en) Wiring board and method of manufacturing the same
US8037586B2 (en) Method for fabricating blind via structure of substrate
WO2000035260A1 (fr) Procede de fabrication d'un substrat ceramique
US20120110839A1 (en) Method of manufacturing wiring board
JP2010062525A (ja) 印刷回路基板及びその製造方法
JP2008034856A (ja) 微細ビアホールの形成方法及びこのビアホールの形成方法を用いた多層印刷回路基板
TWI678954B (zh) 利用印刷電路板的大電流傳輸方法
US20080209722A1 (en) Method for forming via hole having fine hole land
JP4292638B2 (ja) 配線板の製造方法
US20080040920A1 (en) Printed wiring board having multiple instersitial resistors of different electrical resistance values and method of making the same
JP2007067189A (ja) 配線基板及びその製造方法
JP2008016805A (ja) 印刷回路基板及びその製造方法
JP2011061010A (ja) 部品内蔵モジュールの製造方法
JP2015207710A (ja) 配線基板
JP4681023B2 (ja) 配線基板の製造方法
US20030215566A1 (en) Fine patterning and fine solid via process for multi-layer substrate
JP2013187458A (ja) 多層プリント配線基板の製造方法及び多層プリント配線基板
US20240196542A1 (en) Electrical interconnect structure with circuit bearing dielectric layers and resultant dielectric spacing control and circuit pitch reduction
US8415246B2 (en) Method of forming a high density structure
JP2009200294A (ja) 積層基板およびその製造方法

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090804

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091104

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100309