US20080209722A1 - Method for forming via hole having fine hole land - Google Patents
Method for forming via hole having fine hole land Download PDFInfo
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- US20080209722A1 US20080209722A1 US12/068,457 US6845708A US2008209722A1 US 20080209722 A1 US20080209722 A1 US 20080209722A1 US 6845708 A US6845708 A US 6845708A US 2008209722 A1 US2008209722 A1 US 2008209722A1
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- Prior art keywords
- via hole
- forming
- copper
- hole
- clad laminate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09545—Plated through-holes or blind vias without lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0542—Continuous temporary metal layer over metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1394—Covering open PTHs, e.g. by dry film resist or by metal disc
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a via hole and a method for forming the same. More particularly, the present invention relates to a via-hole having a fine hole land, with which the density of circuit patterns can be increased, and a method for forming the same.
- Multilayer PCBs enable interconnections to be achieved three dimensionally as well as in planes. Particularly, multilayer PCBs can improve the integration of functional devices, such as ICs (integrated circuit), LSICs (large scale integrated circuit), etc., allowing electronic products to have slimness, lightness, and high performance, to achieved structural integration of electric functions and to be produced in a significantly reduced assembly time period and at a low cost.
- ICs integrated circuit
- LSICs large scale integrated circuit
- Via-holes corresponding to passageways for interlayer electric connection, were conventionally formed using mechanical drills.
- mechanical drilling results in too large a hole to form fine circuits, in addition to increasing the production cost.
- laser drilling is preferred.
- microvias Generally representative of new, smaller vias, called “microvias”, a blind via is drilled from the surface of a PCB and terminates within the substrate.
- the removal of material is the result of an electrochemical reaction to laser pulse or plasma treatment, which is different from a cutting action or treatment.
- removal processes similar to laser pulse or plasma treatment eliminate materials around the central line as well.
- micro via drilling Because it primarily results in round holes, such removal, whether using laser, plasma, or others, competes with mechanical drilling. The formation of the round holes is often called ‘drilling’ due to the removal of materials around the central line, and is thus termed “micro via drilling”.
- the conventional method for forming via holes in a PCB by laser drilling comprises a laser drilling process, a desmearing and copper plating process, and a circuit patterning process.
- via holes in a PCB starts with the drilling of a copper clad laminate 101 of FIG. 1A to form via holes 102 which travel through two layers, as shown in FIG. 1B .
- a desmearing process is conducted, immediately followed by plating the inner walls of the holes with copper to form a copper-plated layer 103 .
- the copper-plated layer 103 is patterned to form a circuit.
- the via holes 102 require hole lands for electrical interconnection.
- the hole lands of via holes act as hindrances to the increase of the degree of integration of circuit patterns.
- FIG. 2A which shows conventional via-holes in a plan view
- hole lands 104 a - 104 c prevent circuit lines 105 a - 105 c from being arranged near each other.
- the via holes are disposed in a zigzag manner in order to reduce the distance between circuit lines 105 a - 105 c
- the hole lands 104 a - 104 c still interfere with the approach of the circuit line 105 a - 105 c to each other.
- FIG. 2B is a perspective view showing a via hole according to a conventional technology.
- the via hole as shown in FIG. 2B , comprises a hole inner wall 107 associated with an upper hole land 104 u at its upper portion and with a down hole land 104 d at its lower portion.
- the upper hole land 104 u is extended through a circuit line 105 to a wire bonding pad while the down hole land 104 d is associated with a solder ball pad 108 .
- the hole lands 104 u and 104 d still occupy large areas.
- a via hole having a fine hole land comprising a first conductive layer formed on an inner wall in contact with an insulation layer; a second conductive layer outside the first conductive layer; and a circuit line, formed on the insulation layer, connecting to the second conductive layer, wherein the hole land is formed by the first and the second conductive layer.
- the first conductive layer is extended over the insulating layer.
- the first layer is an electroless plated layer.
- the second conductive layer is an electroplated layer.
- a method for forming a via hole having a fine hole land comprising: step 1 of forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; step 2 of forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and step 3 of forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.
- FIGS. 1A to 1D are schematic views showing conventional processes of forming via holes in a printed circuit board using a laser drill
- FIGS. 2A and 2B are a plan view and a perspective view, respectively, showing via holes formed according to the conventional processes
- FIGS. 3A and 3B are a perspective view and a plan view, respectively, showing a via hole having a fine hole land in accordance with the present invention
- FIGS. 4A to 4R are schematic views showing processes of forming a via hole having a fine hole land in accordance with the present invention.
- FIG. 3A shows the perspective view of FIG. 3A while FIG. 3B . shows the arrangement of a plurality of the via holes in a plan view.
- a via hole having a fine hole land comprises a conductive inner wall layer 207 , an upper hole land 204 u (consisting of 204 ui and 204 uo ), a down hole land 204 d (consisting of 204 di and 204 do ), a wire bonding pad 206 , a solder ball pad 208 , and a circuit line 205 for connecting the wire bonding pad 206 with the upper hole land 204 u , as shown in FIG. 3A .
- the hole land 204 u is as large as the conductive inner wall layer 207 and is divided into an inner hole land 204 ui and an outer hole land 204 uo , which extends from the inner hole land 204 ui .
- the outer hole land 204 uo ranges in thickness from 0 to 15 gm.
- the inner hole land 204 u i has a thickness of 10 pm.
- the inner hole land 204 ui and the outer hole land 204 uo are different in crystalline structure from each other because different processes are used.
- the inner hole land 204 ui is electroplated with copper while the outer hole land 204 uo consists of an electroless copper plated layer and electro-copper plated layer.
- FIG. 3B shows the arrangement of a plurality of the via holes having the fine hole lands 204 ui and 204 uo in a plan view.
- the thinness of the outer hole lands 204 uoa to 204 uoc allows circuit lines 205 a to 205 c to be disposed closely adjacent to each other, increasing the degree of integration of the circuit patterns.
- FIGS. 4A to 4R a method of forming a via hole in accordance with an embodiment of the present invention is illustrated in a stepwise manner.
- a copper clad laminate 410 comprising an insulation layer 411 with respective copper layers 412 a and 412 b formed on opposite faces thereof is provided.
- the insulation layer 411 is based on resin.
- Resinous materials show high insulation properties, but suffer from the disadvantage of being poor in mechanical strength and being dimensionally more unstable in response to temperature change than metallic materials.
- paper, glass fiber, or glass non-woven fabric is used as a reinforcement.
- the reinforcement increases the strength of the resinous material in both widthwise and lengthwise directions and decreases the dimensional change with temperature.
- the copper clad laminate 410 although shown having copper layers 412 a and 412 b on opposite faces thereof, may comprise only one copper layer.
- FIG. 4B is a schematic cross sectional view after the copper clad laminate ( 410 ) is drilled to form via holes 420 .
- Excimer laser is not applied to PCBs.
- a YAG laser using 355 nm can drill through the copper layer, but is 90% reflected by glass epoxy, which may be used in a prepreg form for the insulation layer.
- a CO2 laser of 9.4 ⁇ m can be applied for drilling the copper clad laminate because it is absorbed in an amount of 80%.
- etching resists 430 a , 430 b are formed on either or both surfaces of the copper clad laminate 410 having the via holes 420 therein.
- the formation of the etching resists can be achieved in a photographic process or a screen printing process.
- a dry film may be an etching resist, as in a D/F method, or a liquid photosensitive material may be used.
- FIG. 4D is a cross sectional view after an image forming process is conducted to form a pattern of the etching resists 430 a , 430 b on the copper layers 412 a , 412 b , respectively and an etchant is sprayed to remove the copper layer 412 a , 412 b from predetermined areas, with the pattern of the etching resists serving as a mask.
- the resulting copper clad laminate 410 is shown in the plan view of FIG. 4E and in the rear view of FIG. 4F .
- a circuit line 435 a extends into the via hole 420 .
- a circuit line 435 b is formed on the lower surface of the copper clad laminate 410 so as to extend into or over the via hole 420 , as shown in FIG. 4F .
- the resulting copper clad laminate 410 is shown in the plan view of FIG. 4H and in the rear side view of FIG. 4I .
- electroless plating or sputter
- the seed layer 440 preferably has a thickness from 0.5 to 1.5 ⁇ m.
- Electroless copper plating is a technique for providing conductivity for insulators such as resins, ceramics, glass, etc. Performed in such a way that a substrate is immersed in a plating solution, electroless copper plating allows all parts of the substrate, including the inner wall of the hole, to be plated with copper. By this electroless copper plating, called primary copper plating, the upper copper layer is electrically connected with the lower copper layer. The primary copper plating results in a preliminary thin coat for subsequent electroplating. Due to poor physical properties, the electroless plated copper coat must be overcoated with copper through electroplating.
- the electric conductivity imparted to the inner wall of the hole by electroless copper plating enables electroplating to be applied thereto.
- the copper coat formed by electroplating is much thicker and exhibits better physical properties than the copper coat formed by electroless plating.
- a photoresist 450 a , 450 b is selectively formed over the copper clad laminate 410 in such a way that only the inner wall of the via hole 420 is exposed.
- the photoresist 450 a , 450 b can be formed using a photographic method or a screen printing method.
- a dry film may be used as an etching resist, as in a D/F method, or a liquid photosensitive material may be used.
- an image forming process is performed to remove the part of the photoresist 450 a , 450 b corresponding to the via hole 420 to expose the inner wall of the via hole 420 .
- the resulting structure of the copper clad laminate 410 is shown in the plan view of FIG. 4K and in a rear side view of FIG. 4L . As shown in both FIGS. 4K and 4L , only the inner wall of the via hole 420 is exposed.
- FIG. 4M is a cross sectional view after a copper coat is formed on the inner wall of the via hole 420 with the seed layer 440 serving as a plating bar.
- the copper coat 460 has a thickness of 10 .tm or greater. A 10 ⁇ m thick or thicker copper coat 460 assures reliable electric conduction between the upper and the lower layers.
- the relatively thin seed layer 440 is formed on the inner wall of the via hole 420 while being coated with the relatively thick copper layer 460 .
- the photoresist 450 a , 450 b is peeled off and the seed layer is removed by flash etching so as to form a circuit.
- the present invention can decrease the area occupied by hole lands so as to increase the density of via holes, thereby realizing slimness of the PCB.
- the present invention increases the number of circuit lines per unit area, thus increasing the density of circuit patterns.
- the present invention can be applied to the slimness of all electronic appliances which require fine patterns.
Abstract
A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.
Description
- This application is a U.S. divisional application filed under 35 USC 1.53(b) claiming benefit of U.S. Ser. No. 11/484,708 filed in the United States on Jul. 12, 2006, which claims earlier benefit of Korean Patent Application No. 10-2005-0121752 filed in Korea on Dec. 12, 2005, the contents of which are hereby incorporated by reference.
- The present invention relates to a via hole and a method for forming the same. More particularly, the present invention relates to a via-hole having a fine hole land, with which the density of circuit patterns can be increased, and a method for forming the same.
- With the recent evolution of electronics to slimness, lightness and high performance and with the rapid increase in the application of built-up PCBs (printed circuit boards) to light, slim and small electronic products including wireless communication terminals, digital camcorders, mobile computers, etc., multilayer PCBs are very extensively used.
- Multilayer PCBs enable interconnections to be achieved three dimensionally as well as in planes. Particularly, multilayer PCBs can improve the integration of functional devices, such as ICs (integrated circuit), LSICs (large scale integrated circuit), etc., allowing electronic products to have slimness, lightness, and high performance, to achieved structural integration of electric functions and to be produced in a significantly reduced assembly time period and at a low cost.
- Almost all the built-up PCBs employed in such applications have via-holes through which interlayer connection is achieved. The recent tendency toward slimness and lightness is causing laser drills to be the new rising technology used for the formation of the via-holes.
- Via-holes, corresponding to passageways for interlayer electric connection, were conventionally formed using mechanical drills. However, mechanical drilling results in too large a hole to form fine circuits, in addition to increasing the production cost. Nowadays, laser drilling is preferred.
- Generally representative of new, smaller vias, called “microvias”, a blind via is drilled from the surface of a PCB and terminates within the substrate.
- If the cross-sectional area that a via occupies decreases, the ability to utilize vias increases by a similar amount.
- However, the reduction of via size to microvia size means that mechanical drilling is of no commercial use, implying the generalization of some alternative processes, such as removal by way of laser or plasma.
- The removal of material is the result of an electrochemical reaction to laser pulse or plasma treatment, which is different from a cutting action or treatment. However, removal processes similar to laser pulse or plasma treatment eliminate materials around the central line as well.
- Because it primarily results in round holes, such removal, whether using laser, plasma, or others, competes with mechanical drilling. The formation of the round holes is often called ‘drilling’ due to the removal of materials around the central line, and is thus termed “micro via drilling”.
- With reference to
FIGS. 1A to 1D , the formation of via-holes in a PCB using a conventional laser drilling process is schematically shown in a stepwise manner. - The conventional method for forming via holes in a PCB by laser drilling, as shown in
FIGS. 1A to 1D , comprises a laser drilling process, a desmearing and copper plating process, and a circuit patterning process. - The formation of via holes in a PCB starts with the drilling of a copper
clad laminate 101 ofFIG. 1A to form viaholes 102 which travel through two layers, as shown inFIG. 1B . - Next, as shown in
FIG. 1 C, a desmearing process is conducted, immediately followed by plating the inner walls of the holes with copper to form a copper-platedlayer 103. - Subsequently, the copper-plated
layer 103 is patterned to form a circuit. - As a rule, the
via holes 102 require hole lands for electrical interconnection. However, the hole lands of via holes act as hindrances to the increase of the degree of integration of circuit patterns. Referring toFIG. 2A , which shows conventional via-holes in a plan view,hole lands 104 a-104 c preventcircuit lines 105 a-105 c from being arranged near each other. As shown inFIG. 2A , although the via holes are disposed in a zigzag manner in order to reduce the distance betweencircuit lines 105 a-105 c, thehole lands 104 a-104 c still interfere with the approach of thecircuit line 105 a-105 c to each other. -
FIG. 2B is a perspective view showing a via hole according to a conventional technology. The via hole, as shown inFIG. 2B , comprises a holeinner wall 107 associated with an upper hole land 104 u at its upper portion and with a down hole land 104 d at its lower portion. The upper hole land 104 u is extended through acircuit line 105 to a wire bonding pad while the down hole land 104 d is associated with asolder ball pad 108. As can be seen, the hole lands 104 u and 104 d still occupy large areas. - Therefore, it is an object of the present invention to provide a via hole having a fine hole land with which circuit patterns can be constructed at a high density, and a method for forming the same.
- In accordance with an aspect of the present invention, provided is a via hole having a fine hole land, comprising a first conductive layer formed on an inner wall in contact with an insulation layer; a second conductive layer outside the first conductive layer; and a circuit line, formed on the insulation layer, connecting to the second conductive layer, wherein the hole land is formed by the first and the second conductive layer.
- In a preferable embodiment, the first conductive layer is extended over the insulating layer.
- In another preferable embodiment, the first layer is an electroless plated layer.
- In a further preferable embodiment, the second conductive layer is an electroplated layer.
- In accordance with another aspect of the present invention, provided is a method for forming a via hole having a fine hole land, comprising: step 1 of forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; step 2 of forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and step 3 of forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.
- The application of the preferred embodiments of the present invention is best understood with reference to the accompanying drawings, in which like reference numerals are used for like and corresponding parts, wherein:
-
FIGS. 1A to 1D are schematic views showing conventional processes of forming via holes in a printed circuit board using a laser drill; -
FIGS. 2A and 2B are a plan view and a perspective view, respectively, showing via holes formed according to the conventional processes; -
FIGS. 3A and 3B are a perspective view and a plan view, respectively, showing a via hole having a fine hole land in accordance with the present invention; -
FIGS. 4A to 4R are schematic views showing processes of forming a via hole having a fine hole land in accordance with the present invention. - Below, a detailed description is given of an embodiment of the present invention with reference to the accompanying drawings.
- A via-hole having a fine hole land in accordance with an embodiment of the present invention is shown in the perspective view of
FIG. 3A whileFIG. 3B . shows the arrangement of a plurality of the via holes in a plan view. - In accordance with the present invention, a via hole having a fine hole land comprises a conductive
inner wall layer 207, anupper hole land 204 u (consisting of 204 ui and 204 uo), a down hole land 204 d (consisting of 204 di and 204 do), awire bonding pad 206, asolder ball pad 208, and acircuit line 205 for connecting thewire bonding pad 206 with theupper hole land 204 u, as shown inFIG. 3A . - The
hole land 204 u is as large as the conductiveinner wall layer 207 and is divided into aninner hole land 204 ui and anouter hole land 204 uo, which extends from theinner hole land 204 ui. Preferably, theouter hole land 204 uo ranges in thickness from 0 to 15 gm. Theinner hole land 204 ui has a thickness of 10 pm. Although they are made from the same material, that is, copper, theinner hole land 204 ui and theouter hole land 204 uo are different in crystalline structure from each other because different processes are used. Specifically, theinner hole land 204 ui is electroplated with copper while theouter hole land 204 uo consists of an electroless copper plated layer and electro-copper plated layer. -
FIG. 3B shows the arrangement of a plurality of the via holes having the fine hole lands 204 ui and 204 uo in a plan view. As shown inFIG. 3B , the thinness of theouter hole lands 204 uoa to 204 uoc allowscircuit lines 205 a to 205 c to be disposed closely adjacent to each other, increasing the degree of integration of the circuit patterns. - With reference to
FIGS. 4A to 4R , a method of forming a via hole in accordance with an embodiment of the present invention is illustrated in a stepwise manner. - First, as shown in
FIG. 4A , a copper cladlaminate 410 comprising aninsulation layer 411 withrespective copper layers - The
insulation layer 411 is based on resin. Resinous materials show high insulation properties, but suffer from the disadvantage of being poor in mechanical strength and being dimensionally more unstable in response to temperature change than metallic materials. In order to overcome the disadvantages, paper, glass fiber, or glass non-woven fabric is used as a reinforcement. The reinforcement increases the strength of the resinous material in both widthwise and lengthwise directions and decreases the dimensional change with temperature. - The copper clad
laminate 410, although shown havingcopper layers -
FIG. 4B is a schematic cross sectional view after the copper clad laminate (410) is drilled to form viaholes 420. - As currently available technologies for forming via holes in PCBs, there are excimer, Nd:YAG and CO2 laser drilling processes.
- Excimer laser is not applied to PCBs. A YAG laser using 355 nm can drill through the copper layer, but is 90% reflected by glass epoxy, which may be used in a prepreg form for the insulation layer.
- In contrast, a CO2 laser of 9.4 μm can be applied for drilling the copper clad laminate because it is absorbed in an amount of 80%.
- Afterward, as shown in
FIG. 4C , etching resists 430 a, 430 b are formed on either or both surfaces of the copper cladlaminate 410 having the via holes 420 therein. The formation of the etching resists can be achieved in a photographic process or a screen printing process. For the photographic process, a dry film may be an etching resist, as in a D/F method, or a liquid photosensitive material may be used. -
FIG. 4D is a cross sectional view after an image forming process is conducted to form a pattern of the etching resists 430 a, 430 b on the copper layers 412 a, 412 b, respectively and an etchant is sprayed to remove thecopper layer laminate 410 is shown in the plan view ofFIG. 4E and in the rear view ofFIG. 4F . As shown inFIG. 4E , acircuit line 435 a extends into the viahole 420. In addition, acircuit line 435 b is formed on the lower surface of the copper cladlaminate 410 so as to extend into or over the viahole 420, as shown inFIG. 4F . - Subsequently, as shown in
FIG. 4G , copper plating is conducted to form aseed layer 440. The resulting copper cladlaminate 410 is shown in the plan view ofFIG. 4H and in the rear side view ofFIG. 4I . For the copper plating, electroless plating (or sputter) is performed prior to electroplating. Theseed layer 440 preferably has a thickness from 0.5 to 1.5 μm. - Electroless copper plating (or sputtering) is a technique for providing conductivity for insulators such as resins, ceramics, glass, etc. Performed in such a way that a substrate is immersed in a plating solution, electroless copper plating allows all parts of the substrate, including the inner wall of the hole, to be plated with copper. By this electroless copper plating, called primary copper plating, the upper copper layer is electrically connected with the lower copper layer. The primary copper plating results in a preliminary thin coat for subsequent electroplating. Due to poor physical properties, the electroless plated copper coat must be overcoated with copper through electroplating.
- The electric conductivity imparted to the inner wall of the hole by electroless copper plating enables electroplating to be applied thereto. The copper coat formed by electroplating is much thicker and exhibits better physical properties than the copper coat formed by electroless plating.
- Subsequently, as shown in
FIG. 4J , aphotoresist laminate 410 in such a way that only the inner wall of the viahole 420 is exposed. Thephotoresist - Afterwards, an image forming process is performed to remove the part of the
photoresist hole 420 to expose the inner wall of the viahole 420. The resulting structure of the copper cladlaminate 410 is shown in the plan view ofFIG. 4K and in a rear side view ofFIG. 4L . As shown in bothFIGS. 4K and 4L , only the inner wall of the viahole 420 is exposed. -
FIG. 4M is a cross sectional view after a copper coat is formed on the inner wall of the viahole 420 with theseed layer 440 serving as a plating bar. Preferably, thecopper coat 460 has a thickness of 10 .tm or greater. A 10 μm thick orthicker copper coat 460 assures reliable electric conduction between the upper and the lower layers. - The resulting structure of the copper clad laminate, in which the
copper coat 460 is formed on the inner wall of the viahole 420, is shown in the plan view ofFIG. 4N and in the rear side view ofFIG. 4O . - With reference to
FIGS. 4N and 4O , the relativelythin seed layer 440 is formed on the inner wall of the viahole 420 while being coated with the relativelythick copper layer 460. - Thereafter, as shown in
FIG. 4P , thephotoresist - Then, a photo solder resist process and subsequent processes are conducted as usual.
- As described hereinbefore, the present invention can decrease the area occupied by hole lands so as to increase the density of via holes, thereby realizing slimness of the PCB.
- That is, the present invention increases the number of circuit lines per unit area, thus increasing the density of circuit patterns.
- In addition, the present invention can be applied to the slimness of all electronic appliances which require fine patterns.
- Examples are described in terms of the preferred embodiment of present invention. However, it should be understood that such disclosure is not limited to the explicit description of the present invention. The description and the claims of present invention are to be interpreted as covering all alterations and modifications within the true scope of this invention.
Claims (7)
1. A method for forming a via hole having a fine hole land, comprising:
(a) forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate;
(b) forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and
(c) forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.
2. The method as set forth in claim 1 , wherein operation (a) comprises;
forming the via hole in the copper clad laminate using a drilling process;
coating an etching resist in a circuit pattern over the copper clad laminate in a circuit pattern; and
forming a circuit pattern using an exposure process.
3. The method as set forth in claim 1 , wherein operation (b) comprises:
forming the seed layer using an electroless plating process and an electroplating process;
layering the photoresist on the seed layer; and
exposing the inner wall of the via hole through an exposure and development process with the photoresist serving as a mask.
4. The method as set forth in claim 3 , wherein the seed layer is 1.5 μm thick.
5. The method as set forth in claim 1 , wherein operation (c) comprises:
forming a copper layer on the inner wall of the via hole with the seed layer serving as a plating bar;
removing the photoresist; and
removing the seed layer by flash etching.
6. The method as set forth in claim 5 , wherein the copper layer has a thickness of 15 μm or greater.
7. The method as set forth in claim 1 , further comprising operation (d) of exposing a circumference of the via hole, wherein the circumference of the via hole is plated upon the formation of the plated layer on the inner wall of the via hole in operation (c).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/068,457 US20080209722A1 (en) | 2005-12-12 | 2008-02-06 | Method for forming via hole having fine hole land |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2005-0121752 | 2005-12-12 | ||
KR1020050121752A KR100722625B1 (en) | 2005-12-12 | 2005-12-12 | Via hole having fine hole land and method thereof |
US11/484,708 US7629692B2 (en) | 2005-12-12 | 2006-07-12 | Via hole having fine hole land and method for forming the same |
US12/068,457 US20080209722A1 (en) | 2005-12-12 | 2008-02-06 | Method for forming via hole having fine hole land |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/484,708 Division US7629692B2 (en) | 2005-12-12 | 2006-07-12 | Via hole having fine hole land and method for forming the same |
Publications (1)
Publication Number | Publication Date |
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US20080209722A1 true US20080209722A1 (en) | 2008-09-04 |
Family
ID=38138472
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US11/484,708 Expired - Fee Related US7629692B2 (en) | 2005-12-12 | 2006-07-12 | Via hole having fine hole land and method for forming the same |
US12/068,457 Abandoned US20080209722A1 (en) | 2005-12-12 | 2008-02-06 | Method for forming via hole having fine hole land |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/484,708 Expired - Fee Related US7629692B2 (en) | 2005-12-12 | 2006-07-12 | Via hole having fine hole land and method for forming the same |
Country Status (4)
Country | Link |
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US (2) | US7629692B2 (en) |
JP (1) | JP4314263B2 (en) |
KR (1) | KR100722625B1 (en) |
TW (1) | TWI331490B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US8440916B2 (en) | 2007-06-28 | 2013-05-14 | Intel Corporation | Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method |
TWI471984B (en) * | 2008-05-23 | 2015-02-01 | Advanced Semiconductor Eng | Circuit board with buried conductive trace formed thereon and method for manufacturing the same |
US8114712B1 (en) * | 2010-12-22 | 2012-02-14 | General Electric Company | Method for fabricating a semiconductor device package |
CN106982522A (en) * | 2017-03-14 | 2017-07-25 | 开平依利安达电子第三有限公司 | Multi net voting through hole circuit board and its manufacture method |
KR102309827B1 (en) | 2020-05-15 | 2021-10-12 | 주식회사 디에이피 | Method for producing Multi-layer PCB and Multi-layer PCB thereof |
Citations (4)
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US5218761A (en) * | 1991-04-08 | 1993-06-15 | Nec Corporation | Process for manufacturing printed wiring boards |
US5495665A (en) * | 1994-11-04 | 1996-03-05 | International Business Machines Corporation | Process for providing a landless via connection |
US20050124196A1 (en) * | 2002-06-27 | 2005-06-09 | Olson Kevin C. | Single or multi-layer printed circuit board with improved via design |
US20050241954A1 (en) * | 2004-05-03 | 2005-11-03 | Samsung Electro-Mechanics Co., Ltd. | Electrolytic gold plating method of printed circuit board |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH04286389A (en) | 1991-03-15 | 1992-10-12 | Citizen Watch Co Ltd | Manufacture of circuit board |
JPH08186373A (en) * | 1994-12-28 | 1996-07-16 | Nec Toyama Ltd | Manufacture of printed wiring board |
JP2000151067A (en) | 1998-11-06 | 2000-05-30 | Mitsui Mining & Smelting Co Ltd | Novel printed wiring board and manufacturing multilayer printed wiring board |
EP1163269A4 (en) * | 1999-03-15 | 2005-06-08 | Merck & Co Inc | ISOFORMS OF MOUSE SEROTONIN 5-HT2c RECEPTOR |
JP3048360B1 (en) | 1999-04-06 | 2000-06-05 | 日東電工株式会社 | Double-sided printed wiring board and method for manufacturing the same |
US20020117753A1 (en) | 2001-02-23 | 2002-08-29 | Lee Michael G. | Three dimensional packaging |
JP2004146668A (en) | 2002-10-25 | 2004-05-20 | Sharp Corp | Multilayer printed circuit board and manufacturing method thereof |
JP4113024B2 (en) | 2003-03-31 | 2008-07-02 | 三菱製紙株式会社 | Substrate manufacturing method |
JP2005286296A (en) | 2004-03-03 | 2005-10-13 | Mitsubishi Paper Mills Ltd | Method of manufacturing circuit board |
KR100632579B1 (en) * | 2004-04-07 | 2006-10-09 | 삼성전기주식회사 | How to Form Via Holes in Printed Circuit Boards |
-
2005
- 2005-12-12 KR KR1020050121752A patent/KR100722625B1/en active IP Right Grant
-
2006
- 2006-07-10 TW TW095125038A patent/TWI331490B/en not_active IP Right Cessation
- 2006-07-12 US US11/484,708 patent/US7629692B2/en not_active Expired - Fee Related
- 2006-11-13 JP JP2006306612A patent/JP4314263B2/en not_active Expired - Fee Related
-
2008
- 2008-02-06 US US12/068,457 patent/US20080209722A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218761A (en) * | 1991-04-08 | 1993-06-15 | Nec Corporation | Process for manufacturing printed wiring boards |
US5495665A (en) * | 1994-11-04 | 1996-03-05 | International Business Machines Corporation | Process for providing a landless via connection |
US20050124196A1 (en) * | 2002-06-27 | 2005-06-09 | Olson Kevin C. | Single or multi-layer printed circuit board with improved via design |
US20050241954A1 (en) * | 2004-05-03 | 2005-11-03 | Samsung Electro-Mechanics Co., Ltd. | Electrolytic gold plating method of printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
TWI331490B (en) | 2010-10-01 |
US20070132087A1 (en) | 2007-06-14 |
US7629692B2 (en) | 2009-12-08 |
JP4314263B2 (en) | 2009-08-12 |
KR100722625B1 (en) | 2007-05-28 |
JP2007165863A (en) | 2007-06-28 |
TW200723971A (en) | 2007-06-16 |
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