JP2008027938A - 不揮発性メモリ - Google Patents
不揮発性メモリ Download PDFInfo
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- JP2008027938A JP2008027938A JP2006195070A JP2006195070A JP2008027938A JP 2008027938 A JP2008027938 A JP 2008027938A JP 2006195070 A JP2006195070 A JP 2006195070A JP 2006195070 A JP2006195070 A JP 2006195070A JP 2008027938 A JP2008027938 A JP 2008027938A
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- source
- gate electrode
- memory
- memory cell
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- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000002784 hot electron Substances 0.000 description 12
- 230000010354 integration Effects 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】データを電気的に書き込み・消去可能なEEPROM等の不揮発性メモリにおいて、前記メモリを構成する各メモリセルが、半導体基板に形成されたソース/ドレイン領域23a、24a、23b、24bと、前記半導体基板のチャネル領域上に形成されるゲート電極27と、前記半導体基板と前記ゲート電極27との間に形成されるシリコン窒化膜を含む3層のゲート絶縁膜26とを備えている。そして、前記ゲート電極側27から平面的に見たときに、前記ソース/ドレイン領域23a、24a、23b、24bが前記チャネル領域から少なくとも3方向に延びる構成を採用する。
【選択図】図3
Description
22 第1半導体領域
23a,23b,24a,24b ソース/ドレイン領域
34a,34b,34c ソース/ドレイン領域
44a,44b,44c,44d,44e,44f ソース/ドレイン領域
29a,29a’、29b、29b’ ビット
39a,39b,39c ビット
49a,49b,49c,49d,49e,49f ビット
17,27 ゲート電極
Claims (5)
- データを電気的に書き込み・消去可能な不揮発性メモリにおいて、
前記メモリを構成する各メモリセルは、
半導体基板に形成されたソース/ドレイン領域と;
前記半導体基板のチャネル領域上に形成されるゲート電極と;
前記半導体基板と前記ゲート電極との間に形成されるゲート絶縁膜とを備え、
前記ゲート電極側から平面的に見たときに、前記ソース/ドレイン領域が前記チャネル領域から少なくとも3方向に延びることを特徴とする不揮発性メモリ。 - 前記ゲート絶縁膜は、第1及び第2の絶縁膜層と、これらの絶縁膜層の間に形成される誘電体層とを含むことを特徴とする請求項1に記載の不揮発性メモリ。
- 前記第1絶縁膜層および第2絶縁膜層がシリコン酸化膜からなり、前記誘電体層がシリコン窒化膜からなることを特徴とする請求項2に記載の不揮発性メモリ。
- メモリセルを平面的に見た場合に、前記ソース/ドレイン領域は、帯状に成形された前記ゲート電極上において交差する2本の帯状の拡散領域によって形成されることを特徴とする請求項1,2又は3に記載の不揮発性メモリ。
- メモリセルを平面的に見た場合に、前記ソース/ドレイン領域は、帯状に成形された前記ゲート電極上において交差する3本の帯状の拡散領域によって形成されることを特徴とする請求項1,2又は3に記載の不揮発性メモリ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006195070A JP2008027938A (ja) | 2006-07-18 | 2006-07-18 | 不揮発性メモリ |
US11/819,216 US7741674B2 (en) | 2006-07-18 | 2007-06-26 | Non-volatile memory with source/drains in multiple directions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006195070A JP2008027938A (ja) | 2006-07-18 | 2006-07-18 | 不揮発性メモリ |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008027938A true JP2008027938A (ja) | 2008-02-07 |
Family
ID=38970628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006195070A Pending JP2008027938A (ja) | 2006-07-18 | 2006-07-18 | 不揮発性メモリ |
Country Status (2)
Country | Link |
---|---|
US (1) | US7741674B2 (ja) |
JP (1) | JP2008027938A (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031698A (ja) * | 2001-07-11 | 2003-01-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2003282746A (ja) * | 2002-03-27 | 2003-10-03 | Fujitsu Ltd | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2005116667A (ja) * | 2003-10-06 | 2005-04-28 | Renesas Technology Corp | 半導体記憶装置及びその駆動方法 |
JP2006120719A (ja) * | 2004-10-19 | 2006-05-11 | Fujitsu Ltd | 不揮発性半導体記憶装置及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
DE10241173A1 (de) * | 2002-09-05 | 2004-03-11 | Infineon Technologies Ag | Halbleiterspeicher mit vertikalen Speichertransistoren in einer Zellenfeldanordnung mit 1-2F2-Zellen |
-
2006
- 2006-07-18 JP JP2006195070A patent/JP2008027938A/ja active Pending
-
2007
- 2007-06-26 US US11/819,216 patent/US7741674B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031698A (ja) * | 2001-07-11 | 2003-01-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2003282746A (ja) * | 2002-03-27 | 2003-10-03 | Fujitsu Ltd | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2005116667A (ja) * | 2003-10-06 | 2005-04-28 | Renesas Technology Corp | 半導体記憶装置及びその駆動方法 |
JP2006120719A (ja) * | 2004-10-19 | 2006-05-11 | Fujitsu Ltd | 不揮発性半導体記憶装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20080017919A1 (en) | 2008-01-24 |
US7741674B2 (en) | 2010-06-22 |
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