JP2007535779A - マルチビットフラッシュメモリデバイスの高性能な書込方法及びシステム - Google Patents
マルチビットフラッシュメモリデバイスの高性能な書込方法及びシステム Download PDFInfo
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- 230000015654 memory Effects 0.000 claims abstract description 119
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- 230000008859 change Effects 0.000 description 6
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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- Non-Volatile Memory (AREA)
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Abstract
【選択図】 図2
Description
Claims (10)
- 高速書込動作用のデュアルビットフラッシュメモリセル(316、318、320、322)のアレイ部を特定し、
書込動作前に上記特定された高速書込アレイ部に対し高速書込を可能にする消去動作(200)を実行し、
前記高速書込を可能にする消去動作は、高速書込用に特定されていないメモリセルの通常書込アレイ部からなる別のアレイ部に実行される消去動作とは異なる、マルチビットフラッシュメモリアレイを高速書込部と通常書き込部とに分割する方法。 - 前記高速書込を可能にする消去動作は、
上記特定された高速書込アレイ部の各セル(204)の第1ビット位置及び第2ビット位置の両方を消去し、
上記特定された高速書込アレイ部の各セル(206)の上記第1ビット位置に電荷を印加し、
上記第1ビット位置に上記印加された電荷は、ユーザデータとは関係ないために、引き続き各セルの上記第2ビット位置への高速書込動作を実行する、請求項1に記載の方法。 - 前記高速書込アレイ部の特定は、
コマンドレジスタ(354、406)に、前記特定された高速書込アレイ部に関連するコマンドレジスタ内の1つの位置での高速書込モードを示す値をロードし、
フラッシュメモリアレイ(402)を「高速書込モード」に設定し、
それ以降の全コマンドは高速書込部に関連するものとする、請求項1に記載の方法。 - さらに、マルチビットフラッシュメモリアレイの消去を実行することを含み、
前記消去の実行には、
消去すべき一部のメモリアレイを特定し(316)、
上記特定された消去すべきアレイ部に関連する1つの場所のコマンドレジスタ(354、406)のモードを判断し、
前記判断に基づいて前記特定されたアレイ部に、高速書込消去動作(410)または、前記高速書込消去動作とは異なる通常消去動作(412)のいずれかを実行する、請求項3に記載の方法。 - 前記アレイ部(402)は、互いに物理的に連続していない複数のメモリブロックから構成される、請求項1に記載の方法。
- 複数のアレイ部で構成されるマルチビットフラッシュメモリセルから構成されるコアセルアレイ(402)と、
前記複数のアレイ部を高速書込部及び通常書込部の一方に分割するよう構成される制御回路(404)と、から構成されるマルチビットフラッシュメモリ(400)。 - 前記制御回路(404)は、前記コアセルアレイの前記高速書込アレイ部に対して、高速書込ブロック消去動作を実行するように構成される高速書込制御論理回路(410)を備え、
前記高速書込制御論理回路(410)は、前記高速書込ブロック消去動作において、電荷を除去することで前記高速書込アレイ部の各フラッシュメモリセルの第1ビット位置及び第2ビット位置の両方をブロック消去(204)するように構成され、さらに、その後前記高速書込アレイ部の各セルの前記第1ビット位置に電荷を印加する(206)ことにより、引き続き実行される、前記高速書込アレイ部の1つ以上のセルの第2ビット位置に対する高速書込動作(208)を容易にする、請求項6に記載のマルチビットフラッシュメモリ。 - さらにコマンドレジスタ(354、406)を備え、
前記複数のアレイ部に関連する複数の記憶位置を含み、かつ前記記憶位置に前記アレイ部が高速書込アレイ部か通常書込アレイ部かを示すデータを含み、
前記制御回路(404)は、前記複数のアレイ部を分割するコマンドレジスタ(359、406)にアクセスするように構成される、請求項6に記載のマルチビットメモリ。 - 前記コマンドレジスタ(406)に接続するユーザI/Oインターフェイス(408)をさらに備え、ユーザによる前記複数のアレイ部の前記分割を容易にするように構成される、請求項8に記載のマルチビットメモリ。
- それぞれ通常及び高速書込区分に分割される複数のメモリ区分(402)と、
フラッシュメモリの前記通常書込区分及び高速書込区分に、書込、消去、及び読取の動作コマンドを入力するように構成される制御回路(404)と、を備え、
前記通常書込区分と前記高速書込区分とに対する前記制御回路の前記書込コマンドは異なり、
前記高速書込区分に関連する前記書込コマンドがセットアップモードを含み、
ユーザデータを保持するようには構成されていない第1ビットは第1の状態に設定される、マルチビットフラッシュメモリ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US56304604P | 2004-04-16 | 2004-04-16 | |
US11/037,477 US7206224B1 (en) | 2004-04-16 | 2005-01-18 | Methods and systems for high write performance in multi-bit flash memory devices |
PCT/US2005/004552 WO2005106891A1 (en) | 2004-04-16 | 2005-02-11 | Methods and systems for high write performance in multi-bit flash memory devices |
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JP2007535779A true JP2007535779A (ja) | 2007-12-06 |
JP4674234B2 JP4674234B2 (ja) | 2011-04-20 |
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JP2007508335A Expired - Fee Related JP4674234B2 (ja) | 2004-04-16 | 2005-02-11 | マルチビットフラッシュメモリデバイスの高性能な書込方法及びシステム |
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US (2) | US7206224B1 (ja) |
JP (1) | JP4674234B2 (ja) |
KR (1) | KR101092011B1 (ja) |
DE (1) | DE112005000866T5 (ja) |
GB (1) | GB2427947B (ja) |
TW (1) | TWI397914B (ja) |
WO (1) | WO2005106891A1 (ja) |
Cited By (1)
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KR100902008B1 (ko) * | 2007-02-09 | 2009-06-12 | 삼성전자주식회사 | 메모리 셀에 멀티 비트 데이터를 저장하는 플래시 메모리를 포함한 메모리 시스템 |
JP5032290B2 (ja) * | 2007-12-14 | 2012-09-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
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- 2005-02-11 JP JP2007508335A patent/JP4674234B2/ja not_active Expired - Fee Related
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- 2005-02-11 GB GB0620164A patent/GB2427947B/en not_active Expired - Fee Related
- 2005-02-11 DE DE112005000866T patent/DE112005000866T5/de not_active Ceased
- 2005-04-06 TW TW094110806A patent/TWI397914B/zh not_active IP Right Cessation
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- 2006-11-01 KR KR1020067022965A patent/KR101092011B1/ko active IP Right Grant
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TW200608406A (en) | 2006-03-01 |
US7206224B1 (en) | 2007-04-17 |
GB0620164D0 (en) | 2006-11-22 |
WO2005106891A1 (en) | 2005-11-10 |
KR20070010160A (ko) | 2007-01-22 |
US20070115730A1 (en) | 2007-05-24 |
KR101092011B1 (ko) | 2011-12-09 |
GB2427947A (en) | 2007-01-10 |
GB2427947B (en) | 2007-08-08 |
US7283402B2 (en) | 2007-10-16 |
TWI397914B (zh) | 2013-06-01 |
DE112005000866T5 (de) | 2007-03-08 |
JP4674234B2 (ja) | 2011-04-20 |
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