JP2007522683A - マルチゲート構造の半導体素子及びその製造方法 - Google Patents
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Abstract
Description
122 第1側面
124 第2側面
126 上面
140a 第2活性領域
150 絶縁膜
150a ゲート絶縁膜
160a ゲートライン
Claims (37)
- 基板上で相互逆方向である第1側面、第2側面及び上面をそれぞれ有する複数のスラブから構成される第1活性領域と、
前記複数のスラブを相互連結させるように、前記基板上で前記スラブの少なくとも一端部に接して延びている第2活性領域と、
前記スラブの少なくとも第1側面、第2側面及び上面上に形成されているゲートラインと、
前記スラブと前記ゲートラインとの間に介在されているゲート絶縁膜とを備えることを特徴とする半導体素子。 - 前記第1活性領域は、ライン・アンド・スペースパターン状に形成されたことを特徴とする請求項1に記載の半導体素子。
- 前記第2活性領域は、前記第1活性領域とは異なる物質からなることを特徴とする請求項1に記載の半導体素子。
- 前記スラブの上面は、前記基板から第1距離ほど離隔されており、
前記第2活性領域は、前記基板から前記第1距離と同じであるか、またはさらに長い第2距離ほど離隔されている上面を有することを特徴とする請求項1に記載の半導体素子。 - 前記第2距離は、前記第1距離より長いことを特徴とする請求項4に記載の半導体素子。
- 前記第2距離は、第1距離と同じであることを特徴とする請求項4に記載の半導体素子。
- 前記第2活性領域は、前記スラブの両端部に接している状態で、前記スラブの延長方向と直交する方向に延びていることを特徴とする請求項1に記載の半導体素子。
- 前記第2活性領域は、前記スラブのうち、前記第1側面、第2側面及び上面の一部と接して延びているオーバーラップ領域を有することを特徴とする請求項1に記載の半導体素子。
- 前記第1活性領域は、単結晶シリコンからなり、
前記第2活性領域は、ポリシリコン、非晶質シリコン、またはシリコンを含有する半導体化合物からなることを特徴とする請求項1に記載の半導体素子。 - 前記第1活性領域及び第2活性領域は、ソース/ドレイン領域を構成することを特徴とする請求項1に記載の半導体素子。
- 前記第1活性領域は、チャンネル領域を備えることを特徴とする請求項1に記載の半導体素子。
- 前記ゲートラインは、前記スラブの延長方向と直交する方向に延びていることを特徴とする請求項1に記載の半導体素子。
- 前記ゲートラインは、前記第2活性領域の延長方向と平行な方向に延びていることを特徴とする請求項1に記載の半導体素子。
- 前記ゲートラインは、導電性ポリシリコン、金属、金属窒化物または金属シリサイドからなることを特徴とする請求項1に記載の半導体素子。
- 前記ゲート絶縁膜は、SiO2、SiON、Si3N4、GexOyNz 、GexSiyOz 、HfO2、ZrO2、Al2O3、TiO2またはTa2O5を含むことを特徴とする請求項1に記載の半導体素子。
- 前記基板は、埋没酸化膜及びシリコン層を備えるSOI基板であり、
前記第1活性領域及び第2活性領域は、前記埋没酸化膜上に形成されていることを特徴とする請求項1に記載の半導体素子。 - 前記第1活性領域のうち、前記スラブの第1側面及び第2側面に近接して、前記ゲートラインと対面する部分にそれぞれ位置する第1チャンネル領域及び第2チャンネル領域をさらに備えることを特徴とする請求項1に記載の半導体素子。
- 前記第1活性領域のうち、前記スラブの上面に近接して、前記ゲートラインと対面する部分に位置する第3チャンネル領域をさらに備えることを特徴とする請求項17に記載の半導体素子。
- 第1物質からなる第1活性領域を基板上に形成する工程と、
前記第1活性領域の少なくとも一部に接して延び、第2物質からなる第2活性領域を前記基板上に形成する工程と、
前記第1活性領域上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲートを形成する工程とを含むことを特徴とする半導体素子の製造方法。 - 前記第1活性領域は、ライン・アンド・スペースパターン形状を有することを特徴とする請求項19に記載の半導体素子の製造方法。
- 前記第2物質は、前記第1物質とは異なる物質であることを特徴とする請求項19に記載の半導体素子の製造方法。
- 前記第1活性領域を形成する工程では、相互逆方向である第1側面、第2側面及び上面をそれぞれ有し、前記基板上に第1方向に延びる複数のスラブを形成することを特徴とする請求項19に記載の半導体素子の製造方法。
- 前記スラブの上面は、前記基板から第1距離ほど離隔されており、
前記第2活性領域は、前記基板から前記第1距離と同じでるか、またはそれより長い第2距離ほど離隔されている上面を有するように形成されることを特徴とする請求項22に記載の半導体素子の製造方法。 - 前記第2活性領域は、前記スラブの両端部に接しつつ、前記第1方向と直交する第2方向に延びるように形成されることを特徴とする請求項22に記載の半導体素子の製造方法。
- 前記第2活性領域は、前記スラブのうち、前記第1側面、第2側面及び上面の一部と接して延びているオーバーラップ領域を有するように形成されることを特徴とする請求項22に記載の半導体素子の製造方法。
- 前記第2活性領域を形成する工程は、
前記スラブの両端部を露出させるように、前記スラブの一部を覆うマスクパターンを前記基板上に形成する工程と、
前記第2物質を蒸着して、前記スラブの露出された両端部及び前記マスクパターンを覆う第2物質層を形成する工程と、
前記第2物質層を平坦化して前記第2活性領域を形成する工程とを含むことを特徴とする請求項22に記載の半導体素子の製造方法。 - 前記マスクパターンは、SiON膜、Si3N4膜またはSiO2膜から構成される単一膜、または、それらの組み合わせから構成される多重膜からなることを特徴とする請求項26に記載の半導体素子の製造方法。
- 前記マスクパターンは、SiON膜及びSi3N4膜から構成される二重膜からなることを特徴とする請求項27に記載の半導体素子の製造方法。
- 前記マスクパターンが形成された後、前記マスクパターンの周りで、前記複数のスラブのそれぞれの上面が一部露出されるように、前記マスクパターンは、前記スラブの上面の一部のみを覆うことを特徴とする請求項26に記載の半導体素子の製造方法。
- 前記第2物質層を平坦化するに当って、前記マスクパターンをエッチング停止層として利用することを特徴とする請求項26に記載の半導体素子の製造方法。
- 前記マスクパターンは、前記スラブに接したSiON膜と、前記マスクパターンの上面を構成するSi3N4膜とを備えることを特徴とする請求項30に記載の半導体素子の製造方法。
- 前記第2物質層を平坦化するために、CMPまたはエッチバック方法を利用することを特徴とする請求項26に記載の半導体素子の製造方法。
- 前記第1物質は、単結晶シリコンであり、
前記第2物質は、ポリシリコン、非晶質シリコン、またはシリコンを含有する半導体化合物からなることを特徴とする請求項19に記載の半導体素子の製造方法。 - 前記ゲート絶縁膜は、SiO2、SiON、Si3N4、GexOyNz 、GexSiyOz 、HfO2、ZrO2、Al2O3、TiO2またはTa2O5を含むことを特徴とする請求項19に記載の半導体素子の製造方法。
- 前記ゲートを形成するために、前記スラブのうち、前記第1側面、第2側面及び上面を覆うように、前記第1方向と直交する第2方向に延びるゲートラインを形成することを特徴とする請求項22に記載の半導体素子の製造方法。
- 前記ゲートラインは、導電性ポリシリコン、金属、金属窒化物または金属シリサイドからなることを特徴とする請求項35に記載の半導体素子の製造方法。
- 前記基板として、埋没酸化膜と、その上に形成された単結晶シリコン層とを備えるSOI基板を準備する工程をさらに含み、
前記第1活性領域は、前記単結晶シリコン層をパターニングして形成されることを特徴とする請求項19に記載の半導体素子の製造方法。
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KR1020040010472A KR100574971B1 (ko) | 2004-02-17 | 2004-02-17 | 멀티-게이트 구조의 반도체 소자 및 그 제조 방법 |
PCT/KR2005/000357 WO2005078804A1 (en) | 2004-02-17 | 2005-02-05 | Semiconductor device having multi-gate structure and method of manufacturing the same |
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US (2) | US7838915B2 (ja) |
JP (1) | JP4642786B2 (ja) |
KR (1) | KR100574971B1 (ja) |
CN (1) | CN100472806C (ja) |
DE (1) | DE112005000394B4 (ja) |
WO (1) | WO2005078804A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012525004A (ja) * | 2009-04-21 | 2012-10-18 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多重Vt電界効果トランジスタ素子 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7566623B2 (en) | 2007-02-02 | 2009-07-28 | Freescale Semiconductor, Inc. | Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device |
US8518767B2 (en) | 2007-02-28 | 2013-08-27 | International Business Machines Corporation | FinFET with reduced gate to fin overlay sensitivity |
US7452758B2 (en) * | 2007-03-14 | 2008-11-18 | International Business Machines Corporation | Process for making FinFET device with body contact and buried oxide junction isolation |
US8063437B2 (en) * | 2007-07-27 | 2011-11-22 | Panasonic Corporation | Semiconductor device and method for producing the same |
US8004045B2 (en) | 2007-07-27 | 2011-08-23 | Panasonic Corporation | Semiconductor device and method for producing the same |
JP2010056541A (ja) | 2008-07-31 | 2010-03-11 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP5718585B2 (ja) * | 2010-05-19 | 2015-05-13 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法、並びにデータ処理システム |
US8377759B2 (en) | 2010-08-17 | 2013-02-19 | International Business Machines Corporation | Controlled fin-merging for fin type FET devices |
US8383490B2 (en) | 2011-07-27 | 2013-02-26 | International Business Machines Corporation | Borderless contact for ultra-thin body devices |
KR101262643B1 (ko) * | 2011-10-17 | 2013-05-08 | 숭실대학교산학협력단 | 멀티 트랜지스터 |
CN103578996B (zh) * | 2012-07-27 | 2016-09-28 | 中芯国际集成电路制造(上海)有限公司 | 晶体管制造方法 |
US9240352B2 (en) * | 2012-10-24 | 2016-01-19 | Globalfoundries Inc. | Bulk finFET well contacts with fin pattern uniformity |
CN103219384B (zh) * | 2013-04-03 | 2015-05-20 | 北京大学 | 一种抗单粒子辐射的多栅器件及其制备方法 |
US8912609B2 (en) * | 2013-05-08 | 2014-12-16 | International Business Machines Corporation | Low extension resistance III-V compound fin field effect transistor |
CN106415800B (zh) | 2013-12-19 | 2020-04-14 | 英特尔公司 | 自对准栅极边缘和局部互连件及其制造方法 |
US9064890B1 (en) * | 2014-03-24 | 2015-06-23 | Globalfoundries Inc. | Methods of forming isolation material on FinFET semiconductor devices and the resulting devices |
US9871104B2 (en) * | 2015-06-30 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nanowire semiconductor device structure and method of manufacturing |
US10181526B2 (en) | 2016-06-02 | 2019-01-15 | Samsung Electronics Co., Ltd. | Field effect transistor including multiple aspect ratio trapping structures |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6315471A (ja) * | 1986-07-07 | 1988-01-22 | Seiko Instr & Electronics Ltd | 薄膜トランジスタとその製造方法 |
JPH04268767A (ja) * | 1991-02-25 | 1992-09-24 | Fujitsu Ltd | 半導体装置 |
JPH08181323A (ja) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2572003B2 (ja) * | 1992-03-30 | 1997-01-16 | 三星電子株式会社 | 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法 |
US6118161A (en) * | 1997-04-30 | 2000-09-12 | Texas Instruments Incorporated | Self-aligned trenched-channel lateral-current-flow transistor |
US6365465B1 (en) * | 1999-03-19 | 2002-04-02 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
JP2003017508A (ja) * | 2001-07-05 | 2003-01-17 | Nec Corp | 電界効果トランジスタ |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
JP4141138B2 (ja) | 2001-12-21 | 2008-08-27 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
KR100521377B1 (ko) | 2003-02-21 | 2005-10-12 | 삼성전자주식회사 | 핀 전계효과 트랜지스터의 형성방법 |
US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US6716686B1 (en) * | 2003-07-08 | 2004-04-06 | Advanced Micro Devices, Inc. | Method for forming channels in a finfet device |
US7186599B2 (en) * | 2004-01-12 | 2007-03-06 | Advanced Micro Devices, Inc. | Narrow-body damascene tri-gate FinFET |
-
2004
- 2004-02-17 KR KR1020040010472A patent/KR100574971B1/ko active IP Right Grant
-
2005
- 2005-02-05 CN CNB200580009982XA patent/CN100472806C/zh active Active
- 2005-02-05 WO PCT/KR2005/000357 patent/WO2005078804A1/en active Application Filing
- 2005-02-05 US US10/590,101 patent/US7838915B2/en active Active
- 2005-02-05 DE DE112005000394T patent/DE112005000394B4/de active Active
- 2005-02-05 JP JP2006554019A patent/JP4642786B2/ja active Active
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2010
- 2010-10-20 US US12/908,452 patent/US20110033989A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6315471A (ja) * | 1986-07-07 | 1988-01-22 | Seiko Instr & Electronics Ltd | 薄膜トランジスタとその製造方法 |
JPH04268767A (ja) * | 1991-02-25 | 1992-09-24 | Fujitsu Ltd | 半導体装置 |
JPH08181323A (ja) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012525004A (ja) * | 2009-04-21 | 2012-10-18 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多重Vt電界効果トランジスタ素子 |
Also Published As
Publication number | Publication date |
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KR100574971B1 (ko) | 2006-05-02 |
US7838915B2 (en) | 2010-11-23 |
JP4642786B2 (ja) | 2011-03-02 |
DE112005000394T5 (de) | 2007-02-22 |
US20110033989A1 (en) | 2011-02-10 |
CN100472806C (zh) | 2009-03-25 |
CN1938861A (zh) | 2007-03-28 |
KR20050082099A (ko) | 2005-08-22 |
DE112005000394B4 (de) | 2008-07-17 |
WO2005078804A1 (en) | 2005-08-25 |
US20070272925A1 (en) | 2007-11-29 |
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