JP2007514221A - メモリコントローラ - Google Patents
メモリコントローラ Download PDFInfo
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- JP2007514221A JP2007514221A JP2006543402A JP2006543402A JP2007514221A JP 2007514221 A JP2007514221 A JP 2007514221A JP 2006543402 A JP2006543402 A JP 2006543402A JP 2006543402 A JP2006543402 A JP 2006543402A JP 2007514221 A JP2007514221 A JP 2007514221A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
【解決手段】本発明によると、メモリコントローラ(1)は、コマンドに対して静的に割り当てられた優先度と、チャネルに対して動的に割り当てられる優先度に基づきメモリバンクコマンド伝送の優先度を割り当てるコマンドスケジューラ(3)を備えている。
【選択図】図3
Description
2 SDRAMモジュール
3 コマンドスケジューラ
4 メモリバンク制御ユニット
5 メモリバンクスケジューリングユニット
6 入力チャネル
7 出力チャネル
8 AMBAバス
21、22、23、24 メモリバンク
31 コマンド分析器
32 スケジューラ
33 優先度割当ユニット
34 レジスタファイル
41、42、43、44 ステートマシン
Claims (14)
- 少なくとも1つのメモリバンク(21、22、23、24)を有し、少なくとも1つのチャネル(6、7、8)経由でICと通信する外部DRAM(2)と、該ICとの通信方法において、
メモリバンクコマンド伝送の優先度は、コマンドに対して静的に割り当てられた優先度と、チャネルに対して動的に割り当てられる優先度に基づき割り当てられること、
を特徴とする方法。 - 静的に優先度が割り当てられるコマンドは、最も高い優先度である“バースト終了”コマンド、2番目に高い優先度である“読み出し”又は“書き込み”コマンド、3番目に高い優先度である“アクティベート”コマンド、及び、最も低い優先度である“プリチャージ”コマンドを含むこと、
を特徴とする請求項1に記載の方法。 - 動的に優先度が割り当てられるチャネルは、コマンド送信後、最も低い優先度が割り当てられるチャネルを含むこと、
を特徴とする請求項1又は2に記載の方法。 - 動的に優先度が割り当てられるチャネルは、現在のクロックサイクルにおいて最も高い優先度でなく、他のチャネル(6、7、8)がコマンドを送信したとき、次のクロックサイクルにおいて最も高い優先度が割り当てられるチャネル(6、7、8)を含むこと、
を特徴とする請求項1から3のいずれか1項に記載の方法。 - 動的に優先度が割り当てられるチャネルは、コマンドを送信したときのみ最も高い優先度を失うチャネル(6、7、8)を含むこと、
を特徴とする請求項1から4のいずれか1項に記載の方法。 - チャネル(6、7、8)は、外部DRAM(2)の物理的に異なる記憶領域にアクセスすること、
を特徴とする請求項1からの5のいずれか1項に記載の方法。 - チャネル(6、7、8)は、外部DRAM(2)の共通して使用する記憶領域に対して、連続するアクセス操作を行わないこと、
を特徴とする請求項1からの5のいずれか1項に記載の方法。 - 少なくとも1つのチャネル(6、7、8)がいくつかのメモリバンク(21、22、23、24)にアクセスできるように、ネットワーク(5)が設けられていること、
を特徴とする請求項1から7のいずれか1項に記載の方法。 - 1つのメモリバンク(21、22、23、24)への2つのアクセス操作の間には、他のメモリバンク(21、22、23、24)へのアクセス操作を持つこと、
を特徴とする請求項1から8のいずれか1項に記載の方法。 - 1つのメモリバンク(21、22、23、24)への2つの連続するアクセス操作は、メモリバンク(21、22、23、24)の同じロウに対して行われる場合に許可されること、
を特徴とする請求項1から9のいずれか1項に記載の方法。 - メモリバンク(21、22、23、24)の状態は、対応するステートマシン(41、42、43、44)により示されること、
を特徴とする請求項1から10のいずれか1項に記載の方法。 - 複数のDRAMモジュールが使用され、モジュール選択のため、チップイネーブル信号が送信されること、
を特徴とする請求項1から11のいずれか1項に記載の方法。 - 少なくとも1つのメモリバンク(21、22、23、24)を有し、少なくとも1つのチャネル(6、7、8)経由でICと通信する外部DRAM(2)を使用する該ICのためのメモリコントローラにおいて、
コマンドに対して静的に割り当てられた優先度と、チャネルに対して動的に割り当てられる優先度に基づきメモリバンクコマンド伝送の優先度を割り当てるコマンドスケジューラを有することを特徴とするメモリコントローラ。 - 記録媒体の記録再生装置であって、
請求項1から12のいずれか1項に記載の方法を使用する、又は、請求項13に記載のメモリコントローラ(1)を有すること、
を特徴とする記録再生装置。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10357697.5 | 2003-12-09 | ||
DE10357697 | 2003-12-09 | ||
DE102004009428.4 | 2004-02-24 | ||
DE200410009428 DE102004009428A1 (de) | 2004-02-24 | 2004-02-24 | Speicher-Controller |
PCT/EP2004/012940 WO2005059764A1 (en) | 2003-12-09 | 2004-11-15 | Memory controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007514221A true JP2007514221A (ja) | 2007-05-31 |
JP5005350B2 JP5005350B2 (ja) | 2012-08-22 |
Family
ID=34701981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006543402A Expired - Fee Related JP5005350B2 (ja) | 2003-12-09 | 2004-11-15 | メモリコントローラ |
Country Status (7)
Country | Link |
---|---|
US (1) | US7873797B2 (ja) |
EP (1) | EP1692617B1 (ja) |
JP (1) | JP5005350B2 (ja) |
KR (1) | KR101198981B1 (ja) |
CN (1) | CN1882928B (ja) |
DE (1) | DE602004020504D1 (ja) |
WO (1) | WO2005059764A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
EP1692617B1 (en) | 2009-04-08 |
EP1692617A1 (en) | 2006-08-23 |
CN1882928A (zh) | 2006-12-20 |
US20070091696A1 (en) | 2007-04-26 |
WO2005059764A1 (en) | 2005-06-30 |
JP5005350B2 (ja) | 2012-08-22 |
US7873797B2 (en) | 2011-01-18 |
CN1882928B (zh) | 2011-03-23 |
DE602004020504D1 (de) | 2009-05-20 |
KR20060127400A (ko) | 2006-12-12 |
KR101198981B1 (ko) | 2012-11-07 |
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