JP2007511091A5 - - Google Patents

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Publication number
JP2007511091A5
JP2007511091A5 JP2006539568A JP2006539568A JP2007511091A5 JP 2007511091 A5 JP2007511091 A5 JP 2007511091A5 JP 2006539568 A JP2006539568 A JP 2006539568A JP 2006539568 A JP2006539568 A JP 2006539568A JP 2007511091 A5 JP2007511091 A5 JP 2007511091A5
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JP
Japan
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JP2006539568A
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Japanese (ja)
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JP2007511091A (ja
JP4854514B2 (ja
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Priority claimed from PCT/US2004/036048 external-priority patent/WO2005048302A2/en
Publication of JP2007511091A publication Critical patent/JP2007511091A/ja
Publication of JP2007511091A5 publication Critical patent/JP2007511091A5/ja
Application granted granted Critical
Publication of JP4854514B2 publication Critical patent/JP4854514B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006539568A 2003-11-05 2004-10-29 既製チップ構造を機能性電子システムに集積する方法 Expired - Lifetime JP4854514B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US51743203P 2003-11-05 2003-11-05
US60/517,432 2003-11-05
PCT/US2004/036048 WO2005048302A2 (en) 2003-11-05 2004-10-29 Method for integrating pre-fabricated chip structures into functional electronic systems

Publications (3)

Publication Number Publication Date
JP2007511091A JP2007511091A (ja) 2007-04-26
JP2007511091A5 true JP2007511091A5 (enExample) 2011-02-03
JP4854514B2 JP4854514B2 (ja) 2012-01-18

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Family Applications (1)

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JP2006539568A Expired - Lifetime JP4854514B2 (ja) 2003-11-05 2004-10-29 既製チップ構造を機能性電子システムに集積する方法

Country Status (4)

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US (2) US7338836B2 (enExample)
EP (1) EP1680803B1 (enExample)
JP (1) JP4854514B2 (enExample)
WO (1) WO2005048302A2 (enExample)

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