JP2007508688A - 電子装置及びそのためのキャリア基板 - Google Patents
電子装置及びそのためのキャリア基板 Download PDFInfo
- Publication number
- JP2007508688A JP2007508688A JP2006530964A JP2006530964A JP2007508688A JP 2007508688 A JP2007508688 A JP 2007508688A JP 2006530964 A JP2006530964 A JP 2006530964A JP 2006530964 A JP2006530964 A JP 2006530964A JP 2007508688 A JP2007508688 A JP 2007508688A
- Authority
- JP
- Japan
- Prior art keywords
- carrier substrate
- pads
- contact pads
- core
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
11 集積回路Vdd、perifI/O路ボンド・パッド
12 コア機能部供給電圧Vdd、core用集積回路ボンド・パッド
13 (コア機能部)接地Vss用集積回路ボンド・パッド
15 熱拡散層
18 集積回路の(第1の)面
19 接着層
20 キャリア基板
20A キャリア基板の誘電体層
20B キャリア基板の第1面上の導電層
20C キャリア基板の第2面上の導電層
21 キャリア基板の第1の面
22 キャリア基板の第2の面
29 補剛材/補剛材層
31 コア領域
32 周辺領域
41 (コア機能部)接地Vss用キャリア基板ボンド・パッド
42 コア機能部供給電圧Vdd、core用キャリア基板ボンド・パッド
43 周辺機能部供給電圧Vdd、perif及びI/O路用キャリア基板ボンド・パッド
49 ボンド・ワイヤ
51 キャリア基板の第2面上の周辺領域内接地面
52 キャリア基板の第1面上のコア領域内接地面
53 伝送線(伝送線特性を有する相互接続部)
61 コア機能部接地Vss、core用コンタクト・パッド(及びはんだボール)
62 コア機能部供給電圧Vdd、core用コンタクト・パッド(及びはんだボール)
63 信号伝送I/O用コンタクト・パッド(及びはんだボール)
64 周辺機能部接地Vss、perif用コンタクト・パッド(及びはんだボール)
65 周辺機能部供給電圧Vss、perif、Vdd、perif用コンタクト・パッド(はんだボール)
66 垂直相互接続部
67 水平相互接続部
73 信号伝送用コンタクト・パッド向け垂直相互接続部
74 周辺領域接地Vss、perif用コンタクト・パッド向け垂直相互接続部
75 周辺領域供給電圧Vss、perif、Vdd、perif用コンタクト・パッド向け垂直相互接続部
100 電子装置
164 接地用の一つの中心パッドを有するコンタクト・パッドのサブグループ
165 接地又は電圧供給用の一つの中心パッドを有するコンタクト・パッドのサブグループ
110 半導体装置10のコア機能部
111 デカップリング・コンデンサ
112 コア能動素子
210 半導体装置10の周辺機能部
211 デカップリング手段、特に、デカップリング・コンデンサ
212 周辺能動素子
301 電源
302 インダクタ
303 負荷コンデンサ
Claims (10)
- 側面に複数のボンド・パッドが設けられた少なくとも一つの半導体装置と、
電気的絶縁材料の層を備え、導電層が各々設けられた第1の面及び反対側の第2の面を有し、前記第1の面上には前記集積回路の前記複数のボンド・パッドへの結合に適する複数のボンド・パッドが存在し、前記第2の面上には外部結合用の複数のコンタクト・パッドが存在し、前記複数のコンタクト・パッドと前記複数のボンド・パッドとが所望のパターンに従って電気的に相互接続され、前記複数のコンタクト・パッドの第1の部分が接地接続用に画定され、前記複数のコンタクト・パッドの第2の部分が電圧供給接続用に画定され、そして、前記複数のコンタクト・パッドの第3の部分が信号伝送用に画定されている、キャリア基板とを備えた電子装置であって、
前記少なくとも一つの半導体装置にはコア機能部と周辺機能部とが設けられ、前記コア機能部及び周辺機能部には各々電圧供給接続部と接地接続部とが設けられ、
前記キャリア基板はコア領域と周辺領域とに横方向に細分化され、前記コア領域には前記コア機能部用の複数のコンタクト・パッドが設けられ、前記周辺領域には前記周辺機能部用の複数のコンタクト・パッドが設けられ、
前記キャリア基板は、前記周辺機能部の前記接地接続部と前記コア機能部の前記接地接続部とを相互接続するための少なくとも一つの相互接続部を備え、
前記コア機能部及び周辺機能部の電圧供給を共通接地に対してデカップリングするための手段が存在する電子装置。 - 前記周辺領域は前記コア領域の周辺に位置し、
前記キャリア基板の前記第2面上の前記周辺領域内に接地面が画定され、該接地面は、前記周辺機能部の前記接地接続部と前記コア機能部の前記接地接続部とを互いに相互接続するための相互接続部であり、
前記周辺機能部の前記複数のコンタクト・パッドと前記複数のボンド・パッドとの間の相互接続部が前記キャリア基板の前記第1面上に画定され、前記相互接続部は伝送線特性を有する、請求項1に記載の電子装置。 - 前記デカップリング手段は前記周辺機能部内にデカップリング・コンデンサを備え、該デカップリング・コンデンサは前記少なくとも一つの半導体装置内に又は前記キャリア基板上に位置する、請求項1又は2に記載の電子装置。
- 前記コア領域内の前記複数のコンタクト・パッドはアレイに画定され、前記接地接続用の前記複数のパッドの各々が最も近傍の複数パッドとして電圧供給接続用の複数のパッドを有するように、前記複数の接地接続及び前記電圧供給接続用パッドが前記アレイ内に配される、請求項2に記載の電子装置。
- 前記周辺領域内の前記複数のコンタクト・パッドは複数のサブグループに画定され、各サブグループは、1個の電圧接続用コンタクト・パッド又は1個の接地接続用コンタクト・パッドといくつかの信号伝送用コンタクト・パッドとを備え、前記信号伝送用パッドはすべて、前記電圧接続又は接地接続用コンタクト・パッドを隣接パッドとして備える、請求項2に記載の電子装置。
- 前記コア領域内において、前記接地面が前記キャリア基板の前記第1面上に画定され、そして、垂直相互接続部を介して、前記周辺領域内の前記接地面に結合される、請求項2又は4に記載の電子装置。
- 前記キャリア基板の前記第1の面上に機械的補剛材層が存在し、前記導電層の一部を覆う、請求項1又は2に記載の電子装置。
- 前記半導体装置がフリップチップ方向に前記キャリア基板上に設置され、前記半導体装置における前記複数のボンド・パッドと、前記キャリア基板の前記第1の面上の前記複数のコンタクト・パッドとが対応する態様で配置され、前記キャリア基板の前記第1面上と、前記複数のボンド・パッドの側部から背けられた前記半導体装置の側部上とに放熱層が設けられている、請求項1又は7に記載の電子装置。
- 電源直列インダクタがさらに設けられている、請求項1に記載の電子装置。
- 半導体装置のための、電気的絶縁材料のキャリア基板であって、導電層が各々設けられた第1の面及び反対側の第2の面を有し、前記第1の面上には前記半導体装置の複数のボンド・パッドへの結合に適する複数のボンド・パッドが存在し、前記第2の面上には外部結合用の複数のコンタクト・パッドが存在し、前記複数のコンタクト・パッドと前記複数のボンド・パッドとが所望のパターンに従って電気的に相互接続され、前記複数のコンタクト・パッドの第1の部分が接地接続用に画定され、前記複数のコンタクト・パッドの第2の部分が電圧供給接続用に画定され、そして、前記複数のコンタクト・パッドの第3の部分が信号伝送用に画定されている、キャリア基板であって、
前記キャリア基板はコア領域と周辺領域機能部とに横方向に細分化され、前記コア領域には前記集積回路のコア機能部のための複数のコンタクト・パッドが設けられ、前記周辺領域には前記半集積回路の周辺機能部のための複数のコンタクト・パッドが設けられ、前記コア機能部及び周辺機能部には各々電圧供給接続部と接地接続部とが設けられ、
前記キャリア基板は、前記周辺機能部の前記接地接続部と前記コア機能部の前記接地接続部とを相互接続するための少なくとも一つの相互接続部を備えるキャリア基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03103758 | 2003-10-10 | ||
PCT/IB2004/051945 WO2005036643A1 (en) | 2003-10-10 | 2004-10-01 | Electronic device and carrier substrate for same |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007508688A true JP2007508688A (ja) | 2007-04-05 |
Family
ID=34429470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006530964A Pending JP2007508688A (ja) | 2003-10-10 | 2004-10-01 | 電子装置及びそのためのキャリア基板 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7253516B2 (ja) |
EP (1) | EP1673807B1 (ja) |
JP (1) | JP2007508688A (ja) |
KR (1) | KR101099925B1 (ja) |
CN (1) | CN100550365C (ja) |
TW (1) | TWI353663B (ja) |
WO (1) | WO2005036643A1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101098709B1 (ko) * | 2003-10-10 | 2011-12-23 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 전자 장치 및 캐리어 기판 |
US7272802B2 (en) * | 2005-05-11 | 2007-09-18 | Lsi Corporation | R-cells containing CDM clamps |
US8643163B2 (en) * | 2005-08-08 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit package-on-package stacking system and method of manufacture thereof |
KR101247138B1 (ko) * | 2005-09-14 | 2013-03-29 | 하테체 베타일리궁스 게엠베하 | 플립-칩 모듈 및 플립-칩 모듈의 제조 방법 |
US7518230B2 (en) * | 2005-12-14 | 2009-04-14 | Rohm Co., Ltd | Semiconductor chip and semiconductor device |
US20080197474A1 (en) * | 2007-02-16 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with multi-chips and method of the same |
US8946873B2 (en) | 2007-08-28 | 2015-02-03 | Micron Technology, Inc. | Redistribution structures for microfeature workpieces |
KR101006748B1 (ko) * | 2009-01-29 | 2011-01-10 | (주)인디링스 | 패드들의 동시 스위칭을 제어하는 고체 상태 디스크를 위한컨트롤러 |
TWI452665B (zh) * | 2010-11-26 | 2014-09-11 | 矽品精密工業股份有限公司 | 具防靜電破壞及防電磁波干擾之封裝件及其製法 |
US8628636B2 (en) * | 2012-01-13 | 2014-01-14 | Advance Materials Corporation | Method of manufacturing a package substrate |
US9515017B2 (en) * | 2014-12-18 | 2016-12-06 | Intel Corporation | Ground via clustering for crosstalk mitigation |
JP6337867B2 (ja) * | 2015-10-26 | 2018-06-06 | 株式会社村田製作所 | 帯域通過型フィルタ及びデュプレクサ |
WO2017171738A1 (en) | 2016-03-30 | 2017-10-05 | Intel Corporation | Hybrid microelectronic substrates |
US11205613B2 (en) * | 2019-09-26 | 2021-12-21 | Intel Corporation | Organic mold interconnects in shielded interconnects frames for integrated-circuit packages |
CN111224317B (zh) * | 2020-04-20 | 2021-03-19 | 深圳市汇顶科技股份有限公司 | 激光发射装置 |
US20230290746A1 (en) * | 2022-03-11 | 2023-09-14 | Chipletz, Inc. | Semiconductor package with integrated capacitors |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10270643A (ja) * | 1997-03-18 | 1998-10-09 | Lsi Logic Corp | オン・ダイ型のデカップリング・キャパシタンスを有する半導体ダイ |
JPH11312752A (ja) * | 1998-04-27 | 1999-11-09 | Kyocera Corp | 配線基板 |
JP2000031329A (ja) * | 1998-07-15 | 2000-01-28 | Ngk Spark Plug Co Ltd | 多層配線基板 |
JP2000040879A (ja) * | 1998-07-23 | 2000-02-08 | Kyocera Corp | 配線基板 |
JP2001168266A (ja) * | 1999-12-13 | 2001-06-22 | Hitachi Ltd | 半導体装置 |
JP2002164462A (ja) * | 2000-11-28 | 2002-06-07 | Nec Corp | 半導体装置およびその実装方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5258575A (en) * | 1990-05-07 | 1993-11-02 | Kyocera America, Inc. | Ceramic glass integrated circuit package with integral ground and power planes |
US5741729A (en) * | 1994-07-11 | 1998-04-21 | Sun Microsystems, Inc. | Ball grid array package for an integrated circuit |
EP0743929B1 (en) | 1994-12-12 | 1998-07-15 | Koninklijke Philips Electronics N.V. | Substrate of a ceramic material |
AU4697496A (en) * | 1995-01-24 | 1996-08-14 | Intel Corporation | High performance integrated circuit package |
DE19939483A1 (de) | 1999-08-20 | 2001-03-08 | Philips Corp Intellectual Pty | Passives Bauelement mit Verbundwerkstoff |
NL1014192C2 (nl) * | 2000-01-26 | 2001-08-08 | Industree B V | Printplaat. |
US6509646B1 (en) * | 2000-05-22 | 2003-01-21 | Silicon Integrated Systems Corp. | Apparatus for reducing an electrical noise inside a ball grid array package |
TW525417B (en) * | 2000-08-11 | 2003-03-21 | Ind Tech Res Inst | Composite through hole structure |
US6448639B1 (en) * | 2000-09-18 | 2002-09-10 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
US6472747B2 (en) * | 2001-03-02 | 2002-10-29 | Qualcomm Incorporated | Mixed analog and digital integrated circuits |
US6696763B2 (en) * | 2001-04-02 | 2004-02-24 | Via Technologies, Inc. | Solder ball allocation on a chip and method of the same |
TW511414B (en) * | 2001-04-19 | 2002-11-21 | Via Tech Inc | Data processing system and method, and control chip, and printed circuit board thereof |
TW498472B (en) * | 2001-11-27 | 2002-08-11 | Via Tech Inc | Tape-BGA package and its manufacturing process |
US6930381B1 (en) * | 2002-04-12 | 2005-08-16 | Apple Computer, Inc. | Wire bonding method and apparatus for integrated circuit |
WO2004064151A2 (en) | 2003-01-13 | 2004-07-29 | Koninklijke Philips Electronics N.V. | Electronic device and method of manufacturing a substrate |
-
2004
- 2004-10-01 JP JP2006530964A patent/JP2007508688A/ja active Pending
- 2004-10-01 US US10/574,882 patent/US7253516B2/en active Active
- 2004-10-01 KR KR1020067006911A patent/KR101099925B1/ko active IP Right Grant
- 2004-10-01 EP EP04770150.3A patent/EP1673807B1/en active Active
- 2004-10-01 WO PCT/IB2004/051945 patent/WO2005036643A1/en active Application Filing
- 2004-10-01 CN CNB2004800294565A patent/CN100550365C/zh active Active
- 2004-10-07 TW TW093130419A patent/TWI353663B/zh active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10270643A (ja) * | 1997-03-18 | 1998-10-09 | Lsi Logic Corp | オン・ダイ型のデカップリング・キャパシタンスを有する半導体ダイ |
JPH11312752A (ja) * | 1998-04-27 | 1999-11-09 | Kyocera Corp | 配線基板 |
JP2000031329A (ja) * | 1998-07-15 | 2000-01-28 | Ngk Spark Plug Co Ltd | 多層配線基板 |
JP2000040879A (ja) * | 1998-07-23 | 2000-02-08 | Kyocera Corp | 配線基板 |
JP2001168266A (ja) * | 1999-12-13 | 2001-06-22 | Hitachi Ltd | 半導体装置 |
JP2002164462A (ja) * | 2000-11-28 | 2002-06-07 | Nec Corp | 半導体装置およびその実装方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1864259A (zh) | 2006-11-15 |
CN100550365C (zh) | 2009-10-14 |
KR20060122826A (ko) | 2006-11-30 |
TWI353663B (en) | 2011-12-01 |
WO2005036643A1 (en) | 2005-04-21 |
US7253516B2 (en) | 2007-08-07 |
EP1673807B1 (en) | 2019-12-11 |
US20070018287A1 (en) | 2007-01-25 |
KR101099925B1 (ko) | 2011-12-28 |
TW200518307A (en) | 2005-06-01 |
EP1673807A1 (en) | 2006-06-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7545036B2 (en) | Semiconductor device that suppresses variations in high frequency characteristics of circuit elements | |
US6400019B1 (en) | Semiconductor device with wiring substrate | |
KR100891763B1 (ko) | 반도체 장치 | |
US7733661B2 (en) | Chip carrier and fabrication method | |
JP2007508688A (ja) | 電子装置及びそのためのキャリア基板 | |
US6300161B1 (en) | Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise | |
JP2001024150A (ja) | 半導体装置 | |
US7795709B2 (en) | Shielding noisy conductors in integrated passive devices | |
JP4597512B2 (ja) | 複数の集積回路デバイスを含む単一パッケージ及び半導体デバイスをパッケージする方法 | |
US8178901B2 (en) | Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip | |
JP4975437B2 (ja) | 電子装置 | |
JP2002252300A (ja) | 基板および半導体チップパッケージ | |
US20050104184A1 (en) | Semiconductor chip package and method | |
JP4124618B2 (ja) | 半導体装置 | |
JP4390634B2 (ja) | 半導体装置 | |
JP2004320047A (ja) | 半導体装置 | |
US20070040284A1 (en) | Two layer substrate ball grid array design | |
JPH09246425A (ja) | 半導体パッケージおよび半導体装置 | |
JPS60143638A (ja) | 半導体集積回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071001 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20080619 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20090422 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100826 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101126 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110524 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110824 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120417 |