JP2007505380A5 - - Google Patents

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Publication number
JP2007505380A5
JP2007505380A5 JP2006525832A JP2006525832A JP2007505380A5 JP 2007505380 A5 JP2007505380 A5 JP 2007505380A5 JP 2006525832 A JP2006525832 A JP 2006525832A JP 2006525832 A JP2006525832 A JP 2006525832A JP 2007505380 A5 JP2007505380 A5 JP 2007505380A5
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JP
Japan
Prior art keywords
electronic unit
bit
signal
shift register
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006525832A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007505380A (ja
JP4392025B2 (ja
Filing date
Publication date
Priority claimed from US10/660,217 external-priority patent/US7392445B2/en
Application filed filed Critical
Publication of JP2007505380A publication Critical patent/JP2007505380A/ja
Publication of JP2007505380A5 publication Critical patent/JP2007505380A5/ja
Application granted granted Critical
Publication of JP4392025B2 publication Critical patent/JP4392025B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006525832A 2003-09-11 2004-09-10 障害条件に対するオートノミック・バスの再構成 Expired - Fee Related JP4392025B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/660,217 US7392445B2 (en) 2003-09-11 2003-09-11 Autonomic bus reconfiguration for fault conditions
PCT/EP2004/052135 WO2005024633A1 (en) 2003-09-11 2004-09-10 Autonomic bus reconfiguration for fault conditions

Publications (3)

Publication Number Publication Date
JP2007505380A JP2007505380A (ja) 2007-03-08
JP2007505380A5 true JP2007505380A5 (enExample) 2009-07-02
JP4392025B2 JP4392025B2 (ja) 2009-12-24

Family

ID=34273623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006525832A Expired - Fee Related JP4392025B2 (ja) 2003-09-11 2004-09-10 障害条件に対するオートノミック・バスの再構成

Country Status (9)

Country Link
US (1) US7392445B2 (enExample)
EP (1) EP1683018B1 (enExample)
JP (1) JP4392025B2 (enExample)
KR (1) KR20060061359A (enExample)
CN (1) CN100419701C (enExample)
AT (1) ATE367606T1 (enExample)
DE (1) DE602004007681T2 (enExample)
TW (1) TWI300527B (enExample)
WO (1) WO2005024633A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070233930A1 (en) * 2006-03-14 2007-10-04 International Business Machines Corporation System and method of resizing PCI Express bus widths on-demand
US8953292B2 (en) * 2007-05-30 2015-02-10 Infineon Technologies Ag Bus interface and method for short-circuit detection
JP5099222B2 (ja) * 2008-05-30 2012-12-19 富士通株式会社 情報処理装置、転送回路及び情報処理装置のエラー制御方法
JP5163298B2 (ja) * 2008-06-04 2013-03-13 富士通株式会社 情報処理装置、データ伝送装置及びデータ伝送方法
KR101593702B1 (ko) * 2009-03-22 2016-02-15 엘지전자 주식회사 무선 통신 시스템에서 참조 신호 전송 방법 및 장치
WO2015006946A1 (en) * 2013-07-18 2015-01-22 Advanced Micro Devices, Inc. Partitionable data bus
US9454419B2 (en) 2013-07-18 2016-09-27 Advanced Micro Devices, Inc. Partitionable data bus
US10642951B1 (en) * 2018-03-07 2020-05-05 Xilinx, Inc. Register pull-out for sequential circuit blocks in circuit designs

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2473820A1 (fr) * 1980-01-11 1981-07-17 Telecommunications Sa Procede et systeme d'initialisation de la securisation d'une ligne d'une artere de transmission numerique
JP2825630B2 (ja) * 1990-09-07 1998-11-18 株式会社日立製作所 回線切替方式
JPH06259343A (ja) * 1993-03-10 1994-09-16 Hitachi Ltd 多重バス制御方式及びそれを用いたシステム
US5440538A (en) * 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5678065A (en) * 1994-09-19 1997-10-14 Advanced Micro Devices, Inc. Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency
US5875301A (en) * 1994-12-19 1999-02-23 Apple Computer, Inc. Method and apparatus for the addition and removal of nodes from a common interconnect
US5867645A (en) 1996-09-30 1999-02-02 Compaq Computer Corp. Extended-bus functionality in conjunction with non-extended-bus functionality in the same bus system
US6366557B1 (en) * 1997-10-31 2002-04-02 Nortel Networks Limited Method and apparatus for a Gigabit Ethernet MAC (GMAC)
US6018810A (en) * 1997-12-12 2000-01-25 Compaq Computer Corporation Fault-tolerant interconnection means in a computer system
JP3994360B2 (ja) * 1998-05-20 2007-10-17 ソニー株式会社 情報処理装置、情報処理方法、および記録媒体
US7100071B2 (en) * 1998-07-16 2006-08-29 Hewlett-Packard Development Company, L.P. System and method for allocating fail-over memory
US6466718B1 (en) * 1999-12-29 2002-10-15 Emc Corporation Method and apparatus for transmitting fiber-channel and non-fiber channel signals through common cable
US6574753B1 (en) * 2000-01-10 2003-06-03 Emc Corporation Peer link fault isolation
JP2003014819A (ja) * 2001-07-03 2003-01-15 Matsushita Electric Ind Co Ltd 半導体配線基板，半導体デバイス，半導体デバイスのテスト方法及びその実装方法
KR100448709B1 (ko) * 2001-11-29 2004-09-13 삼성전자주식회사 데이터 버스 시스템 및 그 제어방법
US6898730B1 (en) * 2001-11-30 2005-05-24 Western Digital Technologies, Inc. System and method for fail-over switching in a disk storage medium
JP4188602B2 (ja) * 2002-01-10 2008-11-26 株式会社日立製作所 クラスタ型ディスク制御装置及びその制御方法
US6918068B2 (en) * 2002-04-08 2005-07-12 Harris Corporation Fault-tolerant communications system and associated methods
US7362697B2 (en) * 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
US7194581B2 (en) * 2003-06-03 2007-03-20 Intel Corporation Memory channel with hot add/remove

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