JP2007335076A5 - - Google Patents

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Publication number
JP2007335076A5
JP2007335076A5 JP2007204671A JP2007204671A JP2007335076A5 JP 2007335076 A5 JP2007335076 A5 JP 2007335076A5 JP 2007204671 A JP2007204671 A JP 2007204671A JP 2007204671 A JP2007204671 A JP 2007204671A JP 2007335076 A5 JP2007335076 A5 JP 2007335076A5
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JP
Japan
Prior art keywords
memory
memory block
information
buffer
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007204671A
Other languages
English (en)
Japanese (ja)
Other versions
JP4659792B2 (ja
JP2007335076A (ja
Filing date
Publication date
Priority claimed from SE9502113A external-priority patent/SE514348C2/sv
Application filed filed Critical
Publication of JP2007335076A publication Critical patent/JP2007335076A/ja
Publication of JP2007335076A5 publication Critical patent/JP2007335076A5/ja
Application granted granted Critical
Publication of JP4659792B2 publication Critical patent/JP4659792B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2007204671A 1995-06-09 2007-08-06 メモリ構造 Expired - Lifetime JP4659792B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9502113A SE514348C2 (sv) 1995-06-09 1995-06-09 Minnesstruktur anpassad för lagring och hämtning av vektorer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP50237597A Division JP4036270B2 (ja) 1995-06-09 1996-06-05 メモリ構造

Publications (3)

Publication Number Publication Date
JP2007335076A JP2007335076A (ja) 2007-12-27
JP2007335076A5 true JP2007335076A5 (enExample) 2008-02-14
JP4659792B2 JP4659792B2 (ja) 2011-03-30

Family

ID=20398571

Family Applications (2)

Application Number Title Priority Date Filing Date
JP50237597A Expired - Lifetime JP4036270B2 (ja) 1995-06-09 1996-06-05 メモリ構造
JP2007204671A Expired - Lifetime JP4659792B2 (ja) 1995-06-09 2007-08-06 メモリ構造

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP50237597A Expired - Lifetime JP4036270B2 (ja) 1995-06-09 1996-06-05 メモリ構造

Country Status (8)

Country Link
US (1) US6425064B2 (enExample)
EP (1) EP0839354B1 (enExample)
JP (2) JP4036270B2 (enExample)
AT (1) ATE252250T1 (enExample)
DE (1) DE69630388T2 (enExample)
ES (1) ES2210371T3 (enExample)
SE (1) SE514348C2 (enExample)
WO (1) WO1996042055A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266634B2 (en) 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
EP1311945A1 (en) * 2000-08-22 2003-05-21 Jean-Paul Theis A configurable register file with multi-range shift register support
US7107399B2 (en) * 2001-05-11 2006-09-12 International Business Machines Corporation Scalable memory
US7110400B2 (en) * 2002-04-10 2006-09-19 Integrated Device Technology, Inc. Random access memory architecture and serial interface with continuous packet handling capability
US7339943B1 (en) * 2002-05-10 2008-03-04 Altera Corporation Apparatus and method for queuing flow management between input, intermediate and output queues
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
DE102004038212A1 (de) * 2004-08-05 2006-03-16 Robert Bosch Gmbh FlexRay-Kommunikationsbaustein
DE102004038213A1 (de) * 2004-08-05 2006-03-16 Robert Bosch Gmbh Verfahren und Vorrichtung zum Zugriff auf Daten eines Botschaftsspeichers eines Kommunikationsbausteins
KR101257848B1 (ko) 2005-07-13 2013-04-24 삼성전자주식회사 복합 메모리를 구비하는 데이터 저장 시스템 및 그 동작방법
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
JP5714495B2 (ja) * 2008-10-10 2015-05-07 スパンション エルエルシー 解析システム、およびデータパターン解析の方法
US8818802B2 (en) * 2008-10-10 2014-08-26 Spansion Llc Real-time data pattern analysis system and method of operation thereof
JP5653856B2 (ja) 2011-07-21 2015-01-14 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621339A (en) * 1983-06-13 1986-11-04 Duke University SIMD machine using cube connected cycles network architecture for vector processing
US4747070A (en) 1984-01-09 1988-05-24 Wang Laboratories, Inc. Reconfigurable memory system
JPS60262280A (ja) * 1984-06-07 1985-12-25 Toshiba Corp メモリモジユ−ル
US4858107A (en) * 1985-03-11 1989-08-15 General Electric Company Computer device display system using conditionally asynchronous memory accessing by video display controller
JPS63225837A (ja) * 1987-03-13 1988-09-20 Fujitsu Ltd 距離付きベクトルアクセス方式
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5642444A (en) * 1994-07-28 1997-06-24 Univ North Carolina Specialized image processing system architecture and method for image data arrays
JPH08235130A (ja) * 1995-02-24 1996-09-13 Sony Corp 並列プロセッサ

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