JP2007328900A5 - - Google Patents
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- Publication number
- JP2007328900A5 JP2007328900A5 JP2007028839A JP2007028839A JP2007328900A5 JP 2007328900 A5 JP2007328900 A5 JP 2007328900A5 JP 2007028839 A JP2007028839 A JP 2007028839A JP 2007028839 A JP2007028839 A JP 2007028839A JP 2007328900 A5 JP2007328900 A5 JP 2007328900A5
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- channel mos
- pair
- transistors
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000003068 static effect Effects 0.000 claims 11
- 239000004065 semiconductor Substances 0.000 claims 9
- 239000000758 substrate Substances 0.000 claims 3
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007028839A JP2007328900A (ja) | 2006-05-09 | 2007-02-08 | スタティック型半導体記憶装置 |
| US11/730,977 US7978503B2 (en) | 2006-05-09 | 2007-04-05 | Static semiconductor memory with a dummy call and a write assist operation |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006129832 | 2006-05-09 | ||
| JP2007028839A JP2007328900A (ja) | 2006-05-09 | 2007-02-08 | スタティック型半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007328900A JP2007328900A (ja) | 2007-12-20 |
| JP2007328900A5 true JP2007328900A5 (cg-RX-API-DMAC7.html) | 2010-02-25 |
Family
ID=38684937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007028839A Withdrawn JP2007328900A (ja) | 2006-05-09 | 2007-02-08 | スタティック型半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7978503B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2007328900A (cg-RX-API-DMAC7.html) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7376032B2 (en) * | 2006-06-01 | 2008-05-20 | Qualcomm Incorporated | Method and apparatus for a dummy SRAM cell |
| US7630264B2 (en) * | 2007-07-24 | 2009-12-08 | Infineon Technologies Ag | Memory device and testing with write completion detection |
| US20090285039A1 (en) * | 2008-05-15 | 2009-11-19 | International Business Machines Corporation | Method and apparatus for locally generating a virtual ground for write assist on column selected sram cells |
| US7817481B2 (en) * | 2008-07-03 | 2010-10-19 | International Business Machines Corporation | Column selectable self-biasing virtual voltages for SRAM write assist |
| KR20100028416A (ko) * | 2008-09-04 | 2010-03-12 | 삼성전자주식회사 | 반도체 메모리 장치 및 상기 반도체 메모리 장치의 동작 방법 |
| KR101446337B1 (ko) * | 2008-09-08 | 2014-10-02 | 삼성전자주식회사 | 반도체 메모리 장치 및 상기 반도체 메모리 장치의 동작 방법 |
| KR101505554B1 (ko) | 2008-09-08 | 2015-03-25 | 삼성전자주식회사 | 반도체 메모리 장치 및 상기 반도체 메모리 장치의 동작 방법 |
| US8111579B2 (en) | 2008-11-10 | 2012-02-07 | Intel Corporation | Circuits and methods for reducing minimum supply for register file cells |
| JP2012018718A (ja) | 2010-07-07 | 2012-01-26 | Toshiba Corp | 半導体記憶装置 |
| KR101799482B1 (ko) | 2010-12-29 | 2017-11-20 | 삼성전자주식회사 | 기입 어시스트 회로를 포함하는 정적 메모리 장치 |
| US9093176B2 (en) * | 2012-11-12 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line lowering for write assisted control scheme |
| WO2014112396A1 (ja) * | 2013-01-21 | 2014-07-24 | パナソニック株式会社 | マスク動作時に比較データを上書きするｃａｍセル |
| US20140293679A1 (en) * | 2013-03-26 | 2014-10-02 | International Business Machines Corporation | Management of sram initialization |
| US9299419B1 (en) | 2015-02-02 | 2016-03-29 | Qualcomm Incorporated | System and method for dynamically adjusting memory rail voltage |
| US10014049B2 (en) | 2016-06-22 | 2018-07-03 | Darryl G. Walker | Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits |
| US10403384B2 (en) | 2016-06-22 | 2019-09-03 | Darryl G. Walker | Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor |
| CN109308920B (zh) * | 2017-07-27 | 2020-11-13 | 中芯国际集成电路制造(上海)有限公司 | 静态随机存取存储器阵列的供电控制电路 |
| KR102841136B1 (ko) * | 2020-11-06 | 2025-07-30 | 삼성전자주식회사 | 기입 보조 셀을 갖는 셀 어레이를 포함하는 집적 회로 |
| US11955171B2 (en) | 2021-09-15 | 2024-04-09 | Mavagail Technology, LLC | Integrated circuit device including an SRAM portion having end power select circuits |
| KR102711124B1 (ko) * | 2023-04-03 | 2024-09-26 | 연세대학교 산학협력단 | Sram을 위한 보조 셀, sram 및 이의 동작 방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793671A (en) | 1997-01-21 | 1998-08-11 | Advanced Micro Devices, Inc. | Static random access memory cell utilizing enhancement mode N-channel transistors as load elements |
| US6201757B1 (en) * | 1998-08-20 | 2001-03-13 | Texas Instruments Incorporated | Self-timed memory reset circuitry |
| JP2001143476A (ja) | 1999-11-15 | 2001-05-25 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| JP2002042476A (ja) | 2000-07-25 | 2002-02-08 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| US6363005B1 (en) * | 2001-03-07 | 2002-03-26 | United Microelectronics Corp. | Method of increasing operating speed of SRAM |
| JP4162076B2 (ja) | 2002-05-30 | 2008-10-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP4090967B2 (ja) * | 2003-08-29 | 2008-05-28 | 松下電器産業株式会社 | 半導体記憶装置 |
| JP4050690B2 (ja) * | 2003-11-21 | 2008-02-20 | 株式会社東芝 | 半導体集積回路装置 |
-
2007
- 2007-02-08 JP JP2007028839A patent/JP2007328900A/ja not_active Withdrawn
- 2007-04-05 US US11/730,977 patent/US7978503B2/en not_active Expired - Fee Related