JP2007324296A - Icチップ貼り合わせ用tcp構造体 - Google Patents
Icチップ貼り合わせ用tcp構造体 Download PDFInfo
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- JP2007324296A JP2007324296A JP2006151499A JP2006151499A JP2007324296A JP 2007324296 A JP2007324296 A JP 2007324296A JP 2006151499 A JP2006151499 A JP 2006151499A JP 2006151499 A JP2006151499 A JP 2006151499A JP 2007324296 A JP2007324296 A JP 2007324296A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Wire Bonding (AREA)
Abstract
【解決手段】TCP構造体10は、中央部に開口部6をもつ枠型形状で、ダイアタッチ剤層5、ポリイミド絶縁層1、配線回路及び入出力端子を形成した導体層2、ソルダーレジスト層3とその順序に積層した構造であり、ダイアタッチ剤層5の厚さは5〜25μmからなり、ポリイミド絶縁層1の厚さは10〜40μmからなり、導体層2の厚さは5〜15μmからなり、ソルダーレジスト層3の厚さは5〜20μmからなるICチップ貼り合わせ用の積層体であり、ICチップ11の厚さに合わせこむようにしてICチップ貼り合わせ用TCP構造体10の厚さを形成した。
【選択図】図1
Description
な回路が形成される。次いで、回路チェック等の検証を実施した後、次の工程の投入する。なお、図7の(a)〜(b)のTOCの場合、最適な回路の形成では、ICチップ11、12の回路と、TOC用構造体20aの配線回路と、ワイヤーボンデングの配線等が相互に干渉するため、ICチップの改善に追従するTOC用構造及びワイヤーボンデングの改善が急務となる問題がある。
前記TCP構造体は、中央部に開口部をもつ枠型形状で、ダイアタッチ剤層、ポリイミド絶縁層、配線回路及び入出力端子を形成した導体層、ソルダーレジスト層とその順序に積層した構造であり、
前記ダイアタッチ剤層の厚さは5〜25μmからなり、前記ポリイミド絶縁層の厚さは10〜40μmからなり、前記導体層の厚さは5〜15μmからなり、前記ソルダーレジスト層の厚さは5〜20μmからなるICチップ貼り合わせ用の積層体であり、
当該ICチップの厚さに合わせこむようにしてICチップ貼り合わせ用TCP構造体の厚さを形成したことを特徴とするICチップ貼り合わせ用TCP構造体である。
より薄膜化したTCP構造体となり、ICチップを搭載したパッケージ自体の軽薄短小が図られる。
2…導体層
2a…配線回路
2b…入出力端子
3…ソルダーレジスト層
4…接着剤層
5…ダイアタッチ剤層
6…開口部
10…TCP(TOC用TCP構造体)
11…特定用(用途)ICチップ
12…汎用(用途)ICチップ
13…ワイヤーボンデング
13a…ワイヤーボンデング
13b…ワイヤーボンデング
13c…ワイヤーボンデング
14…樹脂モールド
20…TOC(TOC用TCP構造体を用いた半導体パッケージ)
20a…TOC用構造体
21…キャリアフレームA
22…仮止めテープ
23…キャリアフレームB
24…IC用ベアチップ
25…TCP
26…TOC用構造体
30a…スタックトIC用構造体
30…T−BGA型のTOC(TOC用TCP構造体を用いたスタックトIC構造の半導体パッケージ)
31…配線基板
31a…(配線基板)端子
32…半田ボール
35…ダイアタッチ剤
Claims (2)
- ポリイミドからなる絶縁層の片側に、絶縁層と直接に導体層を形成した極薄厚からなるICチップ貼り合わせ用TCP構造体であって、
前記TCP構造体は、中央部に開口部をもつ枠型形状で、ダイアタッチ剤層、ポリイミド絶縁層、配線回路及び入出力端子を形成した導体層、ソルダーレジスト層とその順序に積層した構造であり、
前記ダイアタッチ剤層の厚さは5〜25μmからなり、前記ポリイミド絶縁層の厚さは10〜40μmからなり、前記導体層の厚さは5〜15μmからなり、前記ソルダーレジスト層の厚さは5〜20μmからなるICチップ貼り合わせ用の積層体であり、
当該ICチップの厚さに合わせこむようにしてICチップ貼り合わせ用TCP構造体の厚さを形成したことを特徴とするICチップ貼り合わせ用TCP構造体。 - 前記ICチップ貼り合わせ用TCP構造体は、前記ICチップと所望のIC間に介在するインターポーザの役割を荷うものであって、スタックトIC用インターポーザとする用途に限定することを特徴とする請求項1記載のICチップ貼り合わせ用TCP構造体。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006151499A JP5092284B2 (ja) | 2006-05-31 | 2006-05-31 | Icチップ貼り合わせ用toc用構造体 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006151499A JP5092284B2 (ja) | 2006-05-31 | 2006-05-31 | Icチップ貼り合わせ用toc用構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007324296A true JP2007324296A (ja) | 2007-12-13 |
JP5092284B2 JP5092284B2 (ja) | 2012-12-05 |
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JP2006151499A Expired - Fee Related JP5092284B2 (ja) | 2006-05-31 | 2006-05-31 | Icチップ貼り合わせ用toc用構造体 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002217354A (ja) * | 2001-01-15 | 2002-08-02 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2005086098A (ja) * | 2003-09-10 | 2005-03-31 | Three M Innovative Properties Co | チップオンフレックス(cof)テープ |
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2006
- 2006-05-31 JP JP2006151499A patent/JP5092284B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002217354A (ja) * | 2001-01-15 | 2002-08-02 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2005086098A (ja) * | 2003-09-10 | 2005-03-31 | Three M Innovative Properties Co | チップオンフレックス(cof)テープ |
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JP5092284B2 (ja) | 2012-12-05 |
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