JP2007310086A - 半導体装置製造におけるパターン形成方法 - Google Patents
半導体装置製造におけるパターン形成方法 Download PDFInfo
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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Abstract
【解決手段】本発明の1態様による感光性樹脂膜パターン形成方法は、半導体基板の上方に被処理膜を形成する工程と、前記被処理膜上に第1の感光性樹脂膜からなる第1のパターンを形成する工程と、前記第1のパターンを形成した第1の感光性樹脂膜に注入するイオンの投影飛程と投影飛程の標準偏差の3倍との和が前記第1の感光性樹脂膜の膜厚より大きくなるようにイオン注入する工程と、前記イオン注入された第1の感光性樹脂膜上に第2の感光性樹脂膜からなる第2のパターンを形成する工程とを具備する。
【選択図】図1
Description
本発明の第1の実施形態は、注入するイオンが感光性樹脂膜の全膜厚にわたり注入される条件でイオン注入することにより下層感光性樹脂膜の膜厚全体を不溶化させる感光性樹脂膜パターン形成方法及びこの感光性樹脂膜パターンを使用する半導体装置のパターン形成方法を提供する。本実施形態を、パック・アンド・カバー(PAC)プロセスを例に以下に説明する。
本発明の第2の実施形態は、感光性樹脂膜パターンと被処理膜との間にイオン阻止膜を設けた感光性樹脂膜パターンの形成方法及び半導体装置のパターン形成方法である。
Claims (5)
- 半導体基板の上方に被処理膜を形成する工程と、
前記被処理膜上に第1の感光性樹脂膜からなる第1のパターンを形成する工程と、
前記第1のパターンを形成した第1の感光性樹脂膜に注入するイオンの投影飛程と投影飛程の標準偏差の3倍との和が前記第1の感光性樹脂膜の膜厚より大きくなるようにイオン注入する工程と、
前記イオン注入された第1の感光性樹脂膜上に第2の感光性樹脂膜からなる第2のパターンを形成する工程と
を具備することを特徴とする、感光性樹脂膜パターン形成方法。 - 前記注入イオンの投影飛程と投影飛程の標準偏差の3倍との和が前記第1の感光性樹脂膜の膜厚より大きくなるようにすることは、前記イオンの投影飛程を前記第1の感光性樹脂膜の膜厚より大きくなるようにすることであることを特徴とする請求項1に記載の感光性樹脂膜パターン形成方法。
- 前記第1の感光性樹脂膜を形成する前に、前記被処理膜上にイオン阻止膜を形成する工程を具備し、
前記イオン阻止膜は、前記注入イオンが前記被処理膜に到達しない膜厚を有することを特徴とする、請求項1又は2に記載の感光性樹脂膜パターン形成方法。 - 前記イオン阻止膜の膜厚は、前記注入イオンの投影飛程と投影飛程の標準偏差の3倍との和よりも大きいことを特徴とする、請求項3に記載の感光性樹脂膜パターン形成方法。
- 半導体基板の上方に被処理膜を形成する工程と、
前記被処理膜上に第1の感光性樹脂膜からなる第1のパターンを形成する工程と、
前記第1のパターンを形成した第1の感光性樹脂膜に注入するイオンの投影飛程と投影飛程の標準偏差の3倍との和が前記第1の感光性樹脂膜の膜厚より大きくなるようにイオン注入する工程と、
前記イオン注入された第1の感光性樹脂膜上に第2の感光性樹脂膜からなる第2のパターンを形成する工程と
前記第1及び第2のパターンを形成した前記第1及び第2の感光性樹脂膜をマスクとして、前記被処理膜をパターニングする工程と
を具備することを特徴とする、半導体装置のパターン形成方法。
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JP2006137982A JP4745121B2 (ja) | 2006-05-17 | 2006-05-17 | 半導体装置製造におけるパターン形成方法 |
US11/798,724 US7749687B2 (en) | 2006-05-17 | 2007-05-16 | Pattern forming method used in semiconductor device manufacturing and method of manufacturing semiconductor device |
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JP2006137982A JP4745121B2 (ja) | 2006-05-17 | 2006-05-17 | 半導体装置製造におけるパターン形成方法 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008185970A (ja) * | 2007-01-31 | 2008-08-14 | Renesas Technology Corp | パターンの形成方法、電子デバイスの製造方法および電子デバイス |
CN101944475A (zh) * | 2009-07-06 | 2011-01-12 | 索尼公司 | 制造半导体器件的方法及图案形成方法 |
WO2014057734A1 (ja) * | 2012-10-09 | 2014-04-17 | 日本電気株式会社 | 配線形成方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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US7759201B2 (en) * | 2007-12-17 | 2010-07-20 | Sandisk 3D Llc | Method for fabricating pitch-doubling pillar structures |
KR100933854B1 (ko) * | 2008-01-14 | 2009-12-24 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성방법 |
US7981592B2 (en) * | 2008-04-11 | 2011-07-19 | Sandisk 3D Llc | Double patterning method |
US7713818B2 (en) * | 2008-04-11 | 2010-05-11 | Sandisk 3D, Llc | Double patterning method |
US20090263751A1 (en) * | 2008-04-22 | 2009-10-22 | Swaminathan Sivakumar | Methods for double patterning photoresist |
US7786015B2 (en) * | 2008-04-28 | 2010-08-31 | Sandisk 3D Llc | Method for fabricating self-aligned complementary pillar structures and wiring |
JP2010027978A (ja) * | 2008-07-23 | 2010-02-04 | Toshiba Corp | パターン形成方法 |
US8026178B2 (en) | 2010-01-12 | 2011-09-27 | Sandisk 3D Llc | Patterning method for high density pillar structures |
JP6002056B2 (ja) | 2013-02-18 | 2016-10-05 | 株式会社東芝 | ガイドパターンデータ補正方法、プログラム、及びパターン形成方法 |
CA2929915C (en) | 2015-05-15 | 2018-10-09 | Apache Corporation | Pressure swing adsorption process for enhanced separation of lighter from heavier species |
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JPS63133629A (ja) * | 1986-11-26 | 1988-06-06 | Nec Corp | 集積回路装置の製造方法 |
JPH08153714A (ja) * | 1994-09-30 | 1996-06-11 | Sanyo Electric Co Ltd | エッチング方法及び半導体装置の製造方法 |
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US6664011B2 (en) | 2001-12-05 | 2003-12-16 | Taiwan Semiconductor Manufacturing Company | Hole printing by packing and unpacking using alternating phase-shifting masks |
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2006
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2007
- 2007-05-16 US US11/798,724 patent/US7749687B2/en not_active Expired - Fee Related
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JPS63133629A (ja) * | 1986-11-26 | 1988-06-06 | Nec Corp | 集積回路装置の製造方法 |
JPH08153714A (ja) * | 1994-09-30 | 1996-06-11 | Sanyo Electric Co Ltd | エッチング方法及び半導体装置の製造方法 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008185970A (ja) * | 2007-01-31 | 2008-08-14 | Renesas Technology Corp | パターンの形成方法、電子デバイスの製造方法および電子デバイス |
CN101944475A (zh) * | 2009-07-06 | 2011-01-12 | 索尼公司 | 制造半导体器件的方法及图案形成方法 |
US8445183B2 (en) | 2009-07-06 | 2013-05-21 | Sony Corporation | Method of manufacturing semiconductor device and pattern formation method |
WO2014057734A1 (ja) * | 2012-10-09 | 2014-04-17 | 日本電気株式会社 | 配線形成方法 |
US9245789B2 (en) | 2012-10-09 | 2016-01-26 | Nec Corporation | Method for forming wiring |
JPWO2014057734A1 (ja) * | 2012-10-09 | 2016-09-05 | 日本電気株式会社 | 配線形成方法 |
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US7749687B2 (en) | 2010-07-06 |
JP4745121B2 (ja) | 2011-08-10 |
US20070269746A1 (en) | 2007-11-22 |
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