JP2007273873A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2007273873A JP2007273873A JP2006099770A JP2006099770A JP2007273873A JP 2007273873 A JP2007273873 A JP 2007273873A JP 2006099770 A JP2006099770 A JP 2006099770A JP 2006099770 A JP2006099770 A JP 2006099770A JP 2007273873 A JP2007273873 A JP 2007273873A
- Authority
- JP
- Japan
- Prior art keywords
- film
- fluorine
- gas
- hard mask
- added carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/36—Carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】基板1上に形成されたフッ素添加カーボン膜20と、このフッ素添加カーボン膜20の上に形成され、SiCO膜23とSiO2膜24とを含むハードマスク層と、前記フッ素添加カーボン膜20とハードマスク層との間に、SiN膜21とSiCN膜22とを下からこの順序で積層して形成されたバリア層と、を備える。SiN膜21によりフッ素添加カーボン膜からハードマスク層へのフッ素の突き抜けが抑えられ、SiCN膜22によりハードマスク層の成膜プロセス時のフッ素添加カーボン膜20の酸化を抑えることができるので、熱処理後のハードマスク層やバリア層の膜剥がれを抑えることができる。
【選択図】図2
Description
基板上に形成されたフッ素添加カーボン膜からなる絶縁膜と、
前記絶縁膜の上に形成され、シリコンと酸素とを含む膜を備えたハードマスク層と、
前記絶縁膜とハードマスク層との間に、窒化シリコン膜と、シリコン、炭素及び窒素を含む膜と、を下からこの順序で積層して形成され、フッ素添加カーボン膜中のフッ素がハードマスク層へ移動することを抑えるためのバリア層と、を備えたことを特徴とする。ここで前記ハードマスク層におけるシリコンと酸素とを含む膜は、酸素添加炭化ケイ素膜又は二酸化シリコン膜である。
次いで前記基板の表面を、シリコン及び窒素の各活性種を含むプラズマに曝して、前記絶縁膜の上に、窒化シリコン膜よりなる第1のバリア層を成膜する工程と、
次いで前記基板の表面を、シリコン、炭素及び窒素の各活性種を含むプラズマに曝して、前記第1のバリア層の表面に、シリコン、炭素及び窒素を含む膜よりなる第2のバリア層を成膜する工程と、
次いで前記基板の表面を、シリコン及び酸素の各活性種を含むプラズマに曝して、前記第2のバリア層の上にシリコンと酸素とを含む膜を成膜する工程と、を含むことを特徴とする。ここで前記シリコンと酸素とを含む膜は、酸素添加炭化ケイ素膜又は二酸化シリコン膜である。
ジシランガスの供給源及び窒素ガスの供給源と、トリメチルシランガスの供給源とが接続されている。この第2の成膜装置41においては、既にフッ素添加カーボン膜20が成膜された基板1を処理容器61内に搬入し、続いて、処理容器61の内部を所定の圧力まで真空引きする。そして、第1のバリア層であるSiN膜21の成膜が行われるが、その成膜プロセスは、先ず、第1のガス供給部64から処理容器61内にプラズマガス例えばArガスを所定の流量例えば600sccmで供給すると共に、第2のガス供給部68から処理容器61内にジシランガス及び窒素ガスを夫々所定の流量、例えば6sccm、50sccmで供給する。そして、処理容器61内を例えばプロセス圧力16Paに維持し、載置台62のウエハ温度を345℃に設定する。一方、マイクロ波発生手段83から2.45GHz、1500Wの高周波(マイクロ波)を供給することにより、このマイクロ波のエネルギーによってArガスをプラズマ化し、このプラズマによりジシランガス及び窒素ガスが励起され、フッ素添加カーボン膜20の上にSiN膜21が成膜される。
(実施例1)
前記半導体製造装置において、図5に示した成膜装置40を用いて、基板であるシリコンベアウエハの上に、フッ素添加カーボン膜20を200nmの膜厚で成膜し、次いで、第2の成膜装置41を用い、フッ素添加カーボン膜20の上にバリア層として、厚さ10nmのSiN膜21と、厚さ8nmのSiCN22膜とを、この順序で成膜した。続いて、第3の成膜装置50を用い、SiCN22膜の上に、ハードマスク層として、厚さ50nmのSiCO膜23と、厚さ150nmのSiO2膜24とを、この順序で成膜した。各膜のプロセス条件については既述の条件で行った。
フッ素添加カーボン膜20の上にSiN膜21を形成せずに、バリア層として厚さ10nmのSiCN膜22のみを形成し、ハードマスク層として、SiCO膜23とSiO2膜24を形成した他は、実施例1と同様にして成膜を行った(図10参照)。
フッ素添加カーボン膜20の上にSiCN膜22を形成せずに、バリア層として厚さ8nmのSiN膜21のみを形成し、ハードマスク層として、SiCO膜23とSiO2膜24を形成した他は、実施例1と同様にして成膜を行った(図11参照)。
B.密着性についての考察
実施例1及び比較例1,2の基板に対して、常圧、窒素雰囲気の下で、400℃で60分間、アニール処理を行った後、これら基板の表面を目視で観察し、またテープを貼り付けて膜剥れの状態を調べた。この結果、比較例1及び比較例2については、膜中から気泡が発生したことに基づく変色域が多く見られ、比較例1ではSiCN膜22とSiCO膜23との界面での膜剥がれが大きく、比較例2ではフッ素添加カーボン膜20とSiN膜21との界面で小さな膜剥がれがあった。
フッ素添加カーボン膜20とSiN膜21との界面や、SiCN膜22とSiCO膜23との界面でも膜剥がれの発生は全く見られなかった。従って、フッ素添加カーボン膜20とハードマスク層を構成するSiCO膜23との間に、バリア層としてSiN膜21とSiCN膜22とを積層して設けることにより、フッ素添加カーボン膜20とバリア層との間や、バリア層とハードマスク層との間の密着性が大きくなることが理解される。
実施例1の基板に対して、前記アニール処理の前後において、二次イオン質量分析法(SIMS:Secondary Ion Mass Spectroscopy)により、積層体中のフッ素濃度のプロファイルを調べた。また比較例1の基板及び比較例2の基板に対しても、同様のアニール処理の前後において積層体中のフッ素濃度のプロファイルを調べた。
D.酸素に対するバリア性の考察
実施例1及び比較例1,2について、SIMSにより積層構造膜の表面にイオンビームを照射スパッタしたときに放出される二次イオンを質量分析し、二次イオン強度を指標として積層構造膜中の酸素濃度のプロファイルを調べた。その結果を、比較例1及び比較例2については図11に、実施例1及び比較例2については図12に夫々示す。図11及び図12においては、縦軸は二次イオン強度(counts/sec)、横軸は膜の深さ(nm)を夫々示しており、図11及び図12中、実線は実施例1、一点鎖線は比較例1、点線は比較例2のデータを夫々示している。
E.ハードマスク層にフッ素が入り込むメカニズム
以上の実施例を踏まえ、本発明者らは、フッ素添加カーボン膜20のハードマスク層にフッ素が入り込むメカニズムを以下のように推察している。先ず比較例1の積層構造膜を形成する場合は、フッ素添加カーボン膜20の表面にSiCN膜22を成膜するが、このときにフッ素添加カーボン膜20のフッ素がSiCN膜22に入り込み、SiCNFを生成する。次いでこの表面にSiCO膜23を成膜し、この後SiO2膜24を成膜すると、この成膜プロセスにおいて酸素プラズマが用いられるため、酸素の活性種がSiCO膜23を突き抜けて前記SiCN膜22に入り込み、ここに存在するSiCNFに酸素がアタックし、これにより窒素が抜けてしまうので、結果としてフッ素が遊離し易い状態となる。そこで後の工程においてアニール処理を行うと、このフッ素がハードマスク層中に入り込む。
10 フッ素添加カーボン膜
11 銅配線層
20 フッ素添加カーボン膜
21 SiN膜
22 SiCN膜
23 SiCO膜
24 SiO2膜
40 第1の成膜装置
41 第2の成膜装置
50 第3の成膜装置
61 処理容器
64 第1のガス供給部
67 第1のガス供給路
68 第2のガス供給部
72 第2のガス供給路
77 アンテナ部
Claims (4)
- 基板上に形成されたフッ素添加カーボン膜からなる絶縁膜と、
前記絶縁膜の上に形成され、シリコンと酸素とを含む膜を備えたハードマスク層と、
前記絶縁膜とハードマスク層との間に、窒化シリコン膜と、シリコン、炭素及び窒素を含む膜と、を下からこの順序で積層して形成され、フッ素添加カーボン膜中のフッ素がハードマスク層へ移動することを抑えるためのバリア層と、を備えたことを特徴とする半導体装置。 - 前記ハードマスク層におけるシリコンと酸素とを含む膜は、酸素添加炭化ケイ素膜又は二酸化シリコン膜であることを特徴とする請求項1記載の半導体装置。
- 基板上にフッ素添加カーボン膜からなる絶縁膜を成膜する工程と、
次いで前記基板の表面を、シリコン及び窒素の各活性種を含むプラズマに曝して、前記絶縁膜の上に、窒化シリコン膜よりなる第1のバリア層を成膜する工程と、
次いで前記基板の表面を、シリコン、炭素及び窒素の各活性種を含むプラズマに曝して、前記第1のバリア層の表面に、シリコン、炭素及び窒素を含む膜よりなる第2のバリア層を成膜する工程と、
次いで前記基板の表面を、シリコン及び酸素の各活性種を含むプラズマに曝して、前記第2のバリア層の上にシリコンと酸素とを含む膜を成膜する工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記シリコンと酸素とを含む膜は、酸素添加炭化ケイ素膜又は二酸化シリコン膜であることを特徴とする請求項3記載の半導体装置の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006099770A JP5119606B2 (ja) | 2006-03-31 | 2006-03-31 | 半導体装置及び半導体装置の製造方法 |
CN2007800013688A CN101356638B (zh) | 2006-03-31 | 2007-03-27 | 半导体装置和半导体装置的制造方法 |
EP07739885A EP2003687A4 (en) | 2006-03-31 | 2007-03-27 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
KR1020087005618A KR100942179B1 (ko) | 2006-03-31 | 2007-03-27 | 반도체 장치 및 반도체 장치의 제조 방법 |
PCT/JP2007/056447 WO2007116758A1 (ja) | 2006-03-31 | 2007-03-27 | 半導体装置及び半導体装置の製造方法 |
TW096111350A TW200805498A (en) | 2006-03-31 | 2007-03-30 | Semiconductor device and manufacturing method therefor |
US12/157,795 US7851351B2 (en) | 2006-03-31 | 2008-06-13 | Manufacturing method for semiconductor devices with enhanced adhesivity and barrier properties |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006099770A JP5119606B2 (ja) | 2006-03-31 | 2006-03-31 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007273873A true JP2007273873A (ja) | 2007-10-18 |
JP5119606B2 JP5119606B2 (ja) | 2013-01-16 |
Family
ID=38581055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006099770A Expired - Fee Related JP5119606B2 (ja) | 2006-03-31 | 2006-03-31 | 半導体装置及び半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP2003687A4 (ja) |
JP (1) | JP5119606B2 (ja) |
KR (1) | KR100942179B1 (ja) |
CN (1) | CN101356638B (ja) |
TW (1) | TW200805498A (ja) |
WO (1) | WO2007116758A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012084638A (ja) * | 2010-10-08 | 2012-04-26 | Tohoku Univ | 半導体装置の製造方法および半導体装置 |
KR101417723B1 (ko) | 2011-09-07 | 2014-07-08 | 도호쿠 다이가쿠 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN104752400A (zh) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | 互连介质层、其制作方法及包括其的半导体器件 |
US9620357B2 (en) | 2015-07-24 | 2017-04-11 | Hitachi Kokusai Electric Inc. | Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013058559A (ja) * | 2011-09-07 | 2013-03-28 | Tokyo Electron Ltd | 半導体装置の製造方法及び基板処理システム |
JP2014036148A (ja) * | 2012-08-09 | 2014-02-24 | Tokyo Electron Ltd | 多層膜をエッチングする方法、及びプラズマ処理装置 |
CN102881611B (zh) * | 2012-10-12 | 2015-05-20 | 上海华力微电子有限公司 | 晶圆电性测试的方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08148562A (ja) * | 1994-11-18 | 1996-06-07 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
WO2000021124A1 (fr) * | 1998-10-05 | 2000-04-13 | Tokyo Electron Limited | Dispositif a semi-conducteurs et procede de fabrication de ce dernier |
JP2000133710A (ja) * | 1998-10-26 | 2000-05-12 | Tokyo Electron Ltd | 半導体装置及びその製造方法 |
WO2000054329A1 (fr) * | 1999-03-09 | 2000-09-14 | Tokyo Electron Limited | Dispositif semi-conducteur et procede de fabrication correspondant |
JP2002252280A (ja) * | 2001-02-26 | 2002-09-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003531493A (ja) * | 2000-04-03 | 2003-10-21 | シャープ株式会社 | 炭化ケイ素密着プロモータ層を用いた低誘電率フッ素含有アモルファスカーボンへの窒化ケイ素の密着性を高めるための方法 |
WO2005069367A1 (ja) * | 2004-01-13 | 2005-07-28 | Tokyo Electron Limited | 半導体装置の製造方法および成膜システム |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6310300B1 (en) * | 1996-11-08 | 2001-10-30 | International Business Machines Corporation | Fluorine-free barrier layer between conductor and insulator for degradation prevention |
JP4194521B2 (ja) | 2004-04-07 | 2008-12-10 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP4555143B2 (ja) * | 2004-05-11 | 2010-09-29 | 東京エレクトロン株式会社 | 基板の処理方法 |
-
2006
- 2006-03-31 JP JP2006099770A patent/JP5119606B2/ja not_active Expired - Fee Related
-
2007
- 2007-03-27 EP EP07739885A patent/EP2003687A4/en not_active Withdrawn
- 2007-03-27 WO PCT/JP2007/056447 patent/WO2007116758A1/ja active Application Filing
- 2007-03-27 KR KR1020087005618A patent/KR100942179B1/ko not_active IP Right Cessation
- 2007-03-27 CN CN2007800013688A patent/CN101356638B/zh not_active Expired - Fee Related
- 2007-03-30 TW TW096111350A patent/TW200805498A/zh not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08148562A (ja) * | 1994-11-18 | 1996-06-07 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
WO2000021124A1 (fr) * | 1998-10-05 | 2000-04-13 | Tokyo Electron Limited | Dispositif a semi-conducteurs et procede de fabrication de ce dernier |
JP2000133710A (ja) * | 1998-10-26 | 2000-05-12 | Tokyo Electron Ltd | 半導体装置及びその製造方法 |
WO2000054329A1 (fr) * | 1999-03-09 | 2000-09-14 | Tokyo Electron Limited | Dispositif semi-conducteur et procede de fabrication correspondant |
JP2003531493A (ja) * | 2000-04-03 | 2003-10-21 | シャープ株式会社 | 炭化ケイ素密着プロモータ層を用いた低誘電率フッ素含有アモルファスカーボンへの窒化ケイ素の密着性を高めるための方法 |
JP2002252280A (ja) * | 2001-02-26 | 2002-09-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
WO2005069367A1 (ja) * | 2004-01-13 | 2005-07-28 | Tokyo Electron Limited | 半導体装置の製造方法および成膜システム |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012084638A (ja) * | 2010-10-08 | 2012-04-26 | Tohoku Univ | 半導体装置の製造方法および半導体装置 |
KR101417723B1 (ko) | 2011-09-07 | 2014-07-08 | 도호쿠 다이가쿠 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN104752400A (zh) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | 互连介质层、其制作方法及包括其的半导体器件 |
US9620357B2 (en) | 2015-07-24 | 2017-04-11 | Hitachi Kokusai Electric Inc. | Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium |
US9881789B2 (en) | 2015-07-24 | 2018-01-30 | Hitachi Kokusai Electric, Inc. | Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium |
Also Published As
Publication number | Publication date |
---|---|
CN101356638A (zh) | 2009-01-28 |
KR100942179B1 (ko) | 2010-02-11 |
EP2003687A1 (en) | 2008-12-17 |
EP2003687A4 (en) | 2011-08-10 |
KR20080034503A (ko) | 2008-04-21 |
CN101356638B (zh) | 2010-12-01 |
TWI362703B (ja) | 2012-04-21 |
JP5119606B2 (ja) | 2013-01-16 |
TW200805498A (en) | 2008-01-16 |
WO2007116758A1 (ja) | 2007-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100743745B1 (ko) | 반도체장치의 제조방법 및 성막시스템 | |
JP4256763B2 (ja) | プラズマ処理方法及びプラズマ処理装置 | |
JP4715207B2 (ja) | 半導体装置の製造方法及び成膜システム | |
JP5119606B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
KR101110103B1 (ko) | 성막 방법, 성막 장치, 기억 매체 및, 반도체 장치 | |
CN101647110B (zh) | 半导体器件及其制造方法 | |
JP2007317872A (ja) | 成膜方法、成膜装置及び記憶媒体、並びに半導体装置 | |
JP4413556B2 (ja) | 成膜方法、半導体装置の製造方法 | |
JP4194521B2 (ja) | 半導体装置の製造方法 | |
JP5082411B2 (ja) | 成膜方法 | |
JP3472196B2 (ja) | エッチング方法及びそれを用いた半導体装置の製造方法 | |
JP2004349458A (ja) | フッ素添加カーボン膜の形成方法 | |
KR100414611B1 (ko) | 반도체 장치의 제조 방법 | |
KR20120092545A (ko) | 비정질 탄소의 도핑에 의해 불화탄소(cfx) 막의 접착성을 향상시키는 방법 | |
US7851351B2 (en) | Manufacturing method for semiconductor devices with enhanced adhesivity and barrier properties | |
JP5304759B2 (ja) | 成膜方法及び半導体装置 | |
JP2005123406A (ja) | プラズマエッチング方法。 | |
JP2008085297A (ja) | 半導体装置の製造方法 | |
JP2006059848A (ja) | レジスト除去方法及び半導体装置の製造方法 | |
JP2009295992A (ja) | 半導体装置の製造方法、半導体装置 | |
JP2008227308A (ja) | 絶縁膜の形成方法およびこれを用いた半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090330 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120508 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120709 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120712 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120925 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121008 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151102 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |