JP2007214571A - 均一な共平面性を有する多層フリップチップバンプの高さを制御する方法及び関連装置 - Google Patents
均一な共平面性を有する多層フリップチップバンプの高さを制御する方法及び関連装置 Download PDFInfo
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- JP2007214571A JP2007214571A JP2007029556A JP2007029556A JP2007214571A JP 2007214571 A JP2007214571 A JP 2007214571A JP 2007029556 A JP2007029556 A JP 2007029556A JP 2007029556 A JP2007029556 A JP 2007029556A JP 2007214571 A JP2007214571 A JP 2007214571A
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- flip chip
- polishing
- chip bump
- bump
- height
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Abstract
【解決手段】方法は、(a)フォトリソグラフィープロセスでフリップチップバンプのパターンを基板上に定め、(b)ステップ(a)でつくられたフリップリップバンプのパターンに、電気めっき法で金属または合金を堆積してフリップチップバンプにし、(c)電気めっき法で堆積されたフリップチップバンプを研磨法で平坦化させ、均一な共平面性を有する平面フリップチップにし、(d)上記ステップ(a)からステップ(c)を繰り返し、(e)フォトレジストとシード層を除去し、(f)平坦化された平面フリップチップバンプをリフロー炉に入れ、リフロープロセスで均一な共平面性を有する球面フリップチップバンプをつくるステップからなる。
【選択図】図2−1
Description
この発明は更に均一な共平面性を有する多層フリップチップバンプの高さを制御する装置を提供する。そのうち研磨プロセスは、研磨台、研磨盤、研磨パッド、研磨スラリー及び基板締付具からなる研磨装置で行われる。
本発明による研磨技術は、めっき後バンプの共平面性を大きく向上させることができるため、精密で高価な電気めっき設備や締付具を必要とせず、作業員の素質に対する要求が低く、電源供給装置の分解能もμAに達しなくてもよいため、製作コストを大幅に削減できる。
図1を参照する。以下に本発明で利用されるプロセス及び設備を説明する。
フォトリソグラフィー(露光及び現像)とは、ポジティブフォトレジスト、ネガティブフォトレジスト、ポリアミドなどをスピンコート法で基板の表面に塗布した後、マスクやステンシルをかけて露光させ、フリップチップバンプの構造を定めるプロセスをいう。
ステップ1:図2−1(a)に示すように、スパッタリング法または蒸着法で基板1の上にクロム2と銅3からなるUBM(アンダーバリアメタル)シードレイヤーを形成する。
ステップ2:図2−1(b)に示すように、第一厚膜フォトレジスト4をスピンコート法で塗布する。
ステップ3:図2−1(c)に示すように、ソフトベーキング、フォトリソグラフィー及びハードベーキングで、第一バンプパターン5を定める。
ステップ4:図2−1(d)に示すように、第一バンプ6をめっきする。
ステップ5:図2−2(e)に示すように、研磨プロセスでめっき後の第一バンプ6の表面を研磨し、第一平面バンプ7にする。
ステップ6:図2−2(f)に示すように、第二厚膜フォトレジスト8をスピンコート法で塗布する。
ステップ7:図2−2(g)に示すように、ソフトベーキング、フォトリソグラフィー及びハードベーキングで、第二バンプパターン9を定める。
ステップ8:図2−2(h)に示すように、第二バンプ10をめっきする。
ステップ9:図2−3(i)に示すように、研磨プロセスでめっき後の第二バンプ10の表面を研磨し、第二平面バンプ11にする。
ステップ10:図2−3(j)に示すように、アセトンやフォトレジスト除去剤で第一厚膜フォトレジスト4、第二厚膜フォトレジスト8、及びクロム2、銅3のUBMシード膜を除去し、二層平面バンプ11にする。
ステップ11:図2−3(k)に示すように、リフロープロセスで二層平面チップ12を加熱して、二層球面バンプ13にする。
上記ステップ2とステップ5は繰り返してもよい。より多層かつアスペクト比の大きいフリップチップバンプを製作するため、上記めっき材と研磨液はバンプ設計の条件に応じて変更できる。
以上はこの発明に好ましい実施例であって、この発明の実施の範囲を限定するものではない。よって、当権利者のなし得る修正、もしくは変更であって、この発明の意図の下においてなされ、この発明に対して均等の効果を有するものは、いずれもこの発明の特許請求の範囲に属するものとする。
2 クロム堆積層
3 銅堆積層
4 第一厚膜フォトレジスト
5 第一バンプパターン
6 第一バンプ
7 第一平面バンプ
8 第二厚膜フォトレジスト
9 第二バンプパターン
10 第二バンプ
11 第二平面バンプ
12 二層平面バンプ
13 二層球面バンプ
21 荷重
22 研磨スラリー
23 研磨パッド
24 研磨盤
25 研磨液貯蔵槽
26 タービンポンプ
31 基板締付具
32 PVCリング
33 多孔質弾性パッド
Claims (9)
- MEMS(微小電子機械システム)技術に属する多層フォトリソグラフィープロセス、電気めっきプロセス、研磨プロセス、フォトレジスト除去プロセスとシード層成膜プロセス、及びリフロープロセスからなる、均一な共平面性を有する多層フリップチップバンプの高さを制御する方法であって、
(a)フォトリソグラフィープロセスでフリップチップバンプのパターンを基板上に定め、
(b)ステップ(a)でつくられたフリップリップバンプのパターンに、電気めっき法で金属または合金を堆積してフリップチップバンプにし、
(c)電気めっき法で堆積されたフリップチップバンプを研磨法で平坦化させ、均一な共平面性を有する平面フリップチップにし、
(d)上記ステップ(a)からステップ(c)を繰り返し、
(e)フォトレジストとシード層を除去し、
(f)平坦化された平面フリップチップバンプをリフロー炉に入れ、リフロープロセスで均一な共平面性を有する球面フリップチップバンプをつくるステップからなることを特徴とする多層フリップチップバンプの高さ制御方法。 - 前記ステップ(b)でつくられるフリップチップバンプの第一層は、シード層と同じく銅または銅合金からなることを特徴とする請求項1記載の多層フリップチップバンプの高さ制御方法。
- 前記ステップ(b)でつくられるフリップチップバンプの第二層以上は、すず鉛合金または鉛フリーのすず、すず銀合金、すず銅合金、すずビスマス合金、またはすず銀銅合金からなることを特徴とする請求項1記載の多層フリップチップバンプの高さ制御方法。
- 前記ステップ(c)でつくられる平面フリップチップバンプの高さを、研磨法で所定範囲にすることを特徴とする請求項1記載の多層フリップチップバンプの高さ制御方法。
- 均一な共平面性を有する多層フリップチップバンプの高さを制御する装置において、研磨プロセスが、研磨台、研磨盤、研磨パッド、研磨スラリー及び基板締付具からなる研磨装置で行われることを特徴とする多層フリップチップバンプの高さ制御装置。
- 前記研磨盤は硬質のステンレス鋼または鋳鉄からなることを特徴とする請求項5記載の多層フリップチップバンプの高さ制御装置。
- 前記研磨パッドは接着式の軟質パッドであることを特徴とする請求項5記載の多層フリップチップバンプの高さ制御装置。
- 前記研磨スラリーとして、研磨台の回転速度、めっき金属の成分及び研磨パッドの硬さに応じて、Al2O3、SiO2、CeO2またはZrO2を使用することを特徴とする請求項5記載の多層フリップチップバンプの高さ制御装置。
- 前記基板締付具は、弾力性のある多孔質パッドと、これを囲んで基板と同じ高さを有するリングからなることを特徴とする請求項5記載の多層フリップチップバンプの高さ制御装置。
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TW095104212 | 2006-02-08 | ||
TW095104212A TW200731430A (en) | 2006-02-08 | 2006-02-08 | Controllable method for manufacturing uniform planarity of plating-based solder bumps on multi-layer flip chip used in the three-dimensional packaging |
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US20090111299A1 (en) * | 2007-10-31 | 2009-04-30 | International Business Machines Corporation | Surface Mount Array Connector Leads Planarization Using Solder Reflow Method |
US7642135B2 (en) * | 2007-12-17 | 2010-01-05 | Skyworks Solutions, Inc. | Thermal mechanical flip chip die bonding |
US9035459B2 (en) | 2009-04-10 | 2015-05-19 | International Business Machines Corporation | Structures for improving current carrying capability of interconnects and methods of fabricating the same |
US8637392B2 (en) | 2010-02-05 | 2014-01-28 | International Business Machines Corporation | Solder interconnect with non-wettable sidewall pillars and methods of manufacture |
US8492891B2 (en) | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
US8232193B2 (en) | 2010-07-08 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming Cu pillar capped by barrier layer |
US8344504B2 (en) | 2010-07-29 | 2013-01-01 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Semiconductor structure comprising pillar and moisture barrier |
US8314472B2 (en) | 2010-07-29 | 2012-11-20 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Semiconductor structure comprising pillar |
US8492892B2 (en) | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
US8536707B2 (en) | 2011-11-29 | 2013-09-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor structure comprising moisture barrier and conductive redistribution layer |
US8653658B2 (en) * | 2011-11-30 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarized bumps for underfill control |
US8803333B2 (en) | 2012-05-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional chip stack and method of forming the same |
CN103730382B (zh) * | 2013-12-24 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 一种铜铜键合凸点的制作方法 |
US9343420B2 (en) | 2014-02-14 | 2016-05-17 | Globalfoundries Inc. | Universal solder joints for 3D packaging |
US9324557B2 (en) | 2014-03-14 | 2016-04-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method for fabricating equal height metal pillars of different diameters |
US10546836B2 (en) | 2016-09-22 | 2020-01-28 | International Business Machines Corporation | Wafer level integration including design/co-design, structure process, equipment stress management and thermal management |
CN111370572B (zh) * | 2020-02-28 | 2023-11-10 | 浙江东瓷科技有限公司 | 一种气密性电流传感器倒扣焊封装结构 |
CN117747455A (zh) * | 2024-02-21 | 2024-03-22 | 北京大学 | 基于激光加工的微凸点基板及制备方法、微凸点互联结构 |
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JPH0817832A (ja) * | 1994-06-29 | 1996-01-19 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
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