WO2009130442A1 - Method of applying a bump to a substrate - Google Patents

Method of applying a bump to a substrate Download PDF

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Publication number
WO2009130442A1
WO2009130442A1 PCT/GB2009/000972 GB2009000972W WO2009130442A1 WO 2009130442 A1 WO2009130442 A1 WO 2009130442A1 GB 2009000972 W GB2009000972 W GB 2009000972W WO 2009130442 A1 WO2009130442 A1 WO 2009130442A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
solder
layer
conductive pad
masking layer
Prior art date
Application number
PCT/GB2009/000972
Other languages
French (fr)
Inventor
David John Pedder
Simon Mason
Original Assignee
The Welding Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Welding Institute filed Critical The Welding Institute
Publication of WO2009130442A1 publication Critical patent/WO2009130442A1/en

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Definitions

  • the invention relates to a method for applying an electrically conductive bump to a substrate.
  • Adhesive flip chip bonding utilises conductive or non-conductive adhesives to join bumped integrated circuit (IC) chips to devices. Certain devices cannot tolerate adhesives, and problems can be encountered when dispensing adhesive. Curing times can also limit throughput.
  • Thermocompression and thermosonic bonding techniques utilise a combination of heat and pressure or heat, pressure and vibration to create solid state bonds between metallic balls and bond pads. These techniques involve serial bump-by-bump placement, so are therefore relatively slow, and are sensitive to errors in placement through die misalignment.
  • solder bumping was developed for various applications in the 1960s and 70s and is the most widely used technology for bonding of flip chips. These techniques generally require the placement of an under-bump metallisation (UBM) over the bond pad by sputtering, plating, or a similar means.
  • UBM under-bump metallisation
  • the UBM provides ohmic contact to (mostly aluminium) chip conductive pads, and is typically made up of several metallic layers.
  • the chip (or other substrate) surface is typically covered using a protective or "passivation” layer. This can be an organic or inorganic layer such as silicon nitride or polyamide.
  • the UBM allows adequate solder wetting and contact (electrical, thermal, mechanical) between pad and bump.
  • the UBM also prevents corrosion of the bond pad material and reaction/diffusion between pad and solder bump.
  • the UBM has to be carefully selected to take account of bump material and type, operating conditions and process requirements.
  • Different UBM depositing techniques generally marry to specific bump forming methods. Solder bump forming methods include evaporation, electroplating, printing and immersion soldering.
  • Evaporation processes are generally limited to high lead solders, cannot easily be used with larger wafers, have limited throughput and high capital equipment costs.
  • Electroplating processes are widely used and, although less costly than evaporation processes, require several masking and photopatterning steps and so are not truly low cost.
  • US-B-6900117 discloses a method of fabricating anisotropic bumps utilizing a single resist for patterning and electroless nickel bump formation with a resist hardening step, whereby energy is applied to cause cross-linking prior to forming.
  • This cross-linking is implemented to improve adhesion of the resist layer. Lack of resist adhesion during electroless plating is a common problem if the correct combinations of chemicals and conditions are not selected and can lead to the formation of inconsistent bumps.
  • Energy is applied by incorporating a curing regime using a resist baking step combined with light irradiation to cause cross-linking in the resist layer (consisting of a resin and a photosensitive agent) and prevent degradation during the chemically aggressive electroless plating process.
  • Ni bump UBM electroless nickel
  • Immersion soldering does not require lithographic masking or etching processes, or high capital expenditure, and hence is of low cost.
  • the Ni bump structure may be additionally coated with a thin immersion gold (Au) surface layer to ensure good solderability.
  • Au immersion gold
  • the wafer of Ni/Au bumped IC devices is then immersed into and withdrawn from a reservoir of molten solder. Glycerol or another medium that prevents oxidation may be provided as a floating layer or in another fashion to protect the solder.
  • Immersion solder bumping is described as being a low cost alternative to conventional processes in the case where only a thin solder layer is needed. Parameters such as multiple dipping, immersion depth, Ni bump height and dipping rate are mentioned as affecting solder deposition, which is always of a low volume. These very low resulting bump heights can lead to inconsistencies during bonding, and unfortunately limits the applicability of immersion soldering. It is noted that, due to the thin solder layer presented, limitation to such techniques as thermode bonding (pressing using a hot bar) is generally required to ensure proper bonding and overcome inconsistent bump heights, lack of flatness etc.
  • pillar structures is advantageous over isotropically grown structures in interconnecting IC devices to substrates for various reasons including allowing greater stand off distances between devices and substrates to compensate for differences in thermal expansion and to allow fine connecting pitches to be achieved.
  • the use of pillar structures is known in the prior-art:
  • US20050077624A describes a die comprising of a substrate and pillar structures of varying shapes, typically created by electroplating and solder reflow.
  • US6592019B discloses a flip chip interconnect method whereby an elongated column of metal is formed within a hole formed by radiation in a photosensitive polymer (known as a mask) following which the mask is removed.
  • the elongated metal column consists of a low melting temperature upper portion (typically solder) and higher melting temperature lower portion (typically copper) which are deposited in the hole before removal of the mask.
  • the advantages of this method include a reduced use of lead solder, fine pitch and ease of underfill.
  • this method has several disadvantages, namely that a separate mask is obviously required for patterning of the passivation layer prior to the mask for pillar deposition, and that the copper and solder layers which make up the pillar are deposited using electroplating, which also requires a seed layer. This makes for a relatively expensive process.
  • US20050026413A describes a method of forming a series of conductive pillars on a wafer having an active surface.
  • Conductive material is generally electroplated onto a metallic layer formed on the active surface through an opening in a mask layer to create a pillar, which is then followed by a further operation to create a solder cap on top of the cylinder.
  • the mask layer and metallic layer are then removed to leave a cylindrical bonding structure.
  • a reflow operation can be performed to adjust the shape of the solder cap.
  • US20030107132A describes a method for creating an anisotropic, pillar shaped metal bump structure by using the mask to constrain growth of an electroless bump and/or a Au cap (used to prevent oxidation and preserve solder wettability).
  • a Au cap used to prevent oxidation and preserve solder wettability.
  • several masking procedures are used during the different processing steps (again, for patterning of the passivation layer prior to a further mask for forming the bump structures), which lead to a significant increase in cost.
  • a method of applying a bump to a conductive pad on a substrate having a passivation layer over the conductive pad comprises: a) providing a masking layer over the passivation layer; b) patterning and developing the masking layer to define a cavity extending through the masking layer in alignment with the conductive pad; c) removing part of the passivation layer exposed in the cavity so as to expose the conductive pad; d) forming a bump in the cavity contacting the conductive pad; and, e) removing the masking layer; the method further comprising applying a layer of solder to the bump by immersing the substrate in a solder bath.
  • the invention relates to an improved method of producing a bump, particularly for use in a flip chip bonding process that utilises the control of the shape of a bump during its growth, and the structures created using this method.
  • the substrate is typically a semiconductor wafer but could be a MEMS device, ceramic or polymer carrier, or even a metallic item.
  • the ceramic or polymer carrier could be part of a microprocessor component or multidevice module.
  • the preferred bumping methods are electroless processes, in particular an electroless Ni process. While this technology is described as being 'electroless Ni 1 , it should be understood that other elements may be present in the formed bumps, such as quantities of phosphorus or other elements.
  • Alternatives to electroless plating of the bump include deposition of solder pastes by printing, jetting etc.
  • the bump geometries and immersion soldering procedure of the invention provide a truly low cost, simplified process for forming bumped and solder-deposited structures for use in microassembly, particularly in the field of microelectronics and semiconductors, more particularly for use during flip-chip bonding.
  • the volume of solder deposited during immersion solder bumping can be increased by providing a marked discontinuity in slope between the sidewall and upper face of a bump.
  • the invention makes use of a single, relatively thick, mask during integrated circuit back-end processing for both patterning of the integrated circuit passivation layer (a subtractive process) and for constraining the lateral growth of an electroless Ni bump grown on the resulting exposed chip metallisation layer (an additive process).
  • inventive structure formed by this method is often physically discernable from the prior art in that the internal diameter of the passivation (or equivalent dimension for non-cylindrical openings) is substantially equal to the external diameter (or equivalent) of the formed bump, prior to subsequent processing or addition of a protective layer. It can also often be noted that the bump sidewall is substantially continuous over the height of the bump, exhibiting no sharp changes or discontinuities in curvature.
  • a photosensitive polymer layer on the integrated circuit as an in-situ mask for the patterning and removal of the passivation layer from the area of the bond pad.
  • This can typically be of a positive or negative working nature.
  • the invention involves the further use of in-situ polymeric masking as a confinement structure for the growth of the electroless Ni bump, in order to define a columnar structure.
  • the in-situ mask layer may then be partially or totally removed to expose the corners of the bump.
  • This aspect of the invention makes use of the single photoresist layer to fulfil two processing functions, which also results in no additional process costs. This is in contrast to plating based solder bumping technologies where additional masking layers and patterning steps are required.
  • the invention makes a combined or dual use of the thick photoresist mask for the dry etching of the passivation layer and the restraining of the growth of the electroless Ni bump.
  • a separate (undisclosed) process has been used to etch the passivation layer, as can be seen from numerous figures.
  • the extra masking steps required for this process lead to a particular disadvantage, especially with regard to cost of the process.
  • the present invention overcomes this disadvantage by using the same photoresist mask for both removal of the passivation layer and formation of the advantageous pillar structures. That is, for a subtractive operation and additive operation.
  • the subtractive processes e.g. etching of passivation
  • the additive processes e.g. deposition of seed layer/UBM/bump metals
  • the invention uses one masking step to account for both subtractive and additive processes.
  • One embodiment of the invention includes finishing of the electroless Ni bump with an immersion Au layer to preserve solderability and prevent Ni oxidation.
  • This layer may be added over the upper Ni surface while the resist mask is still present and/or to the Ni upper surface and the Ni sides after the resist has been removed.
  • Another embodiment of the invention includes leaving the mask layer in place after processing to provide a supporting collar for the bump that would enhance the thermal cycling fatigue life of the final flip chip solder joint and mechanical shock resistance of the assembly in the case of an IC chip.
  • a benefit of the confined growth of the Ni bump in the inventive process relates to the lack of lateral growth of the bump during the process.
  • Bumps formed according to the invention possess a lower surface area, and an upper surface area substantially equal to the area of the integrated circuit metallisation onto which the bump is grown. This allows the bumping structures to be defined at smaller pitches than conventional bumps or, for a given pitch or Ni bump base diameter, provide an increase in chip metallisation contact area and solder bond area.
  • solder joint thermal cycling fatigue life will reduce electrical resistance, reduce bond current density, improve electromigration reliability, improve thermal transfer and improve solder joint thermal cycling fatigue life. Also, following for example an immersion soldering process, enough solder can be provided for formation of a reliable interconnection with the substrate without the use of further material during the assembly process. Apart from immersion soldering, other solder deposition processes well known in the art can also be used.
  • bump geometries can be formed by the process.
  • these can include geometries with substantially vertical sides, undercut, angled or partially concave sides.
  • the particular bump geometry formed by the invention is of particular benefit when used for immersion solder bumping.
  • No similar bump profile for use during immersion solder bumping has been previously described in the prior-art.
  • An electroless Ni bump formed using the inventive processes typically possesses a marked (often greater or equal to 90 degrees) discontinuity in slope between the sidewall and the upper face that influences the solder separation process in immersion soldering to increase the solder volume retained on the Ni bump.
  • the solder On immersion soldering, the solder is restrained by the edges of the bump, thus giving an anisotropic profile with enhanced quantities of solder.
  • the extra volume of solder retained by the bump is suitable to bond the chip without the need for further bonding material.
  • Other soldering methods are expected to benefit in a similar manner.
  • Substrates processed according to the invention can then be utilised in existing IC wafer and flip chip processing technologies.
  • bumps can be made with a wide range of possible pitches, although these are preferably with a pitch of between 30-180 microns.
  • a typical product formed by the above described processes is an improved flip chip solder bonded assembly. This can be produced by dicing immersion bumped devices from integrated circuit wafers treated as described above, and flip chip bonding them to a substrate with an array of matching solder wettable pads.
  • the total process from provision of a typical oxide-isolated silicon wafer, with metallisation and passivation, provides a low cost solder bumping technology for IC wafers compatible with both conventional tin/lead solder alloys and the recently introduced lead-free solder alloys.
  • bumps created using these inventive methods may also be used in other applications, including bonding of SAW devices, passive filters, detector arrays, MEMs and in non-microelectronic fields.
  • the bumps could be formed away from any active pathways or coated with a non-conductive layer to act as spacers for defining distances between substrate surfaces. This could be for spacing of microelectronic devices, including heatsinks and chips or even non-microelectronic devices.
  • Figure 2 shows a bumping structure formed by an embodiment of a method according to the invention
  • Figures 3 to 10 show some typical process sequences according to the invention
  • Figures 11 to 13 show the steps that occur during an immersion bumping withdrawal process, using a structure formed according to the invention
  • Figures 14 and 15 show bumping structures made according to a conventional process and according to an embodiment of the invention respectively;
  • Figure 16 shows several possible bump profiles
  • Figure 17 shows the positions of the passivation and bump boundaries formed on a prior-art bumping structure.
  • Figure 18 shows the positions of the passivation and bump boundaries formed on a bumping structure according to the invention.
  • a silicon IC device or wafer is provided with a thin (1-3 microns) aluminium alloy metallisation layer and silicon nitride passivation layer.
  • a photosensitive polymer resist mask layer (for example a polyimide or polybenzoxylene, 10-25 micons thick, more typically between 15-20 microns thick) is deposited onto the IC device, which is subsequently developed in selected areas by radiation exposure. This is followed by a dry etching step to remove the passivation in the areas exposed by the mask, forming tall-sided cavities, at the bottom of which lie the exposed regions of metallisation (bond pads).
  • An electroless Ni bump growth process is then used to deposit a typically columnar, anisotropic Ni bump.
  • the bump structure can be protectively coated in Au, prior to mask stripping, or subject to deposition of a Au coating after a mask layer stripping step.
  • the structure can then be immersed in a reservoir of molten solder, which results in the deposition of a solder cap, ready for further processing and incorporation into microelectronic assemblies. All of the above processing operations utilise existing materials and technology well known in the art. Alternative materials and processing technologies know to the skilled practitioner can be substituted for those described above where appropriate.
  • a conventional immersion solder bumping structure is shown in Figure 1 and comprises a silicon IC device 1 on which has been provided a metallisation 2, a silicon nitride passivation layer 3, a Ni bump 4 and a solder cap 5.
  • the solder cap exhibits a relatively low contact angle 6a (typically less than 20°), which is typical of the solder deposition onto conventional, convex, isotropically grown, Ni/Au bumps as the wafer leaves the solder bath.
  • the illustrated solder cap is typical of those provided on conventionally shaped bumps, and is relatively thin (typically less than 10 microns).
  • Figure 2 illustrates an immersion solder bumping structure according to an embodiment of the invention which comprises a silicon IC device 1 on which has been provided a metallisation 2, a silicon nitride passivation layer 3, a Ni bump 8 and a solder cap 9.
  • the solder cap exhibits a relatively high contact angle 6b (typically above 45°), which is noticeable when depositing solder onto a bump grown according to the invention, as the wafer leaves the solder bath.
  • Reference 10 indicates the region at which a supporting polymer mask structure is provided to allow non-isotropic growth of the bump.
  • Figures 3-10 illustrate a typical process sequence according to the invention.
  • Figure 3 shows a silicon IC device or wafer which has been provided with a thin (1-3 microns) aluminium alloy metallisation layer 2 and silicon nitride passivation layer (0.5-2 microns) 3.
  • Figure 4 shows the IC device following deposition of a positive working photosensitive polymer resist mask layer (10-25 microns thick) 11 , which is developed in selected areas defined by the patterning 12 and radiation exposure 13 in Figure 5.
  • the patterning is a photomask defining areas exposed to radiation (typically UV). This defines a cavity 7, shown in Figure 6.
  • Figure 7 illustrates the removal of the passivation 3 by dry etching in pre-defined areas exposed by the mask 11.
  • a bump is grown 8 (typically by electroless Ni process) as shown in Figure 8.
  • the bump shown in Figure 8 which may be cylindrical, is defined by the shape of the cavity into which it is deposited and is typically of a columnar, anisotropic shape.
  • Figure 11 shows deposition of a Au coating 14, after which the mask layer can be optionally stripped.
  • the bump structure can be subject to deposition of a Au coating after a mask layer stripping step immediately proceeding Figure 8, as illustrated in Figure 9.
  • Figure 12-13 illustrate the stages in an immersion bumping withdrawal process.
  • Figure 12 shows the near point of instability and solder meniscus separation as the silicon IC 1 (passivation 3, bond pad 2 and bump 8 are shown) is removed from the solder bath. During this process, the protective Au coating is rapidly dissolved in the solder.
  • Figure 13 shows the remaining quantity of solder left on the bump after complete withdrawal and solder separation. In practice the process that defines the volume and shape of the solder that remains on the electroless Ni bump after the immersion process is complex, but can be illustrated simply, as shown by these figures.
  • the Ni bump is initially wetted by the molten solder and as the bumped wafer is withdrawn the solder meniscus necks down until a point of instability is reached and the solder on the Ni bump and that in the solder bath separate. This solder volume then redistributes itself across the electroless Ni bump surfaces to minimise the overall surface energy.
  • Figures 14 and 15 illustrate another advantage of the invention, and show the difference between a prior-art method and the invention.
  • Figure 14 shows a silicon IC 1 with metallisation 2, known bump geometry 4 and typical volume of solder 5.
  • Figure 15 shows a silicon IC 1 with metallisation 2, bump geometry 8 and solder volume deposited due to the bump shape provided by the invention.
  • the increase in chip metallisation contact area and solder bond area at a given bump base diameter (or pitch) resulting from the use of the inventive process is clearly evident.
  • the solder separation volume depends upon the Ni bump shape and the withdrawal angle with respect to the bump geometry and to gravity.
  • solder volume would then redistribute itself across the Ni bump surfaces to provide an increased solder bump height for the Ni bump profile formed according to the invention, due to the restraining effect of the edged structure, whereas for a conventional Ni bump structure, solder would not be as well restrained and would therefore form a solder bump of lesser height.
  • Figure 16 shows several bump profiles formed according to embodiments of the invention using correspondingly shaped cavities 7, vertical 15, undercut 16, concave 17, although other variations are possible.
  • the structures formed with these edge profiles can be symmetrical (cylindrical, rectangular, other polygonal), or otherwise.
  • Figure 17 illustrates the non-coincidental nature of the passivation 18 and bump boundaries 19 on a prior art columnar bumping structure, such as those formed by processes described in US20030107132A, consisting of bump 22, protective coating 14, passivation 3, bond pad 2 and substrate 1. This is due to the different masking steps used during patterning and formation of the bump. A similar non-coincidental bump/passivation boundary would be seen if the bumping structure was isotropically grown, rather than formed as a column.
  • Figure 18 illustrates the coincidental nature of the passivation 20 and bump boundaries 21 on a bump structure according to the invention, consisting of bump 8, protective coating 14, passivation 3, bond pad 2 and substrate 1.
  • the internal diameter of the passivation is substantially equal to the external diameter of the formed bump and exhibits no sharp changes or discontinuities in curvature. This is due to the common masking step used during patterning and formation of the bump.
  • the boundaries shown are vertical, some degree of angling or curvature may be present along either the bump boundary (as shown in Figure 16), passivation boundary or both. This may be due to design requirements, material types (positive or negative resists) or chemical and physical effects, but the boundaries will always be substantially coincidental.

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Abstract

A method of applying a bump to a conductive pad (2) on a substrate (1) having a passivation layer (3) over the conductive pad. The method comprises: a) providing a masking layer (11) over the passivation layer; b) patterning and developing the masking layer (11) to define a cavity (7) extending through the masking layer in alignment with the conductive pad (2); c) removing part of the passivation layer (3) exposed in the cavity (7) so as to expose the conductive pad; d) forming a bump (8) in the cavity contacting the conductive pad; and, e) removing the masking layer (11); the method further comprising applying a layer of solder (9) to the bump by immersing the substrate in a solder bath.

Description

METHOD OF APPLYING A BUMP TO A SUBSTRATE
Field of Invention
The invention relates to a method for applying an electrically conductive bump to a substrate.
Background
Up to the year 2000, flip chip bonding was employed in about 2 per cent of all silicon device assemblies, with wire bonding being used for the remaining 98 per cent. Over the past 7 years, however, flip chip assembly has seen very significant growth, driven by the relentless demand for higher chip Input/Output (I/O) count, higher operating frequency and lower assembly costs per pin. Flip chip bonding today accounts for 5 per cent of all silicon devices and this figure is predicted to continue to grow over the next five years. There is, therefore, a very strong interest in developing very low cost methods of producing 'bumps' on wafers (bumping technologies) to support this growth rate and to meet the pad pitch and costs per pin targets set out in the industry roadmaps. In this specification, 'bump' means a non-metallic, or preferably metallic, electrically conductive I/O structure. Various technologies exist for flip chip interconnection.
Adhesive flip chip bonding utilises conductive or non-conductive adhesives to join bumped integrated circuit (IC) chips to devices. Certain devices cannot tolerate adhesives, and problems can be encountered when dispensing adhesive. Curing times can also limit throughput. Thermocompression and thermosonic bonding techniques (stud bumping) utilise a combination of heat and pressure or heat, pressure and vibration to create solid state bonds between metallic balls and bond pads. These techniques involve serial bump-by-bump placement, so are therefore relatively slow, and are sensitive to errors in placement through die misalignment.
Solder bumping was developed for various applications in the 1960s and 70s and is the most widely used technology for bonding of flip chips. These techniques generally require the placement of an under-bump metallisation (UBM) over the bond pad by sputtering, plating, or a similar means. The UBM provides ohmic contact to (mostly aluminium) chip conductive pads, and is typically made up of several metallic layers. The chip (or other substrate) surface is typically covered using a protective or "passivation" layer. This can be an organic or inorganic layer such as silicon nitride or polyamide. The UBM allows adequate solder wetting and contact (electrical, thermal, mechanical) between pad and bump. The UBM also prevents corrosion of the bond pad material and reaction/diffusion between pad and solder bump. The UBM has to be carefully selected to take account of bump material and type, operating conditions and process requirements. Different UBM depositing techniques generally marry to specific bump forming methods. Solder bump forming methods include evaporation, electroplating, printing and immersion soldering.
Evaporation processes are generally limited to high lead solders, cannot easily be used with larger wafers, have limited throughput and high capital equipment costs.
Electroplating processes are widely used and, although less costly than evaporation processes, require several masking and photopatterning steps and so are not truly low cost.
Several low-cost techniques exist for creating solder bumps. Stencil printing of solder paste or conductive adhesive is a low-cost technology that has attracted much interest for flip chip interconnection. Apart from being cost efficient, environmental concerns are addressed by this technology as lead free alloy pastes/adhesives are available. However, due to limitations in available materials and stencil geometries, at present this process is limited in pitch down to 150-200 microns for high volumes.
US-B-6900117 discloses a method of fabricating anisotropic bumps utilizing a single resist for patterning and electroless nickel bump formation with a resist hardening step, whereby energy is applied to cause cross-linking prior to forming. This cross-linking is implemented to improve adhesion of the resist layer. Lack of resist adhesion during electroless plating is a common problem if the correct combinations of chemicals and conditions are not selected and can lead to the formation of inconsistent bumps. Energy is applied by incorporating a curing regime using a resist baking step combined with light irradiation to cause cross-linking in the resist layer (consisting of a resin and a photosensitive agent) and prevent degradation during the chemically aggressive electroless plating process. Prior to this, it was known to use baking and/or light irradiation non-simultaneously to improve resist adhesion. Another method is known as 'immersion solder bumping', which offers another low-cost alternative to electroplating, but is presently constrained by the limited volume of solder alloy applied during the process.
Presently available immersion solder bumping techniques, for application in IC flip chip assembly, typically employ an isotropically grown electroless nickel (Ni) bump UBM over the bond pad. Immersion soldering does not require lithographic masking or etching processes, or high capital expenditure, and hence is of low cost. The Ni bump structure may be additionally coated with a thin immersion gold (Au) surface layer to ensure good solderability. The wafer of Ni/Au bumped IC devices is then immersed into and withdrawn from a reservoir of molten solder. Glycerol or another medium that prevents oxidation may be provided as a floating layer or in another fashion to protect the solder. This renders the technology highly cost competitive against processes that employ alternative methods, such as solder paste reflow, solder plating or vapour deposition of solder. In addition, the immersion solder bumping process does not suffer from the bump pitch constraints of the stencil printing technologies that presently offer the lowest cost amongst the other available bumping processes.
In "Immersion soldering - a new way for ultra fine pitch bumping", (Nieland et al, Electronics goes green 2000+. A Challenge for the Next Millennium. Proceedings. Vol. 1: Technical lectures: September 11-13, 2000, Berlin, Germany), the development of a new immersion solder bumping method is discussed. Immersion solder bumping is described as being a low cost alternative to conventional processes in the case where only a thin solder layer is needed. Parameters such as multiple dipping, immersion depth, Ni bump height and dipping rate are mentioned as affecting solder deposition, which is always of a low volume. These very low resulting bump heights can lead to inconsistencies during bonding, and unfortunately limits the applicability of immersion soldering. It is noted that, due to the thin solder layer presented, limitation to such techniques as thermode bonding (pressing using a hot bar) is generally required to ensure proper bonding and overcome inconsistent bump heights, lack of flatness etc.
However, such present immersion soldering methods only provide a thin solder coating (typically less than 10 microns maximum thickness). This severely limits the range of applications for this technique and precludes its more widespread commercial adoption. The reason for the thin coating is believed to be governed by the low wetting angle of the solder onto the conventional convex, isotropically grown, Ni/Au bump as the wafer leaves the solder bath.
The use of pillar structures is advantageous over isotropically grown structures in interconnecting IC devices to substrates for various reasons including allowing greater stand off distances between devices and substrates to compensate for differences in thermal expansion and to allow fine connecting pitches to be achieved. The use of pillar structures is known in the prior-art:
US20050077624A describes a die comprising of a substrate and pillar structures of varying shapes, typically created by electroplating and solder reflow.
US6592019B, discloses a flip chip interconnect method whereby an elongated column of metal is formed within a hole formed by radiation in a photosensitive polymer (known as a mask) following which the mask is removed. The elongated metal column consists of a low melting temperature upper portion (typically solder) and higher melting temperature lower portion (typically copper) which are deposited in the hole before removal of the mask. The advantages of this method include a reduced use of lead solder, fine pitch and ease of underfill. However, this method has several disadvantages, namely that a separate mask is obviously required for patterning of the passivation layer prior to the mask for pillar deposition, and that the copper and solder layers which make up the pillar are deposited using electroplating, which also requires a seed layer. This makes for a relatively expensive process.
US20050026413A describes a method of forming a series of conductive pillars on a wafer having an active surface. Conductive material is generally electroplated onto a metallic layer formed on the active surface through an opening in a mask layer to create a pillar, which is then followed by a further operation to create a solder cap on top of the cylinder. The mask layer and metallic layer are then removed to leave a cylindrical bonding structure. A reflow operation can be performed to adjust the shape of the solder cap. Although this method is successful in creating pillar structures, with the advantages stated above, this is via a relatively expensive process - a separate masking step is required for patterning of the passivation, and two electroplating operations are typically carried out, or an electroplating and printing step.
US20030107132A describes a method for creating an anisotropic, pillar shaped metal bump structure by using the mask to constrain growth of an electroless bump and/or a Au cap (used to prevent oxidation and preserve solder wettability). However, several masking procedures are used during the different processing steps (again, for patterning of the passivation layer prior to a further mask for forming the bump structures), which lead to a significant increase in cost.
Objective of invention
To provide a low cost, simplified process that achieves pillar shaped bumps, particular for use within the field of microelectronics.
Summary of the Invention According to the invention, a method of applying a bump to a conductive pad on a substrate having a passivation layer over the conductive pad comprises: a) providing a masking layer over the passivation layer; b) patterning and developing the masking layer to define a cavity extending through the masking layer in alignment with the conductive pad; c) removing part of the passivation layer exposed in the cavity so as to expose the conductive pad; d) forming a bump in the cavity contacting the conductive pad; and, e) removing the masking layer; the method further comprising applying a layer of solder to the bump by immersing the substrate in a solder bath. The invention relates to an improved method of producing a bump, particularly for use in a flip chip bonding process that utilises the control of the shape of a bump during its growth, and the structures created using this method. The substrate is typically a semiconductor wafer but could be a MEMS device, ceramic or polymer carrier, or even a metallic item. The ceramic or polymer carrier could be part of a microprocessor component or multidevice module. Although the invention can be used for a variety of bumping processes, the preferred bumping methods are electroless processes, in particular an electroless Ni process. While this technology is described as being 'electroless Ni1, it should be understood that other elements may be present in the formed bumps, such as quantities of phosphorus or other elements. Alternatives to electroless plating of the bump include deposition of solder pastes by printing, jetting etc.
The bump geometries and immersion soldering procedure of the invention provide a truly low cost, simplified process for forming bumped and solder-deposited structures for use in microassembly, particularly in the field of microelectronics and semiconductors, more particularly for use during flip-chip bonding. At no point has the prior art recognised that the volume of solder deposited during immersion solder bumping can be increased by providing a marked discontinuity in slope between the sidewall and upper face of a bump.
Aspects of the invention will be further described in relation to the bonding of flip chips, in particular using electroless Ni bump-growth technology, although it is envisaged that other bump growth methods, including those processes utilising electroless Ag, Cu, Sn, chemistries may be used. The conductive pad is typically made of metal although non-metallic pads could also be used. Similarly the bump could be metallic or non-metallic but always electrically conductive.
The invention makes use of a single, relatively thick, mask during integrated circuit back-end processing for both patterning of the integrated circuit passivation layer (a subtractive process) and for constraining the lateral growth of an electroless Ni bump grown on the resulting exposed chip metallisation layer (an additive process). The inventive structure formed by this method is often physically discernable from the prior art in that the internal diameter of the passivation (or equivalent dimension for non-cylindrical openings) is substantially equal to the external diameter (or equivalent) of the formed bump, prior to subsequent processing or addition of a protective layer. It can also often be noted that the bump sidewall is substantially continuous over the height of the bump, exhibiting no sharp changes or discontinuities in curvature.
For typical devices, it is common practice to employ a photosensitive polymer layer on the integrated circuit as an in-situ mask for the patterning and removal of the passivation layer from the area of the bond pad. This can typically be of a positive or negative working nature. The invention involves the further use of in-situ polymeric masking as a confinement structure for the growth of the electroless Ni bump, in order to define a columnar structure. The in-situ mask layer may then be partially or totally removed to expose the corners of the bump. This aspect of the invention makes use of the single photoresist layer to fulfil two processing functions, which also results in no additional process costs. This is in contrast to plating based solder bumping technologies where additional masking layers and patterning steps are required.
The invention makes a combined or dual use of the thick photoresist mask for the dry etching of the passivation layer and the restraining of the growth of the electroless Ni bump. In the nearest prior-art, US20030107132A, a separate (undisclosed) process has been used to etch the passivation layer, as can be seen from numerous figures. The extra masking steps required for this process lead to a particular disadvantage, especially with regard to cost of the process. In relation to this, as mentioned, the present invention overcomes this disadvantage by using the same photoresist mask for both removal of the passivation layer and formation of the advantageous pillar structures. That is, for a subtractive operation and additive operation. Whereas, in US20030107132A and various other prior-art processes, the subtractive processes (e.g. etching of passivation) use separate masking steps from the additive processes (e.g. deposition of seed layer/UBM/bump metals), whereas the invention uses one masking step to account for both subtractive and additive processes.
One embodiment of the invention includes finishing of the electroless Ni bump with an immersion Au layer to preserve solderability and prevent Ni oxidation. This layer may be added over the upper Ni surface while the resist mask is still present and/or to the Ni upper surface and the Ni sides after the resist has been removed. Alternative materials exist that can be used to replace Au as the preservation layer, including silver, palladium, tin and organic materials.
Another embodiment of the invention includes leaving the mask layer in place after processing to provide a supporting collar for the bump that would enhance the thermal cycling fatigue life of the final flip chip solder joint and mechanical shock resistance of the assembly in the case of an IC chip. A benefit of the confined growth of the Ni bump in the inventive process relates to the lack of lateral growth of the bump during the process. Bumps formed according to the invention possess a lower surface area, and an upper surface area substantially equal to the area of the integrated circuit metallisation onto which the bump is grown. This allows the bumping structures to be defined at smaller pitches than conventional bumps or, for a given pitch or Ni bump base diameter, provide an increase in chip metallisation contact area and solder bond area. This in turn will reduce electrical resistance, reduce bond current density, improve electromigration reliability, improve thermal transfer and improve solder joint thermal cycling fatigue life. Also, following for example an immersion soldering process, enough solder can be provided for formation of a reliable interconnection with the substrate without the use of further material during the assembly process. Apart from immersion soldering, other solder deposition processes well known in the art can also be used.
A wide variety of different bump geometries can be formed by the process. For the side profile, these can include geometries with substantially vertical sides, undercut, angled or partially concave sides.
The particular bump geometry formed by the invention is of particular benefit when used for immersion solder bumping. No similar bump profile for use during immersion solder bumping has been previously described in the prior-art. An electroless Ni bump formed using the inventive processes typically possesses a marked (often greater or equal to 90 degrees) discontinuity in slope between the sidewall and the upper face that influences the solder separation process in immersion soldering to increase the solder volume retained on the Ni bump. On immersion soldering, the solder is restrained by the edges of the bump, thus giving an anisotropic profile with enhanced quantities of solder. The extra volume of solder retained by the bump is suitable to bond the chip without the need for further bonding material. Other soldering methods are expected to benefit in a similar manner. Substrates processed according to the invention can then be utilised in existing IC wafer and flip chip processing technologies. Using a method according to the invention, bumps can be made with a wide range of possible pitches, although these are preferably with a pitch of between 30-180 microns.. A typical product formed by the above described processes is an improved flip chip solder bonded assembly. This can be produced by dicing immersion bumped devices from integrated circuit wafers treated as described above, and flip chip bonding them to a substrate with an array of matching solder wettable pads. The total process, from provision of a typical oxide-isolated silicon wafer, with metallisation and passivation, provides a low cost solder bumping technology for IC wafers compatible with both conventional tin/lead solder alloys and the recently introduced lead-free solder alloys.
Although the techniques described above have been illustrated using the example of IC connection, bumps created using these inventive methods may also be used in other applications, including bonding of SAW devices, passive filters, detector arrays, MEMs and in non-microelectronic fields. In one particular example, the bumps could be formed away from any active pathways or coated with a non-conductive layer to act as spacers for defining distances between substrate surfaces. This could be for spacing of microelectronic devices, including heatsinks and chips or even non-microelectronic devices.
Some examples of methods according to the invention will now be described and contrasted with known methods with reference to the accompanying drawings, in which:- Figure 1 shows a bumping structure formed during a conventional immersion solder bumping process;
Figure 2 shows a bumping structure formed by an embodiment of a method according to the invention; Figures 3 to 10 show some typical process sequences according to the invention;
Figures 11 to 13 show the steps that occur during an immersion bumping withdrawal process, using a structure formed according to the invention; Figures 14 and 15 show bumping structures made according to a conventional process and according to an embodiment of the invention respectively;
Figure 16 shows several possible bump profiles;
Figure 17 shows the positions of the passivation and bump boundaries formed on a prior-art bumping structure; and,
Figure 18 shows the positions of the passivation and bump boundaries formed on a bumping structure according to the invention.
All of the drawings are for illustrative purposes only and are not to scale.
A typical process sequence according to the invention, when applied to the bonding of flip chips, shall now be described.
In summary, a silicon IC device or wafer is provided with a thin (1-3 microns) aluminium alloy metallisation layer and silicon nitride passivation layer. A photosensitive polymer resist mask layer (for example a polyimide or polybenzoxylene, 10-25 micons thick, more typically between 15-20 microns thick) is deposited onto the IC device, which is subsequently developed in selected areas by radiation exposure. This is followed by a dry etching step to remove the passivation in the areas exposed by the mask, forming tall-sided cavities, at the bottom of which lie the exposed regions of metallisation (bond pads). An electroless Ni bump growth process is then used to deposit a typically columnar, anisotropic Ni bump. The bump structure can be protectively coated in Au, prior to mask stripping, or subject to deposition of a Au coating after a mask layer stripping step. The structure can then be immersed in a reservoir of molten solder, which results in the deposition of a solder cap, ready for further processing and incorporation into microelectronic assemblies. All of the above processing operations utilise existing materials and technology well known in the art. Alternative materials and processing technologies know to the skilled practitioner can be substituted for those described above where appropriate. A conventional immersion solder bumping structure is shown in Figure 1 and comprises a silicon IC device 1 on which has been provided a metallisation 2, a silicon nitride passivation layer 3, a Ni bump 4 and a solder cap 5. The solder cap exhibits a relatively low contact angle 6a (typically less than 20°), which is typical of the solder deposition onto conventional, convex, isotropically grown, Ni/Au bumps as the wafer leaves the solder bath. The illustrated solder cap is typical of those provided on conventionally shaped bumps, and is relatively thin (typically less than 10 microns).
Figure 2 illustrates an immersion solder bumping structure according to an embodiment of the invention which comprises a silicon IC device 1 on which has been provided a metallisation 2, a silicon nitride passivation layer 3, a Ni bump 8 and a solder cap 9. The solder cap exhibits a relatively high contact angle 6b (typically above 45°), which is noticeable when depositing solder onto a bump grown according to the invention, as the wafer leaves the solder bath. Reference 10 indicates the region at which a supporting polymer mask structure is provided to allow non-isotropic growth of the bump.
Figures 3-10 illustrate a typical process sequence according to the invention. Figure 3 shows a silicon IC device or wafer which has been provided with a thin (1-3 microns) aluminium alloy metallisation layer 2 and silicon nitride passivation layer (0.5-2 microns) 3. Figure 4 shows the IC device following deposition of a positive working photosensitive polymer resist mask layer (10-25 microns thick) 11 , which is developed in selected areas defined by the patterning 12 and radiation exposure 13 in Figure 5. The patterning is a photomask defining areas exposed to radiation (typically UV). This defines a cavity 7, shown in Figure 6. Figure 7 illustrates the removal of the passivation 3 by dry etching in pre-defined areas exposed by the mask 11. This exposes the metallisation layer at the bottom of the cavity, on which a bump is grown 8 (typically by electroless Ni process) as shown in Figure 8. The bump shown in Figure 8, which may be cylindrical, is defined by the shape of the cavity into which it is deposited and is typically of a columnar, anisotropic shape. Figure 11 shows deposition of a Au coating 14, after which the mask layer can be optionally stripped. Alternatively, as shown in Figure 10, the bump structure can be subject to deposition of a Au coating after a mask layer stripping step immediately proceeding Figure 8, as illustrated in Figure 9.
Although this example uses a positive working photosensitive polymer resist mask layer, the use of a negative mask (with appropriate changes in processing steps) is equally feasible.
Figure 12-13 illustrate the stages in an immersion bumping withdrawal process. Figure 12 shows the near point of instability and solder meniscus separation as the silicon IC 1 (passivation 3, bond pad 2 and bump 8 are shown) is removed from the solder bath. During this process, the protective Au coating is rapidly dissolved in the solder. Figure 13 shows the remaining quantity of solder left on the bump after complete withdrawal and solder separation. In practice the process that defines the volume and shape of the solder that remains on the electroless Ni bump after the immersion process is complex, but can be illustrated simply, as shown by these figures. The Ni bump is initially wetted by the molten solder and as the bumped wafer is withdrawn the solder meniscus necks down until a point of instability is reached and the solder on the Ni bump and that in the solder bath separate. This solder volume then redistributes itself across the electroless Ni bump surfaces to minimise the overall surface energy. Although these figures indicate that the substrate remains parallel to the solder bath during withdrawal, the substrate can also be withdrawn with its plane perpendicular to the solder bath or even at an angle, with the bumped face either upwards or downwards.
Figures 14 and 15 illustrate another advantage of the invention, and show the difference between a prior-art method and the invention. Figure 14 shows a silicon IC 1 with metallisation 2, known bump geometry 4 and typical volume of solder 5. Figure 15 shows a silicon IC 1 with metallisation 2, bump geometry 8 and solder volume deposited due to the bump shape provided by the invention. The increase in chip metallisation contact area and solder bond area at a given bump base diameter (or pitch) resulting from the use of the inventive process is clearly evident. The solder separation volume depends upon the Ni bump shape and the withdrawal angle with respect to the bump geometry and to gravity. It can be seen from these figures that, for a given bump base diameter, a greater chip metallisation contact area is achieved from the bump according to the invention due to the coincidental nature of the passivation and bump boundaries. A greater flat top surface is also achieved, giving greater solder separation volume and bump height for the same base diameter. Perpendicular withdrawal of conventional bumps and bumps formed according to the invention at equal top flat surface (approximately equal to passivation opening) diameters would theoretically provide very similar solder separation volumes. This solder volume would then redistribute itself across the Ni bump surfaces to provide an increased solder bump height for the Ni bump profile formed according to the invention, due to the restraining effect of the edged structure, whereas for a conventional Ni bump structure, solder would not be as well restrained and would therefore form a solder bump of lesser height.
Figure 16 shows several bump profiles formed according to embodiments of the invention using correspondingly shaped cavities 7, vertical 15, undercut 16, concave 17, although other variations are possible. The structures formed with these edge profiles can be symmetrical (cylindrical, rectangular, other polygonal), or otherwise.
Figure 17 illustrates the non-coincidental nature of the passivation 18 and bump boundaries 19 on a prior art columnar bumping structure, such as those formed by processes described in US20030107132A, consisting of bump 22, protective coating 14, passivation 3, bond pad 2 and substrate 1. This is due to the different masking steps used during patterning and formation of the bump. A similar non-coincidental bump/passivation boundary would be seen if the bumping structure was isotropically grown, rather than formed as a column.
Figure 18 illustrates the coincidental nature of the passivation 20 and bump boundaries 21 on a bump structure according to the invention, consisting of bump 8, protective coating 14, passivation 3, bond pad 2 and substrate 1. The internal diameter of the passivation is substantially equal to the external diameter of the formed bump and exhibits no sharp changes or discontinuities in curvature. This is due to the common masking step used during patterning and formation of the bump. Although in this figure the boundaries shown are vertical, some degree of angling or curvature may be present along either the bump boundary (as shown in Figure 16), passivation boundary or both. This may be due to design requirements, material types (positive or negative resists) or chemical and physical effects, but the boundaries will always be substantially coincidental.

Claims

1. A method of applying a bump to a conductive pad on a substrate having a passivation layer over the conductive pad, the method comprising: a) providing a masking layer over the passivation layer; b) patterning and developing the masking layer to define a cavity extending through the masking layer in alignment with the conductive pad; c) removing part of the passivation layer exposed in the cavity so as to expose the conductive pad; d) forming a bump in the cavity contacting the conductive pad; and, e) removing the masking layer; the method further comprising applying a layer of solder to the bump by immersing the substrate in a solder bath.
2. A method according to claim 1 , wherein the masking layer is removed before solder is applied.
3. A method according to claim 1 or claim 2, further comprising applying a protective metal coating on the bump formed in step d) prior to applying solder.
4. A method according to claim 3, wherein the protective metal coating comprises Au1 Pd, Ag, Sn or an organic layer.
5. A method according to any of the preceding claims, wherein the bump is electrically conductive.
6. A method according to claim 5, wherein the electrically conductive bump formed in step d) comprises nickel or copper or alloys thereof.
7. A method according to any of the preceding claims, wherein the conductive pad is made of metal.
8. A method according to any of the preceding claims, wherein the bump is formed by electroless plating.
9. A method according to any of the preceding claims, wherein the masking layer comprises one of a photoresist, polymethylmethacrylate, epoxy, polyimide, polybenzoxylene, phenolic resin, and polybenzocyclobutene.
10. A method according to any of the preceding claims, wherein the masking layer has a thickness of at least 10 microns, preferably in the range 10-25 microns, most preferably 10-20 microns.
11. A method according to any of the preceding claims, wherein the cavity is cylindrical.
12. A method according to any of claims 1 to 10, wherein the cavity wall is undercut or concave.
13. A method according to any of the preceding claims, wherein step c) comprises dry etching.
14. A method according to any of the preceding claims, wherein the substrate comprises an integrated circuit.
15. A semiconductor wafer having a conductive pad over which is provided a passivation layer and including a bump which has been manufactured according to any of the preceding claims.
PCT/GB2009/000972 2008-04-24 2009-04-15 Method of applying a bump to a substrate WO2009130442A1 (en)

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GBGB0807485.8A GB0807485D0 (en) 2008-04-24 2008-04-24 Method of applying a bump to a substrate

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US9627304B2 (en) 2013-10-17 2017-04-18 Osram Opto Semiconductors Gmbh Method of producing a large number of support apparatus which can be surface-mounted, arrangement of a large number of support apparatus which can be surface-mounted, and support apparatus which can be surface-mounted
TWI665743B (en) * 2013-03-15 2019-07-11 台灣積體電路製造股份有限公司 Bump joint and method of forming the same
US11304313B2 (en) 2017-12-15 2022-04-12 Hewlett-Packard Development Company, L.P. Three-dimensional printing

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EP0675532A2 (en) * 1994-03-31 1995-10-04 Du Pont Kabushiki Kaisha Method for forming solder bump in IC mounting board
US20010040290A1 (en) * 2000-05-01 2001-11-15 Seiko Epson Corporation Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device
US20030219926A1 (en) * 2002-02-18 2003-11-27 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, and electronic instrument
US20080073783A1 (en) * 2000-09-04 2008-03-27 Fumiaki Matsushima Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument

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Publication number Priority date Publication date Assignee Title
EP0675532A2 (en) * 1994-03-31 1995-10-04 Du Pont Kabushiki Kaisha Method for forming solder bump in IC mounting board
US20010040290A1 (en) * 2000-05-01 2001-11-15 Seiko Epson Corporation Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device
US20080073783A1 (en) * 2000-09-04 2008-03-27 Fumiaki Matsushima Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument
US20030219926A1 (en) * 2002-02-18 2003-11-27 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, and electronic instrument

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI665743B (en) * 2013-03-15 2019-07-11 台灣積體電路製造股份有限公司 Bump joint and method of forming the same
US9627304B2 (en) 2013-10-17 2017-04-18 Osram Opto Semiconductors Gmbh Method of producing a large number of support apparatus which can be surface-mounted, arrangement of a large number of support apparatus which can be surface-mounted, and support apparatus which can be surface-mounted
US11304313B2 (en) 2017-12-15 2022-04-12 Hewlett-Packard Development Company, L.P. Three-dimensional printing

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