201001578 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種施加電性導電凸塊於基板的方 法。 【先前技術】 直到西70 2000年，使用倒裝晶片接合法（flip chip bonding)大約佔據所有⑦裝置組裝之，而打線接合法 (wire bonding)佔據其餘的。然而，在過去的7年期 間’叉到對於較高晶片輸人/輸出（I/O)數目、較高操作頻 率與„腳較低組裝成本之需求的驅使，倒裝晶片組裝已 有非常转貝著的成長。現今，倒震晶片接合法佔據所有石夕裝 置的5% ’亚且在往後的5年期間，這種趨勢預期會持續不 斷的成長。因此，對於發展在晶圓上製造‘凸塊，之極低 成本的方法（凸塊技術（bump丨叩土echn〇 1 〇gy))會有強烈的 關注’用以支持此成長速率並符合工業準則中所提出的接 I 觸墊間距（Pad pitch)以及每接腳之成本的目標。於本專利 兒月書中’凸塊意涵為一種非金屬性（non-metal 1 ic) 或較佳為金屬性之電性導電I/O結構。 對於倒裝晶片互連（interconnection)存在有許多種 不同的技術。 黏著（adhesive)倒裝晶片接合法利用導電性或非導 電性黏合劑，以將凸塊積體電路（IC)晶片接合於裝置。某 些裝置無法接受黏合劑，以及當無法配置黏合劑時可能會 %生問題。硬化時間（cur i ng t i me)也會限制生產量。 3 94664 201001578 熱壓縮（thermocompression)或熱超音波接合 (thermosonic bonding)技術利用熱與壓力或熱、壓力與振 盪之結合以於金屬球與接合墊（bond pad)之間產生固態狀 態接合（solid state bond)。這些技術包括配置連續的， 個接者一個的凸塊（seria 1 bump-by-bump)，所以相對地比 較慢，而且經由模具調整不良（die misalignment)而對於 配置的錯誤較為敏感。 於西元1 960與1970年間，銲料凸塊（s〇ider bumping) 已發展並用於不同的應用，且大部分廣泛地應用於倒裝晶 片接合技術。這些技術通常需利用濺鍍（sputtering)、壓 板（plating)或相似方法，在接合墊上方置放凸塊底層金屬 (under-bump metallistaion，以下簡稱 UBM)。UBM 矸提供 歐姆接觸至晶片導電墊（大部分為鋁（alumini_))並且典 型地由數個金屬層製成。可使用保護層或"鈍化” (passivation)層典型地覆蓋晶片（或其他基板）表面。這可 為有機（organic)或無機（inorganic)層，如氧化石夕 (silicon nitride)或聚醯亞胺（p〇iyamide)。ubm 允許塾 與凸塊之間適當的鮮料潤渥（s〇 1 der wett i ng)與接觸（電 性、熱與機械）。UBM也可預防接合墊材料的腐蝕 (corrosion)與墊與銲料凸塊之間的反應/擴散。u跗必須 小心選擇，以考慮凸塊材料與類型、操作條件與製程要求。 不同的UBM沉積技術通常是結合特定的凸塊形成方法。銲 料凸塊形成方法包括蒸鍍（evap〇rati〇n)、電錢 (electroplating),印刷（printing)與浸潰_接 94664 4 201001578 (immersion soldering) ° 療鑛製程通常受限於南錯鲜料（high lead solder)·， 故無法輕易地應用於較大的晶圓，且有生產量與高資金設 備成本的限制。 電鍍製程受到廣泛使用’雖然其花費少於蒸鍍製程， 但是需要一些遮罩（masking)與光圖案化 (photopatterning)步驟，故無法確實地降低成本。 為產生銲料凸塊而存在一些低成本技術。 f \ ' 銲料膏（s〇lder paste)或導電黏合劑之模板（stencil) 印刷為一種低成本技術，上述技術已吸引較大的興趣，以 應用於倒裝晶片互連技術。除了有效降低成本之外，由於 這種技術係利用無鉛合金（lead free alloy)膏/黏合劑而 可解決環境問題。然而’基於可利用的材料與模板幾何之 限制，目前這種製程係針對量多（high volume)而限制在低 至150至200微米的間距。 ί美國專利號US-B-6900117揭露一種製造非等向性 (anisotropic)凸塊的方法’其利用用於圖案化的單一光阻 劑（res i st)以及具有光阻劑硬化（hardening)步驟之無電 鑛鎳凸塊形成（electroless nickel bump formation)，因 此’施加能ϊ以引起父連（cross-linking)於形成之前。實 施這種交連可改善光阻層的黏著。若無法選擇正確結合的 化學物與條件，則通常在無電鍍期間會發生缺乏光阻劑黏 著的問題，而可能導致不一致的凸塊的形成。能量係藉由 使用光阻劑焙燒（baking)步驟結合光照射（1丨ght 5 94664 201001578 irradiation)以及併入硬化方案（curing regime)而施加 的，以於光阻層（包括樹脂（resin)與光敏劑 (photosensitive agent))引起交連與於化學侵蝕性 (aggressive)無電鍍製程期間預防退化（degradation)。在 這之前’已知可非同時地使用焙燒與/或光照射以改善光阻 劑黏附性。 另一種已知的方法為〃浸潰銲料凸塊（i mmers i on solder bumping)"，其提供另一種低成本電鑛法的選擇， 但這種方法目前由於在製程期間所施加的銲料合金的量有 限而受到限制。 就1C倒裝晶片組裝之應用而言，目前可用之浸潰銲 料凸塊技術典型地利用等向性地（i sotrop i ca 11 y)成長之 無電鍍鎳（Ni)凸塊UBM於接合墊上方。浸潰銲料不需微影 遮罩（1 ithographic masking)、钱刻製程或高資金消耗 (expenditure)’故成本較低。錄凸塊結構可額外塗上薄的 浸潰金（Au)表面層，以確保良好的可銲性。接著，可將鎳/ 金凸塊1C裝置之晶圓浸入溶化的銲料之儲存槽中以及從 該儲存槽收回。甘油（glycerol)或其他預防氧化之媒介可 提供作為浮動層（f 1 oat ing 1 ayer)或以任何其他方式保護 銲料。實行此技術相比於利用其他技術製程的花費較高， 例如銲料膏的回流（reflow)，銲料電鑛或銲料的蒸氣沉 潰。此外，浸潰銲料凸塊製程不需遭受模板印刷技術之凸 塊間距約束，上述技術可提供最低的成本於其他可利用的 凸塊製程中。 6 94664 201001578 於”浸潰銲接-一種用於超精細間距凸塊之新方法 (Immersion soldering-a new way for ultra fine pitch bumping) (Nieland et al, Electronics goes green 2000+. A Challenge for the Next Millennium. Proceedings. Vol. 1 ·· Technical Lectures: September 11-13, 2000, Berlin, Germany)中’討論到新浸潰銲料凸塊方法之發展。浸漬銲 料凸塊係被描述為在僅需一個薄的銲料層之情況下的習知 製程中的低成本的選擇。所提及的參數，例如多重浸潰 (multiple dipping)、浸潰深度、鎳凸塊的高度以及浸潰 速率等將影響銲料沉潰，上述銲料沉積通常為少量。這些 少i所產生的凸塊咼度於銲接期間將導致不一致性 需要確保適當的鲜接 (flatness)之缺乏等 (inconsistencies)，而不幸地限制浸潰銲接的可應用性。 需注意的是’基於所提出的薄的銲料層，要將這種技術限 制為熱模接合（thennode b〇nding)(使用熱條加壓），通常 克服不一致的凸塊高度與平度 而’目前㈣輯銲接方法僅提㈣的銲料塗層201001578 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of applying an electrically conductive bump to a substrate. [Prior Art] Until West 70, 2000, the use of flip chip bonding occupies approximately all of the 7 device assembly, and wire bonding occupies the rest. However, during the past seven years, flip-chip assembly has been very popular, driven by the need for higher wafer input/output (I/O) numbers, higher operating frequencies, and lower assembly cost. Nowadays, the shock-bonding wafer bonding method accounts for 5% of all Shixi devices. In the next five years, this trend is expected to continue to grow. Therefore, for the development of wafer manufacturing 'Bumps, the extremely low-cost method (bump technology (bump ech ech ech ech ech ) gy)) will have a strong focus 'to support this growth rate and meet the industry standard proposed in the I touch pad The pitch of the pad and the cost per pin. In the patent of the patent, the bump is meant to be a non-metal 1 ic or preferably a metallic electrical conduction I/. O Structures There are many different techniques for flip chip interconnects. Adhesive flip chip bonding uses conductive or non-conductive adhesives to bond bump integrated circuit (IC) wafers. Engaged in the device. Some devices are unacceptable Mixtures, and when adhesives are not available, may cause problems. Curing time (cur i ng ti me) also limits production. 3 94664 201001578 Thermocompression or thermosonic bonding technology utilizes heat Combined with pressure or heat, pressure and oscillation to create a solid state bond between the metal ball and the bond pad. These techniques include the configuration of a continuous, one-piece bump (seria 1) Bump-by-bump), so relatively slow, and sensitive to configuration errors via die misalignment. Between 1960 and 1970, solder bumps have been developed and used. For different applications, and most of them are widely used in flip chip bonding technology. These techniques usually require sputtering, plating, or similar methods to place bump underlying metal over the bond pad (under- Bump metallistaion (hereinafter referred to as UBM). UBM 矸 provides ohmic contact to the wafer conductive pad (mostly aluminum (alumini)) and is typically composed of Use is made of a metal layer may be a protective layer or ". Passivation "(passivation) layer is typically covered with a wafer (or other substrate) surface. This can be an organic or inorganic layer such as silicon nitride or p〇iyamide. The ubm allows for proper mashing and contact (electricity, heat and mechanical) between the 塾 and the bump. The UBM also prevents corrosion/diffusion between the corrosion of the bond pad material and the pad and solder bumps. u跗 must be carefully selected to take into account bump material and type, operating conditions and process requirements. Different UBM deposition techniques are often combined with specific bump formation methods. Solder bump forming methods include evaporation (evap〇rati〇n), electroplating, printing, and immersion_94664 4 201001578 (immersion soldering) ° The remedy process is usually limited by the South Refractory (high lead solder)·, so it cannot be easily applied to larger wafers, and there are restrictions on production volume and high capital equipment cost. The electroplating process is widely used. Although it is less expensive than the evaporation process, some masking and photopatterning steps are required, so that the cost cannot be reliably reduced. There are some low cost techniques for producing solder bumps. f \ 'ssert paste or stencil of conductive adhesives is a low-cost technology that has attracted greater interest in flip-chip interconnect technology. In addition to effectively reducing costs, this technology solves environmental problems by utilizing lead free alloy pastes/adhesives. However, based on the limitations of available materials and template geometries, this process is currently limited to pitches as low as 150 to 200 microns for high volumes. U.S. Patent No. US-B-6900117 discloses a method of making anisotropic bumps which utilizes a single photoresist for patterning and a hardening step with a photoresist. The electroless nickel bump formation, so 'apply energy ϊ to cause cross-linking before formation. Performing such cross-linking improves the adhesion of the photoresist layer. If the correct combination of chemicals and conditions cannot be selected, there is usually a problem of lack of photoresist adhesion during electroless plating, which may result in inconsistent bump formation. The energy is applied by using a photoresist baking step in combination with light irradiation (1丨ght 5 94664 201001578 irradiation) and incorporating a curing regime for the photoresist layer (including resin and resin). Photosensitive agents cause cross-linking and prevent degradation during the chemically non-electroplating process. Prior to this, it was known that roasting and/or light irradiation may be used non-simultaneously to improve photoresist adhesion. Another known method is i mmers i on solder bumping", which provides another option for low cost electrominening, but this method is currently due to the solder alloy applied during the process. The amount is limited and limited. For 1C flip chip assembly applications, the currently available impregnated solder bump technology typically utilizes an isotropically grown (i sotrop i ca 11 y) grown electroless nickel (Ni) bump UBM over the bond pad. . Immersion solder does not require lithographic masking, money engraving, or high expenditure (expenditure), so the cost is lower. The bump structure can be additionally coated with a thin layer of impregnated gold (Au) to ensure good solderability. Next, the wafer of the nickel/gold bump 1C device can be immersed in and retracted from the storage bath of the molten solder. Glycerol or other oxidative prevention media can be provided as a floating layer (f 1 oat ing 1 ayer) or in any other way to protect the solder. The implementation of this technique is more expensive than the process using other techniques, such as reflow of solder paste, vapor deposition of solder ore or solder. In addition, the impregnation solder bump process does not require the bump spacing constraints of stencil printing techniques, and the above techniques provide the lowest cost in other available bump processes. 6 94664 201001578 "Immersion soldering-a new way for ultra fine pitch bumping" (Nieland et al, Electronics goes green 2000+. A Challenge for the Next Millennium Proceedings. Vol. 1 · Technical Lectures: September 11-13, 2000, Berlin, Germany) discusses the development of new impregnated solder bump methods. Impregnated solder bumps are described as requiring only a thin Low cost choice in conventional processes in the case of solder layers. The parameters mentioned, such as multiple dipping, dipping depth, height of nickel bumps, and impregnation rate, will affect solder collapse. The above-mentioned solder deposits are usually small. These bumps produced by the minor i will cause inconsistencies during soldering. It is necessary to ensure proper flatness (inconsistencies), and unfortunately limit the properties of the dipping solder. Applicability. It should be noted that 'based on the proposed thin solder layer, this technique is limited to the use of hot junction (thennode b〇nding) (usually using hot strips), usually Overcome the inconsistent bump height and flatness. The current (four) series of soldering methods only mention (4) the solder coating
鎳/金凸塊上。 應用這種技術將嚴重 商業採用。使用薄塗 )dler bath) 、等向性成長之Nickel/gold bumps. Applying this technology will be a serious commercial adoption. Use thin coating) drer bath), isotropic growth
性成長結構有多種原因， :奴日守’使用柱狀結構優於等向 包括其允許於裝置與基板間的5 94664 7 201001578 離更遠以補償熱膨脹（thermal expansion)的差異，以及允 許實現精細的連接間距。先前技術中已知有使用柱狀結構 的有： 美國專利公開號US20050077624A描述一種模具，由 基板與各種形狀的柱狀結構所構成，典型藉由電鍍以及銲 料回流而產生。 美國專利號US6592019B揭露一種倒裝晶片互連方 法’藉此讓瘦長的金屬圓柱形成在洞内，該洞係藉由光敏 聚合物（已知為遮罩）之輻射而形成，接著移除遮罩。瘦長 金屬圓柱包括低熔解溫度之上部份（典型為銲料）與高熔解 溫度之下部分（典型為銅），兩者在移除遮罩之前先沉積於 洞内。這種方法的優點包括減少鉛銲料的使用、精細的間 距以及簡單的底層填充（underf i 11)。然而，這種方法有一 二缺亦即在將遮罩用於柱狀沉積之前，明顯地需要另 外的遮罩用於圖案化鈍化層，而且構成柱狀的銅與銲料層 係利用電鍍沉積，而上述電鍍也需要種子層（seed layer)。這會使得製程變得相當昂貴。 吳國專利公開號US20050026413A描述一種於晶圓上 形成一連串導電柱狀之方法，上述晶圓具有作用表面There are several reasons for the sexual growth structure: the slaves' use of the columnar structure is superior to the isotropic direction, which allows it to be further away from the device and the substrate to compensate for the difference in thermal expansion, and allows for fine Connection spacing. It is known in the prior art to use a columnar structure: U.S. Patent Publication No. US20050077624A describes a mold comprising a substrate and columnar structures of various shapes, typically produced by electroplating and solder reflow. U.S. Patent No. 6,592,019 B discloses a flip chip interconnect method 'by thereby forming an elongated metal cylinder formed in a hole formed by radiation of a photopolymer (known as a mask), followed by removal of the mask . The elongated metal cylinder includes a portion above the low melting temperature (typically solder) and a portion below the high melting temperature (typically copper), which are deposited in the hole before the mask is removed. Advantages of this approach include reduced lead solder usage, fine spacing, and simple underfill (underf i 11). However, there is a deficiency in this method, that is, before the mask is used for columnar deposition, an additional mask is obviously required for patterning the passivation layer, and the pillar-shaped copper and solder layers are deposited by electroplating. The above plating also requires a seed layer. This can make the process quite expensive. U.S. Patent Publication No. US20050026413A describes a method of forming a series of conductive columns on a wafer having an active surface.
Uet1Ve SUFface)。通常導電材料係透過於遮罩層之開口 而電錢於开>成在作用表面之金屬層，以產生柱狀，上述柱 狀，者更操作以在圓柱的頂端產生銲料蓋（solder cap)。 接著：移除遮罩層與金屬層，以保留圓#接合 口*‘作以调整銲料蓋的外形。雖然這種方法可成功的產 94664 8 201001578 生柱狀結構且具有上述之優點，這種透過相當昴貴的製程-需要另外的遮罩步驟，用以圖案化鈍化層以及典型地實現 二個電鍍操作或一個電鍍與印刷步驟。 美國專利公開號US20030107132A描述一種利用遮罩 以抑止電鍍凸塊與/或金蓋（Au cap)(用以預防氧化與保持 銲料溼潤性）的成長，以產生非等向性、柱狀外形金屬凸塊 結構之方法。然而，使用一些遮罩程序於不同製程步驟期 間（再一次，在用於形成凸塊結構之另外的遮罩之前先圖案 化鈍化層），將導致成本的增加。 【發明内容】 本發明提供一種低成本與可達成柱形凸塊之簡易製 程，尤其是可應用於微電子的領域。 根據本發明，一種於基板上施加凸塊至導電墊之方 法，上述基板具有鈍化層在該導電墊上方，上述方法可包 括： a) 在該鈍化層上方設置遮罩層； b) 圖案化並顯影該遮罩層以定義空腔，該空腔延伸通 過該遮罩層而與該導電墊對齊； c) 移除曝露於該空腔之該鈍化層的部分，以曝露該導 電墊； d) 在該空腔中形成凸塊以接觸該導電墊；以及 e) 移除該遮罩層； 該方法復包括藉由將基板浸入溶融銲料槽而施加一 鲜料層至凸塊。 94664 201001578 本發明係關於一種產生凸塊之改善方法以及用此方 法所產生之結構，上述方法尤其是可用於倒裝晶片接合法 製程，該製程可於凸塊成長期間控制凸塊形狀。基板典型 係為半導體晶圓，但亦可為微機電系統（mi croe 1 ectr i c machani c system，以下簡稱 MEMS)裝置、陶莞（ceramic) 或聚合物載體（polymer carrier)，或甚至金屬品 (meta 11 i c i tem)。陶竞或聚合物載體可為微處理器組件或 多裝置（mu 11; i dev i ce)模組之一部分。雖然本發明可應用於 不同的凸塊製程，但較佳的凸塊方法為無電鍍製程，尤其 是無電鍍鎳製程。雖然這種技術被描述為"無電鍍鎳"，但 應可明瞭其他元素亦可出現在形成之凸塊，例如大量的磷 (phosphorus)或其他元素。凸塊之無電電锻的其他選擇包 括利用印刷與喷流（jett ing)等方法沉積錫膏。 本發明之凸塊幾何（bumping geometries)與浸潰銲接 程序確實地提供用於形成凸塊以及銲料沉積結構之低成 本、簡化過程，該凸塊以及銲料沉積結構是用於微組合 (microassembly)，特別是用於微電子與半導體領域，尤其 是在倒裝晶片接合期間使用。在任何時候先前技術皆無法 認定在浸潰銲料凸塊形成期間所形成的銲料量，能藉由在 凸塊的侧壁與上表面之間的斜面提供顯著的不連續，而得 以增加。 本發明之態樣將進一步描述有關倒裝晶片之接合，尤 其是無電鍍鎳凸塊成長技術的使用，但也可考慮其他的凸 塊成長方法，包括利用無電鍍銀（Ag)、銅（Cu)、錫（Sn)或 10 94664 201001578 其他化學物之製程。 導電墊典型由金屬製成，但也可使用非金屬的墊。同 樣地，凸塊可為金屬或非金屬，但通常是電性導電。 本發明使用單一、相當厚的遮罩，在積體電路後段處 理（back-end processing)製程期間，用來圖案化積體電路 鈍化層（減法製程（subtractive process))以及用以抑止 在所得到的曝露晶片金屬化層上成長之無電鍍鎳之橫向成 長（加法製程（additive process))。本發明應用上述方法 所形成的結構與先前技術的實際區別通常在於在後續處理 或增加保護層之前，鈍化層的内部直徑（或等同於非圓柱開 口的尺寸）實質上等同於已形成的凸塊之外部直徑（或相 等）。通常也需注意凸塊侧壁在凸塊高度上方為實質上連 續，且在曲率上呈現出無劇烈的改變或不連續。 就典型的裝置而言’ 一般的貫施係在積體電路上使用 光敏聚合物層作為原位（in-situ)遮罩，用於圖案化鈍化層 並從接合墊之區域移除鼓化層。這種典型可為正向或負向 作用本質（working nature)。本發明復包括應用原位聚合 物遮罩作為限制（confinement)結構以用於成長無電鍍鎮 凸塊，以求定義柱狀結構。接著，可部分地或完全地移除 原位遮罩層以曝露凸塊的角。本發明之此態樣為應用單一 光阻層（single photoresist layer)來實現二個處理功 能，此態樣也不會產生額外的製程成本。這與以電鍍為基 礎的銲料凸塊形成技術相反，以電鍍為基礎的銲料凸塊形 成技術需要額外的遮罩層與圖案化步驟。 11 94664 201001578 本發明結合使用或加倍使用厚光阻遮罩用於乾蝕刻 鈍化層與抑制無電鍍鎳凸塊之成長。於最近的先前技術 中，美國公開專利號US20030107132A，已使用分離（未揭 露）製程用於钱刻鈍化層，如各圖式所示者。此製程所需之 額外遮罩步驟將導致特別的缺點，特別是關於製程成本。 關於這點，如前所述，本發明藉由使用相同的光阻遮罩用 於移除鈍化層以及形成有利的柱狀結構，從而克服此缺 點。也就是說，減法操作與加法操作都用相同的光阻遮罩。 然而，再美國公開專利號US20030107132A與其他各種先前 技術製程中，減法製程（例如蝕刻鈍化層）係使用與加法製 程（例如沉積種子層/UMB/凸塊金屬）不同的遮罩步驟，而本 發明使用一個遮罩步驟來負責進行減法與加法製程二者。 本發明之一個實施例包括對無電鍍鎳凸塊加工一浸 潰金層以保護可銲性與預防鎳氧化。在光阻已移除之後， 可在上層鎳表面上方添加此層，同時仍提供光阻遮罩 (resist mask)與/或給錄之上表面與鎳之側面。可用以取 代金作為保護層（preservation layer)的其他材料包括銀 (sliver)，銘（palladium)、錫（tin)與有機材料。 本發明之另一實施例包括在處理之後保留遮罩層於 適當位置，用以提供支持軸環（collar)給凸塊，從而提升 1C晶片中之最終倒裝晶片銲料結合之熱循環疲勞壽命 (thermal cycling fatigue life)與機械振動阻力 (mechanical shock resistance) ° 本發明之鎳凸塊之限制成長之好處係有關於製程期 12 94664 201001578 間缺乏凸塊橫向成長。根據本發明所形成之凸塊具有下表 面區域以及上表面區域，該上表面區域實質上等同於積體 電路金屬層區域，凸塊係成長於該積體電路金屬層區域 上。相較於傳統凸塊，讓凸塊結構被定義在較小間距處， 或者針對給定的間距或鎳凸塊基本直徑，提供晶片金屬芦 接觸區域以及鮮料接合區域的增加。接著，這將會減低電 阻、降低接合電流密度、改善電遷移可靠性 (electromigration reliability)、改善熱傳送（thennal transfer)與改善銲料接合熱循環疲勞壽命。而且，在例如 浸潰銲接製程之後’能提供足夠的銲料用於與基板形成可 靠互連而不需要於組裝期間使用另外的材料。除了浸潰鋒 接之外，也可使用在該技術領域中熟知的其他銲料沉積製 程。Uet1Ve SUFface). Usually, the conductive material is passed through the opening of the mask layer to make it into a metal layer on the active surface to produce a columnar shape. The column shape is further operated to produce a solder cap at the top end of the cylinder. . Next, the mask layer and the metal layer are removed to retain the circle #口口*' to adjust the shape of the solder cap. Although this method can successfully produce a pillar structure of 94664 8 201001578 and has the above advantages, this is a relatively expensive process - an additional masking step is required to pattern the passivation layer and typically achieve two platings. Operation or a plating and printing step. U.S. Patent Publication No. US20030107132A describes the use of a mask to suppress the growth of plated bumps and/or Au caps (to prevent oxidation and maintain solder wettability) to produce anisotropic, columnar metal protrusions. The method of block structure. However, using some masking procedures during different process steps (again, patterning the passivation layer before the additional mask used to form the bump structure) will result in an increase in cost. SUMMARY OF THE INVENTION The present invention provides a simple process that is low cost and achievable with stud bumps, and is particularly applicable to the field of microelectronics. According to the present invention, a method of applying a bump to a conductive pad on a substrate, the substrate having a passivation layer over the conductive pad, the method may include: a) providing a mask layer over the passivation layer; b) patterning and Developing the mask layer to define a cavity extending through the mask layer to align with the conductive pad; c) removing a portion of the passivation layer exposed to the cavity to expose the conductive pad; d) Forming a bump in the cavity to contact the conductive pad; and e) removing the mask layer; the method further comprising applying a fresh layer to the bump by dipping the substrate into the molten solder bath. 94664 201001578 The present invention relates to an improved method of producing bumps and a structure produced by the method, which is particularly useful for flip chip bonding processes which control bump shape during bump growth. The substrate is typically a semiconductor wafer, but may also be a micro-electromechanical system (MEMS) device, a ceramic or a polymer carrier, or even a metal product ( Meta 11 ici tem). The Tao Jing or polymer carrier can be part of a microprocessor component or a multi-device (mu 11; i dev i ce) module. Although the present invention is applicable to different bump processes, the preferred bump method is an electroless plating process, especially an electroless nickel process. Although this technique is described as "electroless nickel", it should be understood that other elements may also be present in the formed bumps, such as a large amount of phosphorous or other elements. Other options for electroless forging of bumps include depositing solder paste using methods such as printing and jetting. The bump geometries and dip soldering procedures of the present invention do provide a low cost, simplified process for forming bumps and solder deposition structures for micro-assembly, Especially used in the field of microelectronics and semiconductors, especially during flip chip bonding. At any time prior art has failed to determine that the amount of solder formed during the formation of the impregnated solder bumps can be increased by providing significant discontinuities in the slope between the sidewalls of the bumps and the upper surface. Aspects of the present invention will further describe the use of flip chip bonding, particularly electroless nickel bump growth techniques, but other bump growth methods may also be considered, including the use of electroless silver (Ag), copper (Cu). ), tin (Sn) or 10 94664 201001578 Process of other chemicals. The conductive pads are typically made of metal, but non-metallic pads can also be used. Similarly, the bumps can be metallic or non-metallic, but are typically electrically conductive. The present invention uses a single, relatively thick mask for patterning the integrated circuit passivation layer (subtractive process) during the back-end processing of the integrated circuit and for suppressing the resulting The lateral growth of the grown electroless nickel on the exposed metallization layer of the wafer (additive process). The actual difference between the structure formed by the application of the above method and the prior art is generally that the internal diameter of the passivation layer (or equivalent to the size of the non-cylindrical opening) is substantially equivalent to the formed bump before subsequent processing or addition of the protective layer. The outer diameter (or equal). It is also generally noted that the sidewalls of the bumps are substantially continuous above the height of the bumps and exhibit no sharp changes or discontinuities in curvature. In the case of a typical device, the general application is to use a photopolymer layer as an in-situ mask on the integrated circuit for patterning the passivation layer and removing the drum layer from the area of the bond pad. . This typical can be a positive or negative working nature. The present invention includes the use of an in-situ polymer mask as a confinement structure for growing electroless electroless bumps to define a columnar structure. The in-situ mask layer can then be partially or completely removed to expose the corners of the bumps. This aspect of the invention achieves two processing functions using a single photoresist layer, which does not incur additional process costs. This is in contrast to electroplating-based solder bump formation techniques where electroplating-based solder bump formation techniques require additional masking and patterning steps. 11 94664 201001578 The present invention uses or doubles the use of a thick photoresist mask for dry etching the passivation layer and inhibiting the growth of electroless nickel bumps. In a prior prior art, U.S. Patent No. US20030107132A, a separate (not disclosed) process has been used for the engraved passivation layer, as shown in the various figures. The additional masking steps required for this process will result in particular disadvantages, especially with respect to process costs. In this regard, as previously discussed, the present invention overcomes this disadvantage by using the same photoresist mask for removing the passivation layer and forming an advantageous columnar structure. That is to say, both the subtraction operation and the addition operation use the same photoresist mask. However, in U.S. Patent No. US20030107132A and various other prior art processes, the subtractive process (e.g., etching passivation layer) uses a different masking step than the additive process (e.g., deposited seed layer/UMB/bump metal), while the present invention A masking step is used to perform both the subtraction and addition processes. One embodiment of the invention includes processing a gold impregnation layer on an electroless nickel bump to protect solderability and prevent nickel oxidation. After the photoresist has been removed, the layer can be added over the upper nickel surface while still providing a resist mask and/or recording the upper surface and the side of the nickel. Other materials that can be used to replace gold as a preservation layer include silver (sliver), palladium, tin, and organic materials. Another embodiment of the invention includes retaining the mask layer in place after processing to provide a support collar to the bump to enhance the thermal cycle fatigue life of the final flip chip solder bond in the 1C wafer ( Thermal cycling fatigue life and mechanical shock resistance ° The benefits of limiting the growth of the nickel bumps of the present invention are related to the lack of lateral growth of the bumps during the manufacturing process 12 94664 201001578. The bump formed in accordance with the present invention has a lower surface region and an upper surface region which is substantially identical to the integrated circuit metal layer region, and the bump is grown on the integrated circuit metal layer region. Compared to conventional bumps, the bump structure is defined at a small pitch, or for a given pitch or nickel bump basic diameter, providing an increase in the wafer metal contact area and the fresh joint area. This, in turn, reduces resistance, reduces junction current density, improves electromigration reliability, improves heat transfer, and improves solder joint thermal cycle fatigue life. Moreover, sufficient solder can be provided after, for example, the dip soldering process to form a reliable interconnect with the substrate without the need to use additional materials during assembly. In addition to the impregnation front, other solder deposition processes well known in the art can be used.
利用製程可形成廣泛不同種類的凸塊幾何。就側邊輪 廓而言，這些不同的凸塊幾何可包括具有實質垂直側邊、 下部底切（undercut)、斜角（angled)或部分凹入的幾何。 當應用浸潰銲料凸塊時，由本發明所形成之特別的凸 塊幾何疋特別有幫助的。之前在先前技術巾並沒有描述到 在浸潰銲料凸塊期間使用類似的凸塊輪廓^用本發明製 程所形成之無電_凸塊典型地在側壁與上表面之間的斜 面具有顯著的（通常大於或相等於9G度）不連續，此不連 續會影響於浸漬銲接時之銲料分 Λ卄刀離過転，以增加保留於鎳 凸塊上之I干枓夏。關於浸潰輝 抑制，因此會有大量録胸2㈣係文到凸塊邊緣的 —大里鳴加之非等向性輪廓。凸塊所保 94664 13 201001578 留之銲料額外量係適於接合晶片而不需要另外的接合材 料。其他的銲接方法係預期以類似方法得到助益。接著， 可將根據本發明所處理之基板應用到現有的ic晶圓與倒 裝晶片製程技術。使用根據本發明之方法，凸塊能製成具 有大範圍的可能間距，但這些凸塊較佳為具有30至180 微米的間距。 由上述製程所形成之典型產品為改善之倒裝晶片銲 料接合組裝件。這可從如上所處理之積體電路晶圓切下浸 潰凸塊裝置而製得，並且以倒裝晶片的方式將這些凸塊裝 置接合到基板，該基板具有匹配的銲料可濕墊（solder wettable pad)之陣歹ιΐ ° 從提供典型之氧化物隔離矽晶圓，到提供金屬層與鈍 化層，整個製程提供了用於1C晶圓之低成本銲料凸塊技 術，這皆相容於傳統錫/鉛銲料合金與最近引進的無鉛銲料 合金。 雖然上述技術已用1C連接之例子來說明，但使用這 些發明方法所產生之凸塊也可用於其他的應用，包括SAW 裝置、被動濾波器、偵測器陣列（detector array)、MEMs 與於非微電子領域之接合。於一個特別例子中，形成的凸 塊遠離任何活動路徑或塗有非導電層作為用於定義基板表 面之間之距離的間隔物。這可用於微電子裝置的間隔，包 括散熱件（heatsink)與晶片或甚至非微電子裝置。 【實施方式】 第1圖係顯示傳統浸潰銲料凸塊結構且該結構包括矽 14 94664 201001578 w裝置i，在該IC裝置i上已設有金屬層2、氮化石夕純化 層3、鎳凸塊4與銲料蓋5。銲料蓋呈現出相當低的接觸角 ㈣典型地小於20度），該銲料蓋典型地會在晶圓離開溶融 銲料槽時將銲料沉潰到習知凸起、非等向性成長之錄/金凸 塊上。所顯示的銲料蓋係典型地設在傳統外形之凸塊上 者’而且相當薄（典型小於10微米）。 第2圖係顯示㈣本發日狀實施例之浸漬銲料凸塊处 構’該結構包括矽IC裝置！，在該石夕ic裝置！上已設有。 金屬層2、氮切鈍化層3、鎳凸塊8與_料蓋9 = 離開溶融銲料槽時，銲料蓋呈現出有相當高的接觸角 6士b(典型地大於45度），當根據本發明將銲料沉積到凸塊上 r該接觸角此係明顯可見的。元件符號1〇指示一區域， 域設有搞的聚合物遮罩結構，肋允許凸塊非等 向性成長。 一 圖係顯示根據本發明之典型製程順序。第 圖係顯示已設有薄(1至3微米)铭合 ::層：5™…裝置或晶圓。二A wide variety of bump geometries can be formed using the process. In terms of side profiles, these different bump geometries may include geometries having substantially vertical sides, undercuts, angled or partially concave. The particular bump geometry formed by the present invention is particularly helpful when applying solder bumps. Previously, prior art wipes have not described the use of similar bump profiles during the impregnation of solder bumps. The electroless bumps formed by the process of the present invention typically have significant slopes between the sidewalls and the upper surface (typically Less than or equal to 9G degrees) discontinuity, this discontinuity will affect the solder cleavage of the immersion soldering during the immersion soldering to increase the I dry summer retained on the nickel bumps. Regarding the immersion glow suppression, there will be a large number of recorded chest 2 (four) text to the edge of the bump - Da Liming plus anisotropic contour. Bumps are protected 94664 13 201001578 The extra amount of solder left is suitable for bonding wafers without the need for additional bonding materials. Other welding methods are expected to benefit from similar methods. Next, the substrate processed in accordance with the present invention can be applied to existing ic wafer and flip chip process technologies. Using the method according to the invention, the bumps can be made to have a wide range of possible pitches, but the bumps preferably have a pitch of 30 to 180 microns. A typical product formed by the above process is an improved flip chip solder joint assembly. This can be made by cutting the submerged bump device from the integrated circuit wafer as described above, and bonding the bump devices to the substrate in a flip chip manner, the substrate having a matching solder wet pad (solder) Wettable pad) From the typical oxide isolation wafer to the metal layer and passivation layer, the entire process provides low-cost solder bump technology for 1C wafers, which is compatible with traditional Tin/lead solder alloys and recently introduced lead-free solder alloys. Although the above techniques have been illustrated using the 1C connection example, the bumps produced using these inventive methods can be used in other applications, including SAW devices, passive filters, detector arrays, MEMs, and Engagement in the field of microelectronics. In one particular example, the formed bumps are remote from any active path or coated with a non-conductive layer as a spacer for defining the distance between the surfaces of the substrate. This can be used for the spacing of microelectronic devices, including heatsinks and wafers or even non-microelectronic devices. [Embodiment] FIG. 1 shows a conventional impregnated solder bump structure and the structure includes a device 14 having a metal layer 2, a nitride layer, a nickel layer, and a nickel bump. Block 4 and solder cover 5. The solder cap exhibits a relatively low contact angle (four) typically less than 20 degrees), which typically sinks the solder to the conventional bump, non-isotropic growth record/gold as the wafer leaves the molten solder bath On the bump. The solder caps shown are typically placed on bumps of conventional shapes and are relatively thin (typically less than 10 microns). Fig. 2 is a view showing (4) the impregnated solder bump structure of the present embodiment. The structure includes a 矽IC device! In the stone ic device! It is already available. Metal layer 2, nitrogen-cut passivation layer 3, nickel bump 8 and_material cover 9 = when leaving the molten solder bath, the solder cap exhibits a relatively high contact angle of 6 b (typically greater than 45 degrees), according to this The invention deposits solder onto the bumps. This contact angle is clearly visible. The component symbol 1 indicates an area in which the polymer mask structure is provided, and the ribs allow the bumps to grow non-isotropically. A drawing shows a typical process sequence in accordance with the present invention. The figure shows that a thin (1 to 3 micron) inscription :: layer: 5TM... device or wafer has been provided. two
^^Γη〇 ΓΓ(Ρ〇81ΐΐν6 W〇rkin^^^^^H 由^ 25微米厚）11之後的ic褒置，該遮罩層幻 案化/2以及輻射曝光(一。 疋義的ig：擇區域中進行顯畢《。安 + _ =為紫外線卿的先遮㈣二^ = p第6圖所示。第7圖係顯示在由遮罩Π所暴露的預 先疋義區域巾藉由幽__化们。這會在空腔底 94664 15 201001578 部暴露出金屬層，在該金屬層上會成長凸塊8(典型地利用 無電鍍鎳製程），如第8圖所示。第8圖所示之凸塊（可為 圓柱體）係由用來沉積之空腔的外形所定義且典型為柱 狀、非等向性外形。第11圖係顯示金塗層14的沉潰，在 沉積金塗層14之後可視需要地去除遮罩層。或者，如第9 圖所示，在遮罩層去除步驟立刻進行第8圖之後，凸塊結 構能進行金塗層的沉積，如第10圖所示。 雖然此範例使用的是正向作用光敏聚合物光阻遮罩 層，但使用負遮罩層（適當的改變處理步驟）亦同樣可行。 第12至13圖顯示浸潰凸塊收回製程之階段。第12 圖係顯示當矽1C 1(顯示有鈍化層3、接合墊2以及凸塊 8)從焊料溶液移開時之不穩定的近點（near po i nt)與銲料 彎液面（men i scus)分離。於此製程期間，保護的金塗層係 快速地溶解於銲料中。第13圖係顯示於完全收回且銲料分 離之後，遺留在凸塊上之銲料的剩餘數量。實際上，定義 在浸潰製程之後存留在無電鍍鎳凸塊上之銲料的量與形狀 的製程是複雜的，但能夠簡單地顯示，如這些圖式所示。 錄凸塊起初被溶化的銲料潤濕，當凸塊晶圓收回時，彎液 面會收縮，直到到達不穩定點，在該鎳凸塊上的銲料與在 溶融銲料槽裡的銲料分離為止。然後，此銲料量本身在無 電鍍鎳凸塊表面上會重新分配銲料量，用以將整體表面能 量減至最小。雖然這些圖式指示在收回期間基板保持與銲 料槽平行，但基板也可以平面垂直於銲料槽或甚至於使凸 塊面向上或向下成一角度的方式收回。 16 94664 201001578 第14與15圖係顯示本發明之另一優點，並且顯示習 知的方法與本發明的不同。第〗4圖係顯示具有金屬2、已 知的凸塊幾何4與典型量的銲料5之矽1C 1。第15圖係 顯示矽1C 1，其具有金屬層2、幾何凸塊8以及因本發明 所提供之凸塊形狀而沉潰之銲料量。顯然，由於使用本發 明之製程，在給定之凸塊基本直徑（或間距）的銲料接合區 域以及金屬接觸區域明顯會有增加。銲料分離量是根據鎳 凸塊外形與相對於凸塊幾何之收回角度（wi thdrawal angle)與重力（gravity)而決定。由這些圖示看來，就給定 之凸塊基本直徑而言，由於鈍化層與凸塊邊界的本質一致 (co i nc i dent a 1 natur e)，所以根據本發明之凸塊能達到較 大的晶片金屬接觸區域。也可完成較大的平頂端表面，對 於相同的基本直徑給予較多的銲料分離量與凸塊高度。在 相等的頂端平表面（大約相同於鈍化開口）直徑處之傳統凸 塊與根據本發明之凸塊的垂直收回，理論上將提供非常相^^Γη〇ΓΓ(Ρ〇81ΐΐν6 W〇rkin^^^^^H is ^25 microns thick) 11 after the ic device, the mask layer magicalization/2 and radiation exposure (a. 疋 ig ig : Select the area to complete the exhibition. An + _ = is the first cover of the ultraviolet qing (four) two ^ = p shown in Figure 6. Figure 7 shows the pre-definition area towel exposed by the mask 藉 by This will expose a metal layer on the bottom of the cavity 94464 15 201001578, where the bumps 8 will grow (typically using an electroless nickel process), as shown in Figure 8. Figure 8. The bumps shown (which may be cylinders) are defined by the shape of the cavity used for deposition and are typically cylindrical, non-isotropic, and Figure 11 shows the collapse of the gold coating 14 during deposition. The mask layer can be removed as desired after the gold coating 14. Alternatively, as shown in Fig. 9, after the mask layer removal step is immediately performed in Fig. 8, the bump structure can perform gold coating deposition, as shown in Fig. 10. Although this example uses a positive-acting photopolymer photoresist mask layer, it is equally feasible to use a negative mask layer (appropriate change processing steps). Figures 12 through 13 show the stages of the dip bump retraction process. Figure 12 shows the unstable near 矽1C 1 (showing passivation layer 3, bond pad 2 and bump 8) removed from the solder solution. The near po i nt is separated from the meniscus of the solder. During this process, the protected gold coating is rapidly dissolved in the solder. Figure 13 shows the full retraction and solder separation. The remaining amount of solder left on the bumps. In fact, the process of defining the amount and shape of solder remaining on the electroless nickel bumps after the impregnation process is complicated, but can be simply displayed, such as these patterns The recorded bumps are initially wetted by the molten solder. When the bump wafer is retracted, the meniscus shrinks until it reaches an unstable point. The solder on the nickel bumps and the solder in the molten solder bath. The amount of solder itself is then redistributed on the surface of the electroless nickel bump to minimize the overall surface energy. Although these figures indicate that the substrate remains parallel to the solder bath during retraction, the substrate Can also be flat The retraction is perpendicular to the solder bath or even so that the bumps face up or down at an angle. 16 94664 201001578 Figures 14 and 15 show another advantage of the present invention and show that the conventional method differs from the present invention. Figure 4 shows a metal 1 with a known bump geometry 4 and a typical amount of solder 5 矽 1C 1 . Figure 15 shows 矽 1C 1 with metal layer 2, geometric bumps 8 and The amount of solder that is collapsed by the bump shape provided by the invention. Obviously, due to the process of the present invention, the solder joint area and the metal contact area of a given bump basic diameter (or pitch) are significantly increased. It is determined according to the shape of the nickel bump and the wi thdrawal angle and gravity with respect to the geometry of the bump. From these illustrations, the bumps according to the present invention can be made larger in terms of the basic diameter of the bumps, since the passivation layer is in accordance with the nature of the bump boundaries (co i nc i dent a 1 natur e) The metal contact area of the wafer. It is also possible to complete a larger flat top surface, giving more solder separation and bump height for the same basic diameter. The conventional retraction at the diameter of the equal top flat surface (approximately the same as the passivation opening) and the vertical retraction of the bump according to the present invention will theoretically provide a very phase
似的銲料分離量。然後，由於有邊結構（edgeds计udua) 的抑制作用，此鐸料量會在鎳凸塊表面上重新分配，以針 對根據本發騎形成的鎳凸塊輪廓增加銲料凸塊高度，然 而針對傳統鎳凸塊結構，銲料將不會被抑止而因此將形成 較小高度的銲料凸塊。 第16圖係顯示根據本發明之實施例之一些使用對應 外型的空腔7所形成的數個凸塊輪廓，有垂直15、下部底 @ 與inm η ’但其他的變化也可考慮。形成具有有邊 輪廓可為對稱的(圓柱、三烏或其他多邊形)或其他形態。 94664 17 201001578 之柱狀凸塊結構上之本質不-致 脱咖1⑺32Α之 ^那些利用美國專利公開號 “简3、接合==口 =22、保護塗層 化與形成期間使用不同的遮罩塊之圖案 成長，而非形成為柱狀時，看凸4、、·σ構是等向性 凸塊/鲍化邊界。 相的會疋—種相似的非-致 之二Τ顯示在根據本發明之凸塊結構上本質-致 =、2=塊邊界21，包括凸塊δ、保護塗層μ " ° 2與基板卜鈍化之内部直徑實f上等 形成的凸塊的外部直徑並且在曲 、'同： =一。這是因為在凸塊之圖=== 共同的遮罩步驟，於圖式中邊界顯成= 塊邊界(如第16圖所示)、鈍化邊界或二者-:者凸 :;草=型(正❹'光阻)或化學與物:效應：： =::广界將總是實一 :法—參考隨 塊結=_輪s_4剛娜以形成之凸 塊結=圖係顯示根據本發明之方法的實施例所形成之凸 弟3至1G圖係顯示根據本發明之—些典型製程順序； 94664 18 201001578 第11至13圖係顯示利用根據本發明所形成之結構， 在浸潰凸塊收回製程期間所發生的步驟； 第14和15圖係分別顯示根據傳統製程與根據本發明 之實施例所製成之凸塊結構； 第16圖係顯示數個可能的凸塊輪廓； 第17圖係顯示在習知凸塊結構上所形成之鈍化層與 凸塊邊界的位置； 弟18圖係顯不在根據本發明之凸塊結構上所形成之 鈍化層與凸塊邊界的位置； 所有的圖式係僅以說明為目的，並非按一定的比例。 當應用倒裝晶片接合時，應敘述根據本發明之典型製 程順序。 總而言之，矽1C裝置或晶圓係設有薄的（1至3微米） I呂合金金屬層與氮化^夕鈍化層。光敏聚合物光阻遮罩層（例 如聚感亞胺或聚伸苯曱氧基（口〇1756112(^716]16)，10至25 ，微米厚度，更典型地為15至20微米厚度間）係沉積至1C 裝置上’該IC裝置係後續藉由輻射曝光（exposure)於選擇 區域中進行顯影。接著藉由乾钱刻步驟把遮罩所暴露之區 域中的鈍化層移除，形成高侧（tall-sided)空腔，並於該 空腔底部置有金屬之暴露區（接合墊）。然後，使用無電鍍 鎳凸塊成長製程以沉積典型柱狀、非等向性鎳凸塊。在遮 罩剝除之前，凸塊結構可保護性地塗有金，或者在遮罩層 剝除之後沉積金塗層。接著，可將結構浸入溶融銲料之儲 存槽，從而導致銲料蓋的沉潰，以準備進一步的處理以及 19 94664 201001578 與微電子组裝件合併。 上述所有的處理操作係利用已知現有的材料與技 術。可適當地將上述材料與技術替換成該技術領域中已知 的其他材料與處理技術。 【主要元件符號說明】 1 基板 2 導電墊、接合墊 、金屬層 3 鈍化層 4 錄凸塊 5 銲料蓋 6a、6b 接觸角 7 空腔 δ 凸塊 9 銲料蓋；銲料層 10 區域 11 遮罩層 12 圖案化 13 曝光 14 全塗層；保護塗層 15、16 、17 凸塊輪廓 18、20 鈍化 19、21 凸塊邊界 20 94664The amount of solder separation. Then, due to the suppression of the edge structure (edgeds), the amount of the material is redistributed on the surface of the nickel bump to increase the height of the solder bump for the nickel bump profile formed according to the present ride. With the nickel bump structure, the solder will not be inhibited and thus will form a smaller height of solder bumps. Fig. 16 is a view showing a plurality of bump profiles formed by cavities 7 corresponding to the outer shape according to an embodiment of the present invention, having vertical 15, lower bottom @ and inm η ' but other variations are also conceivable. Formed with a beveled profile that can be symmetrical (cylinder, Sanwu or other polygon) or other form. 94664 17 201001578 The nature of the columnar bumps is not the same as those used in the US Patent Publication No. 3, Bonding == Port = 22, protective coating and different masking during formation. When the pattern grows, instead of being formed into a columnar shape, the convex 4, and σ structures are isotropic bumps/barked boundaries. The similarity of the phase is similar to that of the non-induced bismuth. The essence of the bump structure is -, = 2, the block boundary 21, including the outer diameter of the bump formed by the bump δ, the protective coating μ " ° 2 and the internal diameter of the substrate passivation and is in the mean , 'Same: = 1. This is because the common masking step in the diagram of the bump ===, in the diagram the boundary appears = block boundary (as shown in Figure 16), passivation boundary or both -: Convex: grass = type (positive 'resistance') or chemical and matter: effect:: =:: wide bound will always be one: method - reference with block knot = _ round s_4 Gangna to form the bump结=图图 shows a convex 3 to 1G pattern formed according to an embodiment of the method of the present invention showing some typical process sequences according to the present invention; 94664 18 201001578第11至Figure 13 shows the steps that occur during the impregnation bump retraction process using the structure formed in accordance with the present invention; Figures 14 and 15 show bumps made in accordance with an embodiment of the present invention, respectively, according to conventional processes. Structure; Figure 16 shows several possible bump profiles; Figure 17 shows the position of the boundary between the passivation layer and the bump formed on the conventional bump structure; the figure 18 shows that it is not convex according to the present invention. The locations of the passivation layer and bump boundaries formed on the block structure; all of the drawings are for illustrative purposes only and are not to scale. When flip chip bonding is applied, a typical process sequence in accordance with the present invention should be described. In summary, the 矽1C device or wafer is provided with a thin (1 to 3 micron) Ilu alloy metal layer and a nitrided passivation layer. Photopolymer barrier layer (eg, polyimine or polybenzazole) Alkoxy groups (mouth 1756112 (^716] 16), 10 to 25, micron thickness, more typically between 15 and 20 microns thickness) are deposited onto a 1C device. The IC device is subsequently exposed by radiation (exposure) ) developing in the selected area The passivation layer in the exposed area of the mask is then removed by a dry etching process to form a tall-sided cavity, and a metal exposed area (bonding pad) is placed at the bottom of the cavity. An electroless nickel bump growth process is used to deposit typical columnar, anisotropic nickel bumps. The bump structure can be protectively coated with gold or deposited after the mask layer is stripped prior to mask stripping. The gold coating. Next, the structure can be immersed in the storage bath of the molten solder, causing the solder cap to collapse, in preparation for further processing and the merging of the microelectronic assembly with 19 94664 201001578. All of the above processing operations utilize known materials and techniques. The materials and techniques described above may be suitably replaced with other materials and processing techniques known in the art. [Main component symbol description] 1 substrate 2 conductive pad, bonding pad, metal layer 3 passivation layer 4 recording bump 5 solder cap 6a, 6b contact angle 7 cavity δ bump 9 solder cap; solder layer 10 region 11 mask layer 12 Patterned 13 Exposure 14 Fully coated; protective coating 15, 16 , 17 Bump profile 18, 20 Passivation 19, 21 Bump boundary 20 94664