JP2007194516A - 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法 - Google Patents

複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法 Download PDF

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Publication number
JP2007194516A
JP2007194516A JP2006013376A JP2006013376A JP2007194516A JP 2007194516 A JP2007194516 A JP 2007194516A JP 2006013376 A JP2006013376 A JP 2006013376A JP 2006013376 A JP2006013376 A JP 2006013376A JP 2007194516 A JP2007194516 A JP 2007194516A
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JP
Japan
Prior art keywords
wiring board
electrically insulating
insulating substrate
wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006013376A
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English (en)
Japanese (ja)
Other versions
JP2007194516A5 (enExample
Inventor
Tomoe Sasaki
智江 佐々木
Yasuhiro Sugaya
康博 菅谷
Toshiyuki Asahi
俊行 朝日
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006013376A priority Critical patent/JP2007194516A/ja
Publication of JP2007194516A publication Critical patent/JP2007194516A/ja
Publication of JP2007194516A5 publication Critical patent/JP2007194516A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2006013376A 2006-01-23 2006-01-23 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法 Pending JP2007194516A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006013376A JP2007194516A (ja) 2006-01-23 2006-01-23 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006013376A JP2007194516A (ja) 2006-01-23 2006-01-23 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法

Related Child Applications (1)

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JP2011149808A Division JP2011233915A (ja) 2011-07-06 2011-07-06 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法

Publications (2)

Publication Number Publication Date
JP2007194516A true JP2007194516A (ja) 2007-08-02
JP2007194516A5 JP2007194516A5 (enExample) 2009-02-19

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JP2006013376A Pending JP2007194516A (ja) 2006-01-23 2006-01-23 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法

Country Status (1)

Country Link
JP (1) JP2007194516A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009090879A1 (ja) * 2008-01-18 2009-07-23 Panasonic Corporation 立体配線板
JP2010238821A (ja) * 2009-03-30 2010-10-21 Sony Corp 多層配線基板、スタック構造センサパッケージおよびその製造方法
JP2016511552A (ja) * 2013-03-15 2016-04-14 クアルコム，インコーポレイテッド 低減された高さのパッケージオンパッケージ構造
JP2016092196A (ja) * 2014-11-04 2016-05-23 日本特殊陶業株式会社 配線基板
JP2019080037A (ja) * 2017-10-20 2019-05-23 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273464A (ja) * 1994-03-31 1995-10-20 Ibiden Co Ltd Ｉｃ搭載用プリント配線板の製造方法
JPH09214088A (ja) * 1996-01-31 1997-08-15 Sumitomo Kinzoku Electro Device:Kk セラミック基板のプリント配線基板への実装構造
JP2001250909A (ja) * 2000-02-03 2001-09-14 Fujitsu Ltd 電気部品搭載基板のための応力低減インターポーザ
JP2005045150A (ja) * 2003-07-25 2005-02-17 Matsushita Electric Ind Co Ltd 中間接続用配線基材および多層配線基板、ならびにこれらの製造方法
JP2005209904A (ja) * 2004-01-23 2005-08-04 Matsushita Electric Ind Co Ltd 多層配線基板、多層配線基板を備えたモジュール、および、電子機器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273464A (ja) * 1994-03-31 1995-10-20 Ibiden Co Ltd Ｉｃ搭載用プリント配線板の製造方法
JPH09214088A (ja) * 1996-01-31 1997-08-15 Sumitomo Kinzoku Electro Device:Kk セラミック基板のプリント配線基板への実装構造
JP2001250909A (ja) * 2000-02-03 2001-09-14 Fujitsu Ltd 電気部品搭載基板のための応力低減インターポーザ
JP2005045150A (ja) * 2003-07-25 2005-02-17 Matsushita Electric Ind Co Ltd 中間接続用配線基材および多層配線基板、ならびにこれらの製造方法
JP2005209904A (ja) * 2004-01-23 2005-08-04 Matsushita Electric Ind Co Ltd 多層配線基板、多層配線基板を備えたモジュール、および、電子機器

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009090879A1 (ja) * 2008-01-18 2009-07-23 Panasonic Corporation 立体配線板
US8278565B2 (en) 2008-01-18 2012-10-02 Panasonic Corporation Three-dimensional wiring board
JP2010238821A (ja) * 2009-03-30 2010-10-21 Sony Corp 多層配線基板、スタック構造センサパッケージおよびその製造方法
US8446002B2 (en) 2009-03-30 2013-05-21 Sony Corporation Multilayer wiring substrate having a castellation structure
JP2016511552A (ja) * 2013-03-15 2016-04-14 クアルコム，インコーポレイテッド 低減された高さのパッケージオンパッケージ構造
JP2016092196A (ja) * 2014-11-04 2016-05-23 日本特殊陶業株式会社 配線基板
JP2019080037A (ja) * 2017-10-20 2019-05-23 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
JP7207688B2 (ja) 2017-10-20 2023-01-18 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板
JP2023036832A (ja) * 2017-10-20 2023-03-14 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板
JP7480458B2 (ja) 2017-10-20 2024-05-10 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板

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