JP2007181742A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can save a proper control condition by properly monitoring the operation condition of electronic components at the time of the unexpected cut off of a power source. <P>SOLUTION: A CPU makes drive signals output to a dispensing motor off condition in mask impossible interrupting processing when power source cut off interrupt is generated. Thereby, the drive of a ball dispense unit is stopped. Then the detected signals of a winning ball count switch and a ball dispensing count switch as dispensing detecting means are checked for a predetermined period. The processing is shift to the processing for storing the control condition in a backup RAM when a predetermined time passes. Accordingly, even the game balls dispensed about at the time when power source cut off signals is put on according to electric power failure are detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine in which a game is performed according to a player's operation, and more particularly, according to a player's operation in a gaming area on a gaming board. The present invention relates to a gaming machine in which a game is performed.

  As an example of a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are awarded to the player There are things that will be paid out. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  The game value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous to a player who is easy to win and a right to become advantageous to the player. Or a condition that the conditions for paying out premium game media are easily established.

  In the first type pachinko gaming machine having a variable display unit that displays a special symbol, the display result of the variable display unit that displays the special symbol is usually a combination of a specific display mode defined in advance. " When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). Note that an opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the display results that are already deterministic or temporary at the stage where some of the display results of the plurality of variable display portions are not yet derived and displayed. A state in which the display mode of the variable display unit in which “” is derived and displayed satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, when the display result of the identification information variably displayed on the variable display section does not satisfy the condition of “big hit”, it becomes “disconnected”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  When a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board. In the following description, the game control means and other control means control various electrical components provided in the gaming machine, so they may be referred to as electrical component control means.

  As described above, the gaming machine is equipped with various electric component control means including game control means. In general, each electrical component control means includes a microcomputer. Such an electrical component control means generally performs an initialization process and starts control from an initial state when a power supply voltage rises. Then, an unexpected power failure such as a power failure occurs, and then the power returns to the initial state when the power is restored. Therefore, there is a problem that the game value obtained by the player disappears. In order to prevent such a problem from occurring, the game control is interrupted according to a predetermined signal generated as the power supply voltage value decreases, and the power supply to the gaming machine is stopped at that time. In particular, it may be controlled to store in a storage means (backup storage means) that is backed up and wait for the power supply to be completely stopped. Such a gaming machine resumes the game based on the stored control state when power supply is resumed while the game state is stored in the storage means, so that a disadvantage is given to the player. Is prevented.

  However, if the electrical component is operating immediately before performing the process of saving the control state in the backup storage unit, the actual control state may change with respect to the saved control state. For example, when a game ball paid out from a ball payout device for paying out a game ball is detected by a switch means provided at the lower part of the ball payout device and the payout of the game ball is confirmed, Such a problem may occur. That is, the ball payout device executes payout of one game ball immediately before stopping the operation of the ball payout device, a power failure occurs immediately after that, and the control state is stored before the switch means detects the payout. In this case, there is a discrepancy between the stored payout confirmation number (or unpaid number) and the actual payout number. In such a case, if the ball payout process is restarted based on the stored control state when the power supply is resumed, extra game balls will be paid out.

  In addition, since there is a distance between the winning opening provided on the game board and the position of the switch for detecting the winning at the winning opening, a gaming ball is won at the winning opening and the gaming ball is detected by the switch. If a process for saving the control state is performed before the winning, the winning is not detected and is canceled. In addition, even if control is performed to close the grand prize opening in response to the occurrence of a power outage, if a process for saving the control state is performed in response to the occurrence of a power outage, the game balls won immediately before the closing of the big prize opening May not be detected.

  In view of the above, an object of the present invention is to provide a gaming machine that can appropriately monitor the operation state of an electrical component and store an appropriate control state when the power supply is unexpectedly cut off.

  A gaming machine according to the present invention is a gaming machine in which a player can play a predetermined game, and an electrical component control means for controlling an electrical component provided in the gaming machine, and a game medium for detecting the gaming medium Game medium detecting means, memory holding means capable of holding the stored contents of the electrical component control means even when power supply to the gaming machine is stopped, and power supply monitoring means for monitoring the state of a predetermined power source used in the gaming machine And when the electric component control means detects that the power supply state has become a predetermined state determined in advance by the power supply monitoring means, a detection signal input process from the game medium detection means for a predetermined period of time After executing the above, the power supply stop processing related to the storage of the control state is performed.

  The gaming machine includes a payout means as an electrical component for paying out game media, and the game medium detection means includes, for example, a payout detection means for detecting a game medium paid out from the payout means.

  The predetermined period is, for example, a period equal to or longer than the period until the game medium paid out by the payout means reaches the payout detection means.

  When the electric component control means detects that the power supply state has become a predetermined state determined in advance by the power supply monitoring means, after the drive of the payout means is stopped, the detection signal input from the payout detection means It is preferable to execute the processing.

  Even if the power supply to the gaming machine is stopped, an auxiliary driving power source capable of supplying power capable of driving the game medium detecting means in a predetermined period may be provided.

  As the payout detection means, a prize game medium detection means for detecting a prize game medium and a rental game medium detection means for detecting a game medium lent to a player may be provided separately. Good.

  When the electric component control means detects that the power supply state has become a predetermined state determined in advance by the power supply monitoring means, the detection signal is output in the detection signal input process executed from the payout detection means. You may be comprised so that the timer process which can measure a period will be performed.

  There are an award game medium payout route and a rented game medium payout route, and a switching member for switching the payout route is provided, so that the operating position of the switching member can be maintained for a predetermined period even when power supply to the gaming machine is stopped. It may be configured.

  The auxiliary drive power supply may be configured to be able to supply power for maintaining the operating position of the switching member for a predetermined period even when power supply to the gaming machine is stopped.

  As the payout means, a prize game medium payout means for paying out award game media and a rental game medium payout means for paying out game media lent to a player may be provided separately. .

  As described above, according to the present invention, when the electrical component control unit detects that the state of the power source is in the predetermined state determined in advance by the power source monitoring unit, Since the processing for inputting the detection signal from the game medium detection means is executed and then the power supply stop processing related to the storage of the control state is performed, the control state saved by the memory holding means and the actual control state Are guaranteed to match, so that an appropriate control state can be saved.

  A payout means for paying out game media, and when the game medium detection means includes a payout detection means for detecting game media paid out from the payout means, the payout detection means moves away from the position of the payout means. This is effective when the game medium discharged from the payout means is detected at the selected position.

  When the predetermined period is equal to or longer than the period until the game medium paid out by the payout means reaches the payout detecting means, the payout device pays out in the input process of the detection signal from the payout detecting means. The game medium that is being played is reliably detected.

  When the electric component control means detects that the power supply state has become a predetermined state determined in advance by the power supply monitoring means, after the drive of the payout means is stopped, the detection signal input from the payout detection means When the processing is configured to be executed, the predetermined period is paid out from the payout device even if the game medium paid out by the payout means reaches the payout detection means. The game medium that is being played is reliably detected.

  Even if the power supply to the gaming machine is stopped, if an auxiliary drive power source capable of supplying power that can drive the game medium detecting means in a predetermined period is provided, the payout device is paid out in the predetermined period. There will be no situation in which the game medium being played is not detected.

  When the award game medium detecting means and the rented game medium detecting means are provided separately as the payout detecting means, the award game medium and the rented game medium can be detected separately.

  In the input processing of the detection signal from the game medium detection means, which is executed when the electrical component control means detects that the power supply state has become a predetermined state determined by the power supply monitoring means, In the case where the timer process capable of measuring the output period is performed, it is possible to prevent the ON detection by the detection signal from being erroneously performed.

  When there is an award game medium payout route and a rented game medium payout route, a switching member for switching the payout route is provided, and the operating position of the switching member can be maintained for a predetermined period even when power supply to the gaming machine is stopped Even if it is configured to distinguish a prize ball and a ball lending by route switching, the award game medium and the rented game medium can be reliably distinguished and detected.

  If the auxiliary drive power supply can supply power for maintaining the operating position of the switching member for a predetermined period even when power supply to the gaming machine is stopped, the award gaming medium and the rented gaming medium are surely It is guaranteed that the situation can be detected separately.

  Even when the award game medium payout means and the rented game medium payout means are provided separately as the payout means, it is guaranteed that the control state saved by the memory holding means matches the actual control state.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine and may be, for example, a coin gaming machine or a slot machine.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, a variable display including a variable display unit (special symbol display device) 9 for variably displaying a plurality of types of symbols and a normal symbol display device (ordinary symbol display device) 10 using a 7-segment LED. A device 8 is provided. The variable display unit 9 has, for example, three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passing gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch (V winning switch) 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 19, 24, and winning of the game balls to the respective winning holes 19, 24 is performed by correspondingly provided winning hole switches 19a, 19b, 24a, 24b. Detected. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when there is a remaining number of prize balls is provided in the vicinity of one speaker 27, and a sphere that is lit when a supply ball is cut near the other speaker 27. A cut lamp 52 is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the normal symbol display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by one.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol in the normal symbol display 10 is a predetermined symbol (winning symbol = small winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, each board | substrate arrange | positioned at the back surface of the pachinko game machine 1 is demonstrated.
As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2 </ b> A, and the pachinko gaming machine 1 is installed above the gaming machine installation island. The game balls are supplied to the ball storage tank 38. The game balls in the ball storage tank 38 pass through the guide basket 39 and reach the ball payout device covered with the prize ball case 40A.

  On the back side of the gaming machine, there are installed a variable display control unit 29 for controlling the variable display unit 9, a game control board (main board) 31 on which a game control microcomputer and the like are mounted. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control and the like, and a hitting ball launching device for hitting a hitting ball into the game area 7 using the rotational force of the motor are installed. Furthermore, the sound control for controlling the sound generation from the decoration lamp 25, the game effect LED 28a, the game effect lamps 28b and 28c, the lamp control board 35 for sending signals to the prize ball lamp 51 and the ball break lamp 52, and the speaker 27. A launch control board 91 for controlling the board 70 and the ball hitting device is also provided.

  Furthermore, a power supply board 910 on which a power supply circuit for generating DC30V, DC21V, DC12V and DC5V is mounted is provided, and a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. Has been. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center. In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are supplied to the game effect LED 28 a, game effect lamps 28 b and 28 c, the prize ball lamp 51, and the ball break lamp 52 provided on the frame side. Although the electrical relay board A77 for doing this is shown, other relay boards are also provided if necessary for signal relay.

  FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. The balls stored in the ball storage tank 38 pass through the guide rod 39 and pass through the ball break detectors (ball break switches) 187a and 187b, as shown in FIG. 3, through the ball supply rods 186a and 186b. Device 97 is reached. The ball break switches 187a and 187b are switches that detect the presence or absence of a game ball in the game ball passage, but a ball break detection switch 167 that detects a shortage of supply balls in the ball tank 38 is also provided. Hereinafter, the ball break switches 187a and 187b may be expressed as ball break switches 187.

  The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45.

  A lot of premium balls based on the winnings are paid out and the hitting ball supply tray 3 becomes full. Finally, when the game balls reach the contact port 45 and further game balls are paid out, the game balls are surplus via the surplus ball passage 46. It is guided to the ball receiving tray 4. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the hitting ball launching device is also stopped.

  Next, the configuration of the intermediate base unit installed on the mechanism plate 36 will be described. In the intermediate base unit, ball supply rods 186a and 186b and a ball dispensing device 97 are installed. As shown in FIG. 4, connection concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave protrusion 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

  A passage body 184 is fixed to the upper part of the intermediate base unit. A ball dispensing device 97 is fixed to the lower part of the passage body 184. The passage body 184 has payout ball passages 186a and 186b for flowing down two rows of game balls whose flow direction has been changed to the left and right directions by a curve rod 174 (see FIG. 3). On the upstream side of the payout ball passages 186a, 186b, ball break switches 187a, 187b are installed. The ball break switches 187a and 187b detect the presence or absence of a game ball in the payout ball passages 186a and 186b. When the ball break switches 187a and 187b no longer detect a game ball, the payout motor ( The rotation of the ball (not shown in FIG. 4) is stopped and the ball payout is immobilized.

  The ball break switches 187a and 187b are locked by locking pieces 188 at positions where it can be detected that about 27 to 28 game balls are present in the payout ball passages 186a and 186b. In other words, the ball break switches 187a and 187b have a maximum payout amount per unit of prize balls (15 in this embodiment) and a maximum payout amount per unit of ball lending (100 yen: 25 in this embodiment). It is installed at a position where the above can be confirmed.

  The central portion of the passage body 184 is formed in a shape that curves to the left and right so as to weaken the ball pressure of the game ball flowing down inside. A stop hole 189 is formed between the payout ball passages 186a and 186b. A mounting boss provided in the intermediate base unit is fitted into the back surface of the stop hole 189. In this state, the set screw is screwed, and the passage body 184 is fixed to the intermediate base unit. The passage body 184 can be aligned by the locking protrusion 185 provided on the intermediate base unit before being screwed.

  Below the passage body 184, a ball stopper 190 is provided for supplying the game ball to the ball payout device 97 and stopping the supply of the game ball to the ball payout device 97 in the event of a failure. A ball payout device 97 installed below the ball stopper 190 is housed in a rectangular parallelepiped case 198. Projections are provided at four places on the left and right sides of the case 198. The lower end of the case 198 is fitted into the elastic engagement piece provided at the lower part of the intermediate base unit in a state where each protrusion is engaged with the positioning protrusion provided on the intermediate base unit.

  FIG. 5 is an exploded perspective view of the ball dispensing device 97. The configuration and operation of the ball dispensing device 97 will be described with reference to FIG. In the ball dispensing device 97 in this embodiment, a stepping motor (dispensing motor) 289 rotates a screw 288 to pay out pachinko balls one by one. Note that the ball payout device 97 pays out not only a prize ball based on a prize but also a game ball to be lent.

  As shown in FIG. 5, the ball dispensing device 97 has two cases 198a and 198b. Engagement protrusions 280 are provided at two positions on the left and right sides of the cases 198a and 198b. In addition, ball supply paths 281a and 281b are formed in the cases 198a and 198b, respectively. The ball supply paths 281a and 281b have curved surfaces 282a and 282b, and ball feed horizontal paths 284a and 284b are formed below the ends of the curved surfaces 282a and 282b. Furthermore, ball discharge paths 283a and 283b are formed at the ends of the ball feed horizontal paths 284a and 284b.

  The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b are formed in front of partition walls 295a and 295b that divide the cases 198a and 198b in the front-rear direction. Further, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b in front of the partition walls 295a and 295b. The ball pressure buffering member 285 distributes the balls supplied to the ball dispensing device 97 to the left and right sides and guides the balls to the ball supply paths 281a and 281b.

  In addition, below the ball pressure buffering member 285, a payout motor position sensor using a light emitting element (LED) 286 and a light receiving element (not shown) is provided. The light emitting element 286 and the light receiving element are provided at a predetermined interval. The tip of the screw 288 is inserted within this interval. The ball pressure buffering member 285 is completely housed and fixed inside the cases 198a and 198b.

  Screws 288 that are rotated by a payout motor 289 are disposed in the ball feed horizontal paths 284a and 284b. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is fitted into fixing grooves 291a and 291b formed at the rear of the partition walls 295a and 295b. In this state, the motor shaft of the payout motor 289 protrudes in front of the partition walls 295a and 295b, so that the screw 288 is fixed in front of the protrusion. On the outer periphery of the screw 288, there is provided a spiral projection 288a for moving the game ball placed on the ball feed horizontal paths 284a, 284b forward by the rotation of the payout motor 289.

  A recess is formed at the tip of the screw 288 so as to accommodate the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, during one rotation of the screw 288, the light from the light emitting element 286 is detected twice by the light receiving element through the notch 292.

  In other words, the payout motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position, and detects that the payout operation has been performed. The wiring from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively drawn out from a drawing hole formed below the rear portions of the cases 198a and 198b and connected to the connector.

  When the payout motor 289 rotates in a state where the game ball is placed on the ball feed horizontal paths 284a and 284b, the game ball is moved forward on the ball feed horizontal paths 284a and 284b by the spiral protrusion 288a of the screw 288. Moving. And finally, it falls to the ball discharge paths 283a and 283b from the end of the ball feed horizontal paths 284a and 284b. At this time, the left and right ball feed horizontal paths 284a and 284b are alternately dropped. That is, each time the screw 288 is rotated halfway, one game ball falls from one side. Therefore, each time one game ball falls, the light from the light emitting element 286 is detected by the light receiving element.

  As shown in FIG. 4, a ball sorting member (switching member) 311 is provided below the ball dispensing device 97. The ball sorting member 311 is driven by the sorting solenoid 310. For example, when the solenoid 310 is on, the ball sorting member 311 falls to the right, and when it is off, the ball sorting member 311 falls to the left. Below the sorting solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B by proximity switches are provided. At the time of a winning ball based on winning, the ball sorting member 311 falls to the right side, and balls from the ball discharge paths 283a and 283b both pass the winning ball count switch 301A. Further, at the time of lending a ball, the ball sorting member 311 falls to the left side, and balls from the ball discharge paths 283a and 283b both pass the ball lending count switch 301B. Accordingly, the ball payout device 97 can change the payout flow path between the winning ball and the ball lending and pay out a predetermined number of game media.

  In this way, by providing the ball sorting member 311, the ball that has fallen through the two ball passages passes only one of the prize ball count switch 301 </ b> A and the ball lending count switch 301 </ b> B. Accordingly, the number of winning balls or the number of balls lent can be immediately grasped from the detection outputs of the winning ball count switch 301A and the ball lending count switch 301B without determining whether the ball is a winning ball or a lending ball.

  In this embodiment, a ball payout device 97 for paying out game balls by rotation of a stepping motor is used as a ball payout device for paying out game balls by driving an electric drive source. A ball payout device having a structure for delivering a game ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source such as a solenoid and the game ball is discharged by its own weight may be used. In this embodiment, the ball payout device 97 pays out a prize ball based on the prize ball and a loaned ball based on the loan request, but a payout device may be provided for each.

  FIG. 6 is a block diagram illustrating an example of a circuit configuration in the main board 31. 6 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a symbol control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V winning switch 22, a count switch 23, winning port switches 19a, 19b, 24a, 24b, The switch circuit 58 for supplying signals from the tongue switch 48, the ball break switch 187 and the prize ball count switch 301A to the basic circuit 53, the solenoid 16 for opening / closing the variable prize ball device 15, the solenoid 21 for opening / closing the opening / closing plate 20, and the big prize A solenoid circuit 59 for driving the solenoid 21A for switching the route in the mouth according to a command from the basic circuit 53 is mounted.

  Although not shown in FIG. 6, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 that outputs an information output signal such as probability variation information to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of storage means used as a work memory, a CPU 56 that performs control operations according to the program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  Further, the main board 31 is provided with a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory indicator 18, the gate passing memory indicator 41 and the decoration lamp 25 provided on the game board. At the same time, display control of the game effect lamps / LEDs 28a, 28b, 28c, the prize ball lamp 51 and the ball break lamp 52 provided on the frame side is performed. The display control of the variable display unit 9 for variably displaying the special symbol and the normal symbol display 10 for variably displaying the normal symbol is performed by display control means mounted on the symbol control board 80.

  FIG. 7 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full switch 48 is input to the I / O port 57 of the main board 31 through the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball tray 4. The detection signal from the ball break switch 187 (187a, 187b) is also input to the I / O port 57 of the main board 31 through the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 issues a payout prohibition when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Send a control command. When a payout control command for instructing payout is received, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, the detection signal from the prize ball count switch 301A is input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71, and input to the payout control board 37 via the relay board 72. Input to port 372b. The prize ball count switch 301A is provided in a payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a win, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a and drives the ball payout device 97 in accordance with the payout control command to pay out a winning ball.
In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 via the output port 372c. Further, an error signal is output to the error display LED 374 via the output port 372d.

  Further, a detection signal from the ball lending count switch 301B is input to the input port 372b of the payout control board 37 via the relay board 72. The ball lending count switch 301B is provided in a payout mechanism portion of the ball payout device 97, and detects a lending ball actually paid out. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the drive signal to the sorting solenoid 310 is transmitted. Is transmitted to the sorting solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372b and the output port 372e.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where a game ball corresponding to the amount of money is lent out in accordance with coin insertion. That is, the present invention can be applied even when the gaming machine only pays out a prize ball as a game ball.

  FIG. 8 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the symbol control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric part control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate. Note that VSL is generated by rectifying and boosting AC24V with a rectifier element in the rectifier circuit 912. VSL is a solenoid driving power source.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 includes one or a plurality of converter ICs 922 (only one is shown in FIG. 8), generates + 21V, + 12V, and + 5V based on VSL and outputs the generated voltages to the connector 915. A relatively large capacitor 923 is connected to the input side of the converter IC 922. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as + 30V, + 12V, + 5V, etc., decreases relatively slowly. As a result, the capacitor 923 serves as an auxiliary drive power source described later. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board. Further, although one connector 915 is representatively shown in FIG. 8, the connector is provided for each electrical component control board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is in a storage state with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is cut off (a RAM that is backed up, that is, a backup storage means that can be in a storage content holding state even when the power supply is stopped). This is a backup power supply that supplies power so that the Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line. In this embodiment, + 5V for backup is supplied to the main board 31 and the payout control board 37.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  Further, a power supply monitoring IC 902 is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output as a power-off occurs. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. A power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output becomes the power It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 that is separate from the electrical component control board, a power-off signal can be supplied from the power monitoring circuit to the plurality of electrical component control boards. Even if there are any number of electrical component control boards that require a power-off signal, it is only necessary to provide one power supply monitoring means. Therefore, even if each electrical component control means on each electrical component control board performs return control described later. The cost of the gaming machine does not increase so much.

  In the configuration shown in FIG. 8, the detection output (power cut-off signal) of the power monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. However, for example, a configuration may be adopted in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit corresponding to the number of substrates that require a power-off signal may be provided.

  FIG. 9 is a block diagram illustrating a configuration example around the CPU 56 in the main board 31. As shown in FIG. 9, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. The power supply monitoring circuit is a circuit that detects a power supply voltage drop by monitoring the voltage of any of the various DC power supplies used by the gaming machine. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level power cut-off signal is generated. VSL is the largest DC voltage in the gaming machine, and is +30 V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt process.

  FIG. 9 also shows a system reset circuit 65. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same as the power supply voltage monitored by the power supply monitoring circuit, and the voltage value is lower than a predetermined value (the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). When the value is less than or equal to, the output is set to low level. Accordingly, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit, and then the system is reset.

  As shown in FIG. 9, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the power supply monitoring circuit (the voltage that outputs the power-off signal) is + 22V, and the detection voltage for setting the reset signal to low level is + 9V. In such a configuration, since the power supply monitoring circuit and the system reset circuit 65 monitor the voltage of the same power supply VSL, the timing at which the voltage monitoring circuit outputs a power-off signal and the system reset circuit 65 reset the system. It is possible to reliably set the difference in timing for outputting the signal within a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop process in response to the power-off signal from the power supply monitoring circuit until the completion of the power supply stop process.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power source for the gaming machine is cut off. The When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of occurrence of the power failure when recovering from the power failure.

  In the configuration shown in FIG. 9, two reset signals (low level signals) are given to the reset terminal of the CPU 56 when the power is turned on, but the reset is reliably released even if the reset signal rises only once. When the CPU is used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The PIO has 4 bits PB0 to PB3 and 1 byte port PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output.

  FIG. 10 is a block diagram showing the internal configuration of the CPU 56 in more detail. The CPU core 501 has a register and performs arithmetic processing according to a program. The clock generator 502 divides a clock signal supplied from the outside and supplies it to each built-in device. The clock generator 502 can output a 1/2 frequency-divided clock as a system clock from the CLKO terminal, and can output a clock signal obtained by dividing the system clock from the IEO / SCLK0 terminal via the output control circuit 511. is there.

  The reset interrupt controller 503 notifies the CPU core 501 of a system reset signal input to the XRST terminal, a non-maskable interrupt request signal input to the XNMI terminal, and the like. The external bus interface 504 is a bus driver that performs direction control and drive control of an address bus, a data bus, and various control signals. The built-in RAM 55 can be backed up and a program is stored in the built-in ROM 54. The address decoder 505 can output four chip select signals XCS0 to 3 via the output control circuit 511. Note that the terminals of the chip select signals XCS0-3 are also used as input / output ports PB0-PB3.

  The memory control circuit 510 generates signals for controlling the built-in ROM 54 and the built-in RAM 55. In addition, the memory control circuit 510 has a built-in register that sets permission to access the built-in RAM 55.

  The PIO 506 is an 8-bit built-in input port PA0 to PA7. When the built-in PIO is not used, for example, the unused port is set to the input mode, and the port is connected to the ground level. The CTC 508 includes two external clock / timer trigger inputs CLK / TRG 2 and 3 and two timer outputs ZC / TO 0 and 1.

  FIG. 11 and FIG. 12 are explanatory diagrams showing assignment of output ports in this embodiment. As shown in FIG. 11, the output port 0 is an output port for a strobe signal (INT signal) of a control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1, and the 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2. The 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. Then, as shown in FIG. 12, 8-bit data of the voice control command sent to the voice control board 70 is output from the output port 4.

  Further, various information output signals from the output port 5 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output. The output port 6 drives a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening / closing plate 2 of the big prize opening, and a solenoid 21A for switching the path in the big prize opening. A signal is output.

  FIG. 13 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 13, the winning ports 24a, 24b, 24b, 19a, 19b, 19b, start port 17, count switch 23, V Detection signals from the winning switch (specific area switch) 22 and the gate switch 12 are input. Also, the winning ball count switch 301A, the full switch 48, the ball break switch 187 detection signal, and the count switch short-circuit signal are input to bits 0 to 3 of the input port 1, respectively.

Next, the operation of the gaming machine will be described.
FIG. 14 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S6).

  The CPU 56 used in this embodiment has the following three types of maskable interrupt (INT) modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Then, it is confirmed whether or not data protection processing (for example, power failure occurrence NMI processing such as addition of parity data) has been performed in the backup RAM area when the power is turned off (step S7). In this embodiment, when an unexpected power failure occurs, processing for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that there is no backup, the CPU 56 executes an initialization process.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. In this example, as shown in FIG. 15, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, there is no backup (OFF). State).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, and therefore an initialization process that is executed at the time of power-on not at the time of power failure recovery is executed.

  If the check result is normal (step S8), the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power is cut off. (Step S9). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC, and the address is restored.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S11). Also, initial value setting processing is performed for setting initial values in predetermined work areas (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.). Further, processing for initializing the sub-boards (lamp control board 35, payout control board 37, voice control board 70, symbol control board 80) is executed (step S13). The process of initializing the sub board is a process of sending an initial setting command, for example.

  Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S14). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited in step S1 of the initial setting process, the interruption is permitted before the initialization process is completed (step S15).

  In this embodiment, the built-in CTC of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, as shown in FIG. 16, the CPU 56 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S12).

  When the execution of the initialization process (steps S11 to S15) is completed, the main process shifts to a loop process in which it is confirmed whether or not a timer interrupt has occurred (step S17). In the loop, display random number update processing (step S16) is also executed.

  When the CPU 56 recognizes that a timer interrupt has occurred in step S17, it executes the game control process of steps S21 to S31. In the game control process, the CPU 56 first inputs the states of the switches such as the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a, 19b, 24a, and 24b via the switch circuit 58, Is determined (switching process: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting a display control command related to the special symbol in a predetermined area of the RAM 55 and sending the display control command (special symbol command control process: step S27). In addition, a display control command related to the normal symbol is set in a predetermined area of the RAM 55, and a process of sending the display control command is performed (normal symbol command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is established (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in accordance with the drive command, thereby bringing the variable winning ball device 15 or the opening / closing plate 20 into an open state or a closed state.

  Then, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection outputs of the switches 17, 23, 19a, 19b, 24a, 24b for detecting a winning at each winning mouth (step S31). ). Specifically, a payout control command is output to the payout control board 37 in response to winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is executed in the main process, but the game control process is performed in the timer interrupt process. May be executed.

  In addition, the main process includes a process for determining whether or not to shift to the game control process, and whether or not the CPU 56 should shift to the game control process by the timer interrupt process based on the timer interrupt generated periodically. Since the flag for determining whether or not is set or the like, all of the game control processing is surely executed. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  As described above, in this embodiment, the interrupt mode 2 is set in the initial setting process for the CPU 56 incorporating the CTC and PIO. Therefore, a periodic timer interrupt process using the built-in CTC can be easily realized. Also, the timer interrupt process can be set at an arbitrary position on the program. In addition, switch detection processing using the built-in PIO can be easily realized by interrupt processing. As a result, it is possible to obtain effects such as a simplified program configuration and a reduced number of program development steps.

  Note that after the setting of CTC and PIO (step S5) is completed, an internal register for determining the frequency of the clock signal output from the IEO / SCLK0 terminal may be set. At that time, the frequency of the clock signal is set to a frequency corresponding to 2 ms which is the start cycle of the game control process. When such setting is performed, a clock signal having a frequency corresponding to the activation period of the game control process is externally output from the CPU 56 from the IEO / SCLK0 terminal. Then, a signal corresponding to the activation cycle of the game control process can be observed outside the CPU 56. Therefore, it becomes easy to simulate a game control process by the CPU 56 and to test an operation state of the CPU 56 outside the gaming machine using such a signal.

  Also, among the output ports 0 to 6 shown in FIGS. 11 and 12, the output ports 0, 1, 2, 3, and 4 are the special symbol command control process (step S25) in the game control process, and the normal symbols. Access is made by command control processing (step S27), prize ball processing (step S31), or the like. The output port 5 is accessed by the information output process (step S29), and the output port 6 is accessed by the special symbol process (step S25) and the normal symbol process (step S26).

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal continues for a predetermined time, it is certainly determined that the switch is turned on, and processing corresponding to the switch on is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an ON state. As shown in FIG. 17, the switch timer is provided by the number N of detection signals. In this embodiment, N = 12. In the RAM, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (from top to bottom shown in FIG. 13).

  FIG. 18 is a flowchart illustrating a processing example of the switch process in step S21 in the game control process. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs data input to the input port 0 (step S71). Next, “8” is set as the number of processes (step S72), and the address of the switch timer for the winning opening switch 24a is set in the pointer (step S73). Then, a switch check processing subroutine is called (step S74).

  FIG. 19 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S81). Further, clear data (00) is set (step S82). Then, the switch timer pointed to by the pointer (the switch timer address is set) is loaded (step S83), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S84). Data of input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 24a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S85), that is, if the detection signal of the winning opening switch 24a is ON, the value of the switch timer is incremented by 1 (step S87). If the value after addition is not 0, the addition value is returned to the switch timer (steps S88 and S89). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0”, that is, if the detection signal of the winning opening switch 24a is in the OFF state, clear data is set in the switch timer (step S86). That is, if the switch is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S90) and subtracts 1 from the number of processes (step S91). If the number of processes is not 0, the process returns to step S82. Then, the processes in steps S82 to S92 are repeated.

  The processes of steps S82 to S92 are repeated for the number of processes, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially checked to determine whether it is on or off. If it is ON, the value of the corresponding switch timer is incremented by one.

  The CPU 56 inputs the data input to the input port 1 in step S75 of the switch process. Next, “4” is set as the processing number (step S76), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S77). Then, a switch check processing subroutine is called (step S78).

  In the switch check processing subroutine, since the above-described processing is executed, the processing of steps S82 to S92 is repeated for the number of processing, that is, four times, and the detection signal of the switch input to the 4 bits of the input port 1 during that time. Then, a check process is sequentially performed to determine whether the state is on or off. If the state is on, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

  20 to 22 are flowcharts showing an example of the prize ball process in step S31 in the game control process. In this embodiment, in the prize ball processing, it is determined whether or not the prize opening switches 19a, 19b, 24a, 24b, the count switch 23 and the start opening switch 17 are turned on, and if they are turned on, a predetermined payout control command is determined. Is sent to the payout control board 37, and it is determined whether or not the full switch 48 and the ball break switch 187 are turned on, and when it is turned on, a predetermined payout control command is issued. For example, control is performed so as to be sent to the terminal.

  In the prize ball process, the CPU 56 sets “0” as the offset of the input determination value table (step S121), and sets “0” as the offset of the address of the switch timer (step S122). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the switch timer address offset “0” designates the switch timer corresponding to the winning port switch 24a. Means. Also, “4” is set as the number of repetitions (step S123). Then, a switch-on check routine is called (step S124).

  The input determination value table is a ROM area in which a determination value for determining that the switch has been turned on when it is detected how many times it is continuously turned on is set for each switch. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 25, the input determination value table includes “2”, “50”, “250”, “30”, “250”, “1” in order from the top, that is, in order from the smallest address value. The judgment value is set. In the switch-on check routine, the judgment value set at the address determined by the head address and the offset value in the input judgment value table is compared with the value of the switch timer determined by the head address and the offset value of the switch timer. If they match, for example, a switch-on flag is set.

  An example of a switch-on check routine is shown in FIG. In the switch-on check routine, the CPU 56 sets the head address of the input determination value table (see FIG. 25) (step S101). Then, an offset is added to the address (step S102), and a switch-on determination value is loaded from the address after the addition (step S103).

  Next, the CPU 56 sets the start address of the switch timer (step S104), adds an offset to the address (step S105), and loads the value of the switch timer from the address after the addition (step S106). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the values of the switch timers corresponding to the switches are loaded.

  Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S107). If they match, a switch-on flag is set (step 108).

  In this case, in the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the winning opening switch 24a matches the switch-on determination value “2” (step S125). When the switch-on flag is set, 10 counters are incremented by 1 (step S126). The switch check-on routine is executed for the number of repetitions initially set (step S127, S128) while the offset of the switch timer address is updated (step S129). For 24a and 24b, the value of the corresponding switch timer is compared with the switch-on determination value “2”. The 10-piece counter is a counter that indicates the number of paying out 10 game balls as prizes.

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S130), and sets “4” as the offset of the switch timer address (step S131). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the switch timer address offset “4” designates the switch timer corresponding to the start port switch 17. Means. Then, a switch-on check routine is called (step S132).

  In the switch-on check routine, if the value of the switch timer corresponding to the start port switch 17 matches the switch-on determination value “2”, the switch-on flag is set (step S133). (Step S134). The 6-counter is a counter that indicates the number of 6 game ball payouts as a prize.

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S135), and sets “5” as the offset of the switch timer address (step S136). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the offset “5” of the switch timer address indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, a switch-on check routine is called (step S137).

  In the switch-on check routine, if the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S138), so 15 counters are incremented by one. (Step S134). The 15 counter is a counter that indicates the number of paying out 15 game balls as prizes.

  Further, the CPU 56 sets “1” as the offset of the input determination value table (step S150), and sets “9” as the offset of the switch timer address (step S151). The offset “1” in the input determination value table means that the second data “50” in the input determination value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the switch timer address offset “9” specifies the switch timer corresponding to the full switch 48. Means. Then, a switch-on check routine is called (step S152).

  In the switch-on check routine, if the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch on determination value “50”, the switch on flag is set (step S153), so the full tank flag is set. (Step S154). Although not explicitly shown in FIG. 21, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

  Further, the CPU 56 sets “2” as the offset of the input determination value table (step S156), and sets “0A (H)” as the offset of the switch timer address (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the switch timer address offset “0A (H)” is designated by the switch timer corresponding to the ball break switch 187. Means that Then, a switch-on check routine is called (step S158).

  In the switch-on check routine, if the value of the switch timer corresponding to the ball-out switch 187 matches the ball-out switch-on determination value “250”, the switch-on flag is set (step S159). It is set (step S160). Although not explicitly shown in FIG. 21, when a switch-off timer corresponding to the ball-out switch 187 is prepared and the value becomes 50, the ball-out flag is reset.

  Then, the CPU 56 confirms whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command is sent to the payout control board 37. If it is not in the payout stop state, it is confirmed whether or not the above-described ball-out state flag or full tank flag is turned on (step S202).

  When any of them changes to the on state, a command transmission control process related to designation of the payout stop state is performed (step S203). In the command transmission control process, after predetermined data is set in the command transmission table for the payout control command, the payout control command sending process is executed. In step S202, when one of the flags is already in the on state and the other flag is in the on state, the command transmission control process (step S203) is not performed.

  If it is in the payout stop state, it is checked whether both the ball-out state flag and the full tank flag are turned off (step S204). When both are turned off, command transmission control processing relating to designation of canceling the payout stop is performed (step S205).

  Next, the CPU 56 sets a payout control command related to the number of winning balls according to the winning in the command transmission table, and performs control to send out a payout control command according to the set content. First, the value of the 15 counter is checked (step S221). As described above, the 15 counter is counted up when the game ball wins the big winning opening and the count switch 23 is turned on. If the value of the 15 counter is not 0, command transmission control processing relating to the 15 winning ball number instructions is performed (step S222). In the command transmission control process, after predetermined data is set in the command transmission table for the payout control command, the payout control command sending process is executed. Further, the value of the 15 counter is decremented by 1 (step S223). Further, 15 is added to the stored value of the total winning ball number storage buffer (step S224).

  The total winning ball number storage buffer is a buffer for storing a cumulative value of the number of winning balls instructed to the payout control means (however, subtracted when paying out), and is formed in the backup RAM.

  If the value of the 15 counter is 0, the value of the 10 counter is checked (step S225). As described above, the 10 counter is counted up when a game ball wins a winning opening and the winning opening switches 19a, 19b, 24a, 24b are turned on. If the value of the 10 counter is not 0, command transmission control processing relating to the 10 winning ball number instructions is performed (step S226). Also, the value of the 10 counter is decremented by 1 (step S227). Further, 10 is added to the stored value of the total winning ball number storage buffer (step S228).

  If the value of the 10 counter is 0, the value of the 6 counter is checked (step S231). As described above, the six counter is counted up when the game ball wins the start winning opening and the start opening switch 17 is turned on. If the value of the six counter is not 0, command transmission control processing relating to the six prize ball number instructions is performed (step S232). Further, the value of the six counter is decremented by -1 (step S233). Further, 6 is added to the stored value of the total winning ball number storage buffer (step S234).

  As described above, when the payout control command for instructing the number of prize balls is output from the game control means to the payout control board 37, the command transmission table is set and then set in the command transmission table. A payout control command is sent to the payout control board 37. Then, when a payout control command for instructing the number of prize balls is sent, the prize ball payout flag is turned on (step S235). When the prize ball paying flag is on (step S236), the number of prize balls actually paid out from the ball payout device 97 is monitored and the value stored in the total prize ball number storage buffer is subtracted. A number subtraction process is performed (step S237). When the prize ball paying flag changes from on to off, a lamp control command for instructing lighting of the prize ball lamp 51 is sent to the lamp control board 35.

  FIG. 24 is a flowchart illustrating an example of the winning ball number subtraction process. In the winning ball number subtraction process, the CPU 56 first loads the stored value of the total winning ball number storage buffer (step S241). Then, it is confirmed whether or not the stored value is 0 (step S242). If 0, the process ends.

  If it is not 0, the switch timer for the prize ball count switch is loaded (step S243), and the load value is compared with the ON determination value (in this case, “2”) (step S244). If they match (step S245), it is assumed that the prize ball count switch 301A has been turned on, that is, one game ball has been paid out from the ball payout device 97, and the stored value in the total prize ball number storage buffer is set. 1 is subtracted (step S246).

  Also, the value of the prize ball information counter is incremented by 1 (step S247). If the value of the prize ball information counter is 10 or more (step S248), the value of the prize ball information output counter is incremented by 1 (step S249), and the value of the prize ball information counter is incremented by -10 (step S250). The value of the prize ball information output counter is referred to in the information output process (step S29) in the main process shown in FIG. 14, and if the value is 1 or more, the prize ball signal (bit 7 of the output port 5). : See FIG. 12), one pulse is output. Therefore, in this embodiment, each time ten game balls are paid out as prize balls, one prize ball signal is output to the outside of the gaming machine.

  When the value stored in the total prize ball number storage buffer becomes 0 (step S251), the prize ball paying-in flag is cleared (step S252), and a lamp control command is issued to notify that there is no prize ball remaining number. After command data indicating that the prize ball lamp 51 is extinguished is set in the command transmission table (step S253), a lamp control command sending process is executed (step S254).

  Next, a method for sending a control command from the game control means to each electric component control means will be described. FIG. 26 is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to another electrical component control board. In this embodiment, the control command has a 2-byte configuration, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”. Note that the command form shown in FIG. 26 is an example, and other command forms may be used.

  FIG. 27 is a timing chart showing the relationship between an 8-bit control signal and an INT signal (strobe signal) that constitute a control command from the game control board to each of the other electrical component control boards. As shown in FIG. 27, when a predetermined period elapses after MODE or EXT data is output to the output port, the CPU 56 turns on an INT signal that is a signal indicating data output. Further, when a predetermined period has elapsed from that point, the INT signal is turned off.

  When a control command is to be output from the game control means to each electrical component control board such as a payout control board, the command transmission table is set. FIG. 28A is an explanatory diagram showing a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

  Although the EXT data itself may be set in the area of the command data 2, the command data 2 may be set with data for designating the address of the table storing the EXT data. . In this embodiment, if bit 7 (work area reference bit) of command data 2 is 0, it indicates that EXT data itself is set in command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1, it indicates that the other 7 bits are an offset for designating the address of the table storing the EXT data. In this embodiment, a command transmission table is prepared for each control command.

  FIG. 28 (B) is an explanatory diagram showing a configuration example of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is “1”, it indicates that a payout control command should be sent. Therefore, for example, in award ball processing, the CPU 56 sets “01 (H)” in the INT data of the command transmission table for payout control commands when sending out payout control commands.

  Bits 1, 2, and 3 of the INT data are bits indicating whether or not a display control command, a lamp control command, and a voice control command should be sent, respectively. When the CPU 56 should send these commands, , INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MODE data and EXT data are set to the command data 1 and the command data 2.

  When a control command for each electric component control board is output to the corresponding output port (output ports 1 to 4), any one of bits 0 to 3 of output port 0 is turned on for a predetermined period. However, the bit arrangement in the INT data and the bit arrangement in the output port 0 correspond to each other. Therefore, when a command is sent to each electrical component control board, the INT signal can be easily output based on the INT data set in the command transmission table.

  FIGS. 29 to 31 are flowcharts showing a processing example of the non-maskable interrupt processing (power supply stop time processing) executed in response to the power-off signal from the power supply board 910.

  In the power supply stop process, the CPU 56 saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Further, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S454 to S458). When the power is restored, the register contents are restored based on the saved contents, and the interrupt permission / prohibition state is internally set according to the contents of the parity flag.

  Next, in this embodiment, the detection signal of the prize ball count switch 301A is checked for a predetermined period. When the prize ball count switch 301A is turned on, the content of the total prize ball number buffer is reduced by one.

  In this embodiment, a predetermined period measuring counter is used to measure the predetermined period. The value of the counter for measuring the predetermined period is decremented by 1 every time a loop of the switch detection process (a loop starting from S461 and returning to S461) described below is executed once from the initial value m, and the value becomes 0. It is assumed that the predetermined period has ended. Since there is an exception in the detection processing loop, almost constant processing is performed, and therefore, m times the time required for one round of the loop corresponds to a predetermined period.

  In order to measure the predetermined period, a built-in timer of the CPU 56 may be used. That is, a predetermined value (corresponding to a predetermined period) is set in the built-in timer at the start of the switch detection process. Each time the switch detection processing loop is executed once, the count value of the built-in timer is checked. When the count value reaches 0, it is assumed that the predetermined period has ended. An interrupt by the internal timer can be used to detect that the value of the internal timer has reached 0, but at this stage, the control content (such as each value stored in the RAM) should not be changed. A program configuration is preferred in which the count value of the built-in timer is read and checked instead of using a program.

  The predetermined period is set to be equal to or longer than the time from when the game ball falls from the ball dispensing device 97 until it reaches the prize ball count switch 301A. If the distance from the ball payout device 97 to the prize ball count switch 301A is L, the drop time t during that time is t = √ (2L / g) (g: gravitational acceleration). Is set.

  At least for a predetermined period during which the switch detection process is executed, the prize ball count switch 301A must be in a state where it can detect a game ball. Therefore, in this embodiment, as shown in FIG. 8, a capacitor 923 serving as a relatively large capacity auxiliary drive power supply is connected to the input side of the converter IC 922 in the power supply substrate 910. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained in a range in which the switch can be driven for a certain period, and the winning ball count switch 301A becomes operable. The capacitance of the capacitor is determined so that the period is equal to or longer than the predetermined period.

  Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 922, the operation can be performed for a relatively long period even when the power supply is stopped.

  In step S461, an initial value n corresponding to a time of 2 ms is set in the 2 ms measurement counter. Then, until the value of the 2 ms measurement counter becomes 0 (step S462), the value of the 2 ms measurement counter is decremented by 1 (step S463).

  When the value of the 2 ms measurement counter becomes 0, the input of the detection signal of the prize ball count switch 301A is checked. That is, processing similar to the switch processing and switch check processing shown in FIGS. 18 and 19 is performed. Specifically, the data input to the input port 1 is input (step S464). Next, clear data (00) is set (step S465). Further, port input data, in this case, input data from the input port 1 is set as a “comparison value” (step S466). Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S467).

  Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S469). Data of the input port 1 is set as the comparison value. In this case, the detection signal of the winning ball count switch 301A is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S470), that is, if the detection signal of the prize ball count switch 301A is ON, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is “0”, that is, if the detection signal of the prize ball count switch 301A is OFF, clear data is set in the switch timer (step S472). That is, if the switch is off, the value of the switch timer returns to zero.

  When the value of the switch timer becomes 2 (step S473), 1 is subtracted from the value stored in the total prize ball number storage buffer (step S474), and the value of the prize ball information counter is incremented by 1 (step S475). . If the value of the prize ball information counter is 10 or more (step S476), the value of the prize ball information output counter is incremented by 1 (step S477), and the value of the prize ball information counter is incremented by -10 (step S478).

  Next, the value of the counter for measuring the predetermined period is decremented by -1 (step S479). If the value is not 0, the process returns to step S461.

  If the prize ball count switch 301A is turned on within the predetermined period by the above processing, the value of the total prize ball number storage buffer is decremented by one. Since the processing for saving the contents of the backup RAM is performed after such switch detection processing, the total winning ball number storage buffer is always decremented by 1 for winning balls that have been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. In the above switch detection process, a timer process using a detection period counter is performed. That is, the detection output of the prize ball count switch 301A is checked every 2 ms, and it is considered that the prize ball count switch 301A is reliably turned on when it is detected to be turned on twice in succession. Therefore, erroneous switch-on detection is prevented. In addition, in the switch detection process, the calculation of a prize ball information output number counter for outputting prize ball information to the outside of the gaming machine is also performed, so the prize ball information output to the outside and the actual number of paid-out prize balls are different. There is no such thing.

  In this embodiment, the switch detection process of only the winning ball count switch 301A is performed, but the same switch detection process is also performed for the V winning switch 22 and the count switch related to the start winning opening switch and the big winning opening. May be performed. The same switch detection process may be performed for other winnings. When such an on-check is also performed, even if a power failure occurs immediately after a game ball wins a winning opening, the winning is reliably detected and reflected in the saved game state.

  When the predetermined period has elapsed (step S480), that is, when the value of the counter for measuring the predetermined period becomes 0, the backup specified value ("55H" in this example) is stored in the backup flag (step S481). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S482 to S491). That is, first, the clear data (00) is set in the checksum data area (step S482), and the checksum calculation start address is set in the pointer (step S483). Also, the number of checksum calculations is set (step S484).

  Then, an exclusive OR between the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S485). The calculation result is stored in the checksum data area (step S486), the pointer value is incremented by 1 (step S487), and the checksum calculation count value is decremented by 1 (step S488). The processing of steps S485 to S488 is repeated until the value of the checksum calculation count becomes 0 (step S489).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S490). Then, the inverted data is stored in the checksum data area (step S491). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S492). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the clear data (00) in an appropriate register (step S493), and sets the number of processes (in this example, “7”) in another register (step S494). Further, the address of the output port 0 is set in the IO pointer (step S495). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S496), the value of the IO pointer is incremented by 1 (step S497), and the value of the processing number is decremented by 1 (step S498). The processes in steps S496 to S498 are repeated until the value of the number of processes becomes zero. As a result, clear data is set in all the output ports 0 to 6 (see FIGS. 11 and 12). As shown in FIGS. 11 and 12, in this example, “1” is in the on state and “00”, which is the clear data, is set in each output port, so that all the output ports are in the off state.

  Therefore, after the processing for saving the game state (in this example, checksum generation and RAM access prevention) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the gaming state.

  Since each output port is turned off immediately after the processing for saving the gaming state is executed, it is reliably prevented that a situation that does not match the saved gaming state occurs. When the processes shown in FIGS. 29 to 31 are executed, the power supply to the gaming machine is stopped, so that the voltage applied to the electrical component decreases. When the applied voltage falls below the drivable voltage, the driving of the electrical component is stopped. Therefore, when the power supply to the gaming machine is stopped, the driving of the electrical components is stopped although there is a short delay.

  However, if the clear process for the output port as in this embodiment is not performed, the variable winning ball device 15 is further added while the game control means waits for the power supply to stop after the game state is saved. You may win a prize. In such a case, when the power supply is resumed, the saved gaming state is restored, so that the starting winning memory number at the time of saving is displayed on the starting memory display 18. Then, from the viewpoint of the player, it seems that the stored value of the start winning prize has been reduced, which may cause trouble. However, in this embodiment, there is no possibility of such a trouble occurring.

  In addition, after the game state is stored, there may be a case where a winning in a big winning opening as a variable winning ball apparatus occurs. In such a case, there is a possibility that a trouble may occur due to a difference between the number of winnings recognized by the player and the number of winnings displayed on the display unit based on the stored gaming state when power supply is restored. However, in this embodiment, there is no possibility of such a trouble occurring.

  When the clear process for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  In this embodiment, the power supply stop process is executed according to the NMI. However, the power supply stop signal is connected to the maskable terminal of the CPU 56 and the power supply stop process is executed by the maskable interrupt process. May be. Alternatively, a power-off signal may be input to the input port and the power supply stop process may be executed according to the input port check result.

  Further, in this embodiment, the register saving process is performed at the beginning of the process activated in response to the power-off signal, but when the register is not used in the switch detection process, after executing the switch detection process, That is, the register saving process can be performed before the backup flag setting and the checksum calculation process. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Further, even when several registers are used in the switch detection process, the register storage process can be performed before the backup flag setting process and the checksum calculation process for the unused registers.

  The output port clear process may be performed before the switch detection process is executed (before step S460). During execution of the power supply stop process, the CPU 56 and switches are driven by the charging power of the capacitor. When the output port clear process is performed before the switch detection process is executed, even if the big prize opening, variable prize winning device, etc. are configured to be driven by electrical components such as solenoids, they are driven. In other words, the charging power of the capacitor can be effectively used for the power supply stop process.

  However, in the case where the V winning switch 22 is detected after it is detected that the power is cut off, the output port of the solenoid 21 (which operates the member for guiding the large winning opening to the V winning switch) Clear after switch detection processing. In such a case, when a power failure occurs in a state where the V winning, which is a condition for generating the continuation right, is not generated, the game ball that has entered the big winning opening just before the power failure occurs is guided to the V winning switch 22 side. Can do. Therefore, it is possible to prevent the lapse of the unjust right to continue. In this case, the predetermined period is a period equal to or longer than the time required for the game ball that has won the grand prize opening to reach the V winning switch 22. When a latch type solenoid is used, the output port clear process is not necessary.

  In addition, even when the big prize opening is closed by clearing the output port, there is a possibility that there is a game ball in the big prize opening. Therefore, in the switch detection process executed in response to the power-off signal, the count switch 23 is also detected It is desirable to do. The output port clearing process may be performed before the switch detection process, and the above exceptional process is not limited to the first type pachinko gaming machine but the second type pachinko gaming machine or the third type. The same applies to seed pachinko machines.

  FIG. 32 is a flowchart showing a part of the non-maskable interrupt process (process when power supply is stopped) of the game control means according to another embodiment of the present invention. The flowchart shown in FIG. 32 is executed following the processing of steps S451 to S492 shown in FIGS. That is, in this embodiment, after the RAM access prohibited state is set (step S492), the head address of the clear data table is set in the pointer (step S501), and then the data clear process is executed (step S501). S502), a standby state for waiting for system reset is entered. A predetermined register is used as a pointer.

  FIG. 33 is an explanatory diagram of a configuration example of the clear data table. In the example shown in FIG. 33, in the clear data table, the processing number data (in this example, “7”), the output port 0 address, the clear data to be set to the output port 0,. 6 address and clear data to be set to the output port 6 are set. The output port address and the clear data are set in order from the smallest output port address.

  FIG. 34 is a flowchart showing the data clear process in step S502. In the data clear process, the CPU 56 extracts the processing number data from the address pointed to by the pointer (step S511). Then, the pointer value is increased by 1 (step S512). Next, address data (output port address) is extracted from the address pointed to by the pointer (step S513). Further, the value of the pointer is incremented by 1 (step S514).

  Then, clear data is extracted from the address indicated by the pointer (step S515), and the data is set to the address extracted in step S83 (step S516). Next, 1 is subtracted from the value of the processing number (step S517), and when the processing number becomes 0, the data clear processing is terminated (step S518). If the number of processes is not 0, the process returns to step S511.

  Even if the clear data table is used, the clear signal output process can be performed quickly, and the occurrence of inconsistency between the control state stored when the power supply to the gaming machine is stopped and the actual control state is more effectively performed. Can be prevented. When a clear data table is used, the address data and the clear data need not be arranged in the order of addresses in the table, and the degree of freedom of the table configuration is increased. For example, when it is desired not to clear a test signal in a gaming machine that uses a test signal or the like, the clearing process of the test signal can be easily excluded by excluding data relating to the output port relating to the test signal from the table. Further, when the output port is increased or decreased or changed, it is only necessary to change the contents of the table, and there is no need to change the program.

  FIG. 35 is a timing chart showing an example of how detection signal input processing from the payout detection means is executed. In this embodiment, the power-off signal is input to the main board 31 and the payout control board 37 and input to the NMI terminals of the CPU 56 of the main board 31 and the payout control CPU 371. The CPU 56 of the main board 31 executes the above-described power supply stop process by the non-maskable interrupt process.

  As shown in FIG. 35, when the prize ball payout is executed around the time when the power-off signal is turned on (in this example, the change from the high level to the low level), the detection signal input process from the payout detecting means is executed. Within a predetermined period, the prize ball count switch 301A is turned on. Therefore, the ball payout executed when the power-off signal is turned on can also be reflected in the total winning ball number buffer when the power supply stop process is executed.

  When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the reset IC 651 mounted on the main board 31 becomes low level as shown in FIG. Reset state. Note that the CPU 56 has completed the power supply stop process before entering the system reset state.

  When the voltage value of VSL is further decreased to be lower than a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot be operated on each substrate. However, in the main board 31, the power supply stop process is executed, and the CPU 56 is in a system reset state.

  As will be described later, the payout control CPU 371 on the payout control board 37 also enters the system reset state after performing the power supply stop process.

  The pachinko gaming machine 1 according to the above embodiment can give a predetermined game value to a player when a special symbol stop symbol variably displayed on the variable display unit 9 based on a start winning combination is a combination of a predetermined symbol. The first type pachinko gaming machine is, but if there is a prize for a predetermined electric combination that is released when the symbol of the symbol that is variably displayed based on the start winning combination becomes a combination of the predetermined symbol, the predetermined right is given The present invention can be applied even to a third type pachinko game machine that is generated or continued.

  FIG. 36 is an explanatory diagram showing an example of the game area 7 of the third type pachinko gaming machine. In this example, when there is a winning at the start winning opening 30A, the variable display unit 9 starts variable display of symbols. Then, when the symbol stop symbol becomes a combination of predetermined symbols, the right generating electric accessory 30B is opened for a predetermined period so that it becomes easy to win. In this state, when a right is generated by winning a prize in the right-generating electric accessory 30B, the game ball that has entered the rotor 30C driven by a motor or the like is led to the start opening switch of the big winning opening 30D, and the start opening switch If it is detected, the special winning opening 30D is opened. In addition, each switch which detects the game ball which won the start winning opening 30A, the electric power generation tool 30B for rights generation, the rotor 30C, and the big winning opening 30D is provided.

  In such a third type pachinko gaming machine, even when it is configured to save the control state in response to the occurrence of a power failure or the like, first, for example, in the process activated in response to the power-off signal, the output port is cleared. In the process, the motor or the like that drives the rotor 30C is stopped. Since the game ball guided to the start port switch (the switch for detecting the game ball entering the rotor 30C) by the rotor 30C is subjected to the switch detection process for a predetermined period even after it is detected that the power is cut off. It can be detected by the start switch. Therefore, when the power supply is restored, it is guaranteed that the operating condition of the special winning opening 30D is established. In this case, the predetermined period is a period longer than the time until the game ball moves from the part holding the game ball of the rotor 30C to the start port switch. In addition, even for the switch provided in the right-generating electric accessory 30B, even if it is detected that the power supply is cut off, the detection process is executed for a predetermined period, thereby preventing unauthorized loss of the right. .

  When all switches are detected in the switch detection process in the process activated in response to the occurrence of the power-off signal, the switch process shown in FIG. 18 may be called during a predetermined period. . And when comprised in that way, the process when a switch timer value reaches an ON determination value is also performed. For example, when the switch timer value of the winning ball switch reaches the ON determination value, a process for setting the number of winning balls is performed (for example, increment of 15 counters), or the switch timer value of the V winning switch 22 is changed to the ON determination value. When it reaches, processing such as setting a flag indicating that there has been a V prize is performed.

Hereinafter, the gaming state restoration process will be described.
FIG. 37 is a flowchart showing an example of the gaming state recovery process shown in step S9 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (step S91). Then, based on the data stored in the backup RAM, the gaming state at the time of power failure is confirmed and returned. That is, based on the data stored in the backup RAM, the solenoid 16 and the solenoid 21 are driven via the solenoid circuit 59 to restore the open / closed state of the start winning opening 14 and the open / close plate 20 (steps S92 and S93). . In addition, according to the value of the special symbol process flag and the normal symbol process flag stored even when the power is turned off, the control commands corresponding to the progress status of the special symbol process processing and the progress status of the normal symbol process processing when the power is turned off, This is sent to the symbol control board 80, the lamp control board 35, and the voice control board 70 (step S94).

  As described above, in the game state restoration process, the state of various electrical components is restored according to the restored internal state, and control is performed on the symbol control board 80, the lamp control board 35, and the voice control board 70. A control command for returning the state to the state at the time of power-off (control command for causing a control state at the time of power-off) is sent out. Such control commands are generally one or more control commands that were last sent prior to a power failure.

  In this embodiment, when the gaming state is restored to the power-off state, the CPU 56 restores the interrupt permission / prohibition state at the previous power-off, so that the value of the parity flag stored in the backup RAM is restored. Is confirmed (step S95). If the parity flag is off, interrupt permission is set (step S96). However, if the parity flag is in the on state, the gaming state restoration process is terminated as it is (while keeping the interrupt prohibited state set in step S1). The fact that the parity flag is in the on state means that the interrupt was prohibited at the previous power-off as shown in step S452 in FIG. Therefore, when the parity flag is in the on state, no interrupt is permitted.

  Next, as an example of the case where the data storage process and the recovery process are performed in the electrical component control means other than the game control means, the case where the data storage and recovery is performed in the payout control means will be described.

  FIG. 38 is a block diagram showing an example of the configuration around the payout control CPU 371. As shown in FIG. 38, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. Yes. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the non-maskable interrupt process.

  The INT signal from the main board 31 is connected to the CLK / TRG2 terminal of the payout control CPU 371. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. When the register value becomes 0, an interrupt occurs. Therefore, if the initial value of the timer counter register CLK / TRG2 is set to “1”, an interrupt is generated according to the input of the INT signal.

  Although the system reset circuit 975 is also mounted on the payout control board 37, in this embodiment, the reset IC 976 in the system reset circuit 975 outputs an output to the external capacitor for a predetermined time determined by the capacity when the power is turned on. The output is set to a low level and the output is set to a high level when a predetermined time has elapsed. Further, the reset IC 976 monitors the power supply voltage of VSL, and when the voltage value becomes a predetermined value (for example, +9 V) or less, the reset IC 976 sets the output to a low level. Therefore, when the power is turned off, the payout control CPU 371 is system reset by the signal from the reset IC 976 becoming low level.

  The predetermined value for the reset IC 976 to detect power-off is lower than the normal voltage, but is a voltage that allows the payout control CPU 371 to operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage required by the payout control CPU 371 (in this example, +5 V), the monitoring range for the voltage required by the payout control CPU 371 is set. Can be spread. Therefore, more precise monitoring can be performed.

  While power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supplied from the power supply board to the backup terminal, and the power to the gaming machine is cut off. The contents are saved. When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to return to the payout control state at the time of the power failure when recovering from the power failure.

  In the configuration shown in FIG. 38, the system reset circuit 975 outputs a low level during a period determined by the capacitance of the capacitor when power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, as in the case of the main board 31 shown in FIG. 9, a circuit configuration that generates a plurality of reset release timings may be used.

  FIG. 39 is an explanatory diagram showing assignment of output ports in this embodiment. As shown in FIG. 39, the output port C (address 00H) is an output port for a drive signal output to the payout motor 289. The output port D (address 01H) is an output port for a display control signal output to the error display LED 374 which is a 7 segment LED. The output port E (address 02H) is an output port for outputting a drive signal output to the sorting solenoid 310 and an EXS signal and a PRDY signal for the card unit 50.

  FIG. 40 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 40, the input port A (address 06H) is an input port for taking in an 8-bit payout control signal of the payout control command sent from the main board 31. In addition, detection signals from the winning ball count switch 301A, the ball lending count switch 301B, and the motor position sensor are input to bits 0 to 2 of the input port B (address 07H), respectively. Bits 3 to 5 are supplied with a BRDY signal, a BRQ signal, and a VL signal from the card unit 50.

  FIG. 41 is a flowchart showing the main processing of the payout control CPU 371. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a timer interrupt flag is set. When it is detected in the main process that the timer interrupt flag is set, a payout control process is executed. That is, in the timer interrupt process, settings for executing a payout control process, which is an example of an electrical component control process, are made.

  Further, another channel (channel 2 in this embodiment) of the built-in CTC is used as an interrupt generation channel for receiving a payout control command from the game control means, and this channel is used in the counter mode. Used in. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to the counter mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set.

  The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Further, it is possible to set an interrupt processing start address corresponding to the interrupt vector transmitted by the CTC.

  The interrupt based on the count-up of the CTC channel 2 (CH2) is an interrupt that occurs when the value of the timer counter register CLK / TRG2 described above becomes “0”. Therefore, for example, in step S705, the initial value “1” is set in the timer counter register CLK / TRG2 as the specific register. An interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Used as an interrupt. Specifically, the register value of CH3 is subtracted at 1/256 period of the system clock. In step S705, the CH3 register is set to a value corresponding to 2 ms as an initial value.

  Interrupts based on CTC CH2 count-up have a higher priority than interrupts based on CH3 count-up. Therefore, when the count-up occurs simultaneously, the interrupt based on the CH2 count-up, that is, the interrupt that triggers the execution of the command reception interrupt process is given priority.

  Then, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S707). That is, for example, similarly to the processing of the CPU 56 of the main board 31, whether or not backup data exists is confirmed by whether or not the backup flag that is set when the power is turned off is set. If the backup flag is set, it is determined that there is backup data.

  After confirming that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area. In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, and therefore an initialization process that is executed at the time of power-on not at the time of power failure recovery is executed.

  If the check result is normal (step S708), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power is turned off (step S709). Then, it returns to the address indicated by the PC (program counter) stored in the backup RAM area.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated every 2 ms (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713).

  In this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, as shown in FIG. 42, the payout control CPU 371 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S721). In FIG. 42, it is also clearly indicated that the interrupt is permitted (step S720). In the 2 ms timer interrupt process, the interrupt permission state is first set. In other words, since the interrupt is permitted during the 2 ms timer interrupt process, the payout control command receiving process based on the input of the INT signal can be preferentially executed.

  The payout control CPU 371 executes a payout control process after step S751 when detecting that the timer interrupt flag is set in step S724. With the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the payout control process is executed in the main process, but the payout control process may be executed in the timer interrupt process.

  In the payout control process, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch process: Step S751).

  Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor that detects the rotation speed of the payout motor 289) and determining the state of the sensor (input determination processing). : Step S752). The payout control CPU 371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S753).

  Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). Further, a prepaid card unit control process is performed (step S755).

  Next, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756). At this time, the payout control CPU 371 sets the ball sorting member 311 to the ball lending side by the sorting solenoid 310.

  Further, the payout control CPU 371 performs prize ball control processing for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball sorting member 311 to the prize ball side by the sorting solenoid 310. Then, a drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of rotations is performed. (Step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control them. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759).

  The output port C is accessed in the payout motor control process (step S758) in the payout control process. The output port D is accessed by error processing (step S759) in the payout control processing. The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

  FIG. 43 is an explanatory diagram showing an example of use of the RAM built in the payout control CPU 371. In this example, a total number storage (for example, 2 bytes) and a lending ball number storage are formed in the backup RAM area. The total number storage stores the total number of prize balls paid out instructed from the main board 31 side. The rented ball number storage stores the number of balls that have not been paid out.

  Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means, for example, in the prize ball control process (step S757), the content is increased in the total number memory by the indicated number. . In addition, in the ball lending control process (step S756), every time a ball lending request signal is received from the card unit 50, the content is increased in the lending ball number storage by the number of one unit (for example, 25). Further, the payout control CPU 371 reduces the value of the total number memory by 1 when the prize ball count switch 301A detects one prize ball payout in the prize ball control process, and one ball rental count switch 301B in the ball rental control process. When the lending ball payout is detected, the value of the lending ball number storage is reduced by one.

  Therefore, the number of unpaid prize balls and the number of rented balls are stored in a backup RAM area capable of holding the contents for a predetermined period. Therefore, even if an unexpected power failure such as a power failure occurs, the winning ball processing and the ball lending processing stored in the backup RAM area can be continued if the power is restored within a predetermined period. Therefore, the disadvantage given to the player can be reduced.

  44 to 46 are flowcharts showing a processing example of the non-maskable interrupt processing executed in response to the power-off signal from the power supply board 910. FIG. In this example, the power supply stop process is executed according to the NMI, but the power cut signal is connected to the maskable terminal of the payout control CPU 371 and the power supply stop process is executed by the maskable interrupt process. Also good. Alternatively, a power-off signal may be input to the input port and the power supply stop process may be executed according to the input port check result.

  In the non-maskable interrupt process, the payout control CPU 371 saves the AF register in a predetermined backup RAM area (step S801). Further, the interrupt flag is copied to the parity flag (step S802). The parity flag is formed in the backup RAM area. Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S804 to S808). When the power is restored, the register contents are restored based on the saved contents, and the interrupt permission / prohibition state is internally set according to the contents of the parity flag.

  Next, the drive signal output to the dispensing motor 289 is turned off (step S761). Accordingly, the driving of the ball dispensing device 97 is stopped. Thereafter, in this embodiment, the detection signals of the prize ball count switch 301A (corresponding to the prize game medium detection means) and the ball rental count switch 301B (corresponding to the rental game medium detection means) as the payout detection means are checked for a predetermined period. To do. Then, when the prize ball count switch 301A is turned on, the content of the total number memory is reduced by one. Further, when the ball lending count switch 301B is turned on, the content of the lending ball number storage is reduced by one.

  In this embodiment, a predetermined period measuring counter is used to measure the predetermined period. The value of the counter for measuring the predetermined period is decremented by 1 every time a switch detection processing loop (a loop starting from S763 and returning to S763) described below is executed once from the initial value m. It is assumed that the predetermined period has ended. Since there is an exception in the detection processing loop, almost constant processing is performed, and therefore, m times the time required for one round of the loop corresponds to a predetermined period.

  In order to measure the predetermined period, an internal timer of the payout control CPU 371 may be used. That is, a predetermined value (corresponding to a predetermined period) is set in the built-in timer at the start of the switch detection process. Each time the switch detection processing loop is executed once, the count value of the built-in timer is checked. When the count value reaches 0, it is assumed that the predetermined period has ended. An interrupt by the internal timer can be used to detect that the value of the internal timer has reached 0, but at this stage, the control content (such as each value stored in the RAM) should not be changed. A program configuration is preferred in which the count value of the built-in timer is read and checked instead of using a program. Further, the predetermined period is set to be equal to or longer than the time from when the game ball falls from the ball dispensing device 97 until it reaches the prize ball count switch 301A or the ball lending count switch 301B.

  At least during a predetermined period in which the switch detection process is executed, the prize ball count switch 301A and the ball lending count switch 301B must be in a state in which a game ball can be detected. Therefore, in this embodiment, as shown in FIG. 8, a capacitor 923 serving as a relatively large capacity auxiliary drive power supply is connected to the input side of the converter IC 922 in the power supply substrate 910. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained in a range in which the switch can be driven for a certain period, and the winning ball count switch 301A and the ball lending count switch 301B can be operated. The capacitance of the capacitor is determined so that the period is equal to or longer than the predetermined period.

  Since the input port and the payout control CPU 371 are also driven by the + 5V power source created by the converter IC 922, they can operate for a relatively long period even when the power supply is stopped.

  Furthermore, in this embodiment, the sorting solenoid 310 is used to switch between the award ball path and the rental ball path. Therefore, the capacity of the capacitor 923 shown in FIG. 8 is such that the sorting solenoid 310 can be driven at least for the predetermined period. The capacitor 923 is connected in parallel with the power line of the VSL, but the game control means turns off the drive signal of other solenoids (for opening / closing the big prize opening etc.) according to the power-off signal. After the power-off signal is generated, the capacitor 923 only needs to drive only the sorting solenoid 310 among the solenoids.

  Note that the capacitor 923 used in this embodiment is an example of an auxiliary driving power supply, but another auxiliary driving power supply may be used. At least during the above-mentioned predetermined period, auxiliary driving of other modes is possible as long as it can drive the payout control means such as the prize ball count switch 301A, the ball lending count switch 301B, the sorting solenoid 310, and the CPU 371 for payout control. A power supply can be used.

  In the detection signal input process (switch detection process) from the payout detection means, the payout control CPU 371 first sets a value m corresponding to the predetermined period in the predetermined period measurement counter (step S762). Then, the payout control CPU 371 decrements the value of the predetermined period measurement counter by 1 (step S763), and confirms the value of the predetermined period measurement counter (step S764). If the value is 0, the switch detection process is terminated, and the process proceeds to a power supply stop process, which is a process for saving the control state.

  If the value of the counter for measuring the predetermined period is not 0, it is confirmed whether or not the prize ball count switch is on (step S765). If it is ON, the value of the detection period counter is decremented by 1 (step S766), and then it is confirmed whether or not the value of the detection period counter becomes 0 (step S767). If it is 0, the detection signal of the prize ball count switch 301A is confirmed via the input port (step S768), and if the on state is indicated, it is determined that the prize ball count switch 301A is surely turned on. The stored value is decreased by 1 (step S769).

  If it is confirmed in step S765 that the prize ball count switch is not on, the detection signal of the prize ball count switch 301A is confirmed via the input port (step S770). An intermediate flag is set (step S771), and an initial value n is set in the detection period counter (step S772).

  If the prize ball count switch 301A is turned on within the predetermined period by the above processing, the value of the total number storage is decremented by one. Since the process for saving the contents of the backup RAM is performed after such a switch detection process, the total number storage is always reduced by -1 for a prize ball that has been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. In the above switch detection process, a timer process using a detection period counter is performed. In other words, once it is detected that the prize ball count switch 301A is turned on, the switch is not considered to be switched on unless a predetermined time (n times the processing time in the loop from S763 to S767 and back to S763) has elapsed. . Therefore, erroneous switch-on detection is prevented.

  Note that a timer process for preventing erroneous detection is also performed in the normal switch process (step S751 in FIG. 41). Therefore, such normal switch processing may be called. Here, the timer process using the counter for the detection period is performed, but the timer in the switch detection process using the CPU built-in timer is the same as in the case of measuring the predetermined period. Processing may be realized.

  When the winning ball count switch is not on and the ON state of the winning ball count switch 301A cannot be detected, a switch detection process is performed for the ball lending count switch 301B. That is, the payout control CPU 371 checks whether or not the ball lending count switch is on (step S775). If it is ON, the value of the detection period counter is decremented by 1 (step S776), and then it is confirmed whether or not the value of the detection period counter is 0 (step S777). If it is 0, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S778), and if the on state is indicated, it is determined that the ball lending count switch 301B has been turned on, and the lending ball The number storage value is decreased by 1 (step S779).

  If it is confirmed in step S775 that the ball lending count switch is not on, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S780). If the on-state is indicated, the ball lending count switch is turned on. An intermediate flag is set (step S781), and an initial value n is set in the detection period counter (step S782).

  If the ball lending count switch 301B is turned on within the predetermined period by the above processing, the value of the lending ball number storage is decremented by 1. Since the processing for saving the contents of the backup RAM is performed after such switch detection processing, the lending ball number storage is always decremented by 1 for the lending balls that have been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. In the above switch detection process, a timer process using a detection period counter is performed. That is, if the ball lending count switch 301B is not turned on for a predetermined time or more, it is not considered to be switched on. Therefore, erroneous switch-on detection is prevented.

  When the predetermined period has elapsed (step S764), the payout control CPU 371 stores the backup specified value ("55H" in this example) in the backup flag (step S809). The backup flag is formed in the backup RAM area. Next, processing similar to that of the CPU 56 of the main board 31 is performed to create parity data and store it in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the built-in RAM cannot be accessed.

  Further, the payout control CPU 371 sets clear data (00) in an appropriate register (step S821), and sets the number of processes (in this example, “3”) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S824), the value of the IO pointer is incremented by 1 (step S825), and the value of the processing number is subtracted by 1 (step S827). The processes in steps S824 to S826 are repeated until the value of the number of processes becomes zero. As a result, clear data is set to all the output ports C to E (see FIG. 39). As shown in FIG. 39, in this example, “1” is on and clear data “00” is set to each output port, so that all output ports are off.

  Therefore, after the processing for saving the game state (in this example, checksum generation and RAM access prevention) is executed, each output port is immediately turned off. In this embodiment, all RAM areas in which data used in the payout control process are stored are backed up. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the payout control state.

  As described above, in this embodiment, when a power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the ball payout device 97 is stopped, and then the detection signal from the payout detection means is output for a predetermined period. Input processing is executed, and thereafter processing for saving the payout control state is performed. Therefore, the game ball that was being paid out when the power failure occurred is also reflected in the saved contents of the backup RAM.

  In other words, in this embodiment, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent a control contradiction or the like from occurring.

  Note that clearing of output ports other than the output port of the sorting solenoid 310 may be performed before execution of the switch detection processing (before step S761). During execution of the power supply stop process, the payout control CPU 371 and switches are driven by the charging power of the capacitor and the like. When the clear process of the output port is performed before the switch detection process is performed, the charging power of the capacitor can be efficiently used for the power supply stop process.

  When the clear process for the output port is completed, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  Here, a timer (detection period counter) is set when the detection signal of the winning ball count switch 301A or the ball lending count switch 301B indicates an on state, and the detection signal remains on when the timer expires. If it is shown, it is determined that the switch has been reliably turned on. However, like the CPU 56 of the main board 31, the detection signal is determined every time the 2 ms timer (2 ms measurement counter) is up. Also good.

  Also in this embodiment, the register saving process was performed at the beginning of the process activated in response to the power-off signal, but when the register is not used in the switch detection process, after executing the switch detection process, That is, the register saving process can be performed before the backup flag setting and the checksum calculation process. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Further, even when several registers are used in the switch detection process, the register storage process can be performed before the backup flag setting process and the checksum calculation process for the unused registers.

  FIG. 47 is a flowchart showing a part of the non-maskable interrupt process using the clear data table of the payout control means in another embodiment of the present invention. The flowchart shown in FIG. 47 is executed following the processing of steps S801 to S820 shown in FIGS. That is, in this embodiment, after the RAM access prohibited state is set (step S820), the head address of the clear data table is set in the pointer (step S831), and then the data clear process is executed (step S831). S832), a standby state for waiting for system reset is entered. A predetermined register is used as a pointer.

  FIG. 48 is an explanatory diagram of a configuration example of the clear data table. In the example shown in FIG. 48, in the clear data table, the processing number data (in this example, “3”), the output port C address (address 00H), the clear data to be set to the output port C, -The output port E address (address 02H) and clear data to be set to the output port E are set. The output port address and the clear data are set in order from the smallest output port address.

  FIG. 49 is a flowchart showing the data clear process in step S832. In the data clear process, the payout control CPU 371 extracts the processing number data from the address pointed to by the pointer (step S841). Then, the pointer value is increased by 1 (step S842). Next, address data (output port address) is extracted from the address pointed to by the pointer (step S843). Further, the value of the pointer is incremented by 1 (step S844).

  Then, clear data is extracted from the address indicated by the pointer (step S845), and the data is set to the address extracted in step S843 (step S846). Next, 1 is subtracted from the value of the processing number (step S847), and when the processing number becomes 0, the data clear processing is terminated (step S848). If the number of processes is not 0, the process returns to step S841.

  Even if the clear data table is used, the clear signal output process can be performed quickly, and the occurrence of inconsistency between the control state stored when the power supply to the gaming machine is stopped and the actual control state is more effectively performed. Can be prevented. When a clear data table is used, the address data and the clear data need not be arranged in the order of addresses in the table, and the degree of freedom of the table configuration is increased. Further, when the output port is increased or decreased or changed, it is only necessary to change the contents of the table, and there is no need to change the program.

  If the clear data is 00H for all output ports, the clear data need not be included in the clear data table. In that case, the processing of S844 and S845 in the data clear processing shown in FIG. 49 is not necessary, and clear data 00H is set to the address indicated by the address data in step S846.

  In this embodiment, the total number of unpaid prize balls and lending balls is stored, but other storage methods such as storing the number of payouts (for example, 25 per time) are used. However, when the detection signal input process from the payout detection means is executed for a predetermined period in response to the power-off signal, it is possible to prevent inconsistencies in the stored control state. Is done.

  In the above embodiment, the ball dispensing device 97 dispenses both the winning ball and the lending ball, and the winning ball flowing path and the lending ball flowing path are switched by the sorting member 311 driven by the sorting solenoid 310. However, a payout device for paying out a winning ball and a payout device for lending a ball may be provided separately.

  For example, as shown in FIG. 50, a prize ball payout device 97A and a lending ball payout device 97C are provided separately. The prize ball payout device 97A is driven by the payout motor 289 in the same manner as in the above embodiment. On the upstream side of the payout ball passages 186a and 186b on the side of the prize ball payout device 97A, ball break switches 187a and 187b are installed. The ball break switches 187a and 187b are locked by locking pieces 188A and 188B at positions where it can be detected that about 27 to 28 game balls are present in the payout ball passages 186a and 186b. The central portion of the passage body 184A is formed in a shape that curves to the left and right so as to weaken the ball pressure of the game ball flowing down inside. The passage body 184A is fixed to the intermediate base unit, but the passage body 184A can be aligned by a locking protrusion 185A provided on the intermediate base unit.

  Below the passage body 184A, there is provided a ball stopper 190A for supplying game balls to the prize ball payout device 97A and stopping supply of game balls to the prize ball payout device 97A in the event of a failure. A prize ball payout device 97A installed below the ball stopper 190A is housed in a rectangular parallelepiped case 198A. Projections are provided at four places on the left and right sides of the case 198A. With each protrusion engaged with a positioning protrusion provided on the intermediate base unit, the lower end of the case 198A is fitted into the elastic engagement piece provided on the lower part of the intermediate base unit. Below the prize ball payout device 97A, a prize ball count switch 301A by a proximity switch is provided.

  In this embodiment, the lending ball dispensing device 97B is driven by a solenoid. On the side of the lending ball dispensing device 97B, the lending ball dispensing device 97B is fixed to the lower part of the passage body 184C that becomes the lending ball path. The passage body 184B has a payout ball passage 186c through which a row of game balls flow down. A ball break switch 187c is installed on the upstream side of the payout ball passage 186c. The ball break switch 187c detects the presence or absence of a game ball in the payout ball passage 186c. When the ball break switch 187c no longer detects a game ball, a ball lending solenoid (not shown) in the lending ball dispensing device 97B is used. The driving is stopped and the lending of the rental balls is made immobile.

  The central portion of the passage body 184C is formed in a shape that curves to the left and right so as to weaken the ball pressure of the game ball flowing down inside. The passage body 184C is fixed to the intermediate base unit, but the passage body 184C can be aligned by a locking projection 185C provided on the intermediate base unit. The lending ball dispensing device 97C may be installed beside or above the prize ball dispensing device 97A, or when the installation space is insufficient. It may be installed so as to be superimposed on the prize ball payout device 97A.

  Below the passage body 184C, there is provided a ball stopper 190C that supplies the game balls to the lending ball payout device 97C and stops supply of the game balls to the lending ball payout device 97C in the event of a failure or the like. The rental ball payout device 97C installed below the ball stopper 190C is housed in a rectangular parallelepiped case 198C. A ball lending count switch 301B using a proximity switch is provided below the lending ball dispensing device 97C.

  As shown in FIG. 50, even when a payout device for paying out a winning ball and a payout device for lending a ball are provided separately, the processing shown in FIGS. 44 to 46 is performed according to the power-off signal. , And the number of unpaid game balls to be stored can always be made to coincide with the actual number of unpaid games. However, the process of step S761 is a process of stopping driving of the payout device for lending a ball and stopping driving of the payout device for lending a ball. In addition, during the predetermined period during which the switch detection process is performed, the distance between the payout device that performs the prize ball payout ball and the prize ball count switch 301A, the distance between the payout device that performs the ball rental and the ball rental count switch 301B, If they are different, the time corresponding to the longer distance is set.

  As described above, in each of the above-described embodiments, when a power interruption signal is output in response to the occurrence of a power failure or the like, first, after the driving of the dispensing device is stopped, detection from the dispensing detection means for a predetermined period. A signal input process is executed, and thereafter a process for storing the payout control state is performed. Therefore, the game ball that was being paid out when the power failure occurred is also reflected in the saved contents of the backup RAM. Therefore, in a case where the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent inconsistencies between the stored control state and the actual control state. it can.

  In the above-described embodiment, the operation of the ball payout device is stopped at the start of an interrupt process by an interrupt generated in response to a power-off signal (in the above-described example, the non-maskable interrupt process), and the payout detecting means is used for a predetermined period. The detection signal input processing from was performed. However, when power supply to the gaming machine is stopped, a first signal indicating that may be generated first, and a second signal may be generated when the voltage further decreases. Then, the operation of the ball dispensing device is stopped according to the first signal, the detection signal is input from the dispensing detection means, and the control state is stored in the backup RAM according to the second signal. You may go.

  FIG. 51 is a block diagram showing a configuration example of a power supply board 910A for performing such control. In this example, a power supply monitoring IC 932 is also mounted on the power supply board 910A. The power supply monitoring IC 932 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (for example, +24 V), a voltage lowering signal (first signal) is output assuming that the power supply voltage has decreased. Then, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), the power monitoring IC 902 outputs a power-off signal (second signal) as a power-off occurs.

  The period from when the first signal is generated to when the second signal is generated is from the time when the game ball falls from the ball payout device 97 (or the prize ball payout device 97A or the lending ball payout device 97C). It is set to be equal to or longer than the time required to reach the prize ball count switch 301A or the ball lending count switch 301B. That is, the monitoring voltage of the power monitoring ICs 902 and 932 is set so as to be longer than that time. The output of the power monitoring IC 932 reaches the main board 31 and the payout control board 37 via the buffer circuits 939 and 940.

  In the main board 31, the voltage drop signal as the first signal is connected to the maskable external interrupt terminal of the CPU 56. Further, the power-off signal as the second signal is connected to the non-maskable interrupt terminal as in the above-described embodiment. That is, the priority of the interrupt based on the second signal is higher than the priority of the interrupt based on the first signal.

  FIG. 52 is a flowchart illustrating an example of an interrupt process (voltage drop interrupt process) that is activated based on an interrupt that occurs in response to the generation of the first signal. The CPU 56 of the main board 31 saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Further, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S454 to S458).

  Next, the CPU 56 sets an initial value n corresponding to a time of 2 ms in the 2 ms measurement counter (step S461). Then, the value of the 2 ms measurement counter is decremented by -1 (step S465) until the value of the 2 ms measurement counter becomes 0 (step S462). When the value of the 2 ms measurement counter becomes 0, the data input to the input port 1 is input (step S464). Next, clear data (00) is set (step S465). Further, the input data from the input port 1 is set as a “comparison value” (step S466). Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S467).

  Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S469). Data of the input port 1 is set as the comparison value. In this case, the detection signal of the winning ball count switch 301A is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S470), that is, if the detection signal of the prize ball count switch 301A is ON, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is “0”, that is, if the detection signal of the prize ball count switch 301A is OFF, clear data is set in the switch timer (step S472). That is, if the switch is off, the value of the switch timer returns to zero.

  When the value of the switch timer becomes 2 (step S473), 1 is subtracted from the value stored in the total prize ball number storage buffer (step S474), and the value of the prize ball information counter is incremented by 1 (step S475). . If the value of the prize ball information counter is 10 or more (step S476), the value of the prize ball information output counter is incremented by 1 (step S477), and the value of the prize ball information counter is incremented by -10 (step S478). Then, the process returns to step S461.

  Since the power supply voltage is lowered during the switch detection processing in steps S461 to S478, the second signal should be generated. Therefore, an unmaskable interrupt occurs. FIG. 54 is a flowchart illustrating an example of a non-maskable interrupt.

  In the non-maskable interrupt process, the CPU 56 stores the backup specified value (“55H” in this example) in the backup flag (step S481). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S482 to S491).

  Then, after prohibiting RAM access (step S492), all output ports are turned off (steps S493 to S499). When the clear process for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  With the above processing, when the prize ball count switch 301A is turned on within a predetermined period (a period from the first signal generation to the second signal generation), the value of the total prize ball number buffer is decremented by one. Since the processing for saving the contents of the backup RAM is performed after such switch detection processing, the total winning ball number buffer is always set to -1 for the winning ball that has been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. As already described, the input check process may be performed for detection signals of other detection means (switches) other than the payout detection means in a predetermined period.

  Further, the output port clearing process may be performed before the switch detection process (after step S458) in the voltage drop interruption process shown in FIG.

  In this embodiment, the register saving process is performed at the beginning of the process activated in response to the voltage drop signal (first signal). However, when the register is not used in the switch detection process, The register saving process can be performed after the detection process is executed, that is, in the process activated in response to the second signal. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Furthermore, even when some registers are used in the switch detection process, the register storage process can be performed in the process activated in response to the second signal for the unused registers.

  FIG. 55 is a timing chart showing an example of how detection signal input processing from the payout detection means is executed. As shown in FIG. 55, when the ball payout is executed around the time when the voltage drop signal is turned on (in this example, the change from the high level to the low level), the detection signal input processing from the payout detection means is executed. Within the period (period before the second signal is generated), the prize ball count switch 301A is turned on. Therefore, the ball payout executed when the voltage drop signal is turned on can also be reflected in the total winning ball number buffer.

  Also in the payout control board 37, the voltage drop signal as the first signal is connected to the maskable external interrupt terminal of the payout control CPU 371. Further, the power-off signal as the second signal is connected to the non-maskable interrupt terminal as in the above-described embodiment. That is, the priority of the interrupt based on the second signal is higher than the priority of the interrupt based on the first signal.

  FIG. 56 is a flowchart showing an example of an interrupt process (voltage drop interrupt process) activated based on an interrupt generated in response to the generation of the first signal. The payout control CPU 371 first saves the AF register in a predetermined backup RAM area (step S801). Further, the interrupt flag is copied to the parity flag (step S802). The parity flag is formed in the backup RAM area. Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S804 to S808).

  Next, the drive signal output to the dispensing motor 289 is turned off (step S761). Accordingly, the driving of the ball dispensing device 97 is stopped. When the prize ball payout device 97A and the lending ball payout device 97C are provided separately, the drive of both is stopped.

  Then, it is confirmed whether or not the prize ball count switch is on (step S765). If it is ON, the value of the detection period counter is decremented by 1 (step S766), and then it is confirmed whether or not the value of the detection period counter becomes 0 (step S767). If it is 0, the detection signal of the prize ball count switch 301A is confirmed via the input port (step S768), and if the on state is indicated, it is determined that the prize ball count switch 301A is surely turned on. The stored value is decreased by 1 (step S769).

  If it is confirmed in step S765 that the prize ball count switch is not on, the detection signal of the prize ball count switch 301A is confirmed via the input port (step S770). An intermediate flag is set (step S771), and an initial value n is set in the detection period counter (step S772).

  If the prize ball count switch 301A is turned on within the predetermined period by the above processing, the value of the total number storage is decremented by one. Since the process for saving the contents of the backup RAM is performed after such a switch detection process, the total number storage is always reduced by -1 for a prize ball that has been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. In the above processing, timer processing using a detection period counter is performed. That is, once the award ball count switch 301A is detected to be on, the switch is not considered to be on unless a predetermined time (n times the processing time in the loop from S763 to S767 and back to S763) has elapsed. . Therefore, erroneous switch-on detection is prevented.

  When the winning ball count switch is not on and the ON state of the winning ball count switch 301A cannot be detected, a switch detection process is performed for the ball lending count switch 301B. Note that the processing is the same as that of the embodiment already described (see FIG. 45). Since the power supply voltage decreases while the switch detection processing is being performed for the winning ball count switch 301A and the ball lending count switch 301B, the second signal should be generated. Therefore, an unmaskable interrupt occurs.

  Even in this embodiment, at least until the second signal is generated, the portion for performing the switch detection processing of the winning ball count switch 301A, the ball lending count switch 301B and the sorting solenoid 310 and the payout control means can be driven. An auxiliary drive power source (capacitor 923 in this example) is used.

  Also, here, when the detection signal of the winning ball count switch 301A or the ball lending count switch 301B indicates the on state, a timer (detection period counter) is set, and the detection signal is also in the on state when the timer times out. If it is shown, it is determined that the switch has been reliably turned on. However, like the CPU 56 of the main board 31, the detection signal is determined every time the 2 ms timer (2 ms measurement counter) is up. Also good.

  Further, the output port clear process may be performed before the switch detection process (after step S808) in the voltage drop interrupt process shown in FIG.

  FIG. 57 is a flowchart illustrating an example of a non-maskable interrupt. In the non-maskable interrupt process, the payout control CPU 371 first stores the backup specified value (“55H” in this example) in the backup flag (step S809). The backup flag is formed in the backup RAM area. Next, processing similar to that of the CPU 56 of the main board 31 is performed to create parity data and store it in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the built-in RAM cannot be accessed.

  Further, the payout control CPU 371 sets clear data (00) in an appropriate register (step S821), and sets the number of processes (in this example, “3”) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S824), the value of the IO pointer is incremented by 1 (step S825), and the value of the processing number is subtracted by 1 (step S827). The processes in steps S824 to S826 are repeated until the value of the number of processes becomes zero. As a result, clear data is set to all the output ports C to E (see FIG. 39).

  When the clear process for the output port is completed, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  In this embodiment, power supply monitoring means (power monitoring ICs 902 and 932 in this example) mounted on the power supply board 910A monitors the power supply, and the first condition (in this example, the + 30V power supply voltage is + 24V or less). ) Is output, the second signal is output when the second condition (in this example, the +30 V power supply voltage becomes +22 V or less) is satisfied. The period from when the first signal is generated to when the second signal is generated is set to be longer than the time until the game ball paid out from the payout means reaches the payout detection means. The conditions of + 22V and + 24V used in this embodiment are merely examples, and may be different values depending on the type of gaming machine.

  In the process according to the first signal, first, after the driving of the payout device is stopped, the input process of the detection signal from the payout detecting means is repeatedly executed, and then the payout control state according to the second signal. Processing for saving is performed. Therefore, the game ball that was being paid out when the power failure occurred is also detected by the process according to the first signal, and is therefore reflected in the stored contents of the backup RAM in the process according to the second signal. Therefore, in a case where the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent inconsistencies between the stored control state and the actual control state. it can.

  When the ball payout is executed around the time when the voltage drop signal is turned on (in this example, the change from the high level to the low level), the detection signal input process from the payout detection means is executed for a predetermined period (the second signal is Within the period before the occurrence), the prize ball count switch 301A or the ball lending count switch 301B is turned on. In this embodiment, the switch input process is executed in the voltage drop interrupt process (see FIG. 56) activated in response to the generation of the first signal. Therefore, the switch input process is executed when the voltage drop signal is turned on. The ball payout can also be reflected in the total number memory or the lending ball number memory.

  In this embodiment, the register saving process is performed at the beginning of the process activated in response to the voltage drop signal (first signal). However, when the register is not used in the switch detection process, The register saving process can be performed after the detection process is executed, that is, in the process activated in response to the second signal. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Furthermore, even when some registers are used in the switch detection process, the register storage process can be performed in the process activated in response to the second signal for the unused registers.

  Further, in each of the above embodiments, the case where the game control means and the payout control means perform the switch detection process in response to the power-off signal is exemplified, but the display control means, the sound control means, and the lamp control means are also controlled. When state saving processing is performed, in response to the power-off signal, the driving of a predetermined electrical component is stopped, and the control signal is saved after the detection signal of the switch means related to the electrical component is confirmed over a predetermined period. You may comprise so that a process may be performed.

  In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910. However, the power supply monitoring circuit may be provided on an electrical component control board such as the main board 31 or the payout control board 37. When an electrical component control board on which a power supply circuit is mounted is configured, a power supply monitoring circuit is not mounted on the power supply board.

  The pachinko gaming machine 1 according to each of the above-described embodiments mainly provides a player with a predetermined game value when a stop symbol of a special symbol variably displayed on the variable display unit 9 based on a start winning combination is a combination of a predetermined symbol. The first type pachinko gaming machine that can be granted, the second type pachinko that can be given a predetermined game value to the player if there is a winning in a predetermined area of the electric game that is released based on the start winning A third-class pachinko machine where a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when a stop symbol of a symbol that is variably displayed based on a starting prize is a combination of a predetermined pattern The present invention can be applied even to a gaming machine.

  Furthermore, the present invention can be applied to a slot machine or the like provided with an electrical component for paying out the game medium, not limited to a pachinko game machine in which the game medium is a game ball.

It is the front view which looked at the pachinko game machine from the front. It is explanatory drawing which shows each board | substrate provided in the back surface of the pachinko gaming machine. It is the rear view which looked at the mechanism board of the pachinko gaming machine from the back. It is a front view which shows the structure around the intermediate | middle base unit installed in the mechanism board. It is a disassembled perspective view which shows a ball dispensing apparatus. It is a block diagram which shows the circuit structure of a game control board (main board). It is a block diagram which shows the component relevant to prize balls, such as a component of a payout control board and a ball payout apparatus. It is a block diagram which shows one structural example of a power supply board. It is a block diagram which shows one structural example of CPU periphery in a main board | substrate. It is a block diagram which shows the internal structure of CPU in detail. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows an example of the relationship between a backup flag and whether to perform a game state restoration process. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows the example of formation of the switch timer in RAM. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows a switch-on check process. It is a flowchart which shows an example of a prize ball number subtraction process. It is explanatory drawing which shows the structural example of an input determination value table. It is explanatory drawing which shows an example of the command form of a control command. It is a timing diagram showing the relationship between an 8-bit control signal and an INT signal constituting a control command. It is explanatory drawing which shows the example of 1 structure of a command transmission table. It is a flowchart which shows the non-maskable interruption process in a game control means. It is a flowchart which shows the non-maskable interruption process in a game control means. It is a flowchart which shows the non-maskable interruption process in a game control means. It is a flowchart which shows the other example of the process at the time of the electric power supply stop in a game control means. It is explanatory drawing which shows one structural example of a clear data table. It is a flowchart which shows a data clear process. It is a timing diagram which shows an example of a mode that the input process of a detection signal is performed. It is explanatory drawing which shows an example of the game area | region of a 3rd type | mold pachinko gaming machine. It is a flowchart which shows an example of a game state restoration process. It is a block diagram which shows the example of 1 structure around the payout control CPU for power supply monitoring and power supply backup. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a payout control board performs. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows the example of 1 structure of RAM in the payout control means. It is a flowchart which shows the non-maskable interruption process in a payout control means. It is a flowchart which shows the non-maskable interruption process in a payout control means. It is a flowchart which shows the non-maskable interruption process in a payout control means. It is a flowchart which shows the other example of the non-maskable interruption process in a payout control means. It is explanatory drawing which shows one structural example of a clear data table. It is a flowchart which shows a data clear process. It is a disassembled perspective view which shows the other example of a ball dispensing apparatus. It is a block diagram which shows the other structural example of a power supply board. It is a flowchart which shows the voltage drop interruption process of a game control means. It is a flowchart which shows the voltage drop interruption process of a game control means. It is a flowchart which shows the other example of the non-maskable interruption process of a game control means. It is a timing diagram which shows an example of a mode that the input process of a detection signal is performed. It is a flowchart which shows the voltage drop interruption process of a payout control means. It is a flowchart which shows the other example of a non-maskable interruption process of a payout control means.

Explanation of symbols

31 Game control board (main board)
37 Dispensing control board 56 CPU
97 ball dispensing device 301A prize ball count switch 301B ball lending count switch 310 sorting solenoid 311 sorting member 371 dispensing control CPU
910, 910A power supply board 902,932 power monitoring IC (power monitoring means)

Claims (10)

A gaming machine in which a player can play a predetermined game,
Electrical component control means for controlling electrical components provided in the gaming machine;
Game medium detecting means for detecting a game medium;
Memory holding means capable of holding the memory content of the electrical component control means even when power supply to the gaming machine is stopped;
Power monitoring means for monitoring the state of a predetermined power source used in the gaming machine,
The electrical component control means performs input processing of a detection signal from the game medium detection means for a predetermined period when the power supply monitoring means detects that the power supply state has become a predetermined state. After being executed, a gaming machine is characterized in that it performs processing at the time of power supply stop related to storage of control state. With a payout means for paying out game media as electrical parts,
The gaming machine according to claim 1, wherein the game medium detection means includes a payout detection means for detecting a game medium paid out from the payout means. The gaming machine according to claim 2, wherein the predetermined period is a period equal to or longer than a period until the game medium paid out by the payout means reaches the payout detecting means. The electrical component control means inputs the detection signal from the payout detection means after stopping the drive of the payout means when the power supply monitoring means detects that the power supply state has become a predetermined state. The gaming machine according to claim 2 or 3, wherein the processing is executed. The gaming machine according to any one of claims 1 to 4, further comprising an auxiliary driving power source capable of supplying power capable of driving the game medium detecting means for a predetermined period even when power supply to the gaming machine is stopped. 6. The award game medium detection means for detecting a prize game medium and the rental game medium detection means for detecting a game medium lent to a player are separately provided as payout detection means. The gaming machine described. The electrical component control means is an input process of a detection signal from the game medium detection means that is executed when the power supply monitoring means detects that the power supply state has become a predetermined state. The gaming machine according to claim 1, wherein a timer process capable of measuring an output period is performed. There are award game media payout routes and rental game media payout routes,
A switching member for switching the payout route;
The gaming machine according to claim 5 or 6, wherein the operating position of the switching member can be maintained for a predetermined period even when power supply to the gaming machine is stopped. The gaming machine according to claim 8, further comprising an auxiliary drive power source capable of supplying power for maintaining the operating position of the switching member for a predetermined period even when power supply to the gaming machine is stopped. 8. The award game medium payout means for paying out award game media and the rented game medium payout means for paying out game media lent to a player are separately provided as payout means. Game machines.

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