JP2003103024A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which surely performs the detection of a game medium being put out when a power supply is stopped, and can accurately grasp a non-discharge number of the game medium. SOLUTION: In a mask impossible interrupting process, a CPU for the put-out control checks a detection maintaining period, and detection signals of a prize ball-counting switch and a ball-renting counting switch. Then, when the prize ball-counting switch is turned on, the content of a total quantity memory is subtracted by one. Also, when the ball-renting counting switch is turned on, the content of a renting ball quantity memory is subtracted by one. Since a capacitor is provided as a subsidiary driving power source, even when the power supply is stopped, the power source voltage is maintained in a range wherein the switches and sorting solenoids can be driven during a detection maintaining period. Therefore, during the detection maintaining period, a switch detection can be surely performed. Thus, the non-discharge number of the game medium can be accurately grasped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine, which is capable of playing a predetermined game using a gaming medium.

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Furthermore, a variable display unit whose display state can be changed is provided,
There is one configured to give a predetermined game value to the player when the display result of the variable display section becomes a predetermined specific display mode.

The gaming value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who easily wins a hit ball, or is advantageous for the player. To generate the right to pay for the prize, and to make it easier for the conditions for paying out prize balls to be met.

In the pachinko gaming machine, it is usually called a "big hit" that the display result of the variable display section for displaying the special symbol is a combination of predetermined specific display modes.
When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which a hit ball is easy to win is entered. Then, in each opening period, when a predetermined number (for example, 10) of winning holes are won, the winning holes are closed. The number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied when the special winning opening is closed, the jackpot gaming state ends.

Further, in the variable display device, the symbols other than the symbol which is the final stop symbol (for example, the middle symbol of the left and right middle symbols) continue for a predetermined time, and stop and swing in a state in which it matches the specific display mode. , Scaled or deformed state, or multiple symbols fluctuate synchronously in the same symbol, or the position of the displayed symbol is swapped, the possibility of a big hit before the final result is displayed The effect that is performed in a state in which the above is continued (hereinafter, these states are referred to as the reach state) is referred to as the reach effect. A variable display including a reach effect is called a reach variable display. By changing the variation pattern in the reach state from the variation pattern in the normal state, the interest of the game is enhanced. When the display result of the symbols variably displayed on the variably display device does not satisfy the condition for reaching the reach state, the result is “out”, and the variably display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game on the gaming machine is controlled by the game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display unit are controlled by a video display processor (VDP) that generates image data according to an instruction from the microcomputer and transfers the image data to the variable display unit side. The program capacity required by the microcomputer is large.

Therefore, it is not possible to control the identification information and the like displayed on the variable display portion by the microcomputer of the game control means having a limited memory capacity for storing the program, which is different from the microcomputer of the game control means. A pattern control board on which display control means such as a microcomputer for display control is mounted is installed. The game control means for controlling the progress of the game needs to send a command for display control to the display control means.

When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game proceeds to the game mounted on the main board. Since it is controlled by the control means, the number of prize balls based on the winning is determined by the game control means and transmitted to the payout control board. On the other hand, rental of game media is
Since it has nothing to do with the progress of the game, it is generally controlled by the payout control means without passing through the game control means.

As described above, the game machine is equipped with various control means in addition to the game control means. Then, the game control means for controlling the progress of the game sends each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the game control means and other control means may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

[0010]

As described above, the game machine is equipped with various electric component control means including the game control means. Generally, each electric component control means is configured to include a microcomputer. Such electric component control means generally performs an initialization process when the power supply voltage rises, and starts control from an initial state. Then, an unexpected power failure such as a power failure occurs, and then the power returns to the initial state when the power is restored, which may cause a problem that the gaming value or the like obtained by the player disappears. In order to prevent such a problem from occurring, the game control is interrupted in response to a predetermined signal that accompanies the decrease in the power supply voltage value, and the control state at that time is stopped by the power supply to the game machine. In particular, the power may be stored in the storage means that is backed up (backup storage means) and controlled so as to wait until the power supply is completely stopped. In such a gaming machine, if the power supply is restarted while the game state is stored in the storage means, the game is restarted based on the stored control state, which is disadvantageous to the player. Is prevented.

However, if the electric component is in operation immediately before the processing of storing the control state in the backup storage means, the actual control state may change with respect to the stored control state. There is also. For example, in the case of detecting the game ball paid out from the ball payout device for paying out the game ball by the switch means provided in the lower part of the ball payout device and confirming the payout of the game ball, Such problems may occur. That is, the ball payout device executes the payout of one game ball immediately before the operation of the ball payout device is stopped, the power failure occurs immediately after that, and the control state is saved before the switch means detects the payout. In this case, the stored payout confirmation number (or the unpaid number) and the actually paid out number may not match. In such a case, when the power supply is restarted, if the ball payout process is restarted based on the stored control state, extra game balls will be paid out.

Therefore, according to the present invention, even when the power supply is stopped, the game medium paid out can be surely detected, and the number of unpaid game media can be accurately grasped. The purpose is to provide.

[0013]

A gaming machine according to the present invention comprises:
A game machine capable of performing a predetermined game using a game medium, a game control means (for example, CPU 56) for controlling the progress of the game, a prize game medium as a prize, and a loan request from a player. A payout means (for example, a ball payout device 97) capable of paying out a rental game medium to be rented according to
A payout control means (for example, a payout control CPU 56) that controls the payout means based on a command from the game control means.
Etc.), and a prize game medium passage (for example, ball passage 293a) for guiding the game medium paid out by the payout means as a prize game medium, and a lending game medium passage for guiding as a rental game medium (for example, ball passage 293b). ), A passage switching means (for example, a distribution member 311) for switching the passage of the game medium paid out by the payout means to one of the prize game medium passage and the rental game medium passage, and an electric device for driving the passage change means. A drive source (for example, a solenoid 310 or a motor that controls the state of the distribution member 311) and a prize game medium detection means (for example, a prize ball count switch 301) provided in a prize game medium passage and capable of detecting a prize game medium.
A), a lending game medium detection means (for example, a lending ball count switch 301B) provided in the lending game medium passage and capable of detecting the lending game medium, and the stored contents for a predetermined period even if the power supply to the gaming machine is stopped. The variable data storage means (for example, backup RAM 55) that can be held and the state of a predetermined power source used in the gaming machine are monitored, and a detection signal is output when the detection condition related to the stop of power supply is satisfied. Power monitoring means (for example, power monitoring IC 902)
And at least a predetermined detection maintaining period (for example, step S7) after the detection signal is output by the power supply monitoring means.
Auxiliary power supply means (for example, capacitor 923) capable of supplying power to at least one of the prize game medium detection means and the rental game medium detection means in a period until the period (set by 62) elapses, at least Until the detection maintaining period elapses, the operating state holding means (for example, the capacitor 924) capable of holding the state of the passage switching means.
Power supply board 9 that continues to supply power based on the charging power of
10, a distribution member 311 and a motor configured to hold the state of the passage switching means by a mechanical structure, the game control means and the payout control means, respectively, the detection signal from the power supply monitoring means (for example, power supply) Power supply stoppage processing (for example, the processing shown in FIGS. 19 to 21 and the processing shown in FIGS. 45 to 47 for storing the data necessary for restoring the control state in response to the disconnection signal) in the variable data storage means. ) Is executed, and in the power supply stop process, the game control means inputs the detection signal from the prize game medium detection means (for example, step S461 to step S in FIG. 20).
480), and the payout control means inputs the detection signal from at least one of the prize game medium detection means and the rental game medium detection means (for example, FIG. 45).
The processing of steps S763 to S782 in FIG. 46) is performed.

The operation state holding means continues the power supply based on the auxiliary driving power supply means (for example, the charging power of the capacitor 924) for supplying the power for driving the passage switching means at least until the detection maintaining period elapses. Power supply board 910) that operates.

The operating state holding means holds the state of the passage switching means at least until the detection maintaining period elapses. The split member 311 and the motor or the latch type solenoid) may be configured.

The payout control means determines whether or not the payout means is paying out the prize game medium or the lending game medium in the power supply stop process (for example, a prize ball processing flag or a ball lending process flag). The determination is made according to the state of, for example, step S828, step S829), and based on the determination, the input processing of the prize game medium detection means or the rental game medium detection means (for example, step S763 to FIG. 59).
Step S772 and step S763 in FIG.
It may be configured (for example, the configuration shown in FIG. 59 to FIG. 61) so as to selectively perform any one of a to step S782).

The gaming machine according to the present invention is a gaming machine capable of playing a predetermined game using a gaming medium,
Game control means for controlling the progress of the game (for example, CPU 56
Etc.), and a payout means (for example, a ball payout device 97) capable of paying out a prize game medium as a prize and a lending game medium that is lent out in response to a lending request from a player, and a command from the game control means. A payout control means (for example, a payout control CPU 56 or the like) for controlling the payout means, and a prize game medium passage (for example, a ball passage 29) for guiding the game medium paid out by the payout means as a prize game medium.
3a) and a lending game medium passage (for example, ball passage 293b) for guiding as a lending game medium, and a passage for switching the passage of the game medium paid out by the payout means to either the prize game medium passage or the rental game medium passage. A switching means (for example, a distribution member 311), an electric drive source (for example, a solenoid 310 or a motor for controlling the state of the distribution member 311) that drives the passage switching means, and a prize game medium provided in the prize game medium passage. And a rental game medium detecting means (for example, a ball lending count switch 30) provided in the lending game medium passage and capable of detecting a prize game medium detecting means (for example, a ball lending count switch 30).
1B), a variable data storage unit (for example, backup RAM 55) capable of retaining stored contents for a predetermined period even when power supply to the game machine is stopped, and a state of a predetermined power source used in the game machine are monitored. And a power supply monitoring unit (for example, a power supply monitoring IC 902) that outputs a detection signal when a detection condition related to the stop of power supply is satisfied,
Auxiliary power supply means (for example, a capacitor 923) capable of supplying power to the prize game medium detection means and the rental game medium detection means at least until a predetermined detection maintaining period elapses after the payout signal is output by the power supply monitoring means. The power-supply stop process for the payout control means to store the data necessary for restoring the control state in the variable data storage means in response to the detection signal from the power supply monitoring means (for example, FIG. 73, FIG. 47). The process shown in FIG. 73 is executed, and the payout control unit performs an input process of a detection signal from at least one of the prize game medium detection unit and the rental game medium detection unit in the power supply stop process (for example, FIG. 73). The processing after step S763 in) is performed, and it is determined whether the prize game medium or the rental game medium is paid out by the payout means. (For example, determination is made according to the state of the prize ball processing flag or the ball lending processing flag. For example, step S828 and step S829 in FIG. 73), and based on the determination result, the detection signal input in the input processing is The present invention is characterized in that it is possible to specify which one of the prize game medium and the rental game medium is a detection signal based on detection.

In the power supply stop process, the process of clearing the output port for outputting a signal to the outside (eg, step S493 to step S499, step S821).
After performing step S827), the detection signal is input from at least one of the prize game medium detecting means and the rental game medium detecting means (for example, S4 in FIG. 20).
Processing of 60 to step S480. For example, at least one of steps S763 to S772 in FIG. 59 and steps S763a to S782 in FIG. 60) may be performed.

The detection maintaining period is a period until the game medium paid out by the payout means reaches the detection position of either the prize game medium detection means or the rental game medium detection means (for example, released from the sprocket 292). A period derived by √ (2L / g) indicating a drop period until the game ball reaches the detection unit of the prize ball count switch 301A or the ball lending count switch 301B. However, for example, 100 [ms]
A period of about 150 [ms]. ) The configuration may be set for the above period.

The stored contents of the variable data storage means include unpaid amount data which can specify the unpaid amount that has not yet been paid out of the number of prize game media to be paid out based on the satisfaction of the payout condition. When the power supply is started, the control means executes a recovery process (for example, the process shown in FIG. 44) for recovering the control state before the power supply is stopped,
The payout control means saves data indicating the result of the input processing of the detection signal from the prize game medium detection means or the rental game medium detection means in the fluctuation data storage means in the power supply stop processing (for example, step S872), and restores. The processing may be configured to perform processing for updating the data indicating the result of the input processing based on the unpaid amount data (for example, step S889).

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG.
[Fig. 3] is a front view showing the front face of the game board. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine and can be applied to, for example, an image-type gaming machine or a slot machine.

The pachinko gaming machine 1 is composed of an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a frame-shaped glass door frame 2 that is provided in the game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanical parts and the like are attached, and various parts attached to them (excluding a game board described later). It is a structure including and.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply plate (upper plate) 3. Below the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball feed tray 3 and a hitting ball operation handle (operation knob) 5 for firing the hit ball. Glass door frame 2
A game board 6 is detachably attached to the back surface of the. The game board 6 is a structure including a plate-shaped body that constitutes the game board 6 and various parts attached to the plate-shaped body. A game area 7 is formed on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display device (special symbol display device) 9 including a plurality of variable display portions for variably displaying symbols as identification information is provided. The variable display device 9 includes, for example, “left”, “middle”,
There are three "right" variable display parts (symbol display areas).
A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the starting winning opening 14 is guided to the rear surface of the game board 6 and detected by the starting opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the starting winning opening 14. Variable winning ball device 1
The solenoid 5 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. Opening plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 (V winning area)
The entered winning balls are detected by the V winning switch 22, and the winning balls from the opening / closing plate 20 are detected by the count switch 23. On the back surface of the game board 6, a solenoid 21A for switching the route inside the special winning opening is also provided. In addition, in the lower part of the variable display device 9, a special symbol starting memory display (hereinafter, referred to as starting memory display) 18 by four LEDs for displaying the number of effective winning balls that have entered the starting winning opening 14, that is, the number of starting memories. Is provided. Each time there is an effective start prize, the start memory indicator 18 increases the number of LEDs to be turned on by one.
Then, each time the variable display of the variable display device 9 is started,
Decrease the number of lit LEDs by 1.

When a game ball is won in the gate 32 and detected by the gate switch 32a, the variable display of the display of the normal symbol display device 10 is started. In this embodiment, the left and right lamps (the pattern can be visually recognized when turned on) are alternately turned on to perform variable display. For example, when the variable display ends, the right lamp is turned on. And when the stop symbol on the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. Normal symbol display 10
The number of winning balls that entered the gate 32 is displayed near 4
A normal symbol start-up memory display 41 having a display section with two LEDs is provided. Every time there is a prize in the gate 32, the normal symbol starting memory display 41 turns on the LED that is turned on by 1
increase. Then, each time the variable display of the normal symbol display device 10 is started, the number of LEDs to be turned on is reduced by 1.

The game board 6 has a plurality of winning openings 29, 30,
33, 39 are provided, and the winning openings 29, 30, 3 for gaming balls
The prizes for 3 are prize winning opening switches 29a, 30 respectively.
a, 33a, 39a. Each prize hole 2
Reference numerals 9, 30, 33, and 39 form a winning area provided on the game board 6 as an area for accepting a game medium and allowing a prize. It should be noted that the starting winning opening 14 that accepts the game medium and allows the winning, and the special winning opening also constitute the winning area. Decorative lamps 25 that are displayed blinking during the game are provided around the left and right sides of the game area 7, and there is an outlet 26 at the bottom for absorbing hit balls that have not been won. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b and a right frame lamp 28
c is provided. Further, a decorative LED is installed around each structure (a special winning opening, etc.) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of the decorative light-emitting body provided in the game machine.

In this example, the prize ball lamp 51 that lights up when the remaining number of prize balls is present near the left frame lamp 28b.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the top frame lamp 28a.
As described above, the pachinko gaming machine 1 of this example is provided with lamps and LEDs as light-emitting bodies at various places. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming machine 1,
Also shown is a card unit 50 that allows for ball lending by inserting a prepaid card.

In the card unit 50, a usable indicator lamp 151 indicating whether or not the card unit 50 is usable, and a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. A fraction display switch 1 for displaying on a frequency display LED provided in the vicinity of the hit ball supply tray 3
52, the connection stand direction indicator 15 showing which side the pachinko gaming machine 1 the card unit 50 corresponds to
3, a card insertion display lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The game ball shot from the hitting ball launching device enters the game area 7 through the hit ball rail, and then descends from the game area 7. When the ball hits the starting winning opening 14 and is detected by the starting opening switch 14a, if the variable display of the symbol can be started, the variable display device 9 starts the variable display (variation) of the special symbol. If it is not in a state where variable display of symbols can be started, the number of starting memories is increased by 1.

The variable display of the special symbol on the variable display device 9 is stopped when a certain time has elapsed. If the special symbol combination at the time of stop is a big hit symbol (specific display result), the big hit game state is entered. That is, the opening / closing plate 2
0 is released until a fixed time elapses or a predetermined number (for example, 10) of hit balls are won. Then, when the hit ball enters the V winning area while the opening / closing plate 20 is open and is detected by the V winning switch 22, the continuation right is generated and the opening / closing plate 20
Is released again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

A combination of special symbols in the variable display device 9 at the time of stop is a big hit symbol with probability variation (probability variation symbol)
In the case of the combination of, the probability of the next big hit is high. That is, the state of probability change is more advantageous for the player.

When the ball hits the gate 32, the normal symbol display 10 is in a state in which the normal symbol is variably displayed. Further, when the stop symbol in the normal symbol display device 10 is a predetermined symbol (hit symbol), the variable winning ball device 15
Remains open for a predetermined time. Furthermore, in the probable state,
The probability that the stop symbol in the normal symbol display 10 will be a winning symbol is increased, and the opening time and the number of times of opening the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probability variation symbol, and the like, and from a disadvantageous state for the player. Change to an advantageous state. In addition, increasing the number of times of opening is a concept including changing from a closed state to an open state.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a rear view of the gaming machine viewed from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

As shown in FIG. 3, on the back side of the game machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board on which a game control microcomputer and the like are mounted (mainly Substrate) 31 is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decorations L provided on the game board 6
ED, starting memory indicator 18 and normal symbol starting memory indicator 41, decoration lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 28c, prize ball lamp 51 and ball out lamp provided on the frame side. There is also provided a lamp control board 35 on which a lamp control means for controlling lighting of 52 is mounted, and a sound control board 70 on which a sound control means for controlling sound generation from the speaker 27 is mounted. Also, DC30V,
A power supply board 910 and a firing control board 91 on which a power supply circuit for producing DC21V, DC12V and DC5V is mounted are provided.

On the back side of the game machine, a terminal board 160 having terminals for outputting various information to the outside of the game machine is installed above. Terminal board 160
At least, the terminal for ball breakage for introducing the output of the ball breakage detection switch and outputting it externally, the terminal for prize balls for externally outputting the prize ball number signal and the external output for the ball lending number signal A ball lending terminal is provided. Further, in the vicinity of the center, an information terminal board (information output board) 34 provided with each terminal for outputting various information from the main board 31 to the outside of the gaming machine is installed.

Further, a memory content holding means (for example, a backup RA capable of holding the content even when power supply is stopped) included in each board (main board 31, payout control board 37, etc.).
There is provided a switch board 190 on which a clear switch 921 as an operation means for clearing the backup data stored in M) is mounted. Switch board 1
The 90 is provided with a clear switch 921 and a connector 922 connected to another substrate such as the main substrate 31.

The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. 4, the curve gutter 1
After 86, the ball payout device 97 covered with the prize ball case is reached. At the upper part of the ball payout device 97, a ball break switch 187 is provided as a game medium cut detection means. When the out-of-ball switch 187 detects out-of-ball, the ball dispensing device 9
The payout operation of 7 is stopped. The out-of-ball switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage,
The out-of-balls detection switch 167 for detecting the shortage of the supply balls in the storage tank 38 is also provided in the upstream portion of the guide rail 39 (the portion close to the storage tank 38). When the out-of-ball detection switch 167 detects a shortage of game balls, the supply mechanism provided on the game machine installation island supplies game balls to the game machine.

A large number of game balls as prizes based on prizes and game balls based on ball lending requests are paid out, and the hitting ball supply plate 3 becomes full, and finally the game balls reach the contact port 45 and further When paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In that state, the rotation of the payout motor in the ball payout device 97 is stopped, the operation of the ball payout device 97 is stopped, and the driving of the launching device is also stopped.

As shown in FIG. 4, a ball removal passage 191 extending from the curve gutter 186 to the discharge port 192 at the lower portion of the gaming machine is formed on the side of the ball payout device 97. Ball passage 1
A ball removing lever 193 is provided on the upper portion of 91, and when the ball removing lever 193 is operated by a game shop clerk or the like, a game ball passage from the guide rail 39 to the ball removing passage 191 is formed and stored in the storage tank 38. The played game ball is discharged from the discharge port 192 to the outside of the game machine.

FIG. 5 is an exploded perspective view showing a structural example of the ball payout device 97. In this example, the ball payout device 9 is placed inside the three cases 140, 141, 142 as prize balls.
7 are formed. Holes 170 and 171 communicating with the ball passage at the bottom of the ball break switch 187 are provided on the top of the cases 140 and 141, and the game balls are holes 170 and 17
From 1 to the ball dispensing device 97.

The ball payout device 97 includes a payout motor (eg, stepping motor) 289 serving as a drive source. The rotational force of the dispensing motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the dispensing motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls flowing in from the holes 170 and 171 are dropped one by one into the ball passages 293a and 293b below the sprocket 292 by the recesses of the sprocket 292.

The ball passages 293a and 293b are provided with a distribution member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when paying out a prize ball, the game ball falls down one of the flow paths (ball path 293a: an example of a prize game medium path) in the ball paths 293a and 293b, and the ball is lent. Occasionally, the game balls fall down along the other flow path (ball path 293b: an example of a lending game medium path) in the ball paths 293a and 293b. The payout motor 289 and the solenoid 310 are controlled by the payout control CPU mounted on the payout control board 37. Also, C for payout control
PU is a game control CP mounted on the main board 31.
The payout motor 289 and the solenoid 310 are controlled according to a command from U.

A prize ball sensor (prize ball count switch) 301A for detecting the game balls paid out by the ball payout device is provided below the downflow path selected at the time of paying out prize balls.
A ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by a ball payout device is provided below the flow-down path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals.

Incidentally, on the peripheral portion of the gear 291, there is formed a protrusion forming a payout motor position sensor. The protrusion allows the light from the light emitting body (not shown) to pass through or shield the light receiving unit (not shown) of the payout motor position sensor in accordance with the rotation of the gear 291 or the rotation of the payout motor 289. To do. The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

Further, the ball payout device may be configured to perform both prize ball payout and ball lending, but a ball payout device for paying a prize ball and a ball payout device for lending a ball are separately provided. It may be. Further, for example, the rotation direction of the sprocket may be changed to divide the prize ball payout and the ball lending, and the ball payout device having any structure other than the ball payout device 97 exemplified in the present embodiment. The present invention can also be applied by using.

FIG. 6 is a front view showing a portion of the switch board 190 installed on the game board 6. As shown in FIG. 6, the switch substrate 190 is provided with a connector 922 for connecting the output of the clear switch 921 to another substrate such as the main substrate 31 via a cable.

FIG. 7 is a configuration diagram showing an example of the configuration of the clear switch 921 mounted on the switch substrate 190. FIG. 7A shows a clear switch 921 having a push button structure. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the like via the connector 922. If the clear switch 921 is not pressed, a high level (off state) signal is output.

FIG. 7B is a configuration diagram showing another configuration example of the clear switch 921. The clear switch 921 shown in FIG. 7B has a switching operation unit 921a for performing selective switching of "OFF", "ON", and "clear". When "OFF" is selected by the switching operation unit 921a, no signal is generated. "ON"
When is selected, a high level signal is output.
The clear switch 921 may also serve as a switch for switching on / off the power supply to the gaming machine 1. In that case, when "OFF" is selected, the gaming machine 1
The power supply to is stopped (the power of the gaming machine is off). If "ON" or "clear" is selected, the game machine 1 is in a state where power is supplied (the game machine is powered on). Also, when "clear" is selected, a low level clear switch signal is output.

Although the switch board 190 on which the clear switch 921 is mounted is provided separately from the other boards in this embodiment, the clear switch 921 may be mounted on the other board. For example, it may be mounted on the power supply board 910. The clear switch 921 is the power supply board 910.
In the case where the game board 6 is replaced, even if the power board 910 is used as it is for the replaced game board 6 in the case of replacement, etc., the game state is restored as it is in the replaced game board 6. Processing and the like can be executed.
That is, the power supply board 910 can be reused.

FIG. 8 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 8 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the firing control board 91, and the symbol control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
Control circuit 53, a gate switch 32a, a starting opening switch 14a, a V winning switch 22, a count switch 23, winning opening switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for giving the signal from 21 to the basic circuit 53
8 and a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening / closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching the path in the special winning opening according to a command from the basic circuit 53 are mounted.

Although not shown in FIG. 8, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Switches such as the prize ball count switch 301A may be called a sensor. That is, a game medium detecting means capable of detecting a game ball (a game ball detecting means in this example)
If so, the name does not matter. In particular, each of the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a for performing the winning detection is also a winning detection means. The winning detection means may be one that collectively detects each of the gaming balls that have been won separately in a plurality of winning openings. Further, even if a passing gate such as the gate switch 32a is used for paying out prize balls, entering a game ball into the passing gate is a prize, and a switch provided in the passing gate (for example, The gate switch 32a) serves as a winning detection means.

Further, according to the data given from the basic circuit 53, the big hit information indicating the occurrence of the big hit, the effective starting information indicating the number of starting winning balls used to start the variable display of the symbols on the variable display device 9, and the probability variation An information output circuit 64 that outputs an information output signal such as probability variation information indicating that it has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 is a ROM 54 for storing a game control program and the like, and R as a storage means (a means for storing variation data) used as a work memory.
AM55, CPU5 which controls according to the program
6 and I / O port section 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. Note that the 1-chip microcomputer only needs to have at least the RAM 55 built therein, and
The OM 54 and the I / O port unit 57 may be external or built-in.

Further, a part or all of the RAM (which may be a RAM with built-in CPU) 55 is a backup RAM backed up by a backup power supply created in the power supply board 910. In other words, even if the power supply to the gaming machine is stopped, the RAM remains for a predetermined period.
The contents of part or all of 55 are saved.

The hit ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 controls the ball to be fired at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 includes the starting memory indicator 18, the normal symbol starting memory indicator 41 and the decorative lamp 25 provided on the game board. In addition to performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the out-of-ball lamp 52 provided on the frame side is performed. Further, the display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the ordinary symbol is the symbol control board 80.
The display control means mounted on the.

FIG. 9 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 9, the detection signal from the full tank switch 48 is transmitted via the relay board 71 to the main board 3.
1 is input to the I / O port unit 57. The detection signal from the ball break switch 187 is also input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates the full state, a payout control command instructing that the payout should be stopped is sent. When receiving the payout control command instructing that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid award ball.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is an I / O port 372a.
The payout control command is input via the, and the ball payout device 97 is driven according to the payout control command to perform the prize ball payout. In this embodiment, the payout control CPU 371 is
1-chip microcomputer, at least RA
M is built in.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A lent ball number signal indicating the number of lent balls is output to the terminal board 160 via 72c. Furthermore, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signals from the ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually loaned ball. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the distribution solenoid 3 is used.
The drive signal to 10 is transmitted to the distribution solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connecting board direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). To the balance display board 74, a frequency display LED, a ball lending switch and a return switch, which are provided in the vicinity of the hitting ball supply tray 3, are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

Then, the payout control C of the payout control board 37 is used.
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. After that, if the BRDY signal from the card unit 50 is not on,
The prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, the payout control board 3
At least a part of the RAM (may be a RAM with a built-in CPU) existing in 7 is backed up by a backup power supply created in the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is saved for a predetermined period.

In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. May be. Further, the present invention can be applied even when a game ball corresponding to the amount of coins is lent out in response to the coin insertion.

FIG. 10 is a block diagram showing an example of the structure of the power supply board 910. The power supply board 910 includes a main board 31,
Design control board 80, sound control board 70, lamp control board 3
5 and the payout control board 37 and other electric part control boards are installed independently of each other, and each electric part control board in the gaming machine and the voltage used by the mechanical parts are generated. In this example, AC2
4V, VSL (DC + 30V), DC + 21V, DC + 1
Generates 2V and DC + 5V. Further, the backup power source, that is, the capacitor 916 serving as a memory holding unit,
It is charged from DC + 5V, that is, from the line of the power supply that drives the ICs on each substrate. Note that VSL is a rectifier circuit 912.
At, the rectifying element rectifies and boosts AC 24V. VSL serves as a solenoid drive power source.

The transformer 911 converts the AC voltage from the AC power supply into 24V. 24V AC voltage is applied to connector 9
It is output to 15. In addition, the rectifier circuit 912 is an AC 24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 may include one or more converters I
C920 (only one is shown in FIG. 10) and VSL
Based on the above, + 21V, + 12V and + 5V are generated and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 920. Therefore, when the power supply to the game machine from the outside is stopped, the DC voltage of + 21V, + 12V, + 5V, etc., decreases relatively gently. Also, the connector 9
A capacitor 924 having a relatively large capacity is also connected to the input side of 15. Therefore, the + 30V DC voltage output to the connector 915 decreases relatively slowly. As a result, the capacitors 923 and 924 serve as an auxiliary drive power source (auxiliary power supply means, auxiliary drive power supply means) described later. The connector 915 is connected to, for example, a relay board, and the relay board supplies electric power of a required voltage to each electric component control board and mechanical components.

However, the power supply board 910 may be provided with each connector reaching each electric component control board, and each voltage may be supplied from the power supply board 910 to each board without passing through the relay board. Further, although one connector 915 is representatively shown in FIG. 10, the connector is provided for each electric component control board.

+ 5V from the DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the game machine is stopped (RAM whose power is backed up, that is, backup storage means that can be in a storage content holding state even when the power supply is stopped).
It becomes a backup power supply that supplies electric power so that the memory state can be maintained. In addition, a diode 9 for preventing backflow is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, the backup + 5V is applied to the main board 31 and the payout control board 3
7 is supplied.

A battery which can be charged from a + 5V power source may be used as the backup power source. When a battery is used, a rechargeable battery is used which loses its capacity when the power is not supplied from the + 5V power source for a predetermined time.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, it is determined that the power supply is stopped, and a power-off signal is output. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC, is used. Power supply monitoring IC
The power-off signal from 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Further, VSL (+ 30V) is used as the monitoring voltage.
In the case of using, since the voltage supplied to the various switches of the gaming machine is + 12V, it can be expected to prevent erroneous detection of switch-on at the moment of power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in + 12V generated after + 30V is generated, before the voltage starts to drop. When the voltage of the + 12V power supply drops, the switch output starts to turn on. However, if the + 30V power supply voltage that drops earlier than + 12V is monitored and it is recognized that the power supply has stopped, the power supply will turn on before the switch output turns on. It is possible to enter a state of waiting for restoration and enter a state in which no switch output is detected.

Further, VSL (+ 30V) as a monitoring voltage
Unlike the input line to the power supply monitoring IC 902, VSL (+
A large-capacity capacitor 924 is connected to the input line to the connector (915) of 30V. Therefore, VSL (+ 30V) as the monitoring voltage is the large-capacity capacitor 92.
VSL output to connector 915 to which 4 is connected
It drops faster than (+ 30V). That is, even after VSL (+ 30V) as the monitoring voltage starts to drop, the supply state of VSL (+ 30V) as the voltage supplied to the solenoid and the motor is maintained for a predetermined period. After that, VSL as the voltage supplied to the solenoid, motor, etc.
(+ 30V) gradually decreases. Therefore, even when VSL (+ 30V) as the monitoring voltage starts to drop, it is possible to drive the solenoid, motor, etc. for a predetermined period. Further, the stop of the power supply can be recognized before the VSL (+ 30V) output to the connector 915 starts to drop.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric part control board, the power supply cutoff signal can be supplied from the power supply monitoring circuit to the plurality of electric part control boards. Even if there are any number of electric component control boards that require a power-off signal, one power supply monitoring means may be provided. Therefore, even if each electric component control means in each electric component control board performs the return control described later. , The cost of gaming machines does not rise so much.

In the configuration shown in FIG. 10, the detection output (power-off signal) of the power supply monitoring IC 902 is passed through the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control). Although it is transmitted to the substrate 37), for example, one detection output may be transmitted to the relay substrate and the same signal may be distributed from the relay substrate to each electric component control substrate. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, the main substrate 31
Regarding the power-off signal output to the payout control board 37, the monitoring voltage of the power-source monitoring circuit that outputs the power-off signal may be different.

FIG. 11 shows the CPU 56 in the main board 31.
It is a block diagram showing an example of the circumference. As shown in FIG. 11, the power-off signal from the power-supply monitoring circuit (power-supply monitoring means; first power-supply monitoring means) of the power supply board 910 indicates that the CPU
It is connected to 56 non-maskable interrupt terminals (XNMI terminals). Therefore, the CPU 56 causes the non-maskable interrupt (NM
I) It is possible to confirm the occurrence of the stop of the power supply to the gaming machine by the process.

A system reset circuit 65 is also shown in FIG. The reset IC 651 is
The output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level when the predetermined time elapses. That is, the reset signal is raised to the high level to bring the CPU 56 into the operable state. The reset IC 651 monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, and has a predetermined voltage value (lower than the power supply voltage value at which the power supply monitoring circuit outputs a power cutoff signal). When the value is less than or equal to (value), the output goes low. Therefore, the CPU 56 is reset in the system (that is, returned to the initial state of the system) after performing a predetermined power supply stoppage process in response to the power off signal from the power monitoring circuit.

As shown in FIG. 11, the reset IC 651 is used.
The reset signal from is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level.
Then, the Q5 output of the counter IC 941 is the NOT circuit 9
It is input to the NAND circuit 947 via 45 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The NAND circuit 9 is connected to the other input of the OR circuit 949.
The output of 47 is introduced via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. With such a configuration, when the power is turned on, the reset terminal of the CPU 56 is supplied with the reset signal (low level signal) twice.
Reliably starts operation.

Then, for example, the detection voltage of the power supply monitoring circuit (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to the low level is set to + 9V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 have the same power supply VSL.
Since the voltage is monitored, the difference between the timing when the voltage monitoring circuit outputs the power-off signal and the timing when the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop time process to the reliable completion of the power supply stop time process in response to the power off signal from the power supply monitoring circuit.

The power supply voltages monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.
The system reset circuit 65 corresponds to the second power supply monitoring means.

At least part of the RAM is backed up by the backup power supply supplied from the power supply board while the power is not supplied from the + 5V power supply which is the drive power supply of the CPU 56 and the like, even if the power supply to the gaming machine is stopped. Content is saved. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operating state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the game state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

In the configuration shown in FIG. 11, the reset signal (low level signal) is applied twice to the reset terminal of the CPU 56 when the power is turned on, but the reset signal is surely reset even if the rising timing of the reset signal is only once. When using the released CPU, reference numerals 941 to 949
The circuit element indicated by is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has 4 bits of 3 and a 1-byte port of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output.

12 and 13 are explanatory views showing the allocation of output ports in this embodiment. Figure 1
As shown in 2, the output port 0 is an output port of the INT signal of the control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1,
The 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2, and the 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. And in FIG.
As shown in, the 8-bit data of the sound control command sent to the sound control board 70 is output from the output port 4.

Also, from the output port 5, the information output circuit 6
Various information output signals reaching the information terminal board 34 and the terminal board 160 via 4, that is, output data of information relating to control are output. Then, from the output port 6, a solenoid 16 for opening / closing the variable winning ball device 15, a solenoid 21 for opening / closing the opening / closing plate 2 of the special winning opening, and a solenoid 21 for switching a path in the special winning opening.
The drive signal for A is output.

As shown in FIG. 13, the payout control board 37,
An output port for outputting each INT signal (payout control signal INT, display control signal INT, lamp control signal INT, and voice control signal INT) output to the pattern control board 80, the lamp control board 35, and the sound control board 70 ( The output port 0) and the output ports (output ports 1 to 4) for outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 and the sound control signals CD0 to CD7 are different ports. Is.

Therefore, when outputting the INT signal, the payout control signals CD0 to CD7 and the display control signals CD0 to CD0 are mistakenly output.
The possibility of changing the CD7, the lamp control signals CD0 to CD7, and the audio control signals CD0 to CD7 is reduced. Also, when the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 or the voice control signals CD0 to CD7 are output, the I
The possibility of changing the NT signal is reduced. As a result, the command to the electric component control board from the game control means of the main board 31 is more reliably transmitted. Further, since each INT signal is configured to be output from the output port 0, I of the game control means
The load of NT signal output processing is reduced.

FIG. 14 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 14, bits 0 to 7 of the input port 0 have respective winning opening switches 33a, 39a, 29a, 30a, and
Detection signals of the gate switch 32a, the starting opening switch 14a, the count switch 23, and the V winning switch 22 are input. In addition, the detection signals of the prize ball count switch 301A, the full tank switch 48, the ball cut switch 187, the count switch short circuit signal, and the detection signal of the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. In this way, the detection signal of the clear switch 921, that is, the operation input of the operating means, is the input port (the input unit of 8-bit configuration) to which the detection signal of the switch for detecting the game ball is input.
Bit in the same input port as (input port circuit)
Has been entered in.

Next, the operation of the gaming machine will be described. Figure 1
5 is a flowchart showing the main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main processing, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the stack pointer designated address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). After initializing the built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to the accessible state (step S6).

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, the CTC has two external clock / timer trigger inputs CLK / TRG2,3.
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode to always fly to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, the interrupt request from each built-in device can be easily processed, and the interrupt process can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 confirms the state of the output signal of the clear switch 921 inputted via the input port 1 only once (step S7). If ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 1, the on state of the clear switch signal is high level (see FIG. 14). Further, for example, the game shop clerk uses the clear switch 92.
By starting power supply to the gaming machine while turning 1 on, the initialization process can be easily executed. That is, the RAM clear or the like can be performed.

If the clear switch 921 is not in the ON state, data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. When such a protection process is performed, backup is made. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area during the power supply stop process. In this example, as shown in FIG. 16, if "55H" is set in the backup flag area, it means that there is backup (on state), and if a value other than "55H" is set, there is no backup (off). State).

After confirming that there is a backup, the CPU 5
6 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Further, the number of checksum calculations corresponding to the number of checksum target data is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The data after inversion is used as the checksum.

In the power supply stop process, the checksum is calculated by the same process as the above process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If the power is restored after an unexpected power outage such as a power outage, backup RA
Since the data in the M area should have been saved, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply was stopped. In such a case, since the internal state cannot be returned to the state when the power supply was stopped, the initialization process that is executed when the power is turned on, not when the power supply is restored from the stop, is executed.

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply was stopped (step S10). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored.

As described above, the backup RA is backed up using the backup flag and the check data such as the checksum.
By checking whether or not the data in the M area is saved, it is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

Further, if "backup is present" is not confirmed by the state of the backup flag, the initialization process described below is performed without performing the game state recovery process described below, so backup data exists. It is possible to prevent the game state recovery process from being executed despite not doing so, and it is possible to return the control state to the initial state by the initialization process.

Further, when the check result using the check data is not normal, the initialization process described below is performed without performing the game state recovery process described below, so that the power supply is stopped. It is possible to prevent the game state restoration process from being executed based on the backup data that has become different contents,
By the initialization processing, the control state can be returned to the initial state.

In the initialization processing, the CPU 56 first executes R
AM clear processing is performed (step S11). Further, a predetermined work area (for example, a random number counter for normal symbol determination, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
Work area setting processing for setting an initial value to a prize ball flag, out-of-ball flag, payout stop flag, or other flag for selectively performing processing according to the control state is performed (step S1).
2). Further, a process of transmitting a payout permission state designation command (hereinafter, referred to as a payable state designation command) for instructing that the ball can be paid out from the ball payout device 97 to the payout control board 37 (step S13). . Also,
Other sub-boards (lamp control board 35, sound control board 70,
A process of transmitting an initialization command for initializing the pattern control board 80) to each sub-board is executed (step S1).
4). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing to turn off the prize ball lamp 51 and the ball out lamp 52 (for the lamp control board 35) Etc.)

In the initialization processing, the payable state designating command is always transmitted to the payout control board 37. what if,
Even if the state of the gaming machine is a state in which the payout from the ball payout device 97 is not possible, the fact is detected in the game control process executed immediately after that, and a payout instructing that the payout is not possible is issued. Command for specifying prohibited state (hereinafter,
It is called a payout stop state designation command. ) Is sent, so there is no problem. In the process of transmitting the payable state designation command and the initialization command to another sub-board, for example, a table (R
The address of the OM area) may be set in the pointer, and a processing routine such as command setting processing (see FIG. 35) described later may be called.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S15). That is,
A value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number updating process and the initial value random number updating process are executed, the interrupt disabled state is set (step S16), and when the display random number updating process and the initial value random number updating process are completed, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining the symbol displayed on the variable display device 9, and the display random number updating process is a process of updating the count value of the counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random numbers. The initial value random number is a random number for determining an initial value of a count value of a counter (big hit determination random number generation counter) for generating a random number for determining whether or not to make a big hit. In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, the initial value is set to the counter.

Note that the interrupt-prohibited state is set when the display random number updating process is executed, because the display random number updating process is also executed in the timer interrupt process described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt prohibition state is set during the process of step S17.

FIG. 17 is a flow chart showing an example of the game state restoration processing. In the game state recovery process, C
The PU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (a stack pointer save buffer in a work area where power is backed up) in a power supply stop process which will be described later in detail. Therefore,
In step S81, the value of the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the CPU 56 confirms whether or not the payout is stopped (step S82). Whether or not the payout has been stopped is determined by the RAM whose power is backed up.
Predetermined work area stored in the area (for example, random symbol for normal symbol determination, normal symbol determination buffer, special symbol left middle right symbol buffer, special symbol process flag,
The payout stop flag as the payout state data in the payout command storage pointer, the award ball flag, the out-of-ball flag, the payout stop flag, etc.) is confirmed. When it is in the payout stop state, a payout control command (payout stop state designation command) for instructing the stop of payout is transmitted to the payout control means mounted on the payout control board 37 (step S83). If the payout is not stopped, the payout control unit sends a payout control command (payable state designation command) to the payout control means (step S84).

Since the payout control means cannot recognize the shortage of the supply balls and the full capacity of the surplus ball receiving tray 4, the game control means must notify the shortage of the supply balls or the surplus ball receiving tray 4 when the power is restored. There is a risk that the game ball payout process will be started despite the fact that it is a ton. However, in this embodiment, in the game state recovery process, since the payout control command for instructing the stop of the payout or the payout control command for instructing that the payout is possible, the payout control means causes the shortage of the supply balls. And even if the surplus ball receiving tray 4 is full, the game ball payout process is never started.

Here, if the payout state determination means (a part of the game control means) for determining whether or not the game medium can be paid out, detects that the payout is not possible, regardless of the cause. One type of payout stop state designation command (that is, in the present example, the payout stop state designation command is
It is a command that is commonly used regardless of which of a plurality of types of conditions for prohibiting payout is satisfied. ) Is sent, but it may be sent separately for each cause-specific command (in this example, a command indicating a shortage of the supply balls and a command indicating a lower plate full).
Furthermore, when the payout of the game ball is not possible, a command instructing to prohibit the launch of the game ball to prohibit the continuation of the game may be transmitted to the payout control board 37. When the payout control means mounted on the payout control board 37 receives a command instructing to prohibit the launch of a game ball, it stops driving the ball striking device. Further, when the payout of the game ball is not possible, the game control means may directly give the launch control means a signal instructing to prohibit the launch of the game ball. Further, the payout control means may stop the driving of the hitting ball launching device when the payout stop state designation command is received.

Next, the CPU 56 transmits a display control command for restoring the display state of the special symbol on the variable display device 9 when the power supply is stopped (step S85).

Thereafter, the CPU 56 clears the backup flag (step S91), that is, resets the flag indicating that the predetermined storage protection process was executed at the previous power supply stop. Therefore, it is possible to prevent unnecessary information from remaining after the control state is restored.
Also, the saved values of various registers are read from the stack area, and various registers (IX register, HL register, D
Set to E register, BC register) (step S9)
2). That is, register restoration processing is performed. The value of the stack pointer is decremented each time each register is restored. That is, the value of the stack pointer is updated to point to the address immediately before the stack area. Then, when the parity flag is not turned on, the interrupt permission state is set (steps S93 and S94). Finally, AF
The registers (accumulator and flag registers) are restored from the stack area (step S95).

Then, the RET instruction is executed. RET
When the instruction is executed, the CPU 56 realizes the return operation of the program by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state recovery processing. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S92, the stack pointer pointing to the stack area is NM.
It indicates the area where the address of the program being executed when the power supply stop processing by I was started is saved. That is, the return address stored in the stack area pointed to by the restored stack pointer is
This is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, the next RET instruction in step S95 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address data (program address data) saved in the stack area.

When a timer interrupt occurs, the CPU 56
After performing the register saving process (step S20), the game control process of steps S21 to S32 shown in FIG. 18 is executed. In the game control process, the CPU 56 first
Via the switch circuit 58, the detection signals of the switches such as the gate switch 32a, the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a are input to determine their states (switch processing: Step S21).

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used for game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

Further, the CPU 56 carries out special symbol process processing (step S26). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S27). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. And the value of the normal symbol process flag,
It is updated during each process according to the game state.

Next, the CPU 56 performs a process of setting a display control command relating to a special symbol in a predetermined area of the RAM 55 and transmitting the display control command (special symbol command control process: step S28). In addition, the display control command relating to the normal symbol is set in a predetermined area of the RAM 55 and a process of transmitting the display control command is performed (normal symbol command control process: step S29).

Further, the CPU 56 performs an information output process for outputting data such as big hit information, starting information, probability variation information, etc. supplied to the hall management computer (step S30).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). In order to open or close the variable winning ball device 15 or the opening / closing plate 20 or to switch the game ball passage in the special winning opening, the solenoid circuit 59 drives the solenoids 16, 21, 21A according to the drive command. To do.

Then, the CPU 56 causes the winning opening switch 2
A prize ball process is performed for setting the number of prize balls based on the detection signals of 9a, 30a, 33a and 39a (step S32). Specifically, the winning opening switches 29a, 30
The payout control command indicating the number of prize balls is output to the payout control board 37 in response to the winning detection based on the turning on of a, 33a, and 39a. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in response to a payout control command indicating the number of prize balls. afterwards,
The contents of the register are restored (step S33), and the interrupt enabled state is set (step S34).

According to the above control, in this embodiment, the game control process is activated every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set,
The game control process may be executed in the main process.

19 to 21 are flow charts showing a processing example of the non-maskable interrupt processing (power supply stop time processing) executed in response to the power-off signal from the power supply board 910. When a non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 uses the stack pointer as the address of the program being executed at the time of the non-maskable interrupt (specifically, the next address after completion of execution). It is saved in the stack area pointed to by and the value of the stack pointer is increased. That is, the value of the stack pointer is updated to point to the next address in the stack area.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Also, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register and the stack pointer are saved in the backup RAM area (steps S454 to S458). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag.

Next, the CPU 56 causes the clear data (0
0) is set in an appropriate register (step S49
3), the number of processes (“7” in this example) is set in another register (step S494). Further, the address of the output port 0 is set in the IO pointer (step S49).
5). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S49).
6), the value of the IO pointer is incremented by 1 (step S49
7), 1 is subtracted from the value of the number of processes (step S498).
In the processes of steps S496 to S498, the value of the number of processes is 0.
Is repeated until. As a result, clear data is set in all output ports 0 to 6 (see FIGS. 12 and 13). As shown in FIGS. 12 and 13, in this example, “1” is in the ON state and the clear data “0”.
Since "0" is set to each output port, all output ports are turned off.

As described above, since each output port is turned off, it is possible to surely prevent the occurrence of a situation inconsistent with the saved game state. That is, in a gaming machine that has a variable winning ball device, such as a pachinko gaming machine,
Due to the mounting, the position of the variable winning opening in the variable winning ball device and the installation position of the winning opening switch for detecting the winning must be separated to some extent. If you do not immediately turn off the output port, especially the output port that outputs the signal to open the variable winning ball device, when the power supply is stopped, even if you win the variable winning port, even if the power supply is stopped A situation may occur in which execution of the process is started and the winning opening switch is not detected. In that case, the fact that the variable winning a prize has been won is not saved. That is, the actually occurring game state (there is a prize) and the saved game state do not match. However, in this embodiment, since the output port is cleared and the variable winning ball device is closed, it is possible to reliably prevent the occurrence of a situation inconsistent with the saved game state.

In addition, since the output port can be cleared during the power supply stoppage process executed before the electric components cannot be driven, the electric components cannot be driven. Before that, each electric component controlled by the game control means can be put into an appropriate operation stopped state. For example, after closing the open special winning opening and closing the open variable winning ball device 15, the operation of the electric components is disabled after the operation of the electric components is stopped. be able to. Therefore, it becomes possible to wait for the restoration of the power supply in an appropriate stopped state.

Furthermore, since the operation of each electric component is stopped during the power supply stop process, electric power is not consumed to drive each electric component, and the signal is output from the output port. Since the used electric current is cut off, it is possible to suppress the power consumption though it is a small amount.

Furthermore, in this embodiment,
The detection signal of the prize ball count switch 301A is checked. When the prize ball count switch 301A is turned on, the content of the total prize ball count buffer is decremented by one.

In this embodiment, a counter for measuring a predetermined period is used to measure the predetermined period.
The value of the counter for measuring the predetermined period is −1 from the initial value m every time the loop of the switch detection processing (loop starting from S461 and returning to S461) described below is executed once.
Then, when the value becomes 0, it is assumed that the predetermined period has ended. Although there is an exception in the detection processing loop, substantially constant processing is performed, and therefore a time that is m times the time required for one round of the loop corresponds to a substantially predetermined period.

A built-in timer of the CPU 56 may be used to measure the predetermined period. That is, a predetermined value (corresponding to a predetermined period) is set in the built-in timer at the start of the switch detection process. And the loop of the switch detection process is 1
Every time it is executed, the count value of the built-in timer is checked. Then, when the count value becomes 0, it is assumed that the predetermined period ends. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program.

Also, during the predetermined period, the game ball is dropped from the ball payout device 97 (for example, when it is sent to the ball passages 293a and 293b below the sprocket 292 shown in FIG. 5), the prize ball count switch 301A. Also, the time is set to be equal to or longer than the time required to reach the loan ball count switch 301B. Assuming that the distance from the ball payout device 97 to the prize ball count switch 301A and the loan ball count switch 301B is L, the fall time t during that time is t = √
Since it becomes (2 L / g) (g: gravity acceleration), the predetermined period is set to be longer than that. The specific value of the predetermined period is
Depending on the value of the distance L and how much margin is provided from the fall time t, for example, 100 [ms] to 150
It is set to about [ms]. When the distance from the ball payout device 97 to the prize ball count switch 301A is different from the distance to the loan ball count switch 301B, the above distance is calculated based on the distance of the switch away from the ball payout device 97. The predetermined period may be set.

At least, during the predetermined period in which the switch detection process is executed, the prize ball count switch 301A must be in a state where it can detect a game ball. Therefore, in this embodiment, as shown in FIG.
A capacitor 923 serving as an auxiliary drive power source having a comparatively large capacity is connected to the input side of the converter IC 920 in FIG. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained within the switchable range for a certain period of time, and the prize ball count switch 301A.
Becomes operational. The capacitance of the capacitor 923 is determined so that the period is equal to or longer than the above-described predetermined period.

Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 920, they can be operated for a relatively long period even when the power supply is stopped.

In step S461, an initial value n corresponding to a time of 2 ms is set in the 2 ms measuring counter. Then, until the value of the 2 ms measurement counter becomes 0 (step S462), the value of the 2 ms measurement counter becomes −.
1 (step S463).

When the value of the 2 ms measurement counter becomes 0,
The input check of the detection signal of the prize ball count switch 301A is performed. That is, a process similar to the switch process and the switch check process described later is performed. Specifically, the data input to the input port 1 is input (step S464). Then, clear data (0
0) is set (step S465). Further, the port input data, in this case, the input data from the input port 1 is set as the "comparison value" (step S466).
Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S467).

Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (direction from the higher bit to the lower bit) (step S469). ). The data of the input port 1 is set as the comparison value. Then, in this case, the detection signal of the prize ball count switch 301A is pushed out to the carry flag.

If the value of the carry flag is "1" (step S470), that is, the prize ball count switch 30.
If the 1A detection signal is in the ON state, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is "0", that is, if the detection signal of the prize ball count switch 301A is in the off state, clear data is set in the switch timer (step S472).
That is, if the switch is in the off state, the value of the switch timer returns to 0.

When the value of the switch timer becomes 2 (step S473), the value stored in the total prize ball number storage buffer is decremented by 1 (step S474), and the value of the prize ball information counter is incremented by 1 (step S474). Step S475).
When the value of the prize ball information counter is 10 or more (step S476), the value of the prize ball information output counter is incremented by 1 (step S477), and the value of the prize ball information counter is decremented by 10 (step S478).

Next, the value of the counter for measuring for a predetermined period is set to −
1 (step S479), and if the value is not 0, the process returns to step S461.

By the above processing, when the prize ball count switch 301A is turned on within the predetermined period, the value of the total prize ball number storage buffer is decremented by one. Since the processing for storing the contents of the backup RAM is performed after such a switch detection processing, the total prize ball number storage buffer is always decremented by -1 for the prize balls that have been paid out. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the switch detection process, since the prize ball information output frequency counter for outputting the prize ball information to the outside of the gaming machine is also calculated, the prize ball information output to the outside and the actual number of payout prize balls are inconsistent. It doesn't happen.

In the switch detection process described above, the timer process using the detection period counter is performed. That is, the detection output of the prize ball count switch 301A is checked every 2 ms, and when the ON detection is performed twice in succession, it is considered that the prize ball count switch 301A is surely turned on. That is, a predetermined game medium detection determination period (a period for determining whether or not a game medium (here, a prize ball paid out in the power supply stop process) is detected. In this example, a period of 2 ms or more) When the ON detection is performed twice consecutively before and after, it is considered that the payout of one prize ball is completed. As described above, in this example, the game medium detection determination period is the normal game medium detection determination period (a period for determining the presence or absence of the game medium in the normal game state, which is not the process in the power supply stop process. Then, 2 ms determined by the switch-on determination value (see FIG. 31) described later
In the above period, step S24 of FIG.
It is used in the judgment of 4. ) And the same period.
Therefore, it is possible to determine whether or not the prize ball count switch 301A is turned on under the same condition as the normal control. The game medium detection determination period may be different from the normal game medium detection determination period. as mentioned above,
Since the prize ball count switch 301A is considered to be surely turned on when it is detected to be turned on twice consecutively, it is prevented that the switch-on is mistakenly detected, and the prize ball paid out. Can be reliably detected.

In this embodiment, the switch detection processing is performed only for the prize ball count switch 301A, but the same applies to the switch for the start winning opening and the V winning switch 22 and the count switch related to the big winning opening. Switch detection processing may be performed. Further, similar switch detection processing may be performed for other prizes. When such an on-check is also performed, even if a power failure occurs immediately after the game ball has won the winning opening, the winning is surely detected and reflected in the saved game state.

When the predetermined period has elapsed (step S48)
0), that is, when the value of the counter for measuring for a predetermined period becomes 0, the designated value with backup (in this example, "55
H ”) is stored in the backup flag (step S
481). The backup flag is formed in the backup RAM area. Next, the parity data is created (steps S482 to S491). That is, first,
The clear data (00) is set in the checksum data area (step S482), and the checksum calculation start address is set in the pointer (step S483).
Also, the number of checksum calculations is set (step S
484).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S485). The calculation result is stored in the checksum data area (step S48).
6), increment the pointer value by 1 (step S487),
The value of the checksum calculation count is subtracted by 1 (step S4
88). The processes of steps S485 to S488 are repeated until the value of the checksum calculation count becomes 0 (step S489).

When the value of the checksum calculation frequency becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S490). Then, the inverted data is stored in the checksum data area (step S491). This data becomes the parity data that is checked when the power is turned on. Then R
An access prohibition value is set in the AM access register (step S492). After that, the built-in RAM 55 cannot be accessed.

Then, when the access prohibition value is set in the RAM access register, the CPU 56 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the RAM area in which the data used in the game control processing is stored is backed up by the power supply. Therefore, the checksum generation process indicating whether or not the contents are correctly saved, and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for saving the game state.

In this embodiment, the power supply stop processing is executed according to the NMI, but the power-off signal is changed to C
You may connect to the maskable terminal of PU56 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In this embodiment, the register saving process is performed at the beginning of the process started in response to the power-off signal. However, when the register is not used in the switch detecting process, the switch detecting process is performed. The register saving process can be performed after the execution, that is, before the process of setting the backup flag and calculating the checksum. In that case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as the power supply stop process. Further, even when some registers are used in the switch detection process, the register saving process can be performed on the unused registers before the backup flag setting and the checksum calculation process.

In the above example, the output port clearing process is performed before the switch detection process is executed (step S460).
Before). During the execution of the power supply stop process, the CPU 56 and the switches are connected to the capacitors 923 and 92.
It will be driven by the charging power of 4 or the like. Since the output port clearing process is performed before the switch detection process is executed, even if the special winning opening, the variable winning device, etc. are configured to be driven by electric parts such as solenoids, they must be driven. Not a capacitor (especially capacitor 92
The charging power and the like in 4) can be effectively used for the processing at the time of power supply stop.

In the above example, when the V winning switch 22 is detected after the power is cut off, the solenoid 21 (the member for guiding the special winning opening to the V winning switch is operated). The output port of () is cleared after the switch detection processing is executed. By doing so, when a power outage occurs in a state where the V winning that is the condition of continuation right is not generated, guide the game ball that entered the special winning opening just before the power outage to the V winning switch 22 side. You can Therefore, it is possible to prevent the unjustified extinction of the continuation right. In this case, the predetermined period is a period of time or more until the gaming ball that has won the special winning opening reaches the V winning switch 22. When a latch type solenoid is used, it is not necessary to clear the output port.

Further, even if the special winning opening is closed by clearing the output port, it is possible that there is a game ball in the special winning opening. Therefore, in the switch detection processing executed in response to the power-off signal, the count switch 23 It is desirable to detect The above-mentioned exceptional processing is the same not only in the type 1 pachinko gaming machine but also in the type 2 pachinko gaming machine and the type 3 pachinko gaming machine.

FIG. 22 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power off signal: power supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of the monitoring voltage (voltage input to the power supply monitoring IC 902) of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to + 22V, the power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (becomes a low level).

The power-off signal is introduced to the electric component control board (in this embodiment, the main board 31 and the payout control board 37), and the CPU 56 and the payout control CPU 371 have N levels.
It is input to the MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the system reset circuit mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 And the payout control CPU 371 enters the system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stoppage process before being brought into the system reset state.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, at least on the main board 31 and the payout control board 37, the processing at the time of power supply stop is executed, and
56 and the payout control CPU 371 are in the system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Generates a voltage drop signal (power cut detection signal). As shown in FIG. 22, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stoppage process.

Here, the power supply monitoring circuit monitors the voltage branched from the highest power supply VSL of the DC voltage used in the gaming machine. However, the timing of generating the power-off signal is the IC drive voltage. The voltage to be monitored does not have to be the highest voltage of the power supply VSL, as long as the operation time for the electric component control means operating in (3) secures the operation time for performing the predetermined power supply stop processing. That is, if at least a voltage higher than the drive voltage of the IC or the solenoid is monitored, the power-off signal is generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. be able to. In this example, the voltage branched from the power supply VSL is used as the drive voltage of the solenoid or the like, but unlike the line to which the monitored voltage is supplied, a large-capacity capacitor 924 is provided in the line that supplies the drive voltage to the solenoid or the like. Since they are connected, the power-off signal can be generated at a timing when a predetermined period in which the supply of the drive voltage to the solenoid etc. can be continued is secured.

When a voltage other than the highest power source VSL is set as the monitored voltage, it is preferable that the monitored voltage is a voltage that can be expected to prevent erroneous switch-on detection when the power supply is stopped, as described above. That is, since the voltage (switch voltage) supplied to the various switches of the gaming machine is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

FIG. 23 is a timing chart showing an example of how the detection signal input processing from the payout detecting means is executed. In this embodiment, the power-off signal is the main board 31.
And the payout control board 37, and the CP of the main board 31.
It is input to the N56 terminal of the U56 and the payout control CPU 371. The CPU 56 of the main board 31 executes the above-described power supply stop processing by the non-maskable interrupt processing.

As shown in FIG. 23, when the prize-ball payout is executed when the power-off signal turns on (changes from the high level to the low level in this example), the detection signal input process from the payout detection means is performed. The prize ball count switch 301A is turned on within a predetermined period to be executed. Therefore, the ball payout executed when the power-off signal is turned on can be reflected in the total prize ball number buffer when the power supply stop process is executed.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the reset IC 651 mounted on the main board 31 becomes low level as shown in FIG. The CPU 56 enters the system reset state. The CPU 56 completes the power supply stoppage process before the system is reset.

When the voltage value of VSL further decreases and falls below a voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, in the main board 31, the power supply stop processing is executed, and the CPU 56 is in the system reset state.

Note that, as will be described later, the payout control board 37
Similarly, the payout control CPU 371 in (1) also enters the system reset state after performing the power supply stoppage process.

Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch is certainly turned on, and the process corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 24, the switch timers are provided by the number N of detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 13. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 14).

FIG. 25 is a flow chart showing a processing example of the switch processing of step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs the data input to the input port 0 (step S101). Then
The number of processes is set to "8" (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, the switch check processing subroutine is called (step S104).

FIG. 26 is a flow chart showing the switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0 as the "comparison value" (step S121). In addition, clear data (00) is set (step S1
22). Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S).
124). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after addition becomes 0, the added value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in the off state, clear data is set in the switch timer (step S126). That is, if the switch is in the off state, the value of the switch timer returns to 0.

Thereafter, the CPU 56 adds 1 to the pointer (address of the switch timer) (step S130) and subtracts 1 from the processing number (step S13).
1). If the number of processes is not 0, step S122
Return to. Then, the processing of steps S122 to S132 is repeated.

The processing of steps S122 to S132 is repeated for the number of processings, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially turned on or off. If the check process is performed and the switch is on, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes step S of the switch processing.
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S107). Then, the switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is executed, steps S122 to S122
The processing of 132 is repeated for the number of processings, that is, four times, and during that time, with respect to the detection signal of the switch input to the 4 bits of the input port 1, the check processing of whether it is in the on state or the off state is performed sequentially. If it is on, the value of the corresponding switch timer is incremented by one.

In this embodiment, the game control process is activated every 2 ms, so the switch process is also performed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

27 to 29 are flowcharts showing an example of the prize ball process of step S32 in the game control process. In the present embodiment, in the prize ball processing, the prize winning hole switches 33a, 39a, 29a, which are targets of prize ball payout,
30a, count switch 23 and starting opening switch 1
4a is surely turned on, and when turned on, the payout control command indicating the number of prize balls is controlled to be sent to the payout control board 37, and the full tank switch 48 and the out-of-ball switch 187 are controlled. Whether or not it is surely turned on is determined, and when it is turned on, processing such as controlling to send a predetermined payout control command to the payout control board 37 is performed.

In the prize ball processing, the CPU 56 sets "1" as the offset of the input determination value table (step S150) and "9" as the offset of the address of the switch timer (step S151). The offset “1” in the input determination value table (see FIG. 31) is
This means that the second data “50” in the input determination value table is used. Also, each switch timer is shown in FIG.
Since they are arranged in the same order as the bit order of the input ports shown in FIG. 3, the offset "9" of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input judgment value table is set with a judgment value for each switch, for judging how many times the switch is continuously turned on to judge that the switch is turned on.
It is the M region. An example of the configuration of the input determination value table is shown in FIG. As shown in FIG. 31, in the input determination value table, “2”, “50”, “250”, “30”,
The determination values of "250" and "1" are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the switch timer value determined by the start address of the switch timer and the offset value, and they match. In that case, the switch-on flag is set, for example.

An example of the switch-on check routine is shown in FIG. In the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the full-tank switch 48 matches the full-tank switch-on determination value "50" (step S153), so the full-tank flag is set. (Step S
154). Although not explicitly shown in FIG. 27, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

Further, the CPU 56 sets "2" as the offset of the input judgment value table (step S15).
6), "0A (H)" is set as the offset of the switch timer address (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the offset “0A (H)” of the switch timer address is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
59), the out-of-ball flag is set (step S16).
0). Although not clearly shown in FIG. 27, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when the value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 confirms whether or not the dispensing is stopped (step S201). The payout stop state is a state after a payout stop state designating command, which is a payout control command for instructing the payout control board 37 to be in a state where the payout should be stopped, specifically, the work area. The payout stop flag in is set. If it is not in the payout stop state, it is confirmed whether the out-of-ball state flag or the full tank flag is turned on (step S202).

When any of them changes to the ON state,
The payout stop state flag is set (step S
203), the command transmission table relating to the payout stop state designation command is set (step S204), and the command setting process is called (step S205). In step S204, a command transmission table (R
The start address of OM) is set as the address of the command transmission table. In the command transmission table relating to the payout stop state designation command, the INT data, the first byte of the payout control command, and the second byte of the payout control command, which will be described later, are set. In addition, in step S202, when one of the flags is already in the on state and the other flag is in the on state, the processes of steps S203 to S205 are not performed.

If it is in the payout stop state, it is confirmed whether or not both the out-of-ball state flag and the full tank flag are turned off (step S206). When both are in the off state (when the release condition described later is satisfied), the payout stop flag is reset (step S207), and the command transmission table regarding the payable state designation command is set (step S208). The set process is called (step S209). In step S208, the start address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payable state designation command, INT data, which will be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

The cancel condition is a condition for canceling the payout stop state and is satisfied when it is no longer necessary to maintain the payout stop state. In this example, the cancellation condition is that the surplus ball receiving tray 4 is used when the dispensing stop state is set.
Is said to be in a state that is not full and is not out of ball.

Further, the CPU 56 sets "0" as the offset of the input judgment value table (step S22).
1), "0" is set as the offset of the switch timer address (step S222). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the switch timer address offset “0” specifies the switch timer corresponding to the winning opening switch 33a. Means Also, "4" is set as the number of repetitions (step S223).
Then, the switch-on check routine is called (step S224).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 31) (step S281). And
An offset is added to the address (step S28
2) The switch-on determination value is loaded from the added address (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the added address (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, the switch-on flag is set (step 128).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value "2", the switch-on flag is set (step S2).
25). Then, the switch check-on routine is executed for the number of repetitions set initially (steps S228 and S229) while the address offset of the switch timer is updated (step S230).
After all, the winning opening switch 33a, 39a, 29a, 30a
For, the value of the corresponding switch timer is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" as the number of prize balls to be paid out is set in the ring buffer (step S226). Then, 10 is added to the value stored in the total prize ball number storage buffer (step S22).
7). When data is written in the ring buffer, the write pointer is incremented, and when data is written in the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball numbers instructed to the payout control means (however, the value is subtracted when the payout is made).
It is formed in the backup RAM. In this embodiment, when the data is written in the ring buffer, addition processing is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, addition processing of the number of prize balls corresponding to the payout control command to be output may be performed on the stored value of the total prize ball storage buffer.

Next, the CPU 56 sets "0" as the offset of the input determination value table (step S23).
1), "5" is set as the offset of the switch timer address (step S232). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the switch timer address offset "5" specifies the switch timer corresponding to the starting port switch 14a. Means Then, the switch-on check routine is called (step S
233).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a matches the switch-on determination value "2", the switch-on flag is set (step S234). When the switch-on flag is set, "6" as the number of prize balls to be paid out is set in the ring buffer (step S235). In addition, the value stored in the total prize ball storage buffer is 6
Is added (step S236).

Next, the CPU 56 sets "0" as the offset of the input judgment value table (step S24).
1), "6" is set as the offset of the switch timer address (step S242). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the offset "6" of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S
243).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, "15" as the number of prize balls to be paid out is set in the ring buffer (step S245). In addition, 15 is added to the value stored in the total prize ball storage buffer (step S246).

If data exists in the ring buffer (step S247), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (in the ring buffer). It is updated to point to the next area (step S249), the command transmission table regarding the number of prize balls is set (step S250), and the command setting process is called (step S251). The operation of the command set process will be described later in detail.

In step S250, the head address of the command transmission table (ROM) in which the payout control command relating to the number of prize balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of prize balls includes INT data (01
(H)), the first byte of the payout control command (F
0 (H)), and the data of the second byte of the payout control command are set. However, "80 (H)" is set as the second byte of data.

As described above, when the payout control command for instructing the number of prize balls is output from the game control means to the payout control board 37, the address setting of the command transmission table regarding the number of prize balls and the setting of the transmission buffer are performed. Is done. Then, by the command setting process, the payout control command is sent to the payout control board 37 based on the command transmission table regarding the number of prize balls and the setting contents of the transmission buffer. In step S247, it is possible to confirm whether or not there is data by the difference between the write pointer and the read pointer. However, a counter indicating the number of unprocessed data in the ring buffer is provided, and the data is present according to the count value. You may confirm whether or not.

Then, the content of the total prize ball number storage buffer is 0.
If not, that is, if there is still a prize ball left, C
The PU 56 turns on the prize ball payout flag (step S
252, S253).

When the prize ball payout flag is on (step S254), the CPU 56 monitors the number of prize balls actually paid out from the ball payout device 97 and stores it in the total prize ball number storage buffer. The number of prize balls subtraction processing for subtracting the value is performed (step S255). When the prize-ball paying-out flag changes from on to off, the lamp control board 3
5, a lamp control command for instructing lighting of the prize ball lamp 51 is transmitted.

Upon receipt of the payout stop state designation command, the payout control means stops both the ball payout as a prize ball and the ball payout as a ball lend. When the payable state designation command is received, both the ball payout as a prize ball and the ball payout as a ball lend are made possible. However, from the game control means to the payout control means, a payout control command for stopping or restarting ball payout as a prize ball and a payout control command for stopping or restarting ball payout as a ball lending are different control commands. You may make it transmit as.

Further, in this embodiment, even when the payout is stopped (steps S201 and S206), the step S
The processing of 221 to S251 is executed. That is, the game control means can send a payout control command for instructing the number of prize balls even in the payout stopped state.
That is, the command for instructing the number of prize balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is released, the prize ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of prize balls based on the winning in the payout stop state.

Furthermore, in this embodiment, the processing of steps S221 to S251 is executed regardless of the payout status of the game medium. That is, the game control means can send a payout control command for instructing a new prize ball number, regardless of whether or not the specified number of prize balls has been paid out up to the previous time. Therefore, it is possible to reduce the processing load related to the payout of the game control means, and to quickly perform the prize ball payout processing.

Next, a method of sending a control command from the game control means to each electric component control means will be described. When the control command is to be output from the game control means to another electric component control board (sub board), the start address of the command transmission table is set. Figure 3
FIG. 2A is an explanatory diagram showing a configuration example of a command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the 1st byte.
The MODE data of the first byte of the control command is set in the command data 1 of the second byte. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

The EXT data itself may be set in the area of the command data 2, but the command data 2
May be set with data for designating the address of the table in which the EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, command data 2 is EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
In this embodiment, if the work area reference bit is 1, it indicates that the content of the transmission buffer is used as the EXT data. If the work area reference bit is 1, the other 7 bits can be configured to indicate that the other 7 bits are an offset for designating the address of the table in which the EXT data is stored.

FIG. 32B is an explanatory diagram showing a structural example of INT data. Bit 0 in the INT data indicates whether or not the payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, the CPU 56
For example, in the prize ball process (step S32 of the main process), "01 (H)" is set in the INT data. Also,
Bit 1 in the INT data is the design control board 80.
Indicates whether or not the display control command should be sent. If bit 1 is "1", it indicates that the display control command should be sent. Therefore, the CPU 56 sets "02 (H)" to the INT data in the special symbol command control process (step S28 of the main process), for example.

Bits 2 and 3 of the INT data are bits indicating whether or not to send the lamp control command and the sound control command, respectively, and the CPU 56 outputs a special command at the timing to send these commands. In the symbol process processing or the like, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When sending those commands, the corresponding bit of the INT data is set to "1", and the command data 1 and the command data 2 are MOD.
E data and EXT data are set.

In this embodiment, for the payout control command, a ring buffer and a transmission buffer are prepared as shown in FIG. 32 (C). Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. Also, when sending the payout control command regarding the number of prize balls,
One data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 32C, the ring buffer can store data corresponding to 12 payout control commands. That is, there are 12 buffers. The number of buffers in the ring buffer may be any number corresponding to the number of winning openings for generating prize balls. This is because even if the simultaneous winnings occur, it is possible to store the payout control command data based on the respective winnings.

FIG. 33 is an explanatory diagram showing an example of the command form of the control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always "1", and the first bit (bit 7) of the EXT data is always "0". As described above, the control command, which is a command to the electric component control board, is composed of a plurality of data, and can be distinguished by the leading bit. The command form shown in FIG. 33 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used. Further, although FIG. 33 illustrates the payout control command sent to the payout control board 37,
The control commands sent to the other electric component control boards have the same configuration.

FIG. 34 is a diagram showing 8-bit control signals CD0 to CD forming a control command for each electric component control means.
7 is a timing diagram showing the relationship between 7 and the INT signal. As shown in FIG. 34, when the period indicated by A elapses after the MODE or EXT data is output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data. INT which is a signal
Set the signal to high level (on data). When the period indicated by B elapses, the INT signal is set to low level (off data). Furthermore, if there is data to be sent next, that is, after sending the MODE data, the data of the second byte is sent to the output port after a period indicated by C. Regarding the data of the second byte, the periods A and B are the same as the case of the first byte.
In this way, the capture signal is output for each of MODE and EXT data.

The period A is a period during which the CPU 56 prepares to send a command, that is, a period required to set a send command in the buffer, and is a period for stabilizing the data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal as a capture signal is output after a predetermined period (period of A: part of the off output period) has elapsed. Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the OFF output period) is a period in which the electric component control unit is set so that the data can be reliably fetched. In the period of B and C,
The data on the signal line does not change. That is, the data output is maintained until the B and C periods elapse.

In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal for the first byte to the start of the transmission of the data of the second byte, is longer than the reception processing time in the electric component control means that takes the longest time for the command reception processing. Is also set to be long.

Each electric component control means detects that the INT signal has risen, and starts the processing of fetching 1-byte data by, for example, interrupt processing.

Since the periods B and C are longer than the reception processing time in the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing to each electric component control means by the common module. However, any electric component control means can surely receive the control command from the game control means.

The CPU 56 is ready to send the next data after the lapse of a predetermined period after executing the INT signal output process, but the predetermined period (the period of B and C) is IN
It is longer than the period (period A) from the transmission of data before the T signal output process to the start of output of the INT signal. As described above, the period A is the stabilization period in the command signal line, and the periods B and C are the periods for ensuring the time required for the receiving side to take in the data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can surely receive the command, and the transmission of one command is completed. There is also an effect that the period required for is shortened.

FIG. 35 is an explanatory diagram showing an example of the contents of the payout control command. In this example, a plurality of types of payout control commands are used to execute the payout control. Figure 3
In the example shown in FIG. 5, MODE = FF (H), EX
The command FF00 (H) of T = 00 (H) is a payout control command (payable state designation command) for instructing that the payout is possible. MODE = FF (H), EX
The command FF01 (H) of T = 01 (H) is a payout control command (payout stop state designation command) for instructing that the payout should be stopped. Also, MODE
The command F0XX (H) of = F0 (H) is a payout control command (payout number designating command) for designating the number of prize balls. “XX”, which is EXT, indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout ball payout and the ball lending are stopped, and FF00.
When the payout control command (H) is received, prize balls can be paid out and balls can be lent. Further, when the payout control command for designating the number of prize balls is received, the prize ball payout control according to the number designated by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the level of the INT signal changes, and “recognitionally being sent only once” means that in this example, the payout control signal is sent to each of the first byte and the second byte. Accordingly, the INT signal is output only once in a pulse shape (rectangular wave shape).

A control command for each electric component control board is
When outputting to the corresponding output port (output ports 1 to 4), one of the bits 0 to 3 of the output port 0 becomes "1" (high level) for a predetermined period. And the bit array in the output port 0 correspond to each other. Therefore, when the control command is sent to each electric component control board, the INT signal can be easily output based on the INT data.

FIG. 36 is a flow chart showing a processing example of the command set processing (steps S205, S209, S251). The command set process is a process including a command output process and an INT signal output process. In the command setting process, the CPU 56 first saves the address of the command transmission table (contents of the pointer as the transmission signal instruction means) to the stack or the like (step S3).
31). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore,
The address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sends the command data 1
Is read out and is set to the argument 2 (step S334).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S335).

FIG. 37 is a flow chart showing the command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351).
Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of the output port for outputting the payout control signal. Further, the addresses of the ports 2 to 4 are the addresses of the output ports for outputting the display control signal, the lamp control signal and the voice control signal.

Next, the CPU 56 shifts the comparison value right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S355). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (ie, MODE data) is output to the address set as the IO address (step S3
56). When the first shift processing is performed, the address of port 1 is set as the IO address, so the MODE data of the payout control command is set to port 1 at that time.
Is output to.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the processing number (step S358). When the port 1 is shown before the addition, the address of the port 2 is set to the IO address by the addition process for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0,
It returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not the lamp control command and the sound control command should be sent. In this way, when each shift process is performed, the IO address has the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process. It is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
A control command is sent to. That is, one common module can perform a process of sending a control command to each electric component control means.

Further, in this way, since it is determined to which electric component control means the control command should be output only by the shift processing, it is determined to which electric component control means the control command should be output. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 in which the INT data before the shift processing is started (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is a port for outputting the INT signal for each control signal, and bit 0 of port 0
4 to 4 are the payout control INT signal and the display control IN, respectively.
It is a port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and decrements by 1 until the value becomes 0 (steps S363, S36).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S36).
5) output the data to port 0 (step S3)
66). Therefore, the INT signal becomes low level. Then, a predetermined value is set in the wait counter (step S3
62), and subtracts 1 by 1 until the value becomes 0 (steps S368 and S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time that is generated in steps S367 to S369 and the subsequent processing time (if MODE data is output at this time, the time required for control until the EXT data is output). ) Is the period added. By setting the period of C in this way,
Even when the commands are continuously sent, a predetermined period of time elapses after the output of one command is completed and before the sending of the next command is started, and the electric component control means for receiving the command. On the side of, the command delimiters can be easily identified and each command is reliably received.

Therefore, the value set in the wait counter in step S367 is set so that the period C is a period sufficient for surely performing the command receiving process by all the electric component control means which are the control command receiving targets. Value. The value set in the wait counter is
The value is longer than the time (corresponding to the period A) required for the processes of steps S357 to S359. In addition, A
If it is desired to lengthen the period A, a wait process for creating the period A (for example, a process of setting a predetermined value in the wait counter and performing subtraction until the value of the wait counter becomes 0) is performed.

As described above, the 1st byte MODE data of the control command is transmitted. Therefore, CPU5
In step S336 shown in FIG. 36, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S339). If it is not 0, the contents of the transmission buffer are loaded into the argument 2 (step S341). If the extended data is used when the value of the work area reference bit is "1", the start address of the command extended data address table is set in the pointer and the command data is set in the pointer. The address is calculated by adding the values of bit 6 to bit 0 of 2. Then, the data of the area pointed to by the address is loaded into the argument 2.

Since data capable of specifying the number of prize balls is set in the transmission buffer, the data is set in the argument 2. If the extended data is used when the value of the work area reference bit is “1”, the command extended data address table contains
EXT data that can be sent to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table according to the content of the command data 2 is loaded into the argument 2.

Next, the CPU 56 calls the command transmission processing routine (step S342). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent out.

As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte structure is transmitted to the corresponding electric component control means. The electric component control means starts the control command fetching process when the rising edge of the INT signal is detected, but for any electric component control means, a new signal from the game control means is signaled before the fetching process is completed. It is never printed on the line. That is, a reliable command reception process is performed in each electric component control means. In addition, each electric component control means is
The control command acquisition process may be started at the falling edge of the T signal. The polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, in the prize ball processing, when the prize ball payout condition is satisfied, data capable of specifying the number of prize balls is stored in the ring buffer capable of storing a plurality of data at the same time. When the payout control command designating the is sent, the data in the area of the ring buffer pointed by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of prize ball payout conditions are satisfied at the same time, the data capable of specifying the number of prize balls based on the satisfaction of those conditions is stored in the ring buffer, so that the command output process based on the satisfaction of each condition does not pose a problem. To be executed.

Furthermore, in this embodiment, both the payout stop state designating command or the payable state designating command and the command indicating the number of prize balls can be sent in one award ball process. That is, 1 is activated every 2 ms
Multiple commands can be sent within one control period. Further, in this embodiment, since a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, payout control command) to each control means, for example, When data capable of specifying the control command is set in the ring buffer of the control command, the lamp control command, and the sound control command, a plurality of display control commands, lamp control commands, and sound control commands can be performed by one command control process. Can also be configured to deliver. That is, a plurality of control commands can be sent at the same time (meaning in the activation cycle of the game control process, that is, the 2 ms timer interrupt process). Since the transmission timings of those control commands occur at the same time in the progress of the game production, it is convenient to have such a configuration. However, since the payout control command is generated regardless of the progress of the game effect, in general, the display control command,
It is not sent at the same time as the lamp control command and the sound control command.

FIG. 38 is a flow chart showing an example of the award ball number subtracting process. In the process of subtracting the number of prize balls, C
The PU 56 first loads the value stored in the total prize ball number storage buffer (step S381). Then, it is confirmed whether the stored value is 0 (step S382). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the loaded value is compared with the ON determination value (in this case, "2") (step S384). If they match (step S38)
5) Assuming that the prize ball count switch 301A is turned on, that is, one game ball is certainly one ball payout device 9
The value stored in the total prize ball number storage buffer is decremented by 1 assuming that the payout is made from 7 (step S386).

Also, the value of the prize ball information counter is incremented by 1 (step S387). When the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information output counter is incremented by 1 (step S38).
9), the value of the prize ball information counter is decremented by 10 (step S
390). The value of the prize ball information output counter is shown in FIG.
Referred to in the information output process (step S30) in the game control process shown in, and if the value is 1 or more, it is set as 1 as a prize ball signal (bit 7 of output port 5: see FIG. 13).
A pulse is output. Therefore, in this embodiment, 1
Each time 0 game balls are paid out as a prize ball, one prize ball signal is output to the outside of the gaming machine.

Then, when the value stored in the total prize ball number storage buffer becomes 0 (step S391), the prize ball in-progress flag is cleared (step S392) to notify that there is no remaining prize ball number. After the command data indicating that the prize ball lamp 51 is turned off is set in the command transmission table for the lamp control command (step S393), the lamp control command sending process is executed (step S394).

Next, the payout control means will be described as an example of the electric component control means other than the game control means.

FIG. 39 is a block diagram showing an example of the configuration around the payout control CPU 371. As shown in FIG. 39, the power-off signal from the power-supply monitoring circuit (power-supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. There is. Therefore, the payout control CPU 37
1, it is possible to confirm the occurrence of the stop of power supply to the gaming machine by the non-maskable interrupt process.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. Then, when the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt will occur in response to the input of the INT signal.

A system reset circuit 975 is also mounted on the payout control board 37, but in this embodiment,
Reset IC 97 in system reset circuit 975
When the power is turned on, 6 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level after the predetermined time has elapsed. Also, reset IC9
Reference numeral 76 monitors the power supply voltage of VSL and sets the output to a low level when the voltage value becomes a predetermined value (for example, + 9V) or less. Therefore, when the power supply to the gaming machine is stopped, the reset IC 9
When the signal from 76 goes low, the payout control CPU 371 is system reset.

The predetermined value for the reset IC 976 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the payout control CPU 371 can operate for a while. Further, the reset IC 976 is used for the payout control CPU 3
Since it is configured to monitor a voltage higher than the voltage required by 71 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the payout control CPU 371. Therefore, more precise monitoring can be performed. The system reset circuit 975 corresponds to the second power supply monitoring means.

While the power is not being supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal to prevent a power failure or the like. Contents are saved even when power supply to the gaming machine is stopped. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, at the time of recovery from a power failure or the like, the payout control state at the time of power failure can be restored.

In the structure shown in FIG. 39, system reset circuit 975 outputs a low level for a period determined by the capacitance of the capacitor when the power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
Similarly to the case of 1, the circuit configuration in which the reset release timing occurs a plurality of times may be used.

FIG. 40 is an explanatory diagram showing output port allocation in this embodiment. As shown in FIG. 40, the output port C (address 00H) is connected to the payout motor 2
89 is an output port for driving signals and the like output to 89. Further, the output port D (address 01H) is an output port of a display control signal output to the error display LED 374 which is a 7-segment LED. And output port E
(Address 02H) is the drive signal output to the distribution solenoid 310 and the EX to the card unit 50.
It is an output port for outputting the S signal and the PRDY signal.

FIG. 41 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 41, the input port A (address 06H) is an input port for fetching the 8-bit payout control signal of the payout control command sent from the main board 31. Further, the detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Detection signal is input.

FIG. 42 shows payout control means (CP for payout control).
7 is a flowchart showing a main process of U371 and peripheral circuits such as ROM and RAM. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and the stack pointer designated address is set to the stack pointer (step S703). Further, the payout control CPU 37
1 initializes built-in device registers (step S704), and initializes CTC and PIO (step S704).
After performing 705), the RAM is set to the accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the built-in device register setting processing of step S704 and the processing of step S705, register setting for setting the channel to be used in timer mode, register setting for permitting interrupt generation, and register for setting interrupt vector Settings are made. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set in the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, payout control process is executed.

Also, another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means, and that channel is used. Is used in counter mode. Therefore, in the built-in device register setting processing of step S704 and the processing of step S705, in order to set the register setting for setting the channel to be used in the counter mode, the register setting for permitting interrupt generation, and the interrupt vector. Register setting is performed.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set the interrupt processing start address according to the interrupt vector sent by the CTC.

The interrupt based on the count-up of the channel 2 (CH2) of the CTC is an interrupt that occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as the specific register
An initial value "1" is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rising or falling of the signal input to the CLK / TRG2 terminal. You can make a choice. In this embodiment, the timer counter register CLK / TRG is output at the rising edge of the signal input to the CLK / TRG2 terminal.
The count value of 2 is set to -1.

The CTC channel 3 (CH3) count-up interrupt is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes "0". 2m
s Used as a timer interrupt. Specifically, CPU3
A clock obtained by dividing the operation clock of 71 is given to the CTC, the value of the register is subtracted by the input of the clock, and when the value of the register becomes 0, a timer interrupt is generated.
For example, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the CH3 register.

The interrupt based on the count-up of CH2 of CTC has a higher priority than the interrupt based on the count-up of CH3. Therefore, when count-ups occur at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process is prioritized.

Next, the payout control CPU 371 confirms the state of the output signal of the clear switch 921 input through the input port B (see FIG. 41) only once (step S707). When ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S713). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 372, the on state of the clear switch signal is high level. Further, the payout control means does not have to make the determination in step S707.

Note that, like the CPU 56 of the main substrate 31, the payout control CPU 371 also determines that the ON state is at least 2 when the ON detection of the switch detection signal is performed.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms) does not continue, it is not considered to be switch-on, but when the clear switch 921 is detected to be on, ON / OFF is determined by the ON determination. That is, it is determined whether or not the clear switch 921 as the operating means is in a predetermined operating state.
The initialization request detection determination period for U371 to determine is
The period is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detecting means has detected the game medium.

If the clear switch 921 is not turned on, the payout control CPU 371 confirms whether or not backup data exists in the payout control backup RAM area (step S708). For example, similar to the processing of the CPU 56 of the main board 31, whether or not backup data exists is determined by whether or not the backup flag that is set when the power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

When it is confirmed that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) of the backup RAM area. When the power is restored after the power supply is stopped due to an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, it is not possible to return the internal state to the state at the time of stopping the power supply, so the initialization process that is executed when the power is turned on is executed instead of when the power is restored from an insufficient power failure.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power supply was stopped (step S710). Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
First performs a RAM clear process (step S71).
1). Then, the CTC provided in the payout control CPU 371 so that a timer interrupt is periodically applied every 2 ms.
The register is set (step S712). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Since the interrupt is prohibited in step S701 of the initialization process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
71 built-in CTCs are set to repeatedly generate timer interrupts. In this embodiment, the repetition period is 2
Set to ms. And when a timer interrupt occurs,
As shown in FIG. 43, a timer interrupt flag indicating that there is a timer interrupt is set (step S792).
Then, in the main process, when it is detected that the timer interrupt flag is set (step S714), the timer interrupt flag is reset (step S714).
751), payout control process (steps S751 to S76)
0) is executed.

In the timer interruption, as shown in FIG. 43, the interruption permission state is first set (step S79).
1). Therefore, during the timer interrupt process, the interrupt enable state is set, and the payout control command reception process based on the input of the INT signal can be preferentially executed.

In the payout control process, the payout control CPU
371: First, the prize ball count switch 301A and the ball lending count switch 3 input to the input port 372b.
It is determined whether a switch such as 01B is turned on (switch process: step S752).

Next, the payout control CPU 371 sets the payout stop state when the payout stop state designation command is received from the main board 31, and releases the payout stop state when the payable state designation command is received. (Payment stop state setting process: step S753). Further, it analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S754). Further, prepaid card unit control processing is performed (step S755).

Next, the payout control CPU 371 controls the payout of the lent balls in response to the sphere lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the prize ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the 72c and the relay board 72 to perform payout motor control processing for rotating the payout motor 289 for a predetermined number of rotations (step S758). .

In this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control process, eight types of excitation pattern data are repeatedly output to the payout motor 289. Further, in this embodiment, each excitation pattern data is output by 4 ms.

Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

The output port C shown in FIG. 40 has the payout motor control process (step S75) in the payout control process.
Accessed in 8). Further, the output port D is accessed by the error processing in the payout control processing (step S759). Then, the output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 44 is a flow chart showing an example of the payout state recovery process of step S710. In the payout state recovery process, the payout control CPU 371 first performs a stack pointer return process (step S73).
1). The value of the stack pointer is saved in a predetermined RAM area (power source is backed up) in the power supply stoppage process described later. Therefore, step S7
At 31, the value in the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the payout control CPU 371 clears the backup flag (step S732), that is, resets the flag indicating that the predetermined storage protection process has been executed at the previous power supply stop. Further, the saved values of various registers are read from the stack area and set in the various registers (step S733). That is,
Performs register restoration processing. Then, when the parity flag is not turned on, the interrupt enable state is set (step S
734, S735). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S736).

Then, the RET instruction is executed, but the return destination here is not the portion that called the payout state recovery processing. This is because the stack pointer restoration process is performed in step S731, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred at the time of the previous power supply stop in the program. Therefore, the next RET instruction in step S736 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

45 to 47 are non-maskable interrupt processing (N) executed in response to a power-off signal from the power supply board 910.
It is a flow chart which shows the example of processing of MI processing: processing at the time of power supply stop. In this example, the process at the time of stopping the power supply is executed according to the NMI, but a power-off signal is sent to the payout control C
You may connect to the maskable terminal of PU371 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In the non-maskable interrupt process, the payout control CPU 371 sets the AF register to a predetermined backup R.
It is saved in the AM area (step S801). Also, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, IX register and stack pointer are saved in the backup RAM area (steps S804-8).
08). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag.

In this example, as the payout motor 289, a stepping motor which is rotated by a pulse signal (drive signal) from the payout control CPU 371 is used. Therefore, the driving of the ball payout device 97 is stopped by stopping the output of the pulse signal to the payout motor 289.

Next, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes (“2” in this example) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), 1 is subtracted from the value of the number of processes (step S827).
In the processes of steps S824 to S826, the value of the number of processes is 0.
Is repeated until. As a result, clear data is set in the output port C and the output port D (see FIG. 40). As shown in FIG. 40, in this example, “1” is in the ON state and clear data “00” is set in each output port, so that all the output ports C and D are turned off. It becomes a state. In this example, since the output port E is not cleared, the output port of the distribution solenoid 310 is not turned off. Clear processing may be performed on output ports other than the output port of the distribution solenoid 310 in the output port E.

Then, in this embodiment,
Prize ball count switch 301A as payout detection means
(Corresponding to a prize game medium payout detecting means) and a ball lending count switch 301B (corresponding to a lending game medium payout detecting means) are checked. Then, when the prize ball count switch 301A is turned on, the content of the total number memory is set to 1
cut back. When the ball lending count switch 301B is turned on, the content of the number of lent balls is reduced by one.

In this embodiment, a counter for measuring a predetermined period is used to measure the predetermined period.
The value of the counter for measuring the predetermined period is -1 from the initial value m every time the loop of the switch detection process (loop starting from S763 and returning to S763) described below is executed once.
Then, when the value becomes 0, it is assumed that the predetermined period has ended. Although there is an exception in the detection processing loop, substantially constant processing is performed, and therefore a time that is m times the time required for one round of the loop corresponds to a substantially predetermined period.

C for payout control in order to measure a predetermined period
The built-in timer of PU371 may be used. That is, a predetermined value (corresponding to a predetermined period) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the predetermined period ends. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program. In addition, the predetermined period is set to be equal to or longer than the time from when the game ball falls from the ball payout device 97 to when it reaches the prize ball count switch 301A or the ball lending count switch 301B.

At least a predetermined period during which the switch detection process is executed (a period longer than the period from the time when the game ball falls from the ball payout device 97 to the prize ball count switch 301A or the ball lending count switch 301A. For example, In the range of 100 [ms] to 150 [ms].), The prize ball count switch 301A and the ball lending count switch 301B must be in a state capable of detecting a game ball. Therefore, in this embodiment, as shown in FIG. 10, converter IC 920 in power supply substrate 910 is used.
A capacitor 923 as an auxiliary drive power source having a relatively large capacity is connected to the input side of the. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained within a switchable range for a certain period of time, and the prize ball count switch 301A and the ball lend count switch 301.
B becomes operational. The capacitance of the capacitor is determined so that the period is equal to or longer than the above predetermined period. The longer the above predetermined period is, or the longer the switchable period that is longer than the above predetermined period is, the larger the capacity of the capacitor is required. It is desirable not to have too much margin in the switchable period.

Input port and payout control CPU
Since the 371 is also driven by the + 5V power source created by the converter IC 920, it can be operated for a relatively long period even when the power supply is stopped.

Further, in this embodiment, the distribution solenoid 310 is used to switch between the prize ball path and the rental ball path. Therefore, the capacitor 9 shown in FIG.
The capacity of 24 is such that the distribution solenoid 310 can be driven at least during the above-mentioned predetermined period.
The capacitor 924 is connected to a line for supplying electric power to each electric component (a line on the input side of the connector 915), but the game control means is operated by another solenoid (large winning hole) in response to the power-off signal. Since the drive signals (for opening and closing, etc.) are turned off, the capacitor 924 is the distribution solenoid 3 among the solenoids after the power-off signal is generated.
It suffices if only 10 can be driven.

The capacitors 923 and 924 used in this embodiment are only examples of the auxiliary driving power source, but other auxiliary driving power sources may be used. At least during the above predetermined period, the prize ball count switch 301A and the ball lending count switch 3
01B, distribution solenoid 310, and payout control CPU
As long as it can drive the payout control means such as 371, an auxiliary drive power source of another aspect can be used.

In the processing of inputting the detection signal from the payout detecting means (switch detection processing), the payout control CPU 371.
First, the value m corresponding to the predetermined period is set in the counter for measuring the predetermined period (step S762). Then, the payout control CPU 371 decrements the value of the counter for measuring the predetermined period by -1 (step S763), and confirms the value of the counter for measuring the predetermined period (step S764). If the value is 0, the switch detection process is terminated, and the process proceeds to a power supply stop process which is a process for saving the control state.

If the value of the counter for measuring for a predetermined period is not 0, it is confirmed whether or not the prize ball count switch is on (step S765). This confirmation is performed by confirming the state of the flag for turning on the prize ball count switch, which will be described later. If the prize ball count switch ON flag is set, it is determined that the prize ball count switch is ON, the value of the detection period counter is decremented by 1 (step S766), and then the value of the detection period counter is set to 0. It is confirmed whether or not (step S767). If it is 0, the prize ball count switch 301 via the input port
If the detection signal of A is confirmed (step S768) and it is in the ON state, it is determined that the prize ball count switch 301A is surely turned on, and the value of the total number storage is decremented by 1 (step S769).

If it is confirmed in step S765 that the prize ball count switch is not on (the prize ball count switch ON flag is not set), the detection signal of the prize ball count switch 301A is confirmed via the input port. (Step S770) If it is in the ON state, the prize ball count switch ON flag is set (step S771), and the initial value n is set in the detection period counter (step S772).

By the above processing, when the prize ball count switch 301A is turned on within the predetermined period, the value of the total number memory is decremented by one. Since the processing for storing the contents of the backup RAM is performed after such a switch detection processing, the total number of stored prize balls is always -1. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the above switch detection processing, timer processing using a detection period counter is performed. That is,
Once the prize ball count switch 301A is detected to be on, the switch is turned on unless a predetermined time (n times the processing time in the loop from S763 to S767 and returning to S763: a game medium detection determination period) elapses. Not considered. That is, if the ON detection is performed after the predetermined game medium detection determination period elapses after the first ON detection, 1
It is considered that the prize balls have been paid out. Therefore, erroneous switch-on detection can be prevented.

In this case, for example, if n is set so that the game medium detection determination period is approximately 2 ms, the game medium detection determination period is set to the normal game medium detection determination period (not the power supply stop process, (A period of 2 ms or more until it is confirmed that the value of the prize ball count switch on flag is 2 in 751c in Fig. 53 described later) in this example. It is possible to have the same period as. According to this structure, it is possible to determine whether or not the prize ball count switch 301A is turned on under substantially the same conditions as in the normal control.

In the normal switch process (step S752 in FIG. 42), the timer process for preventing erroneous detection is also performed. Therefore, you may make it call such a switch process at the time of normal. Although the timer process using the detection period counter is performed here, the timer in the switch detection process using the CPU built-in timer may be used similarly to the case where the CPU built-in timer may be used in the case of measuring a predetermined period. The processing may be realized.

If the prize ball count switch is not ON and the ON state of the prize ball count switch 301A cannot be detected, switch detection processing is performed for the ball lending count switch 301B. That is, C for payout control
The PU 371 confirms whether or not the ball lending count switch is on (step S775). This confirmation is performed by confirming the state of the flag during ON of the ball lending count switch, which will be described later. If the ball lending count switch ON flag is set, it is determined that the ball lending count switch is on, the value of the detection period counter is decremented by 1 (step S776), and then the value of the detection period counter is set to 0. It is confirmed whether or not (step S777). 0
If so, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S77).
8) If it is in the ON state, it is determined that the ball lending count switch 301B is surely turned on, and the value of the stored number of lent balls is decremented by 1 (step S779).

In step S775, if it is confirmed that the ball lending count switch is not on (the ball lending count switch ON flag is not set), the detection signal of the ball lending count switch 301B is confirmed via the input port. (Step S780) If it is in the on state, the ball lending count switch ON flag is set (step S781), and the initial value n is set in the detection period counter (step S782).

By the above processing, when the ball lending count switch 301B is turned on within the predetermined period, the value of the number of lent balls memorized is decremented. The processing for saving the contents of the backup RAM is performed after such a switch detection processing, so that the number of lent balls is always -1 for the lent balls that have been paid out. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the above switch detection processing, timer processing using a detection period counter is performed. That is, unless the ball lending count switch 301B is turned on for a predetermined time (game medium detection determination period) or more, it is not considered to be switched on. That is, as in the case of detecting the payout of a prize ball, it is considered that the payout of one loan ball is completed when the ON detection is performed after a predetermined game medium detection determination period has elapsed after the first ON detection. Therefore, erroneous switch-on detection can be prevented.

Further, as in the case of the prize ball payout detection, for example, if n is set so that the game medium detection determination period is approximately 2 ms, the game medium detection determination period is set to the normal game medium detection determination period (power). A period for determining the presence / absence of a game medium in the normal game state, which is not the process at the time of supply stop.In this example, it is confirmed that the value of the ball lending count switch on flag is 2 in step S751h in FIG. The period can be the same as the period of 2 ms or more). With this configuration, the ball lending count switch 301 can be operated under almost the same conditions as the normal control.
It is possible to determine whether or not B is turned on.

When the predetermined period has elapsed (step S76)
4) The payout control CPU 371 stores the designated value with backup (“55H” in this example) in the backup flag (step S809). The backup flag is formed in the backup RAM area. Then
Parity data is created by performing the same processing as that of the CPU 56 of the main board 31 and is stored in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). After that, the built-in RAM cannot be accessed.

In this embodiment, the RAM area in which the data used in the payout control process is stored is backed up by power supply. Therefore, the checksum generation process indicating whether the contents are correctly stored, and R for preventing the contents from being rewritten
The AM access prevention process corresponds to the process for storing the payout control state.

As described above, in this embodiment, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the ball payout device 97 is stopped, and then the payout detecting means outputs a predetermined period. Input processing of the detection signal is executed, and then processing for saving the payout control state is performed. Therefore,
The game balls that were being paid out when the power failure occurred are also reflected in the saved contents of the backup RAM.

That is, in this embodiment, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent the control contradiction from occurring.

Further, in this embodiment, when the game medium detecting means detects ON twice in succession before and after the predetermined game medium detection judgment period, the payout of one prize ball or loan ball is completed. Therefore, it is possible to prevent erroneous switch-on detection. Therefore, it is possible to optimize the control when the power is off.

As described above, in this example, the clearing process of the output ports other than the output port of the distribution solenoid 310 is performed before the switch detection process is executed (before step S762). During execution of the power supply stop process, the payout control CPU 371 and switches are connected to the capacitor 92.
It will be driven by the charging power of 3,924 or the like. In this example, since the output port clearing process is performed before the switch detection process is executed, the capacitor charging power and the like can be efficiently used for the power supply stop process.

When the access prohibition value is set in the RAM access register, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

[0320] Here, the prize ball count switch 3
Timer (counter for detection period) when the detection signal of 01A or ball lending count switch 301B indicates the ON state
Is set, and if the detection signal shows the ON state even when the timer times out, it is determined that the switch is surely turned ON. However, like the CPU 56 of the main board 31,
The detection signal may be determined each time the ms timer (2 ms measurement counter) times out.

Also in this embodiment, the register saving process is performed at the beginning of the process started in response to the power-off signal, but if the register is not used in the switch detecting process, the switch detecting process is performed. The register saving process can be performed after the execution, that is, before the process of setting the backup flag and calculating the checksum. In that case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as the power supply stop process. Further, even when some registers are used in the switch detection process, the register saving process can be performed on the unused registers before the backup flag setting and the checksum calculation process.

FIG. 48 is an explanatory diagram showing a usage example of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number memory (for example, 2 bytes) and a rental ball number memory are formed.
The total number storage stores the total number of prize ball payout numbers instructed from the main board 31 side. The loaned ball number storage is for storing the number of unpaid lent balls. In addition,
The backup RAM area is not limited to the area for storing the above-mentioned information regarding the number of game balls, and various kinds of flags such as a flag indicating an error state such as a payout stop flag, an award ball path error flag, and a backup flag, which will be described later, for example. An area for storing flags, an area for storing various buffers such as a reception command buffer, and the like are also formed. Further, the RAM area in which the data used in the payout control process is stored may be backed up by power supply.

Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in the prize ball control processing (step S757), the payout control CPU 371 stores the total number of stored contents in the total number storage. To increase. In addition, in the ball lending control process (step S756), the content is increased in the lending ball number storage by one unit (for example, 25) each time the ball lending request signal is received from the card unit 50. Further, the payout control CPU 3
71 is the prize ball count switch 3 in the prize ball control processing.
When 01A detects the payout of one prize ball, the value of the total number of balls stored is decremented by 1. When the ball lending count switch 301B detects the payout of one ball, the value of the stored number of lent balls is decremented by 1.

Therefore, the number of unpaid prize balls and the number of lent balls are backup RAs that can retain their contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply interruption such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the stored contents of the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is made based on the number of unpaid prize balls and the number of lent balls when the power supply is stopped, and is given to the player. The disadvantage can be reduced.

FIG. 49 is an explanatory diagram showing an example of the structure of a reception buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type reception buffer that can store six 2-byte payout control commands is used. Therefore, the reception buffer is composed of 12-byte areas of the reception command buffers 1 to 12. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter takes a value of 0-11.

FIG. 50 is a flow chart showing the payout control command receiving process by the interrupt process. The payout control INT signal from the main board 31 is sent to the payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 50 is started. In addition, CP for payout control
The U371 is a CPU having a structure in which, when an interrupt occurs, no further maskable interrupt occurs unless the interrupt is permitted by software.

Although the command receiving process of the payout control means will be described here, the same command receiving process is executed by the display control means, the lamp control means and the sound control means. In this embodiment, CLK /
Although the initial setting was made such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the TRG2 terminal rises, that is, the initial setting is made such that an interrupt occurs at the rising edge of the INT signal. CLK / TRG
When the input of 2 terminals falls, timer counter register C
Initialization may be performed such that the value of LK / TRG2 is decremented by one. In other words, the initialization may be performed so that an interrupt occurs at the falling edge of the INT signal.

That is, if the interrupt is generated at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the capture signal, the edge may be a rising edge or a falling edge. It may be. In any case, the interrupt is configured to occur at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the acquisition signal. By doing so, it becomes possible to receive the command promptly at the stage when the command acquisition is instructed. In addition, the period of A (Fig. 3
Since the output of the INT signal is waited until 4) has elapsed, the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output.
Therefore, the payout control command is properly received by the payout control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
Data is read from 72a (see FIG. 9) (step S
851). Then, it is confirmed whether or not it is the first byte of the payout control command having a 2-byte structure (step S8).
52). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is "1". The head bit is "1" in the MODE byte (first byte) of the payout control command having a 2-byte structure (see FIG. 33). Therefore, if the leading bit is "1", the payout control CPU 371 determines that the valid first byte has been received and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step). S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

If the first byte has already been received,
It is confirmed whether the first bit of the received 1 byte is "0". If the first bit is "0",
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The head bit should be "0" in the EXT byte (second byte) of the payout control command having a 2-byte structure (see FIG. 33). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not "0". If it is determined as "N" in step S854, the process of step S856 is not performed, so the command received next is stored in the buffer area where the command received this time should have been stored. It

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether the command reception counter is 12 or more (step S857), and if it is 12 or more, the command reception number counter is cleared (step S858). After that, the saved registers are restored (step S859),
Finally, the interrupt permission is set (step S859).

During the command reception interrupt process, the interrupt is disabled. As described above, since the interrupt is enabled during the 2ms timer interrupt process, if a command reception interrupt occurs during the 2ms timer interrupt process, the command reception interrupt process is executed with priority. It Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since the other interrupt processing is not executed during the command receiving processing, the maximum time required for the command receiving processing is determined. If the other interrupt processing can be executed during the command receiving processing, it is difficult to estimate the maximum time required for the command receiving processing. Since the maximum time required for the command receiving process is determined, the period C in the command sending process of the game control means (see FIG. 34)
Can be accurately determined.

Also, the payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX
It is configured so that it can be immediately distinguished from T) on the receiving side.
That is, the receiving side can immediately detect whether the data as MODE or the data as EXT is received by the first bit. Therefore, as described above, it is possible to easily determine whether or not proper data has been received.

In this embodiment, in the command reception interrupt processing, control for storing the received command in the reception buffer is performed. However, the payout stop state setting processing (see FIG. 52) and the command analysis execution processing described later are performed. (See Figure 53)
May be configured to be executed in the command reception interrupt processing. In this way, when even the command determination processing for determining the command in the reception buffer is executed in the command reception interrupt processing, the command determination is also executed promptly.

FIG. 51 is a flow chart showing an example of the switch process of step S751. In the switch processing, the payout control CPU 371 confirms whether or not the prize ball count switch 301A is in the ON state (step S751a). If it is in the ON state, the payout control CPU 371 increments the prize ball count switch ON counter by 1 (step S751b). The prize ball count switch on counter is the prize ball count switch 30.
This is a counter for counting the number of times the ON state of 1A is detected.

Then, the value of the prize ball count switch ON counter is checked (step S751c), and if the value is 2, it is determined that one prize ball has been paid out. When it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball unpaid counter (the number of prize balls stored in the total number memory) by -1 (step S751d).

When it is confirmed in step S751a that the prize ball count switch 301A is not turned on, the payout control CPU 371 clears the prize ball count switch ON counter (step S751e). And in this embodiment, the ball lending count switch 3
It is confirmed whether or not 01B indicates the ON state (step S751f). If it is in the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by 1 (step S751g). Ball lending count switch ON counter is ball lending count switch 301
This is a counter for counting the number of times the ON state of B is detected.

Then, the value of the ball lending count switch on counter is checked (step S751h), and if the value is 2, it is determined that one ball has been paid out. When it is determined that one loan ball has been paid out, the payout control CPU 371 causes the loan ball unpaid number counter (the number of loan balls stored in the loan ball number storage).
Is decremented by 1 (step S751i).

When it is confirmed in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch ON counter (step S751j).

FIG. 52 is a flow chart showing an example of the payout stop state setting process of step S753. In the payout stop state setting process, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S753a). If there is a receive command in the receive buffer, it is confirmed whether the received payout control command is a payout stop state designation command (step S).
753b). If it is the payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S753c).

When it is confirmed in step S753b that the received command is not the payout stop state designation command, it is confirmed whether or not the received payout control command is the payout possible state designation command (step S753d). If it is the payable state designation command, the payout stop state is canceled (step S753e).

When setting the payout stop state,
For example, the driving of the payout motor 289 is stopped, and an internal flag (payment stopped flag) indicating that the payout is stopped is set. When the payout stop state is released, the driving of the payout motor 289 is restarted and the payout stop flag is reset. That is, in step S753c, data indicating that payout is prohibited (set payout suspension flag)
Is being executed in the predetermined storage area, and in step S753e, the processing for storing the data indicating that the payout is permitted (the reset payout suspension flag) in the predetermined storage area is executed. It is running.

The payout suspension flag is stored in, for example, the backup RAM area. The payout suspension flag has a 1-byte structure including bits D0 to D7, for example. In this case, for example, if D0 is "1", it indicates the state in which the dispensing stop state is set, and if D1 is "1", it indicates the state in which the dispensing stop state is released. Further, D2 is used, for example, to indicate that it is in a waiting state for returning after the payout stop state is released. Note that D3 to D7 are unused areas.

Now, the state of the payout suspension flag in the process of FIG. 52 will be specifically described. Step S753c
In the process of, the payout control CPU 371 sets D0 of the payout suspension flag to “0” and sets D1 to “1”. In the process of step S753e, the payout control CPU 371 sets D0 of the payout suspension flag to “1”, sets D1 to “0”, and sets D2 to “1”. When D2 is set to "1", the payout control CPU 371 sets D2 to "0" after a predetermined period (for example, 1 [s]) has elapsed. In this example, the payout suspension flag indicates that when D0 is "0" and D1 is "1",
Indicates that the dispensing is stopped. Further, when D0 is "1" and D1 is "0", it indicates that the payout permission state (the payout stop state is released). Note that the payout suspension flag may have a configuration other than the 1-byte configuration, and each bit may be used in another manner (for example, by using only D0, D0 is " The payout stop state may be indicated when "0", and the payout permission state may be indicated when D0 is "1").

When the payout stop state is set, the payout motor 289 may be stopped immediately, but instead of performing such control, the payout motor 289 is cut at a good cutting point.
May be stopped. For example, the payout of the game balls may be executed in units of 25, and the payout motor 289 may be stopped when the payout of one unit is completed, and the internal state may be set to the payout stop state. As mentioned above,
Since the ball break switch 187 is installed at a position where it can detect that there are 27 to 28 gaming balls in the payout ball passage, even if the game control means of the main board 31 detects the ball breaking. From that point on, at least 25 payouts are possible. Therefore, there is no problem even if the payout is stopped at the time when one unit of payout is completed. Further, if the payout is stopped at the unit of one unit, the control when the payout is restarted becomes easy.

FIG. 53 is a flow chart showing an example of the command analysis execution processing of step S754. In the command analysis execution processing, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S754a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for designating the number of prize balls (step S7).
54b). The payout control CPU 371 makes a determination in step S754b for the received command stored at the address in the receive buffer pointed to by the read pointer as the command instruction means. After the determination, the value of the read pointer is incremented by +1. When the address pointed to by the read pointer exceeds the address of the reception command buffer 12 (see FIG. 49), the value of the read pointer is updated to point to the reception command buffer 1.

If the received payout control command is a payout control command for designating the number of prize balls, the number instructed by the payout control command is added to the total number storage (step S754c). That is, the payout control CPU 371
Stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

The payout control CPU 371 performs the subtraction of the command reception number counter and the reception command shift processing in the reception buffer, if necessary. Further, the payout stop state setting process and the command analysis execution process may be repeated until the value of the read pointer and the latest command storage position in the reception buffer match. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands, but the repeated processing is executed until they match. , There are no outstanding received commands. That is, all the received commands stored in the reception buffer are read and processed in one process.

FIG. 54 is a flow chart showing an example of the prepaid card unit control process of step S755. In the prepaid card unit control process, the payout control CPU 371 confirms whether or not the VL signal input from the card unit control microcomputer is detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Further, the payout control CPU 37
1 confirms whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CP
The U371 stops the output of the firing control signal to the firing control board 91 and stops the drive motor 94 (step S7).
55d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) When the OFF of the VL signal is continuously detected, the ball firing prohibition state is set.

If the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output control signal output is stopped (step S755f), the payout control CPU 371 starts the output control signal output to the discharge control board 91 to put the drive motor 94 into an operable state (step S755g). .

55 and 56, step S756 is executed.
It is a flow chart which shows an example of the ball lending control processing of.
In addition, in this embodiment, the maximum value of the continuous payout number is one unit (for example, 25) of the lending sphere, but the maximum value of the continuous payout number may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is suspended (step S510). If it is stopped, the process ends.
Whether or not the ball lending is being stopped is confirmed by whether or not the payout in-progress flag set in the payout stop state setting process shown in FIG. 52 is turned on.

If the ball lending is not stopped, the payout control CP
The U371 confirms whether or not the ball lending is being issued (step S511), and if the ball lending is being delivered, the process shifts to the ball lending process shown in FIG. In addition, whether or not the lent-out of the lent-out sphere is being performed is determined by the state of the lent-out-of-ball-lending flag described later. If the loan balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S512). Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending balls nor the prize balls are being paid out, the payout control CPU 371 confirms whether or not there is a ball lending request from the card unit 50 (step S5).
13). When there is a request, the ball lending processing flag is turned on (step S514), and 25 (one unit of ball lending: 100 yen here) is set in the backup RAM area storage of the number of lending balls (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout control CPU 371 sets the motor rotation time for paying out the 25 game balls, or determines the number of output pulses corresponding to the motor rotation time. Then, the payout motor 289 is turned on (step S51
8), and shifts to the processing during ball lending shown in FIG.

The payout motor 289 is turned on as follows.
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the acceptance. The ball lending processing flag is set in the backup RAM area.

FIG. 56 is a flow chart showing the processing during ball lending in the payout control processing by the payout control CPU 371. In the ball lending process, the payout motor 289 is turned on if it is not turned on. In addition, in this embodiment,
In the switch processing of step S751, it is confirmed whether or not the game balls have been paid out based on the detection signal of the ball lending count switch 301B. Therefore, in the ball lending control processing, the storage of the number of loaned balls is not subtracted.

CP for payout control in the ball lending control process
U371 confirms whether or not it is in the waiting time for passing the loan ball (step S519). If it is not during the waiting time for passing the rental ball, the rental ball is paid out (step S520),
It is confirmed whether or not the driving of the payout motor 289 should be ended (whether one unit of payout operation is ended) (step S52).
1). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522).
The lending ball passage waiting time is set (step S52).
3).

If it is in the lending ball passage waiting time in step S519, the payout control CPU 371 confirms whether or not the lending ball passage waiting time has ended (step S52).
4). The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all of the one unit of lending balls have been paid out, so that it is possible to indicate to the card unit 50 that the next ball lending request can be accepted. The EXS signal is turned off (step S525). The distribution solenoid is turned off (step S5).
26), turn off the ball lending processing flag (step S5)
27). If the last payout ball has not passed the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. Also,
In this embodiment, prize balls and ball lending are performed by the same payout device.

After turning off the EXS signal indicating acceptance of the ball lending request, if the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period, the ball lending is performed without turning off the distribution solenoid and the payout motor. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be continuously executed.

The content of the number of lent balls is stored by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the game machine is stopped. Therefore, when the power supply is restored within the predetermined period, the payout control CPU 371 can continue the ball lending process based on the content of the loan ball number storage.

57 and 58, step S757 is executed.
It is a flow chart which shows an example of the prize ball control processing. In addition, in this example, the maximum value of the continuous payout amount is set to the same number as one unit of the lending sphere (for example, 25), but the maximum value of the continuous payout amount may be another number.

In the prize ball control processing, the payout control CPU
The 371 first confirms whether or not the prize ball is stopped (step S530). If it is stopped, the process ends. Whether or not the prize balls are stopped is confirmed by whether or not the payout stopping flag set in the payout stopping state setting process shown in FIG. 52 is turned on.

If the prize ball is not stopped, the payout control CPU
The 371 confirms whether or not the lending balls are being paid out (step S531), and if the lending balls is being paid out, the process is ended. Whether or not the ball lending is being paid out is determined by the state of the ball lending processing flag. If the payout of the rented balls is not in progress, it is confirmed whether or not the prize ball payout processing has already been started, that is, whether or not the prize balls are being paid out (step S53).
2). If it is in the prize ball, the process moves to the process in the prize ball shown in FIG. Whether or not a prize ball is in play is determined by the state of a prize ball processing flag, which will be described later.

If the prize balls are not being paid out, the payout control CPU
371 confirms whether the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number memory is 2.
It is confirmed whether it is 5 or more (step S536). The prize ball processing flag is set in the backup RAM area.

When the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 instructs the payout motor 289 to rotate the payout motor 289 until the 25 game balls are paid out. In order to output the drive signal by the operation, the 25-piece payout operation is set (step S53).
7). Specifically, the motor rotation time for paying out the 25 game balls is set, and the number of output pulses corresponding to the motor rotation time is determined.

If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 rotates the payout motor 289 until the game balls corresponding to the number stored in the total number memory are paid out. In order to output the drive signal so as to perform the above operation, the all-pieces payout operation is set (step S538). Specifically, the motor rotation time for paying out the game balls is set, and the number of output pulses corresponding to the motor rotation time is determined. Next, the payout motor 289 is turned on (step S539). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the prize ball side. Then, the process shifts to the process of paying out prize balls in the prize ball control process shown in FIG.

FIG. 58 is a flow chart showing an example of a prize ball process in the payout control process by the payout control CPU 371. In the prize ball control processing, the payout motor 289
If is not on, turn it on. In this embodiment, in the switch processing of step S751, it is confirmed whether or not the game balls have been paid out by the detection signal of the prize ball count switch 301A. Is not done.

[0370] The payout control CPU in the process of winning a prize
The 371 confirms whether or not it is during the prize ball waiting time (step S540). If it is not during the prize ball passage waiting time, whether or not the prize balls should be paid out (step S541) and the driving of the payout motor 289 should be ended (whether the payout operation of 25 or a predetermined number of less than 25 has ended). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the prize ball passage waiting time (step S544). The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

If it is during the prize ball passage waiting time in step S540, the payout control CPU 371 confirms whether or not the prize ball passage waiting time is over (step S545).
When the prize ball waiting time is over, step S537
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
If the award ball passage waiting time has ended, the award ball processing flag is turned off (step S546). If the last payout ball has not passed the prize ball count switch 301A before the prize ball passage waiting time has elapsed, a prize ball path error is determined.

In this embodiment, step S5
11, the ball lending is prioritized over the prize ball processing according to the determination in step S531, but the prize ball processing may be prioritized over the ball lending.

The contents of the total number storage and the number of rented balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored within a predetermined period, the payout control C
The PU 371 can continue the payout process based on the content of the total number storage.

Although the payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number memory, the prize ball number is stored for each prize ball number (for example, 15, 10, 6).
Individual). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, the subtraction process is performed in the payout control process).
Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored within the predetermined period, the payout control CP
The U371 can continue the prize ball payout process based on the contents of the respective number counters.

In this embodiment, the payout control means detects that the INT signal relating to the payout control signal has risen, and starts the process of fetching 1-byte data by, for example, an interrupt process. Since a receiving ring buffer (a receiving buffer in this example) capable of storing a plurality of payout control commands is provided, after the payout control command is received, the next payout control command is issued before the control based on the command is started. The receipt of the command does not mean that the command is not received by the payout control means.

In the payout control means, the interrupt process is activated even in the payout stop state, so that the payout control means can receive the payout control command even when the payout is stopped. Then, while the payout is stopped, the payout process according to the received payout control command is stopped, but since a receiving ring buffer capable of storing a plurality of payout control commands is provided, it is sent from the game control means. The payout control command does not disappear in the payout control means.

Then, in the payout control means, a command reception number counter is used as an address designating means for indicating in which area in the reception ring buffer the transmission command is stored. Therefore, it is easy to determine which area should be used.

In the above embodiment, the case where the RAM is used as the fluctuation data storage means is shown. However, as the fluctuation data storage means, any electrically rewritable storage means other than RAM can be used. You may use.

Further, in the above embodiment, the power supply monitoring means is provided on the power supply board 910 and the circuit for generating the signal for system reset is provided on the electric part control board. It may be provided on the substrate.

As described above, in the power supply stoppage process (see FIGS. 19 to 21 and 45 to 48), the capacitors 923 and 92 are operated until the detection maintaining period elapses.
The power supply board 910 (which is a board having a function of an auxiliary power supply means and an operation state holding means) uses the electric power charged to 4 and a prize ball count switch 301A (an example of prize game medium detection means) and a ball. While supplying electric power capable of driving the lending count switch 301B (an example of a lending game medium detecting means), a solenoid 310 (an example of a passage switching means) supplies driving power for holding the state of the distribution member 311. The game control means (CPU 56) performs input processing of the detection signal from the prize ball count switch 301A (steps S460 to S480), and the payout control means (payout control CPU 371) has the prize ball count switch 301A and the ball lending count switch 301B.
Since the processing for inputting the detection signal from (step S762 to step S782) is performed, the prize gaming medium paid out in the power supply stop process (the game paid as a prize based on the winning in the winning area) It is possible to reliably detect a medium) and a rental game medium (a game medium that is rented in response to a lending request from a player).
That is, according to the above-mentioned gaming machine, it is possible to reliably execute the detection of the game medium paid out in the power supply stop process, so that the number of unpaid game media can be accurately grasped. become.

Further, as described above, until the detection maintaining period elapses, the converter IC 920 (an example of the operation state holding means) can drive the distribution member 311 with respect to the solenoid 310. Is supplied, it is possible to maintain the drive state of the solenoid 310 as the passage switching means by an electrical configuration. Since it is configured as above,
The converter IC 920 functions as an auxiliary drive power supply unit that supplies power for maintaining the state of the distribution member 311 until the detection maintaining period elapses.

Further, as described above, in the above embodiment, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the ball payout device 97 is stopped, and then the predetermined detection maintaining period is reached. , Payout detecting means (prize ball count switch 3
01A or the ball lending count switch 301B) is input with a detection signal, and then a process for saving the payout control state is performed. Therefore, the game balls that were being paid out when the power failure occurred are also reflected in the saved contents of the backup RAM. Therefore, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent a contradiction or the like from occurring between the stored control state and the actual control state. it can.

In the above-described embodiment, the payout control means sets the prize ball count switch 301A and the ball lending count switch 301B in the power supply stop process.
Although it is configured to confirm whether or not each switch is turned on, the configuration may be configured to confirm the state of either one of the switches.

FIGS. 59 to 61 show non-maskable interrupt processing (NMI) executed in response to a power-off signal from the power supply board 910 in the case of confirming the state of one of the switches as described above. It is a flowchart which shows the example of a process of a process: power supply stop process. In addition, FIG.
Detailed description of the processes and the like already described with reference to FIGS.

In the non-maskable interrupt process, the payout control CPU 371 executes steps S801 to S808.
After performing the process of step S821 to step S8
The output port clear process shown in 27 is performed. After that, in this embodiment, a detection signal of a prize ball count switch 301A (corresponding to prize game medium payout detection means) or a ball lending count switch 301B (corresponding to rental game media payout detection means) for a predetermined period (detection maintaining period) Check.
In this example, the detection signal is checked only for the switches that may detect the game ball. When the switch that may be detected is the prize ball count switch 301A, the prize ball count switch 301A is checked, and when it is turned on, the content of the total number storage is decremented by one. Also,
If the switch that may be detected is the ball lending count switch 301B, the ball lending count switch 3
If 01B is checked and turned on, the content of the number of lent balls is reduced by 1.

In this example, the payout control CPU 371 is
It is confirmed whether or not the award ball processing flag is turned on (step S828). If the award ball processing flag is turned on, it means that the award ball is being processed, and therefore the award ball count switch 301A may detect the award ball. To determine. If the prize ball processing flag is not on, the payout control CPU 371 confirms whether the ball lending processing flag is on (step S8).
29) If it is on, it is determined that the ball lending count switch 301B may detect the ball lending because the ball lending process is being performed.

In this example, the counter for measuring the predetermined period is used to measure the predetermined period regardless of which switch is checked. When the prize ball count switch 301A is checked, the value of the counter for measuring the predetermined period is from the initial value m to a loop of prize ball count switch detection processing (loop starting from S763 and returning to S763) described below. It is decremented by 1 each time it is executed, and when the value becomes 0, it is assumed that the predetermined period has ended.
Further, when checking the ball lending count switch 301B, the value of the counter for measuring the predetermined period is from the initial value m, the loop of the ball lending count switch detection process described below (loop starting from S763a and returning to S763a). -1 is executed every time is executed, and when the value becomes 0, it is assumed that the predetermined period ends. Although there is an exception in the detection processing loop, substantially constant processing is performed, and therefore a time that is m times the time required for one round of the loop corresponds to a substantially predetermined period. The internal timer of the payout control CPU 371 may be used to measure the predetermined period.

If the prize ball in-process flag is turned on in step S828, the payout control CPU 371 executes a process of inputting a detection signal from the prize ball count switch 301A (prize ball count switch detection process). In the prize ball count switch detection process, the payout control CPU 371 first sets a value m corresponding to a predetermined period in a predetermined period measurement counter (step S762). Then, the payout control CPU 371 sets the value of the counter for measuring the predetermined period to −1.
(Step S763), the value of the counter for measuring the predetermined period is confirmed (step S764). If the value is 0, the prize ball count switch detection process is terminated and the process proceeds to the power supply stop process which is a process for storing the control state.

If the value of the counter for measuring the predetermined period is not 0, the step S765 is performed as in the case of FIG.
-The process of step S772 is performed. However, in the prize ball count switch detection processing, if the value of the detection period counter is not 0 in step S767,
In either case, when the prize ball count switch 301A does not indicate the ON state in 770, or when the initial value n is set in the detection period counter in step S772, the process in step S763 is performed after those processes. Return. By the above processing, if the prize ball count switch 301A is turned on within the predetermined period, the value of the total number memory is -1.
To be done.

If the ball lending processing flag is turned on in step S829, the payout control CPU 371 executes a process of inputting a detection signal from the ball lending count switch 301B (ball lending count switch detection process). In the ball lending count switch detection processing, the payout control CPU 371
First, a value m corresponding to a predetermined period is set in the counter for measuring the predetermined period (step S762a). And
The payout control CPU 371 decrements the value of the counter for measuring the predetermined period by -1 (step S763a), and confirms the value of the counter for measuring the predetermined period (step S764a). If the value is 0, the ball lending count switch detection process is terminated, and the process proceeds to the power supply stop process which is a process for saving the control state.

If the value of the counter for measuring the predetermined period is not 0, as in the case of FIG. 46 described above, step S775.
-The process of step S782 is performed. However, in the ball lending count switch detection processing, if the value of the detection period counter is not 0 in step S777, or if the ball lending count switch 301B is not in the ON state in step S780, in step S782. In any case where the initial value n is set in the detection period counter, the processing returns to step S763a after the processing. By the above processing, when the ball lending count switch 301B is turned on within a predetermined period, the value of the number of lent balls memorized is decremented by one.

Also, step S828 and step S82.
If both the prize ball processing flag and the ball lending processing flag are not turned on at 9, prize ball count switch 301A
Since there is no possibility of turning on both the ball lending count switch 301B and the ball lending count switch 301B, the payout control CPU 371 performs a process such as saving the contents of the backup RAM similar to the process of FIG. 47 described above without checking the switch ( After performing steps S809 to S820, a standby state (loop state) is entered.

As described above, when there is no possibility that a game ball will be detected, neither the prize ball count switch 301A nor the ball lending count switch 301B is detected. It can be omitted, and the processing at the time of stopping the power supply (FIGS. 59 to 61) can be quickly performed. That is, when it is not necessary to confirm the payout state of the lent balls and the prize balls, the detection signal output when the payout of the game medium is detected is not input. The processing can be performed quickly.

As described above, of the prize ball count switch 301A or the ball lend count switch 301B, the detection state is selectively confirmed only for the switch in which the game ball may be detected. Thus, useless processing can be omitted. Also, FIG.
Since the processing period of the switch detection loop processing shown in FIGS. 59 and 60 is shorter than that of the switch detection processing loop processing shown in FIG. 5 and the like, even if the value set in the predetermined time measurement counter is the same, Also, since there is a difference in the processing period in the final loop processing, the above configuration allows the power supply stop processing (FIGS. 59 to 61) to be quickly performed. Therefore, as compared with the case where the power supply stop process shown in FIG.
The capacity of 3,924 can be reduced.

In the above example, when the award ball processing flag is not on, the state of the ball lending processing flag is confirmed. The switch detection process may be executed. Further, the state of the ball lending processing flag may be confirmed without checking the prize ball processing flag, and the prize ball count switch detection processing may be executed immediately if the ball lending processing flag is not on. According to this structure, it is possible to quickly confirm the state of the switch that has a possibility of being detected.

In the above example, neither the detection state of the prize ball count switch 301A nor the ball lending count switch 301B is confirmed, or the detection state of either the prize ball count switch 301A or the ball lending count switch 301B is set. Although the confirmation is performed, both the prize ball count switch 301A and the ball lending count switch 301B may be confirmed. With this configuration, it is possible to recognize whether the prize ball or the loan ball is detected when the detection signal is input, without checking which switch the detection signal is from. be able to. For example, if the detection signal from the count switch is input after confirming that the prize ball processing flag is turned on, the payout control CPU
It suffices that the 371 recognize that the detection signal from the prize ball count switch 301A has been input. Therefore, if configured as described above, whether the detected game ball is a prize ball or a loan ball even if the game ball paid out by one count switch for prize balls and ball lending is detected Can be accurately determined.

Further, in each of the above-described embodiments, the distribution member 311 is arranged to fall down so that the game ball flows down to the ball lending side / prize ball side in accordance with the turning on / off of the solenoid 310. The position where the distribution member 311 falls may be controlled by a motor, and the distribution member 311 may alternately fall to the ball lending side / prize ball side each time the motor is turned on. In this configuration, the distribution member 311 will continue to maintain the current state unless the motor is newly turned on. Therefore, by configuring as described above, the distribution member 3 has a mechanical structure in the power supply stop process regardless of the voltage state of the drive power source of the motor.
The state of 11 can be maintained. In the case of the above configuration, in the restoration process (see FIG. 44) or the initialization process after the power supply is started,
The process of returning the state of the distribution member 311 to the initial state (for example, the state in which the game ball flows down to the ball lending side) may be executed. If the sorting member 311 can be alternately tilted to the ball lending side / prize ball side each time a predetermined process is performed, a member other than the motor (for example, a latch-type solenoid) should be used. May be. In the case of the above-described configuration, the motor that controls the position where the distributing member 311 falls down functions as the passage switching means, and the distribution that has a mechanism that can maintain the current state unless there is a drive signal from the motor. The member 311 will function as an operation state holding means. Further, the mechanism of the distribution member 311 capable of maintaining the state of the ball lending side / prize ball side functions as a holding mechanism capable of holding the state of the passage switching means until the detection maintaining period elapses. Become.

In each of the above embodiments, n is set so that the game medium detection determination period (the period measured by the detection period counter) is approximately 2 ms (step S772).
Or step S782) may be set. However, for example, a predetermined delay period (step S763) is executed after step S763 so that the loop processing of returning from step S763 to step S763 is executed every 2 ms. 2m
(A period obtained by subtracting the period required for normal loop processing from s)
It may be configured to perform a process of delaying until elapse. The delay period may be measured by, for example, a software timer. Note that step S763a
The same applies to the loop processing that returns from step S763a. Further, the period may be other than 2 ms.

Further, in each of the above embodiments, in the power supply stop process, it is monitored whether or not the game balls have been paid out, and when the game balls have been paid out, it is stored as the number of unpaid game balls. Although the process of subtracting the stored value (step S474, step S769, step S779) was performed, the prize ball count switch 301A and the ball lending count switch 30 are not performed without the process of subtracting the stored value of the unpaid amount.
The configuration may be such that it is confirmed whether or not the 1B is turned on, and the confirmation result is stored in the RAM whose power is backed up. In this case, in the recovery process (see FIGS. 17 and 44) after the power supply is started, the prize ball count switch 301A and the ball are switched while the power supply stop process is being executed based on the stored contents of the RAM backed up by the power supply. If it is confirmed that the lending count switch 301B is turned on, a process of subtracting the stored value of the unpaid amount may be performed. As described above, when the prize ball count switch 301A or the ball lending count switch 301B is turned on in the power supply stop process, the award ball count switch 301A or the ball lending count switch 301B is updated without updating the unpaid amount. If the configuration is such that the result of the input processing of the detection signal of is saved and the number of unpaid amounts is updated according to the saved input process result at the time of restoration, it is stored as the unpaid amount in the power supply stop process. Since it is not necessary to perform the process of changing the value being processed, it becomes possible to finish the process quickly, and the process executed to manage the number of unpaid gaming balls before the power supply is stopped It can be completed more reliably. It should be noted that an example of the above-described configuration is realized in Embodiment 3 described later.

As described above, if the power supply stop process is quickly completed, it is possible to prevent a fraudulent act which causes a big hit by causing a stack overflow and executing an initialization process. That is, even if the power supply is not stopped, if the power-off signal is continuously input to the signal line from the detection circuit side that detects power-off to the interrupt terminal of the microcomputer, the stack Although the size of the area is limited, the data is repeatedly stored in the stack area due to the repeated interrupt processing, which eventually causes a stack overflow. As a result, the contents of the RAM area are destroyed due to the stack overflow, and the program runaway occurs. Therefore, the watchdog timer times up, the microcomputer is reset, and the contents of the RAM area are lost. Is initialized. Whether or not to generate a big hit is generally a big hit in which a count value of a random number generation counter formed in the RAM area is predetermined at a predetermined timing (for example, when a start prize is generated, that is, when a start prize signal is input). It is determined by whether or not it matches the judgment value. When the power-off signal is continuously input, the system is reset as described above, and the RAM contents are initialized in the initialization process, so a random number is generated to determine whether or not a big hit should be generated. The count value of the use counter is also initialized (returned to 0). Then, since the count value starts from 0, it is possible to easily grasp the timing when the count value coincides with the predetermined jackpot determination value. In other words, a fraudulent means such as a fraudulent board is mounted on a gaming machine, and a power-off signal (interrupt signal) is continuously input to the microcomputer from the fraudulent means, and the count value of the random number generation counter is the jackpot judgment value It is possible to illegally generate a big hit by illegally sending a start winning signal to the game control board on which the microcomputer is mounted at a timing that coincides with. In the above example, the power supply stop process is performed quickly, so the power supply stop process based on the input of the first power supply stop signal is completed before the power supply stop signal is continuously input due to an illegal act. You can increase the possibility that you are doing. Therefore, even if an illegal act such as illegally sending an interrupt signal is performed, it can be expected to invalidate the act. Even when the power supply stop process is quickly ended by another configuration described later (for example, a switch check in the power supply stop process is performed only for prize balls or loan balls), The same effect can be obtained.

Further, in each of the above-mentioned embodiments, the ball payout device 97 pays out the prize balls and the lending balls, and the distribution solenoid 31.
By the distribution member 311 driven by 0, the prize ball downflow path (prize game medium path) and the rental ball downflow path (rental game medium path) were switched. However, a payout device for paying a prize ball and a payout device for lending a ball may be separately provided.

Furthermore, in each of the above-described embodiments, the stepping motor that rotates in response to the pulse signal (driving signal) from the payout control CPU 371 is used as the payout motor 289, but a solenoid may be used. In this case, in the power supply stop process,
The process of stopping the driving of the payout motor 289 may be performed before the process of confirming the state of the prize ball count switch 301A or the ball lending count switch 301B (for example, before step S762). According to this structure, even if the payout motor 289 is configured by using the solenoid, the power consumption can be suppressed.

Embodiment 2. FIG. 62 is a control command (payout control command, display control command, lamp control command) transmitted from the main board 31 to each of the other electric component control boards (sub-boards) in the second embodiment (Embodiment 2). , Sound control command). In this example, a control command of a form different from that of the above-described embodiment is used. That is, 8-bit command data is output from the output port (output port 1) 571 of the main board 31 shown in FIG.
Interrupt signal and strobe signal (STB signal) from 0
Is output. The interrupt signal is input to the interrupt terminal of the display control CPU 101. Further, the STB signal is input to the I / O port.

As shown in FIG. 62, after the command data is output from the main board 31 (main), the interrupt signal and the STB signal are turned on. In this way, the game control means, in relation to the output of the command data, instructs the input of the command data to the electric component control means at the same timing as the output timing of the data outputting signal (STB signal in this example). It outputs an interrupt signal as an instruction signal for.

After that, the interrupt signal from the main is turned off, and the STB signal from the main is turned off at the timing after the electric component control means of the sub-board completes the command receiving process.

FIG. 63 is a flowchart showing an example of command control processing for transmitting a payout control command. The command control process for transmitting the payout control command is executed, for example, in the prize ball process of step S32 in the flowchart shown in FIG. In the command control process for transmitting the payout control command, the CPU 56 stores the output content of the output port 1 (the area for storing the output content of the output port 1. The payout control command for making a request to send the payout control command) Command data of the payout control command to be sent is written in (provided corresponding to the send request flag) (step S321). Then, the payout control command transmission request flag is set (step S322). In step S321, command data is written in another area of the backup RAM instead of the output port 1 output content storage area, and when the command data is actually output to the output port 1, the command is output to the output port 1 output content storage area. It may be configured to write data.

For example, any one of 01 (H) to 0F (H) is used as a payout control command for designating the number of prize balls to be paid out. Therefore, the number of payouts of 1 to 15 prize balls can be designated. Further, as a payout control command for designating the payout control state, 01 (H) to 0F
1-byte data other than (H) is used. For example,
11 (H) is used to specify the withdrawal prohibition, and 12 (H) is used to specify the withdrawal prohibition. Alternatively, the payout control command may be defined for each of the causes of prohibition of payout / release of prohibition of payout. For example, F0 (H) in the case of running out of balls (insufficient supply balls) and F0 in the case of releasing it.
1 (H), F2 (H) when the lower plate is full, and F3 (H) when the lower plate is released. Furthermore, 1
The upper 4 bits of the byte may be data indicating the type of instruction, and the lower 4 bits may be data indicating specific contents. For example, if the upper 4 bits are 0000, the number of prize balls to be paid out is designated, and the lower 4 bits indicate the number of prize balls. Further, if the upper 4 bits are 0001, the payout prohibition / payout prohibition cancellation may be instructed.

In this example, the port output process is executed in the interrupt process shown in FIG. 18 (however, in this example, the interrupt process is executed at a timing different from the process of FIG. 18), and the port output process is executed. A control command is output by the output processing. Here, a port output process for outputting a payout control command will be described. In the port output process, the CPU 56 outputs the data in the output content storage area of the output port 1 to the output port 1 if the payout control command transmission request flag is set. This timing corresponds to the start of section a in FIG.

Next, the CPU 56 sets the bit of the interrupt signal of the output port 0 of the output port 0 corresponding to the output port 1 which has output the data (one of the bits 0 to 3 (here, bit 0 because it is a payout control command). : Payout control signal interrupt signal)) and the bit of the STB signal of the output port 0 (any one of bits 4 to 7 (here, since it is a payout control command, bit 4: payout control signal STB signal)), "1. Is output. This timing corresponds to the start of section b in FIG. A delay time may be provided between the output of the command data and the output of the interrupt signal and the STB signal.

Then, the payout control command transmission request flag is cleared. The output state of output port 0 is copied to the output content storage area of output port 0.

Then, after waiting for a time corresponding to the sum of the times of the section b and the section c in FIG. 62, the bit (here, bit 0) of the interrupt signal of the output port 0 corresponding to the output port 1 which has output the data is waited. : The payout control signal interrupt signal) is set to "0" (step S349). Further, the output state of the output port 0 is copied to the output content of the output port 0 storage area. This timing is d in FIG.
It corresponds to the start of the section. The section b is the main board 31.
Corresponds to the delay time from the output of the interrupt signal to the acceptance of the interrupt by the sub-board (here, the payout control board 37).

Further, after waiting for a time corresponding to the sum of the times of the d section and the e section in FIG. 62, the bit of the STB signal of the output port 0 corresponding to the output port (here, output port 1) that has output the data. (Here, bit 4: STB signal for payout control signal) is set to "0". Further, the output state of the output port 0 is copied to the output content of the output port 0 storage area. This timing corresponds to the end of section e in FIG.

In this example, the timer interrupt processing is 4m.
It is executed every s. Therefore, the above-mentioned port output processing is also executed only once in 4 ms. Therefore, at most one control command is output from the main board 31 to each electric component control board in one control period (4 ms in this example).

As described above, the control command is sent to the sub-board at the timing shown in FIG. If a plurality of types of control command transmission request flags are turned on when the timer interrupt occurs, for example, the port output processing is performed for one of the control command transmission request flags according to a predetermined priority order. To be executed.

As described above, in this embodiment, when the command data of the control command is output, the data in the port output content storage area is output to the output port. Then, the data in the port output content storage area is set in the backup RAM in which the content is stored for a predetermined period even if the power supply is stopped. In this example, in the main process, a backup RAM is used instead of the port output content storage area.
Command data is written in the other area in the above, and when the command data is actually output to the output port, the command data is written in the port output content storage area. Therefore, when the command data is output to the output port, the command data output to the output port is set in the port output content storage area.

Next, the payout control CPU 3 in this example
The processing of 71 will be described. FIG. 64 is a flowchart showing main processing executed by the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) according to a program. In the main processing, the payout control CPU 371 performs the watchdog clear processing (step S705A) after executing the above-described processing of steps S701 to S705 (see FIG. 42) to set the RAM in the accessible state. (Step S
706). In step S705A, the payout control CPU
When the watchdog function is built in the 371 and is utilized, initialization of the watchdog function and timer clear processing are performed.

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the built-in device register setting processing of step S704 and the processing of step S705, register setting for setting the channel to be used in timer mode, register setting for permitting interrupt generation, and register for setting interrupt vector Settings are made. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt every 1 ms, for example, a value corresponding to 1 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set in the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, payout control process is executed.

Also, another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means, and that channel is used. Is used in counter mode. Therefore, in the built-in device register setting processing of step S704 and the processing of step S705, in order to set the register setting for setting the channel to be used in the counter mode, the register setting for permitting interrupt generation, and the interrupt vector. Register setting is performed.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set the interrupt processing start address according to the interrupt vector sent by the CTC.

An interrupt based on the count-up of CTC channel 2 (CH2) is an interrupt that occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as the specific register
An initial value "1" is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rising or falling of the signal input to the CLK / TRG2 terminal. You can make a choice. In this embodiment, the timer counter register CLK / TRG is output at the rising edge of the signal input to the CLK / TRG2 terminal.
The count value of 2 is set to -1.

The interrupt based on the count-up of the CTC channel 3 (CH3) is an interrupt that occurs when the register value becomes "0" by counting down the internal clock (system clock) of the CPU, and will be described later. 1m
s Used as a timer interrupt. Specifically, CPU3
A clock obtained by dividing the operation clock of 71 is given to the CTC, the value of the register is subtracted by the input of the clock, and when the value of the register becomes 0, a timer interrupt is generated.
For example, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 1 ms is set as an initial value in the CH3 register.

An interrupt based on the count-up of CTC CH2 has a higher priority than an interrupt based on the count-up of CH3. Therefore, when count-ups occur at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process is prioritized.

Next, the payout control CPU 371 will be described with reference to FIG.
As described in step 2, step S707 to step S707.
A part or all of the determination processing of 709 is executed.

In this example, the payout control CPU 37
1 is not considered to be switch-on unless the on-state continues for at least 1 ms (when the detection signal is turned on immediately before detection in the first processing of the processing started every 1 ms), but the clear switch 921 is turned on. In the case of detection, ON / OFF is determined by one ON determination. That is, it is determined whether the clear switch 921 as the initialization operation means is in a predetermined operation state or not.
The initialization request detection determination period for determining is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detecting means has detected the game medium.

If the check result in step S709 is not normal, an initialization process is executed which is executed when the power is turned on rather than when the power is restored from an unexpected power failure. In the initialization process, steps S711 to S7 described above are performed.
The process of 13 is executed (see FIG. 42). In this example, in step S712, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically taken every 1 ms. That is, a value corresponding to 1 ms as an initial value is set in a predetermined register (time constant register). Further, in this example, in the initialization process, a process of setting the internal state to the payout prohibition state is executed.

Thus, also in the electric component control means other than the game control means in this example, when the power supply is started, it is determined whether or not to restore the control state before the power supply is stopped. There are a plurality of restoration conditions, and the electric component control means restores the control state before the power supply is stopped if all the restoration conditions are satisfied, and initializes the control state if at least one of the restoration conditions is not satisfied. It is configured to perform an initialization process for converting the data into a new one. Therefore, it is possible to prevent erroneous recovery processing and erroneous control. In this example, the recovery condition is satisfied because the clear switch 921 is not pressed, the backup flag is in the ON state, and the result of the parity check is normal.

If the check result is normal in step S709, the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state at the time of stopping the power supply (step S710). In this example, the payout control CPU 371 performs, in the payout state recovery process, a process of setting the internal state to the payout prohibited state in addition to the process shown in FIG. 44. Note that setting the internal state to the payout prohibition state means setting a corresponding internal flag, for example. Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area.

In this embodiment, the backup flag, which is 1-byte data, is used as the flag indicating that the power supply stop time process has been executed. A flag having such a form may be used. There may be a plurality of such flags.

Next, payout control processing (step S751)
A to S760) are repeatedly executed (in a loop process).

In the payout control process, the payout control CPU
The 371 first executes a watchdog clear process (step S751A). In step S751A, the payout control CPU 371 incorporates a watchdog function,
When using this, a process of writing data for clearing the timer in the built-in watchdog timer is performed. The watchdog function may be realized by giving a signal to the reset IC 976.
Output a pulse signal.

Then, the processes of steps S752 to S760 described above are executed (see FIG. 42). Then, the process returns to step S751A. In this example, as will be described later, in the timer interrupt process, the data of the input port is stored in a predetermined RAM area. Therefore,
In the switch process of step S752, the detection signals of the switches such as the prize ball count switch 301A and the ball lending count switch 301B are recognized through the RAM area, and the state determination is performed. Further, in this embodiment, as will be described later, in the timer interrupt processing, the data in the output port output content storage area is output to the output port. Therefore, in the payout motor control process of step S758, a drive signal or the like is set in the output port output content storage area.

FIG. 65 is a flow chart showing the timer interrupt processing in this example. In the timer interrupt process, the payout control CPU 371 performs the register saving process (step S793), and then the port input process (step S794) and the port output process (step S795).
And timer update processing (step S796). Then, register restoration processing is performed (step S79).
7), the interrupt enabled state is set (step S798), and the process is terminated.

The port input process of step S794 is a process of reading the data of the input port and writing the read data in a predetermined RAM area. In the payout control process (loop process shown in FIG. 64), the input state of the input port is recognized based on the contents of the RAM area. The port output process of step S795 is a process of outputting the content of the output port output content storage area to the corresponding output port. The timer updating process of step S796 is a process of subtracting the values of various timers used in the payout control process. For example, in the payout control process, a value corresponding to the measurement time is set in the timer and the timer value is 0.
When it becomes, it recognizes that it has timed out.

FIG. 66 is a flow chart showing a command reception interrupt process activated in response to an interrupt signal (for payout control) from the main board 31. In the command reception interrupt process, the payout control CPU 371 performs the register saving process (step S850), and then the input port B (FIG. 4).
1) is input (step S861). Then, the bit 7 is confirmed (step S862).
In this example, bit 7 of the input port B is S for payout control.
It is assumed that the TB signal is input.
If the payout control STB signal is on, the data of the input port A (see FIG. 41) is input (step S86).
3). Then, the input data is stored in the reception command buffer indicated by the command reception number counter (step S864), and the value of the command reception number counter is updated (step S865).

Thereafter, register restoration processing is performed (step S859), and the interrupt enabled state is set (step S86).
0), the process ends. As described above, in this embodiment, the payout control means inputs the command data when the output of both the instruction signal (interrupt signal) and the data output signal (STB signal) is detected (step S86
3) will be executed.

In this example, a ring buffer type reception buffer capable of storing four payout control commands is used as a receive buffer for storing the payout control commands received from the main board 31. Therefore, the reception buffer is composed of the 4-byte area of the reception command buffers 1 to 4. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter has a value of 0 to 3.

The command analysis execution process is executed in the main process shown in FIG. 64. In the process, the contents of the receive buffer pointed to by the read pointer are read and the value of the read pointer is incremented by one. In addition, the main substrate 31
The game control means of sends only one payout control command in the control period of 4 ms. Therefore, normally, a plurality of payout control commands are not stored in the reception buffer.

67 and 68 are non-maskable interrupt processing (NM) executed by the payout control CPU 371 in this example in response to a power-off signal from the power-supply board 910.
It is a flowchart showing a processing example of (I processing: power supply stop processing).

In the power supply stop process, the payout control CPU 371 executes the processes of steps S801 to S807 described above (see FIG. 45). The processing of steps S801 to S807 corresponds to the data saving processing for saving the data necessary for restoring the control state in the variable data storage means according to the detection signal of the power supply monitoring means.

Next, a predetermined value is set as the number of processing loops (step S831), and the process shifts to a loop process for executing the check process of the prize ball count switch 301A and the payout control command receiving process for a predetermined period. The payout control CPU 371 first performs a watchdog clear process (step S832). Next, input port B (see FIG. 41: in this example, bit 7
Inputs data of STB signal for payout control) (step S833). Then, the bit 7 (STB signal for payout control) of the input data is confirmed (step S834). If the payout control STB signal is in the ON state and the confirmation of the ON state is the first confirmation (step S835), the data of the input port A (see FIG. 41) is input and the input data is stored in the command buffer. Yes (step S836).

The command buffer is a backup command storage area provided in a RAM area different from the reception buffer as a normal command storage area used during normal control, and is stored for a predetermined period even when power supply is stopped. It

Then, a predetermined value is set as the number of port checks (step S83).
7) Input the data of the input port B (step S8)
38). If the switch check timing has not come (step S839), the port check count is subtracted (step S840), and if the value is not 0, the process returns to step S838 (step S8).
41). If it is 0, the process proceeds to step S847.

If the switch check timing has come, switch check processing is carried out (step S
842). When it is detected that the prize ball count switch 301A is turned on (step S843), the value of the total number storage (total prize ball number storage buffer) is decremented by 1 (step S844), and the process proceeds to step S847. Also,
When it is detected that the ball lending count switch 301B is turned on (step S845), the value of the lent ball number storage (loan ball number storage buffer) is decremented by 1 (step S84).
6) and proceeds to step S847. The switch check process is a process of detecting whether or not the prize ball count switch 301A is surely turned on and detecting whether or not the ball lending count switch 301B is surely turned on, for example, a predetermined number of consecutive times. Then, when the ON state of the prize ball count switch 301A or the ball lending count switch 301B is detected, it is determined in step S843 that the prize ball count switch 301A has indeed turned on, or in step S845 the ball lending count switch 301.
It is judged that B is on.

In step S847, the number of processing loops is subtracted, and if the number of processing loops is not 0, the process returns to step S832 (step S848). If the number of processing loops is 0, the process proceeds to step S808.

At step S808, the stack pointer is saved in the backup RAM area. Then, the payout control CPU 371 executes the above-described processing of steps S809 to S820 (see FIG. 47).

After that, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset. When the watchdog timer is used, the watchdog timer is timed out because the watchdog clear processing is not performed in the loop state. However, when the power supply is stopped normally, the system is reset before that. However, for example, when NMI is caused by noise or the like, the system is not reset because the power supply is not stopped, but the watchdog timer is reset and the loop can be exited.

In the periods b to e shown in FIG. 62, the power supply is stopped and the non-maskable interrupt is the CPU 56 of the main board 31.
At this point, the CPU 56 does not change the output state of the output port, so that the output state is maintained when the payout control STB signal is output. That is, the game control means outputs a data outputting signal (STB signal in this example) indicating that the command data is being output in association with the output of the command data, and after starting the power supply stop time process. Also maintains the output of the data output signal for a predetermined period (in the above example, until the system is reset and is shorter than the period until the payout control means completes command reception). When the power supply is stopped, the payout control CPU 371 also receives a non-maskable interrupt. Loop time) The state of the data output signal is monitored (step S83).
4) If the data output signal is output, the process of capturing command data is executed. Then, the command data is received and stored in the command buffer (step S836). Therefore, when the power supply is stopped in the period from b to e, the payout control means completes the reception of the payout control command which is being transmitted.

In the periods c to d shown in FIG. 62, the power supply is stopped and the non-maskable interrupt is the CP of the main substrate 31.
In the case of U56, depending on the timing of stopping the power supply, the command reception interrupt process may be restored by the payout state recovery process after the power supply is restarted, and the payout control command may be received by the command reception interrupt process. .

Therefore, in this embodiment, in the command analysis execution processing (step S754) in the main processing, it is first confirmed whether or not there is data in the command buffer. The command buffer is a backup command storage area for storing the payout control command received in the power supply stop process, and is stored for a predetermined period even when the power supply is stopped. If there is data in the command buffer, execute command analysis processing for that data, then clear the contents of the command buffer and
Further, the reception buffer serving as the command storage area during normal operation is cleared. That is, the contents of the normal command storage area are invalidated.

The command analysis process is a process of analyzing what command the payout control command received is. For example, if it is confirmed that the payout control command indicates the number of award balls, The content of the number storage (total prize ball number storage buffer) is updated. Then, the command reception counter is initialized. That is, it is matched with the value of the read pointer.

If such control is performed in the main processing, when the power supply is stopped, the command reception interrupt processing is in the process, the power supply is restored, and the execution of the command interrupt processing is restarted. Even if the received command is stored in the receive buffer, the received command is discarded in the main process. Therefore, the situation where the payout control command is stored in both the command buffer and the receiving buffer, that is, the situation where the payout control command is received twice does not occur. As described above, if an unexpected power outage such as a power failure occurs during the command reception interrupt process, the payout control command that should be originally received by the command reception interrupt process is received by the power supply stop process. Stored in the command buffer.

Even with the configuration of the second embodiment as described above, the same effect as that of the first embodiment can be obtained. Specifically, in the power supply stop process (see FIGS. 67 and 68), after the number of loops is set in the detection maintaining period (step S831), the loop process for the set number of times is completed and step S848. Until the time "Y" is reached, the power supply board 910 (a board having a function of an auxiliary power supply means and an operating state holding means) is used by using the electric power charged in the capacitors 923 and 924. Is supplied with electric power capable of driving the prize ball count switch 301A (an example of the prize game medium detecting means) and the ball lending count switch 301B (an example of the lending game medium detecting means), and the solenoid 310 (passage switching). (An example of a means) supplies drive power for maintaining the state of the distribution member 311 and the payout control means (the payout control CPU 371) causes the prize ball counts. Pitch 3
01A and input processing of detection signals from the ball lending count switch 301B (steps S837 to S84)
Since it is configured to perform 8), in the power supply stop process,
It is possible to reliably detect a paid-out game medium (a game medium that is paid out as a prize based on a prize in a prize area) or a rented-out game medium (a game medium that is lent out in response to a loan request from a player). Like That is, according to the gaming machine having the configuration of the above-described second embodiment, it is possible to reliably detect the gaming medium paid out in the power supply stop process, so that the gaming medium is not paid yet. You will be able to grasp the number accurately.

Also in the above-described second embodiment, the payout control means confirms the state of one of the prize ball count switch 301A and the ball lending count switch 301B in the power supply stop process. It may be configured to.

Embodiment 3. FIG. FIG. 69 is a control command (payout control command, display control command, lamp control command, sound) transmitted from the main board 31 to each electric component control board (sub-board) in the third embodiment (Embodiment 3). It is a timing chart which shows the transmission form of (control command). In this example, the command data of the control command is 1
It consists of bytes.

As shown in FIG. 69, when the interrupt signal from the main board 31 (main) is turned on and then turned off, command data is output. Further, the STB signal is turned on. In this way, the game control means outputs the command data after transmitting the signal (in this example, an interrupt signal) indicating the opportunity for the electric component control means to execute the input process of inputting the command data, and outputs the command data. After the output, the instruction signal (STB signal in this example) is output as a signal indicating the trigger of actual input during execution of the input process. On the sub-board, the microcomputer constituting the electric component control means is interrupted at the rising edge of the interrupt signal, and the control command reception process (input process) is started.

The electric component control means of the sub-board fetches the command data when the STB signal is turned on in the receiving process. After that, the STB signal from the main is turned off at a timing after the electric component control means of the sub-board completes the command receiving process.

Also in this embodiment, the game control means carries out the same control as that of each of the above-mentioned embodiments except for the control command sending processing and the like. That is, the power supply stop process is executed according to the power-off signal (see FIGS. 19 to 21). Also, when it is confirmed that the restoration condition is satisfied at the start of power supply, the gaming state restoration processing is performed. In addition,
In this embodiment, the input / output port signal assignment is
This is the same as the case of the second embodiment.

In this example, the port output process is executed in the interrupt process shown in FIG. 18 (however, in this example, the interrupt process is executed at a different timing from the process in FIG. 18). A control command is output by the output processing. Here, a port output process for outputting a payout control command will be described. In the port output processing, if the payout control command transmission request flag is set, the CPU 56 sets the bit of the interrupt signal of the output port 0 (here bit 0: interrupt signal for payout control signal) for outputting the command data. "1" is output, the payout control command transmission request flag is reset, and
The output state of the output port 0 is copied to the output content storage area of the output port 0. This timing corresponds to the start of section a in FIG.

Next, the CPU 56 waits for a time corresponding to the total of the time of the section a and the time of the section b in FIG. The bit of the interrupt signal of the output port 0 corresponding to 1) (here, bit 0: interrupt signal for payout control signal) is set to "0". In addition,
The output state of the output port 0 is copied to the output content storage area of the output port 0. This timing corresponds to the start of section c in FIG. The section a corresponds to the delay time from when the main board 31 outputs the interrupt signal to when the sub board receives the interrupt.

Next, the CPU 56 stores the data in the port output content storage area (here, output port 1 output content storage area) corresponding to the control command transmission request flag confirmed when the payout control signal interrupt signal is turned on, Output to the corresponding output port (here, output port 1).

In the main process, the command data is written not in the port output content storage area but in another area of the backup RAM, and when the command data is actually output to the output port, the command data is written in the port output content storage area. It may be written. In this case, when outputting command data to the output port,
The command data output to the output port may be set in the port output content storage area. Also,
A delay time may be set before outputting the command data.

Next, the CPU 56 waits for a time corresponding to the time of section d in FIG.
Of the STB signal of the output port 0 corresponding to the output port that outputs the command data (here, output port 1) (here, bit 4: STB signal for payout control signal)
"1" is output to. The output state of output port 0 is copied to the output content storage area of output port 0. This timing corresponds to the start of section e in FIG. The above process may be performed without waiting for a time corresponding to the time of the d section. In the sub-board, the reception process is started with a slight delay from the timing of the start of section d. The delay is a processing delay of the microcomputer in the sub-board (delay until the software detects that the STB signal is turned on).

Then, the CPU 56 executes the e in FIG.
After waiting for the time corresponding to the time of the section, the bit of the STB signal of the output port 0 of the output port 0 corresponding to the output port (here, output port 1) of the output port 0 (bit 4: for payout control signal) "0" is output to the STB signal). The output state of output port 0 is copied to the output content storage area of output port 0. This timing corresponds to the end of section e in FIG.

As described above, the control command is sent to the sub-board at the timing shown in FIG. If a plurality of types of control command transmission request flags are turned on when the timer interrupt occurs, for example, according to a predetermined priority, one of the control command transmission request flags outputs the above port output. The process is executed.

As described above, in this embodiment, when the command data of the control command is output, the data in the port output content storage area is output to the output port. Then, the data in the port output content storage area is set in the backup RAM in which the content is stored for a predetermined period even if the power supply is stopped. As described above, in the main process, the command data is written not in the port output content storage area but in another area of the backup RAM, and when the command data is actually output to the output port, the command data is written in the port output content storage area. When configured to write, when the command data is output to the output port, the command data output to the output port is set in the port output content storage area.

Next, the processing of the payout control CPU 371 in this embodiment will be described. The payout control means can also perform the main processing and the timer interrupt processing as in the case of each of the above-described embodiments, but is executed when it is confirmed that the restoration condition is satisfied at the start of the power supply in the main processing. The payout state restoration process, the command reception interrupt process, and the power supply stop process that are different from those of the respective embodiments. In this embodiment, signal allocation of input / output ports is the same as that in the second embodiment.

FIG. 70 is a flow chart showing the command reception interrupt processing in this embodiment. In the command reception interrupt process, the payout control CPU 371 performs the register save process (step S850), and then S
The TB signal waiting counter is set (step S89).
7). Then, the data of the input port B (see FIG. 41: in this example, bit 7 is assigned to the payout control STB signal) is input (step S861),
The bit 7 (STB signal for payout control) is confirmed (step S862). If the payout control STB signal is on, the process proceeds to step S863.

If the payout control STB signal is not in the ON state, the count value of the STB signal waiting counter is decremented by 1 (step S898), and it is confirmed whether or not the count value is 0 (step S899). If not 0, the process returns to step S861. If it is 0, the process proceeds to step S859.

[0471] In Step S863, the payout control C
The PU 371 inputs the data of the input port A (see FIG. 41). Then, the input data is stored in the reception command buffer indicated by the command reception number counter (step S864), and the value of the command reception number counter is updated (step S865).

Thereafter, register restoration processing is performed (step S859), and the interrupt enabled state is set (step S86).
0), the process ends.

The command reception interrupt process is activated when the interrupt signal from the main board 31 is turned on. Then, in the command interrupt process, when it is detected that the STB signal is turned on, the command data is fetched (step S863). If the STB signal does not turn on within the predetermined period (the time corresponding to the initial value of the STB signal waiting counter), the process ends.

FIG. 71 is a flow chart showing an example of a non-maskable interrupt process (NMI process: power supply stop time process) executed in response to a power-off signal from the power supply board 910 in this embodiment.

In the power supply stop process, the payout control CPU 371 executes the processes of steps S801 to S807 described above (see FIG. 45). The processing of steps S801 to S807 corresponds to the data saving processing for saving the data necessary for restoring the control state in the variable data storage means according to the detection signal of the power supply monitoring means.

Next, a predetermined value is set as the number of port checks (step S871), and the process shifts to a loop process for executing the check process of the prize ball count switch 301A and the payout control command reception process for a predetermined period. The payout control CPU 371 first determines the input port B.
(See FIG. 41: However, in this example, bit 7 is assigned to the payout control STB signal) (step S838). Then, switch check processing is performed (step S842), and when it is detected that the prize ball count switch 301A is turned on (step S8).
43), the prize ball count value is incremented by 1 (step S87)
2). When it is detected that the ball lending count switch 301B is turned on (step S845), the ball lending count value is incremented by 1 (step S873). The prize ball count value and the ball lend count value are formed in the backup RAM, and in the payout state restoration process, the count number of the prize ball count value is reflected in the total number storage, and the count number of the ball lend count value is stored in the loan ball number storage. Reflected.

Then, the number of port checks is subtracted (step S840), and if the value is 0, the process proceeds to step S808 shown in FIG. 68 described above. If it is not 0, the software timer sets a delay time of a predetermined time (corresponding to the delay time for setting the switch check interval) (step S874). Next, the process based on the weight code is executed (step S875), the software timer is decremented (step S876), and if the delay time has not elapsed, the process returns to step S875 (N in step S877). If the delay time has elapsed, step S838.
(Y in step S877). The process based on the wait code is a process for gaining time until the delay time elapses, and is a process that does not affect other control contents.

FIG. 72 is a flow chart showing an example of the payout state recovery processing in this embodiment. In the payout state recovery process, the payout control CPU 371 first performs a stack pointer recovery process (step S8).
81). The value of the stack pointer is saved in a predetermined RAM area (power source is backed up) in the power supply stoppage process described later. Therefore, step S
At 881, the value of the RAM area is set in the stack pointer to restore the value. The area pointed to by the restored stack pointer (that is, the stack area)
The register value and the value of the program counter (PC) when the power supply is stopped are saved in.

In this embodiment, the CPU of the main board 31
56 performs a process of outputting the saved contents of the port output contents storage area to the output port in the game state recovery process that is executed if the recovery condition is satisfied at the start of power supply. Therefore, in this embodiment, the payout control C
In consideration of such a situation, the PU 371 selects the main board 31.
After confirming that the contents of the port output contents storage area have been output from the device, control is performed to return to the address that was executed immediately before the power supply was stopped.

First, the payout control CPU 371 sets the number of processing loops (step S882). And
Data of the input port A (see FIG. 41), that is, command data is input (step S883). Then, it is confirmed whether or not the input data is the same as the previously input data (step S884). If they are the same, the number of processing loops is decremented by 1 (step S885). If the number of processing loops is not 0, the process returns to step S883. If the number of processing loops is 0, step S8
Go to 87. Also, when it is confirmed that the data input in step S884 is the same as the previously input data, the process proceeds to step S887.

In step S887, the payout control C
The PU 371 performs initial settings of built-in devices such as CTC and PIO, reads the saved values of various registers from the stack area, and sets them in various registers. That is, register restoration processing is performed. Here, the process of setting the RAM access permission state is also performed. Further, the backup flag is cleared (step S888). Next, the prize ball count value stored in the power supply stop processing executed when the power supply is stopped is reflected in the total number storage (step S889). For example, the prize ball count value is subtracted from the content of the total number memory. In addition, the lending count value stored in the power supply stop process executed when the power supply is stopped is reflected in the number of lent balls stored (step S890). For example, the lending count value is subtracted from the stored contents of the number of lent balls. In addition, the contents of areas other than the protected area in the RAM area are cleared (step S891). Then, when the parity flag is not turned on, the interrupt permission state is set (steps S892 and S8).
93). Finally, the internal state is set to the payout prohibition state (step S894), and the AF register (accumulator and flag register) is restored from the stack area (step S895).

If the state of the input port does not change within the predetermined time (the time corresponding to the initial value of the number of processing loops), that is, the command data from the game control means in the processing of steps S882 to S886. If the output of is not confirmed, the program counter (PC) is initialized (step S896) and the RET instruction is executed. Therefore, in this embodiment, after executing the payout state recovery process, the payout control is started from the initial state.

With the above processing, in the payout state restoration processing executed when the restoration condition is satisfied when the power supply is started, the input port of the input port to which the command data from the main board 31 is inputted is input. After confirming that the state has changed, the NMI is restored to the address where the power supply was stopped. Therefore, when the address is the address in the command reception interrupt process, it is confirmed that the CPU 56 of the main board 31 has performed the process of outputting the content of the saved port output content storage area to the output port. Then, the command reception interrupt process can be restarted. Therefore, the payout control command can be surely received, and the payout control command can be surely prevented from being lost. When the command reception interrupt process is completed, the payout control is started from the initial state.

Unlike the second embodiment, in this embodiment, the processing for continuing the reception of the payout control command is not executed in the power supply stop processing. However, in the payout state recovery processing, after confirming that the CPU 56 of the main board 31 has performed the processing of outputting the content of the saved port output content storage area to the output port, the command reception interrupt processing is restarted. . That is, when the power supply is started, the output state of the command data to the output port by the game control means is monitored, and the process of fetching the command data according to the output state can be restarted. Therefore, even if the reception of the payout control command is started immediately before the power supply is stopped, but the reception is not completed,
When the power supply is restored, the command reception process can be surely completed.

In this embodiment, the CPU 56 of the main board 31 outputs the port output contents within a predetermined time to confirm that the CPU 56 has output the contents of the port output contents storage area to the output port. When it was not possible to confirm that the processing of outputting the contents of the storage area to the output port was performed, the initial state was restored. Should not have been performed, and will not recover to the command reception processing. That is, if it is not confirmed that the CPU 56 has performed the process of outputting the contents of the port output contents storage area to the output port, there is no problem in returning to the initial state. Further, since the contents of the protected area of the RAM are preserved when returning to the initial state, no disadvantage is given to the player.

Further, since the area other than the protected area is cleared in the payout state recovery processing, it is possible to prevent erroneous control due to incorrect data. In this embodiment, areas other than the protected area are cleared in the payout state recovery process, but if the command reception process is restored when power supply is started, the command data is taken in the command reception process. After executing, the area other than the protected area may be cleared.

Even with the configuration of the third embodiment as described above, the same effect as that of the first embodiment can be obtained. Specifically, in the power supply stop process (see FIG. 71 and FIG. 68), after the number of port checks is set in the detection maintaining period (step S837), the set number of port checks are completed and Until the time of "Y" in S841) elapses, the electric power charged in the capacitors 923 and 924 is used to function as a power supply substrate 910 (auxiliary power supply means and operating state holding means). The board) supplies electric power capable of driving the prize ball count switch 301A (an example of the prize game medium detecting means) and the ball lending count switch 301B (an example of the lending game medium detecting means), and the solenoid 310 (passage). An example of a switching means) supplies drive power for maintaining the state of the distribution member 311;
The payout control means (payout control CPU 371) has a prize ball count switch 301A and a ball lending count switch 30.
Since the input processing of the detection signal from 1B (step S837 to step S848) is performed, the paid game media (paid as a prize based on the winning in the winning area is paid out in the power supply stop processing. It becomes possible to reliably detect a game medium) and a lending game medium (a game medium lent out in response to a lending request from a player). That is, according to the gaming machine having the configuration of the above-described third embodiment, it is possible to reliably execute the detection of the gaming medium paid out in the power supply stop process, so that the gaming medium is not paid yet. You will be able to grasp the number accurately.

Also in the third embodiment described above, the payout control means confirms the state of either the prize ball count switch 301A or the ball lending count switch 301B in the power supply stop process. It may be configured to.

In the above-described second and third embodiments, the processing of the payout control means has been mainly described. Processing such as confirmation is similarly executed by the game control means.

Further, in each of the above-mentioned embodiments, the payout control means distinguishes the prize ball count switch 301A and the ball lending count switch 301B and confirms the state thereof (for example, FIG. 46, FIG. 59 and FIG. 59). 60,
67 and 71), the count switches can be confirmed without distinction. Figure 7
Process 3 is a non-maskable interrupt process (NMI process: power supply stop process) when the prize ball count switch 301A and the ball lending count switch 301B are not distinguished from each other and the states of the count switches are confirmed. It is a flowchart which shows an example. Note that detailed description of the processing and the like already described in FIG. 45 and the like will be omitted.

In the non-maskable interrupt process shown in FIG. 73, the payout control CPU 371 performs the processes of steps S801 to S808 and then executes step S821.
The output port clearing process shown in step S827 is performed. Then, in this embodiment, a predetermined period (detection maintaining period), payout detecting means (count switch: prize ball count switch 301A, ball lending count switch 301)
Check the detection signal of B). In this example, it does not matter whether the detection signal to be checked is the detection signal from the prize ball count switch 301A or the ball lending count switch 301B. In this example, if either of the count switches is turned on, it is confirmed whether the paid game ball is a prize ball or a loan ball, and if it is a prize ball, the content of the total number memory is decremented by 1. If the paid game ball is a loan ball, the content of the number of loaned balls stored is reduced by one.

In the input processing of the detection signal from the payout detecting means, the payout control CPU 371 first sets the value m corresponding to the predetermined period in the counter for measuring the predetermined period (step S762). Then, the payout control CPU 371
The value of the counter for measuring for a predetermined period is decremented by 1 (step S76
3) Confirm the value of the counter for measuring the predetermined period (step S764). If the value is 0, the switch detection process is terminated, and the process proceeds to a power supply stop process which is a process for saving the control state.

If the value of the counter for measuring the predetermined period is not 0, it is confirmed whether any of the count switches is on (step S765a). If it is on, after the value of the detection period counter is decremented by 1 (step S766), it is confirmed whether or not the value of the detection period counter has become 0 (step S767). If it is 0, the detection signal from the count switch is confirmed via the input port (step S768a), and if it is in the ON state, the paid game ball is a prize ball or a loan ball. Check if. In this example, the payout control CPU 37
1, it is confirmed whether or not the award ball processing flag is turned on (step S828), and if it is turned on, the award ball is being processed, so it is determined that the paid game ball is an award ball. To do. When it is determined that the paid game ball is a prize ball, the payout control CPU 371 decrements the value of the total number memory by 1 (step S769).

If the prize ball processing flag is not on, the payout control CPU 371 confirms whether the ball lending processing flag is on (step S829), and if it is on, ball lending processing is on. Therefore, it is determined that the paid game ball is a lending ball. When it is determined that the paid game ball is a rented ball, the payout control CPU 371
Decrements the value stored in the number of lent balls by 1 (step S77).
9).

When it is confirmed in step S765a that neither count switch is on, the detection signal of each count switch is confirmed via the input port (step S770a), and one of the count switches indicates the on state. If so, the count switch ON flag is set (step S771a), and
An initial value n is set in the detection period counter (step S772). In the count switch detection process, if the value of the detection period counter is not 0 in step S767, or if none of the count switches is in the ON state in step S770a, step S770.
In any case where the initial value n is set in the detection period counter in 772, the processing returns to step S763 after the processing.

With the above processing, when any of the count switches is turned on within the predetermined period, if it is confirmed that the prize ball payout processing is being carried out, the value of the total number memory is decremented by 1 and the ball lending processing is being carried out. If this is confirmed, the value of the number of lent balls stored is decremented by one.

As described above, the prize ball count switch 30
Input processing of the detection signal is performed without distinguishing 1A and the ball lending count switch 301B, and when the detection signal is input, it is confirmed whether the game ball paid out is a prize ball or a loan ball. As a configuration, even if a game ball paid out as a prize ball passes through a lending ball passage and is paid out, the game ball is accurately detected as a prize ball. Further, even if a game ball paid out as a rental ball passes through a prize ball passage and is paid out, the game ball is accurately detected as a rental ball. Therefore, the distribution member 311 is used during the processing when the power supply is stopped.
Even if the state of No. is not maintained, it is possible to accurately determine whether a prize ball or a lent ball, and it can be reflected in the number of unpaid coins stored in the backup RAM area. Therefore, it is not necessary to secure a power source for driving the distribution solenoid 310 during the processing when the power supply is stopped. In the supply stop process, the paid game balls can be detected by distinguishing the prize balls from the loan balls.

The pachinko gaming machine of each of the above embodiments is
Mainly, a predetermined game value can be given to the player when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols.
Although it was a kind of pachinko machine, a kind of pachinko machine that can give a predetermined game value to the player if there is a prize in the predetermined area of the electric role to open based on the start prize, and a start prize Even if it is a third-class pachinko game machine, a predetermined right is generated or continues when there is a prize for a predetermined electric accessory that is released when a stop symbol of the symbols variably displayed based on the above is a combination of predetermined symbols The present invention can be applied.

Furthermore, the present invention is applicable not only to a pachinko gaming machine in which the game medium is a game ball, but also to a slot machine or the like provided with an electric component for paying out the game medium.

[0500]

As described above, according to the first aspect of the present invention, the gaming machine is a prize game in a period until at least a predetermined detection maintaining period elapses after the detection signal is output by the power source monitoring means. Auxiliary power supply means capable of supplying power to at least one of the medium detection means and the rental game medium detection means, and an operation state in which the state of the passage switching means can be maintained at least until the detection maintaining period elapses. Stopping power supply for saving the data necessary for the game control means and the payout control means to restore the control state in response to the detection signal from the power supply monitoring means in the variable data storage means, including the holding means. Run time processing,
In the power supply stop process, the game control means performs an input process of a detection signal from the prize game medium detection means, and the payout control means is at least one of the prize game medium detection means and the rental game medium detection means. Since the detection signal from one side is input, there is an effect that the paid-out prize game medium or the rental game medium can be surely detected in the power supply stop process.

According to the second aspect of the present invention, the operating state holding means is configured to be an auxiliary drive power supply means for supplying electric power capable of driving the passage switching means at least until the detection maintaining period elapses. Therefore, the drive state of the passage switching means can be maintained by the electrical configuration.

According to the third aspect of the present invention, the operating state holding means is configured to be a holding mechanism capable of holding the state of the passage switching means at least until the detection maintaining period elapses. The drive state of the switching means can be maintained by a mechanical structure.

According to the fourth aspect of the invention, the payout control means determines whether or not the payout means is paying out the prize game medium or the rental game medium during the power supply stop process, and based on the determination. Since the input processing of the prize game medium detecting means or the lending game medium detecting means is selectively performed, the power supply stop processing can be quickly performed.

Further, in the invention according to claim 5, the gaming machine, the prize gaming medium detecting means and the renting gaming medium until at least a predetermined detection maintaining period elapses after the detection signal by the power source monitoring means is output. The auxiliary power supply means capable of supplying electric power to the detection means, for the payout control means to store the data necessary for restoring the control state in the fluctuation data storage means in response to the detection signal from the power supply monitoring means. The power supply stop processing is executed, and the payout control means performs the input processing of the detection signal from at least one of the prize game medium detection means and the rental game medium detection means in the power supply stop processing. , It is determined whether or not the payout means pays out the prize game medium or the rental game medium, and based on the determination result, the detection input during the input process. It is possible to specify whether the signal is a detection signal based on the detection of the prize game medium or the rental game medium. There is an effect that it is possible to reliably detect that the game medium has been paid out.

According to the sixth aspect of the present invention, in the power supply stop process, after performing the process of clearing the output port for outputting a signal to the outside, the prize game medium detecting means and the rental game medium detecting means are provided. Since it is configured to perform the input processing of the detection signal from at least one of them, it is possible to reduce the power consumption in the power supply stop processing.

In the invention according to claim 7, the detection maintaining period is equal to or longer than the period until the game medium paid out by the payout means reaches the detection position of either the prize game medium detection means or the rental game medium detection means. Since it is configured to be set in the period of, it is possible to reliably detect the paid-out game medium.

In the invention as set forth in claim 8, the payout control means changes the data showing the result of the input processing of the detection signal from the prize game medium detecting means or the rental game medium detecting means in the power supply stop processing to the variable data storing means. In the recovery process, the data indicating the result of the input process is configured to perform the process of updating the unpaid amount data based on the unpaid amount data, so that the process at the time of power supply stop can be performed quickly. It can be carried out.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is a front view showing the front surface of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine viewed from the back side.

FIG. 4 is a rear view of a mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a front view showing a portion of a switch board installed on the game board.

FIG. 7 is a configuration diagram showing an example of a configuration of a clear switch.

FIG. 8 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 9 is a block diagram showing a circuit configuration example of a payout control board.

FIG. 10 is a block diagram showing a circuit configuration example of a power supply board.

FIG. 11 is a block diagram showing an example of a configuration around a CPU for power supply monitoring and power supply backup.

FIG. 12 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 13 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 14 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 15 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 16 is an explanatory diagram showing an example of the relationship between the backup flag and whether or not to execute the game state recovery process.

FIG. 17 is a flowchart showing a game state recovery process.

FIG. 18 is a flowchart showing a 2 ms timer interrupt process.

FIG. 19 is a flowchart showing non-maskable interrupt processing (processing when power supply is stopped).

FIG. 20 is a flowchart showing a non-maskable interrupt process (power supply stop process).

FIG. 21 is a flowchart showing non-maskable interrupt processing (processing when power supply is stopped).

FIG. 22: Power supply drop and N when power supply to a game machine is stopped
It is a timing diagram which shows a mode of MI signal.

FIG. 23 is a timing chart showing an example of how a detection signal input process is executed.

FIG. 24 is an explanatory diagram showing a formation example of a switch timer in a RAM.

FIG. 25 is a flowchart showing an example of a switch process.

FIG. 26 is a flowchart showing an example of a switch check process.

FIG. 27 is a flowchart showing an example of prize ball processing.

FIG. 28 is a flowchart showing an example of prize ball processing.

FIG. 29 is a flowchart showing an example of prize ball processing.

FIG. 30 is a flowchart showing a switch-on check process.

FIG. 31 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 32 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 33 is an explanatory diagram showing an example of a command form of a control command.

FIG. 34 is a timing diagram showing a relationship between an 8-bit control signal forming a control command and an INT signal.

FIG. 35 is an explanatory diagram showing an example of contents of a payout control command.

FIG. 36 is a flowchart showing a processing example of command set processing.

FIG. 37 is a flowchart showing a command transmission processing routine.

FIG. 38 is a flowchart showing an example of award ball number subtraction processing.

FIG. 39 is a block diagram showing a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 40 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 41 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 42 is a flowchart showing a main process executed by a CPU in a payout control board.

FIG. 43 is a flowchart showing a 2 ms timer interrupt process.

FIG. 44 is a flowchart showing a payout state recovery process.

FIG. 45 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 46 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 47 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

48 is an explanatory diagram showing a configuration example of a RAM in the payout control means. FIG.

FIG. 49 is an explanatory diagram showing a configuration example of a reception command buffer.

FIG. 50 is a flowchart showing an example of command reception processing of the payout control CPU.

FIG. 51 is a flowchart showing an example of switch processing.

FIG. 52 is a flowchart showing an example of payout stop state setting processing.

FIG. 53 is a flowchart showing an example of command analysis execution processing.

FIG. 54 is a flowchart showing an example of prepaid card unit control processing.

FIG. 55 is a flowchart showing an example of ball lending control processing.

FIG. 56 is a flowchart showing an example of ball lending control processing.

FIG. 57 is a flowchart showing an example of prize ball control processing.

FIG. 58 is a flowchart showing an example of prize ball control processing.

FIG. 59 is a flowchart showing another example of the non-maskable interrupt process (power supply stop process).

FIG. 60 is a flowchart showing another example of unmaskable interrupt processing (power supply stop processing).

FIG. 61 is a flowchart showing another example of the non-maskable interrupt process (power supply stop process).

FIG. 62 is a timing chart showing how control commands are sent from the main board to the sub-board in the second embodiment.

FIG. 63 is a flowchart showing command control processing.

FIG. 64 is a flowchart showing a main process executed by a CPU in the payout control board.

FIG. 65 is a flowchart showing a timer interrupt process.

FIG. 66 is a flowchart showing command reception processing.

FIG. 67 is a flow chart showing an example of non-maskable interrupt processing (power supply stoppage processing) in the second embodiment.

FIG. 68 is a flowchart showing an example of non-maskable interrupt processing (power supply stop processing) in the second embodiment.

FIG. 69 is a timing diagram showing how control commands are sent from the main board to the sub-board in the third embodiment.

FIG. 70 is a flowchart showing command reception processing.

71 is a flow chart showing an example of non-maskable interrupt processing (power supply stop processing) according to the third embodiment. FIG.

FIG. 72 is a flowchart showing an example of payout state recovery processing according to the third embodiment.

FIG. 73 is a flowchart showing still another example of the non-maskable interrupt process (power supply stop process).

[Explanation of symbols]

1 Pachinko machine 31 Game control board (main board) 37 Discharge control board 56 CPU 97 Ball dispensing device 301A prize ball count switch 301B ball lending count switch 310 Sorting solenoid 311 Sorting member 371 CPU for payout control 910 Power board 902 Power supply monitoring IC (power supply monitoring means) 923,924 capacitors

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Fumitaka Sekine             Gunma Prefecture Kiryu City Sakaino-cho 6-460 Stock             Company Sankyo F term (reference) 2C088 BA21 BC58 BC70 DA09 EA09

Claims (8)

[Claims] 1. A game machine capable of performing a predetermined game using a game medium, comprising: game control means for controlling the progress of the game; and a prize game medium as a prize and a loan request from a player. According to a command from the game control means, a payout control means for controlling the payout means, a payout means capable of paying out a rental game medium to be rented out according to the payout means, and a game medium paid out by the payout means as a prize A prize game medium passage for guiding as a game medium, a rental game medium passage for guiding as a rental game medium, and a passage of the game medium paid out by the payout means, the prize game medium passage and the rental game medium passage A passage switching means for switching to any of the above, an electric drive source for driving the passage switching means, and a prize game medium provided in the prize game medium passage for detecting a prize game medium Noble game medium detecting means, lending game medium detecting means provided in the lending game medium passage and capable of detecting the lending game medium, and retains stored contents for a predetermined period even when power supply to the gaming machine is stopped And a power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a detection signal when a detection condition regarding stop of power supply is satisfied, Power is supplied to at least one of the prize game medium detection unit and the rental game medium detection unit during a period until at least a predetermined detection maintaining period elapses after the detection signal is output by the power supply monitoring unit. A possible auxiliary power supply means, and an operation state holding means capable of holding the state of the passage switching means at least until the detection maintaining period elapses, The game control means and the payout control means each process the power supply stop time for storing the data necessary for restoring the control state in the variable data storage means in response to the detection signal from the power supply monitoring means. In the power supply stop process, the game control means performs an input process of a detection signal from the prize game medium detection means, and the payout control means determines the prize game medium detection means and the loan. A game machine characterized by performing input processing of a detection signal from at least one of the game medium detecting means. 2. The gaming machine according to claim 1, wherein the operating state holding means is an auxiliary drive power supply means for supplying electric power capable of driving the passage switching means at least until the detection maintaining period elapses. 3. The gaming machine according to claim 1, wherein the operating state holding means is a holding mechanism capable of holding the state of the passage switching means at least until the detection maintaining period elapses. 4. The payout control means determines whether or not the payout means is paying out a prize game medium or a rental game medium in the power supply stop process, and based on the determination, the prize game medium detection means. Alternatively, the game machine according to any one of claims 1 to 3, wherein the input processing of the rental game medium detection means is selectively performed. 5. A game machine capable of playing a predetermined game using a game medium, comprising game control means for controlling the progress of a game, a prize game medium as a prize, and a loan request from a player. According to a command from the game control means, a payout control means for controlling the payout means, a payout means capable of paying out a rental game medium to be rented out according to the payout means, and a game medium paid out by the payout means as a prize A prize game medium passage for guiding as a game medium, a rental game medium passage for guiding as a rental game medium, and a passage of the game medium paid out by the payout means, the prize game medium passage and the rental game medium passage A passage switching means for switching to any of the above, an electric drive source for driving the passage switching means, and a prize game medium provided in the prize game medium passage for detecting a prize game medium Noble game medium detecting means, lending game medium detecting means provided in the lending game medium passage and capable of detecting the lending game medium, and retains stored contents for a predetermined period even when power supply to the gaming machine is stopped And a power supply monitoring means for monitoring the state of a predetermined power supply used in the gaming machine and outputting a detection signal when the detection condition related to the stop of power supply is satisfied, Auxiliary power supply means capable of supplying power to the prize game medium detection means and the rental game medium detection means at least until a predetermined detection maintaining period elapses after the detection signal is output by the power supply monitoring means. And the payout control means stores the data necessary for restoring the control state in the fluctuation data storage means in response to the detection signal from the power supply monitoring means. A supply stop process is executed, and the payout control unit performs an input process of a detection signal from at least one of the prize game medium detection unit and the rental game medium detection unit in the power supply stop process. It is determined whether or not the payout means pays out either the prize game medium or the rental game medium, and based on the result of the judgment, the detection signal input in the input process is the prize game. A gaming machine, characterized in that it is possible to specify which of a medium and the rental game medium is a detection signal based on detection. 6. The power supply stoppage process executes a process of clearing an output port for outputting a signal to the outside, and then, at least one of the prize game medium detection means and the rental game medium detection means. The gaming machine according to any one of claims 1 to 5, which performs input processing of a detection signal. 7. The detection maintaining period is set to a period equal to or longer than a period until the game medium paid out by the payout means reaches a detection position of either the prize game medium detection means or the rental game medium detection means. The gaming machine according to any one of claims 1 to 6. 8. The storage content of the variable data storage means includes unpaid amount data capable of specifying the unpaid amount that has not yet been paid out of the number of prize game media to be paid out based on the establishment of the payout condition. When the power supply is started, the payout control means executes a recovery process for restoring the control state before the power supply is stopped, and the payout control means detects the prize game medium in the power supply stop process. Data indicating the result of the input processing of the detection signal from the means or the rental game medium detecting means is stored in the variable data storage means, and the data indicating the result of the input processing is based on the unpaid amount data in the restoration processing. The gaming machine according to any one of claims 1 to 7, which executes a process of updating the unpaid amount data.