JP2003169904A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a disagreement from being generated in the recognition regarding the putting out of game mediums between a game controlling means and a put-out controlling means. <P>SOLUTION: The put-out controlling means 371A which is loaded on a put-out controlling board 37 controls the putting-out of game mediums to be a put-out prohibited state wherein the putting out of the game mediums are prohibited in a recovery process when the supply of power is resumed. The game controlling means 56A which is loaded on a main board 31 transmits a recovery command indicating that the control state is recovered to the put-out controlling means 371A in the recovery process, and then, performs the setting of a timer interruption to determine the starting timing for the control. At the same time, the game controlling means 56A performs a register returning process to recover the content of a register, and returns to a state wherein the game control is possible. The put-out controlling means 371A resumes the control by performing the timer interruption setting process and the register returning process provided that the recovery command is received in the recovery process. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game using a game medium.

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Furthermore, a variable display unit whose display state can be changed is provided,
There is one configured to give a predetermined game value to the player when the display result of the variable display section becomes a predetermined specific display mode.

The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is advantageous for a player who easily wins a game ball, or an advantageous state for the player. To generate the right to become, and to be in a state where the conditions for paying out prize balls are easily established.

In the pachinko gaming machine, it is usually called a "big hit" that the display result of the variable display section for displaying the special symbol is a combination of predetermined specific display modes.
When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which game balls are easy to win is entered.
Then, in each opening period, a predetermined number (for example, 10)
If there is a prize in the prize hole, the prize hole will be closed. The number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied when the special winning opening is closed, the jackpot gaming state ends.

Further, in the variable display device, the symbols other than the symbol which is the final stop symbol (for example, the middle symbol of the left and right middle symbols) continue for a predetermined time, and stop and swing in a state in which it matches the specific display mode. , Scaled or deformed state, or multiple symbols fluctuate synchronously in the same symbol, or the position of the displayed symbol is swapped, the possibility of a big hit before the final result is displayed The effect that is performed in a state in which the above is continued (hereinafter, these states are referred to as the reach state) is referred to as the reach effect. A variable display including a reach effect is called a reach variable display. By changing the variation pattern in the reach state from the variation pattern in the normal state, the interest of the game is enhanced. When the display result of the symbols variably displayed on the variably display device does not satisfy the condition for reaching the reach state, the result is “out”, and the variably display state ends. A player plays a game while enjoying how to generate a big hit.

When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game proceeds to the game mounted on the main board. Since it is controlled by the control means, the number of prize balls based on the winning is determined by the game control means, and a command indicating the number of prize balls is transmitted to the payout control board. On the other hand, the lending of the game medium is unrelated to the progress of the game, and thus is generally controlled by the payout control means, not through the game control means.

Further, the game machine is equipped with various control means in addition to the game control means and payout control means. Then, the game control means for controlling the progress of the game sends each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the game control means and other control means may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

[0008]

As described above, the game machine is equipped with various electric component control means including the game control means. Generally, each electric component control means is configured to include a microcomputer. Such electric component control means generally performs an initialization process when the power supply voltage rises, and starts control from an initial state. Then, an unexpected power failure such as a power failure occurs, and then the power returns to the initial state when the power is restored, which may cause a problem that the gaming value or the like obtained by the player disappears. In order to prevent such a problem from occurring, the game control is interrupted in response to a predetermined signal that accompanies the decrease in the power supply voltage value, and the control state at that time is stopped by the power supply to the game machine. In particular, the power may be stored in the storage means that is backed up (backup storage means) and controlled so as to wait until the power supply is completely stopped. In such a gaming machine, if the power supply is restarted while the game state is stored in the storage means, the game is restarted based on the stored control state, which is disadvantageous to the player. Is prevented.

Further, when the unpaid number is stored in the backup storage means in the payout control means for controlling the ball payout device, when the power supply is restarted, the payout control means is based on the stored unpaid quantity. The control for paying out the game balls from the ball payout device is restarted. However, when the power supply is restarted, if the payout control means is configured to stand up first, the ball payout from the ball payout device may be started before the game control means rises to the controllable state. is there. If the ball payout from the ball payout device is started before the game control means rises to the controllable state, the number of ball payouts grasped by the game control means and the number of ball payouts grasped by the payout control means are different from each other. On the contrary, when the game control means is configured to start up first,
The payout control means may not be able to receive the command sent by the game control means. As a result, a control discrepancy may occur between the game control means and the payout control means regarding the payout control of the game balls.

Therefore, the present invention provides a gaming machine capable of preventing a discrepancy between the control contents relating to the payout of the game medium, which are grasped by the game control means and the payout control means, respectively. To aim.

[0011]

A gaming machine according to the present invention comprises:
It is possible to play a predetermined game using the game medium,
A game machine that pays out a game medium based on the establishment of a predetermined payout condition (for example, a prize has been won in a prize area provided in the game area, a request for lending a game medium has been made by a player). The payout means for paying out the game medium, the game control means for controlling the progress of the game (for example, the game control means including the CPU 56: the game control means 56A shown in FIG. 61), and the command from the game control means A payout control unit (for example, the payout control CPU 37) that controls the payout unit (for example, the ball payout device 97) based on the above.
Dispensing control means including 1: Dispensing control means 37 shown in FIG.
1A) and variable data storage means (for example, a main board 31 provided with a backed-up power supply R that can retain the stored contents for a predetermined period even if the power supply to the gaming machine is stopped)
RAM with power backup included in AM 55 and payout control board 37: fluctuation data storage means 55 shown in FIG.
A, 55B) and the state of a predetermined power supply used in the gaming machine, and detecting conditions related to the stop of power supply to the gaming machine (for example, the voltage value of VSL (+ 30V) which is the monitoring voltage decreases to + 22V). And a power supply monitoring unit (for example, a power supply monitoring IC 902) that outputs a detection signal (for example, a power supply cutoff signal) when the condition is satisfied when the game control unit and the payout control unit respectively monitor the power supply. In order to save the data including the contents of the register (for example, the data of the register used in the CPU 56 or the payout control CPU 371) as the data necessary for restoring the control state according to the detection signal from the means in the variable data storage means. The power supply stop process (for example, the process shown in FIGS. 35 to 37 and the process shown in FIGS. 58 to 60) is executed, and the power supply is restored to a predetermined level. Conditions and steps of the old conditions (for example, step S7~ step S9 S707～ step S709
Recovery condition (for example, game condition recovery process shown in FIG. 18) that restores the control state to the state before the power supply is stopped based on the stored contents stored in the fluctuation data storage means on condition that the condition) is satisfied. And the payout state recovery process shown in FIG. 45) and the initialization process (for example, steps S11 to S15 and steps S711 to S714) for initializing the control state is executed when a predetermined recovery condition is not satisfied. It is possible that the game control means, in the recovery processing, after transmitting a recovery command indicating the recovery of the control state to the payout control means (for example, step S85), the setting of the timer interrupt processing that is regularly activated. The timer interrupt setting process (for example, step S86) is performed, and the register restoration process (for example, step S88) for restoring the contents of the register is performed. The control is restarted, and the payout control unit performs the timer interrupt setting process (for example, step S735) and the register restoring process (for example, step S736) on the condition that the restoration command is received in the restoration process (for example, step S723). ), The control is restarted (for example, the process returns to the payout control after the process of step S741).

A flag indicating that the payout control means prohibits the payout of the game medium regardless of whether the power supply is started and the recovery process is executed or the power supply is started and the initialization process is executed. (For example, a payout stop flag) is set (for example, steps S713, S
732), the flag is reset on condition that a predetermined command (for example, payout state permission designation state command) is received from the game control means (for example, step S753).
e) may be configured.

The game control means is capable of transmitting a payout number designation command indicating the number of prize game medium payouts when a predetermined prize game medium payout condition is satisfied, and transmits the payout number designation command as a recovery command. It may have been done.

In the recovery process, the game control means and the payout control means restore the interrupt state flag indicating whether the state before the power supply was stopped is the interrupt permitted state or the prohibited state (for example, step S89, S738).

When the power supply is restored, the game control means and the payout control means restore a plurality of restoration conditions to determine whether to restore the control state before the power supply was stopped (for example, step S7-). The restoration process is executed when all the conditions of step S9 and the conditions of steps S707 to S709 are satisfied, and the initialization process is executed when at least one condition among the plurality of recovery conditions is not satisfied. It may be configured.

After the game control means starts the power supply and executes the initialization process or the recovery process, a predetermined payout prohibition condition (for example, when the lower plate is full or when the ball is out) , A payout prohibition state designation command for instructing to prohibit the payout of the game medium based on the establishment of a condition that is satisfied when the payout of the game medium cannot be performed or is not appropriate (for example, steps S161 to S164). ), The payout permission state designation command for permitting the payout of the game medium may be transmitted based on the cancellation of the payout prohibition condition (for example, steps S165 to S168).

If any one of the plurality of payout prohibition conditions is satisfied, the game control means sends a payout prohibition state designation command, the payout prohibition condition is canceled, and any payout prohibition condition is satisfied. If there is no state,
Regardless of which of the plurality of payout prohibition conditions is satisfied, a common payout permission state designation command indicating that the payout of the game medium is permitted is transmitted (for example, steps S165 to S168). It may have been done.

Storage state detecting means (for example, full tank switch) for detecting whether or not a predetermined amount or more of the game medium is stored in a storage portion (for example, surplus ball receiving tray 4) in which the paid-out game medium is stored. 48) may be provided, and the payout prohibition condition may be configured to include a condition that is satisfied when the storage state detecting means stores a predetermined amount or more of the game medium.

The game medium out detection means (for example, the ball out switch 187) for detecting whether or not a predetermined amount or more of the game medium supplied to the payout means is secured, and the payout prohibition condition is the game medium out detection. It may be configured to include a condition that is satisfied when the means detects that the game medium is not secured in a predetermined amount or more.

The game control means may be configured to use the payout prohibition state designation command or the payout permission state designation command as the recovery command.

The game control means stores the program address data related to the address of the control program in the variable data storage means as data necessary for restoring the control state in the power supply stop processing (eg, masking is impossible). The return address is saved when the interrupt processing occurs, and the recovery processing is based on the program address data saved in the variable data storage means (for example, RET processing to the address data saved in the stack area). May be configured to resume control).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of a pachinko gaming machine as seen from the front, and FIG. 2 is a front view showing the front surface of the gaming board. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine and can be applied to, for example, an image-type gaming machine or a slot machine.

The pachinko gaming machine 1 is composed of an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame mounted inside the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a frame-shaped glass door frame 2 that is provided in the game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanical parts and the like are attached, and various parts attached to them (excluding a game board described later). It is a structure including and.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply plate (upper plate) 3. Below the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a ball hitting handle (operation knob) 5 for launching the game ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-shaped body that constitutes the game board 6 and various parts attached to the plate-shaped body. A game area 7 is formed on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display device (special symbol display device) 9 including a plurality of variable display portions for variably displaying symbols as identification information is provided. The variable display device 9 includes, for example, “left”, “middle”,
There are three "right" variable display parts (symbol display areas).
A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the starting winning opening 14 is guided to the rear surface of the game board 6 and detected by the starting opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the starting winning opening 14. Variable winning ball device 1
The solenoid 5 is opened by the solenoid 16.

At the lower part of the variable winning ball device 15, an opening / closing plate 20 is provided which is opened by a solenoid 21 in a specific game state (big hit state). Opening plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 (V winning area)
The entered winning balls are detected by the V winning switch 22, and the winning balls from the opening / closing plate 20 are detected by the count switch 23. On the back surface of the game board 6, a solenoid 21A for switching the route inside the special winning opening is also provided. In addition, in the lower part of the variable display device 9, a special symbol starting memory display (hereinafter, referred to as starting memory display) 18 by four LEDs for displaying the number of effective winning balls that have entered the starting winning opening 14, that is, the number of starting memories. Is provided. Each time there is an effective start prize, the start memory indicator 18 increases the number of LEDs to be turned on by one.
Then, each time the variable display of the variable display device 9 is started,
Decrease the number of lit LEDs by 1.

When the game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the display of the normal symbol display 10 is started. In this embodiment, the left and right lamps (the pattern can be visually recognized when turned on) are alternately turned on to perform variable display. For example, when the variable display ends, the right lamp is turned on. And when the stop symbol on the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. Normal symbol display 10
The number of winning balls that entered the gate 32 is displayed near 4
A normal symbol start-up memory display 41 having a display section with two LEDs is provided. Every time there is a prize in the gate 32, the normal symbol starting memory display 41 turns on the LED that is turned on by 1
increase. Then, each time the variable display of the normal symbol display device 10 is started, the number of LEDs to be turned on is reduced by 1.

The game board 6 has a plurality of winning openings 29, 30,
33, 39 are provided, and the winning openings 29, 30, 3 for gaming balls
The prizes for 3 are prize winning opening switches 29a, 30 respectively.
a, 33a, 39a. Each prize hole 2
Reference numerals 9, 30, 33, and 39 form a winning area provided on the game board 6 as an area for accepting a game medium and allowing a prize. It should be noted that the starting winning opening 14 that accepts the game medium and allows the winning, and the special winning opening also constitute the winning area. Decorative lamps 25 that are displayed blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 that absorbs a game ball that has not won is provided in the lower part. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b and a right frame lamp 2
8c is provided. Further, a decorative LED is installed around each structure (a special winning opening, etc.) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of the decorative light-emitting body provided in the game machine.

In this example, the prize ball lamp 51 that lights up when there is a remaining prize ball number near the left frame lamp 28b.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the top frame lamp 28a.
As described above, the pachinko gaming machine 1 of this embodiment is provided with the lamps and the LEDs as the light emitting bodies at various places. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming machine 1 and enables a ball lending by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in an usable state, and a connecting stand direction indicator indicating which side the card unit 50 corresponds to the pachinko gaming machine 1. 153, a card insertion display lamp 154 indicating that a card is inserted in the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The game ball shot from the hitting ball launching device enters the game area 7 through the hit ball rail, and then descends from the game area 7. When the game ball enters the starting winning opening 14 and is detected by the starting opening switch 14a, if the variable display of the symbol can be started, the variable display device 9 starts the variable display (variation) of the special symbol. If it is not in a state where variable display of symbols can be started, the number of starting memories is increased by 1.

The variable display of the special symbol on the variable display device 9 is stopped when a certain time has elapsed. If the special symbol combination at the time of stop is a big hit symbol (specific display result), the big hit game state is entered. That is, the opening / closing plate 2
0 is released until a certain time has elapsed or a predetermined number (for example, 10) of game balls are won. And
When the game ball enters the V winning area and is detected by the V winning switch 22 while the opening / closing plate 20 is open, the continuation right is generated and the opening / closing plate 20 is opened again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

A combination of special symbols in the variable display device 9 at the time of stop is a big hit symbol with a probability variation (probability variation symbol)
In the case of the combination of, the probability of the next big hit is high. That is, the state of probability change is more advantageous for the player.

When the game ball wins the gate 32, the normal symbol display 10 is in a state in which the normal symbol is variably displayed. Further, when the stop symbol in the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 1
5 is opened only for a predetermined time. Furthermore, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 will be a winning symbol is increased, and the opening time and the number of times of opening the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probability variation symbol, and the like, and from a disadvantageous state for the player. Change to an advantageous state. In addition, increasing the number of times of opening is a concept including changing from a closed state to an open state.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a rear view of the gaming machine viewed from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

As shown in FIG. 3, on the back side of the game machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board (mainly a game control microcomputer, etc.) is mounted. Substrate) 31 is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decorations L provided on the game board 6
ED, starting memory indicator 18 and normal symbol starting memory indicator 41, decoration lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 28c, prize ball lamp 51 and ball out lamp provided on the frame side. There is also provided a lamp control board 35 on which a lamp control means for controlling lighting of 52 is mounted, and a sound control board 70 on which a sound control means for controlling sound generation from the speaker 27 is mounted. Also, DC30V,
A power supply board 910 and a firing control board 91 on which a power supply circuit for producing DC21V, DC12V and DC5V is mounted are provided.

On the back side of the game machine, a terminal board 160 having terminals for outputting various information to the outside of the game machine is installed above. Terminal board 160
At least, the terminal for ball breakage for introducing the output of the ball breakage detection switch and outputting it externally, the terminal for prize balls for externally outputting the prize ball number signal and the external output for the ball lending number signal A ball lending terminal is provided. Further, in the vicinity of the center, an information terminal board (information output board) 34 provided with each terminal for outputting various information from the main board 31 to the outside of the gaming machine is installed.

The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. 4, the curve gutter 1
After 86, the ball payout device covered with the prize ball case 40A is reached. At the upper part of the ball payout device, a ball break switch 187 is provided as a game medium cut detection means. When the out-of-ball switch 187 detects out-of-ball, the payout operation of the ball payout device is stopped. The out-of-ball switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage, but the out-of-ball detection switch 167 that detects a shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail 39 (the storage tank 38). (Provided near). When the out-of-ball detection switch 167 detects a shortage of game balls, the supply mechanism provided on the game machine installation island supplies game balls to the game machine.

A large number of game balls as prizes based on prizes and game balls based on ball lending requests are paid out, and the hitting ball supply plate 3 becomes full, and finally the game balls reach the contact port 45 and further When paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In that state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the launching device is also stopped.

As shown in FIG. 4, a ball removing passage 191 extending from the curve gutter 186 to the discharge port 192 at the lower portion of the game machine is formed on the side of the ball payout device. Ball passage 19
1 is provided with a ball removing lever 193, and when the ball removing lever 193 is operated by a game store clerk or the like, a game ball passage from the guide rail 39 to the ball removing passage 191 is formed and stored in the storage tank 38. The played game ball is discharged from the discharge port 192 to the outside of the game machine.

FIG. 5 is an exploded perspective view showing a structural example of the ball payout device 97. In this example, a ball payout device 97 is formed inside the three cases 140, 141, 142 as the prize ball case 40A. Holes 170, 171 communicating with the ball passage at the bottom of the ball break switch 187 are provided in the upper part of the cases 140, 141, and the game ball has holes 170, 171.
It flows into the ball payout device 97 from 171.

The ball payout device 97 includes a payout motor (eg, stepping motor) 289 serving as a drive source. The rotational force of the dispensing motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the dispensing motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls flowing in from the holes 170 and 171 are dropped one by one into the ball passages 293a and 293b below the sprocket 292 by the recesses of the sprocket 292.

Sphere passage (an example of a game medium payout passage) 293
The a and 293b are provided with a distribution member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the distribution solenoid 310, and when paying out the prize balls,
The game balls fall down one of the flow paths (ball path 293a: an example of a prize game medium path) in the ball paths 293a and 293b, and when the ball is lent, the ball paths 293a and 293 are provided.
The game ball falls down in the other flow-down path (ball passage 293b: an example of a lending game medium passage) in b. The payout motor 289 and the distribution solenoid 310 are
It is controlled by a payout control CPU mounted on the payout control board 37. Further, the payout control CPU controls the payout motor 289 and the distribution solenoid 310 in accordance with a command from the game control CPU mounted on the main board 31.

A prize ball sensor (prize ball count switch) 301A for detecting the game balls paid out by the ball payout device is provided below the downflow path selected at the time of paying out prize balls.
A ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by a ball payout device is provided below the flow-down path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals. In addition, prize ball count switch 301
The detection signal A is also input to the CPU of the main board 31.
Power supply board 91 for ball lending count switch 301B
The power supply from 0 is performed through the payout control board 37. Although power is supplied from the power supply board 910 to the prize ball count switch 301A through the main board 31, it may be supplied through the payout control board 37. In addition, a plurality of prize ball sensors and ball lending sensors may be provided respectively. Moreover, as the prize ball sensor, one for the main board 31 and one for the payout control board 37 may be provided separately.

Incidentally, on the peripheral portion of the gear 291, there is formed a protrusion forming a payout motor position sensor. The protrusion allows the light from the light emitting body (not shown) to pass through or shield the light receiving unit (not shown) of the payout motor position sensor in accordance with the rotation of the gear 291 or the rotation of the payout motor 289. To do. The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

Further, the ball payout device may be configured to perform both prize ball payout and ball lending, but a ball payout device for paying a prize ball and a ball payout device for lending a ball are separately provided. It may be. Further, for example, the rotation direction of the sprocket may be changed to divide the prize ball payout and the ball lending, and the ball payout device having any structure other than the ball payout device 97 exemplified in the present embodiment. The present invention can also be applied by using.

FIG. 6 is a front view showing an exposed portion of the power supply board 910 installed on the game board 6. As shown in FIG. 6, most of the power supply board 910 overlaps with the main board 31, but there is an exposed portion that is visible from the outside without overlapping with the main board 31. In this exposed portion, a power switch 914 as a power supply permission means for executing or cutting off power supply to each electric component control board of the gaming machine 1 and each electric part, and each board (main board 31 and payout control) A memory content holding unit (for example, a backup R capable of holding the content even when the power supply is stopped) included in the substrate 37 or the like.
A clear switch 921 is provided as an operating means for clearing the backup data stored in (AM). In this way, since the power switch 914 and the clear switch 921 are arranged close to each other, the operation of the clear switch 921 related to starting power supply to the gaming machine by the power switch 914 becomes easy.

FIG. 7 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 7 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the firing control board 91, and the symbol control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
Control circuit 53, a gate switch 32a, a starting opening switch 14a, a V winning switch 22, a count switch 23, winning opening switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for giving the signal from 21 to the basic circuit 53
8 and a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening / closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching the path in the special winning opening according to a command from the basic circuit 53 are mounted.

Although not shown in FIG. 7, the count switch short circuit signal is also transmitted to the basic circuit 53 through the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Switches such as the prize ball count switch 301A may be called a sensor. That is, a game medium detecting means capable of detecting a game ball (a game ball detecting means in this example)
If so, the name does not matter. In particular, each of the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a for performing the winning detection is also a winning detection means. The winning detection means may be one that collectively detects each of the gaming balls that have been won separately in a plurality of winning openings. Further, even if a passing gate such as the gate switch 32a is used for paying out prize balls, entering a game ball into the passing gate is a prize, and a switch provided in the passing gate (for example, The gate switch 32a) serves as a winning detection means.

Further, according to the data given from the basic circuit 53, the big hit information indicating the occurrence of the big hit, the effective starting information indicating the number of the starting winning balls used for starting the variable display of the symbols on the variable display device 9, and the probability variation. An information output circuit 64 that outputs an information output signal such as probability variation information indicating that it has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 is a ROM 54 for storing a game control program and the like, and R as a storage means (means for storing variation data) used as a work memory.
AM55, CPU5 which controls according to the program
6 and I / O port section 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. Note that the 1-chip microcomputer only needs to have at least the RAM 55 built therein, and
The OM 54 and the I / O port unit 57 may be external or built-in.

Further, a part or all of the RAM (which may be a RAM with a built-in CPU) 55 is a backup RAM backed up by a backup power supply created in the power supply board 910. In other words, even if the power supply to the gaming machine is stopped, the RAM remains for a predetermined period.
The contents of part or all of 55 are saved.

In this embodiment, a low active power-off signal is input from the power supply board 910 to the main board 31. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the CPU 56.

A hitting ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on a launching control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the launch control board 91 controls the game ball to be launched at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 includes the starting memory indicator 18, the normal symbol starting memory indicator 41 and the decorative lamp 25 provided on the game board. In addition to performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the out-of-ball lamp 52 provided on the frame side is performed. Further, the display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the ordinary symbol is the symbol control board 80.
The display control means mounted on the.

FIG. 8 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full tank switch 48 is transmitted via the relay substrate 71 to the main substrate 3.
1 is input to the I / O port unit 57. The detection signal from the ball break switch 187 is also input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates the full state, a payout control command instructing that the payout should be stopped is sent. When receiving the payout control command instructing that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71, and the payout control is also performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid award ball.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port (output port 0) 570 outputs a 1-bit INT signal. The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is
Input a payout control command through the O port 372a,
The ball payout device 97 is driven in accordance with the payout control command to perform prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a built-in RAM.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A lent ball number signal indicating the number of lent balls is output to the terminal board 160 via 72c. Furthermore, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signals from the ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually loaned ball. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the distribution solenoid 3 is used.
The drive signal to 10 is transmitted to the distribution solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a usable indicator lamp 151, a connecting stand direction indicator 153, a card insertion indicator lamp 154 and a card insertion slot 155 (see FIG. 1). To the balance display board 74, a frequency display LED, a ball lending switch and a return switch, which are provided in the vicinity of the hitting ball supply tray 3, are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. As described above, the balance display board 74 and the card unit 50 are connected to each other via the payout control board 37 without being directly connected. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BR).
The Q signal), the ball lending completion signal (EXS signal) and the pachinko machine operation signal (PRDY signal) are exchanged via the input port 372b and the output port 372e. In addition, between the card unit 50 and the payout control board 37,
An interface board (not shown) is interposed. Between the card unit 50 and the payout control board 37, a connection signal (V
Signals such as L signal) are exchanged via the interface board. Further, signals are not directly exchanged between the balance display board 74 and the interface board.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

Then, the payout control C of the payout control board 37 is used.
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. After that, if the BRDY signal from the card unit 50 is not on,
The prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, the payout control board 3
At least a part of the RAM (may be a RAM with a built-in CPU) existing in 7 is backed up by a backup power supply created in the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is saved for a predetermined period.

In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. May be. Further, the present invention can be applied even in the case where a game ball corresponding to the amount of coins is lent out according to the coin insertion.

FIG. 9 is a block diagram showing an example of the structure of the power supply board 910. The power supply board 910 is a main board 31, a pattern control board 80, a sound control board 70, and a lamp control board 35.
And, it is installed independently of the electric component control board such as the payout control board 37, and generates the voltage used by each electric component control board and the mechanical parts in the gaming machine. In this example, AC24
V, VSL (DC + 30V), DC + 21V, DC + 12
Generates V and DC + 5V. Further, the capacitor 916 serving as a backup power source, that is, a memory holding unit is
It is charged from C + 5V, that is, from the line of the power supply that drives the ICs on each substrate. Note that VSL is generated in the rectifier circuit 912 by rectifying and boosting AC24V with a rectifying element. VSL serves as a solenoid drive power source.

The power supply board 910 is provided with a power switch 914 for executing or cutting off power supply to each electric part control board and mechanical parts in the game machine. The transformer 911 converts the AC voltage from the AC power supply into 24V. The AC 24V voltage is output to the connector 915.
The rectifier circuit 912 also generates a DC voltage of + 30V from AC 24V and outputs the DC voltage to the DC-DC converter 913 and the connector 915. DC-DC converter 913
Has one or more converter ICs 920 (only one is shown in FIG. 9) and is +21 based on VSL.
V, + 12V and + 5V are generated and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 920. Therefore,
When the power supply to the game machine from the outside is stopped,
DC voltages such as + 30V, + 12V, and + 5V drop relatively slowly. Also, on the input side of the connector 915,
A relatively large-capacity capacitor 924 is connected. Therefore, the + 30V DC voltage output to the connector 915 drops more gently than other DC voltages. As a result, the capacitors 923 and 924 serve as an auxiliary drive power source, which will be described later. The connector 915 is connected to, for example, a relay board, and the relay board supplies electric power of a required voltage to each electric component control board and mechanical components.

However, the power supply board 910 may be provided with each connector reaching each electric component control board so that each voltage can be supplied from the power supply board 910 to each board without the relay board. In addition, one connector 9 is shown in FIG.
Although 15 is representatively shown, the connector is provided for each electric component control board.

+ 5V from the DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the game machine is stopped (RAM whose power is backed up, that is, backup storage means that can be in a storage content holding state even when the power supply is stopped).
It becomes a backup power supply that supplies electric power so that the memory state can be maintained. In addition, a diode 9 for preventing backflow is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, the backup + 5V is applied to the main board 31 and the payout control board 3
7 is supplied.

A battery that can be charged from a + 5V power source may be used as the backup power source. When a battery is used, a rechargeable battery is used which loses its capacity when the power is not supplied from the + 5V power source for a predetermined time. Further, instead of the capacitors 923 and 924 described above, a battery that can be charged from a + 30V power source may be used.
When a battery is used instead of the capacitor 923, a rechargeable battery that can supply power to the prize ball count switch 301A and the ball lending count switch 301B for a period equal to or longer than a payout confirmation period described later is used. Also, the capacitor 924
When a battery is used instead of the rechargeable battery, a rechargeable battery that can supply power to the distribution solenoid 310 for a period equal to or longer than a payout confirmation period described later is used. The above-mentioned battery does not have to have a charging function, and a battery such as a nicad battery, an alkaline battery, a manganese battery, or the like can be used.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, it is determined that the power supply will be stopped, and a power-off signal is output (specifically, set to low level). The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC
Is used. The power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Furthermore, VSL (+ 30V) is used as the monitoring voltage.
In the case of using, since the voltage supplied to the various switches of the gaming machine is + 12V, it can be expected to prevent erroneous detection of switch-on at the moment of power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in + 12V generated after + 30V is generated, before the voltage starts to drop. When the voltage of the + 12V power supply drops, the switch output starts to turn on. However, if the + 30V power supply voltage that drops earlier than + 12V is monitored and it is recognized that the power supply has stopped, the power supply will turn on before the switch output turns on. It is possible to enter a state of waiting for restoration and enter a state in which no switch output is detected.

Further, VSL (+ 30V) as a monitoring voltage
Unlike the input line to the power supply monitoring IC 902, VSL (+
A large-capacity capacitor 924 is connected to the input line to the connector (915) of 30V. Therefore, VSL (+ 30V) as the monitoring voltage is the large-capacity capacitor 92.
VSL output to connector 915 to which 4 is connected
It drops faster than (+ 30V). That is, even after VSL (+ 30V) as the monitoring voltage starts to drop, the supply state of VSL (+ 30V) as the voltage supplied to the solenoid and the motor is maintained for a predetermined period. After that, VSL as the voltage supplied to the solenoid, motor, etc.
(+ 30V) gradually decreases. Therefore, even when VSL (+30 V) as the monitoring voltage starts to drop, the solenoid, the motor, etc. can be driven for a predetermined period. Further, the stop of the power supply can be recognized before the VSL (+ 30V) output to the connector 915 starts to drop.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric part control board, the power supply cutoff circuit can supply the power supply cutoff signal to the plurality of electric part control boards. Even if there are any number of electrical component control boards that require a power-off signal, one power source monitoring means may be provided, so that even if each electrical component control means in each electrical component control board performs recovery control described below. , The cost of gaming machines does not rise so much.

In the configuration shown in FIG. 9, the detection signal (power-off signal) of the power supply monitoring IC 902 is transmitted through the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control circuit). Although it is transmitted to the substrate 37), for example, one detection signal may be transmitted to the relay substrate and the same signal may be distributed from the relay substrate to each electric component control substrate. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Furthermore, regarding the power-off signal output to the main board 31 and the payout control board 37,
The monitoring voltage of the power supply monitoring circuit that outputs the power-off signal may be different.

As shown in FIG. 9, the power supply board 910 includes
A clear switch 921 having a push button structure is mounted. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the like via the connector 915. If the clear switch 921 is not pressed, a high level (off state) signal is output. In this embodiment, when the clear signal in the ON state is output, the operation signal is output from the clear switch 921 as the operation unit. The clear switch 921
It may have a configuration other than the push button structure.

In this embodiment, the clear switch 92
Since 1 is mounted on the power board 910, even if the power board 910 is used as it is for the game board 6 after replacement when the game board 6 is replaced, etc., the game board 6 after replacement remains unchanged. It is possible to execute a game state restoration process and the like. That is, the power supply board 910 can be reused. Note that the clear switch 92 may be provided on another board such as a switch board instead of the power board 910.
1 may be mounted.

The power supply board 910 is equipped with a return signal generating circuit 970 for supplying a return signal to each board. The return signal is output to the main board 31 via the buffer circuit 961 and is output to the payout control board 37 via the buffer circuit 962.
Is output to.

FIG. 10 is a block diagram showing a configuration example of the return signal generation circuit 970. Return signal generation circuit 970
Includes a counter 971 that is an example of a return signal output unit that measures the standby period and outputs a return signal. Counter 9
71 counts the clock signal from the oscillator 975 when the power-off signal goes low and the clear is released. Then, upon counting up, one high-level pulse is generated as the Q output. The pulse signal is logically inverted by the inversion circuit 972 and input to the buffer circuit 973 and the buffer circuit 974. The output of the buffer circuit 973 is supplied to the payout control board 37 as a return signal, and the output of the buffer circuit 974 is supplied to the main board 31 as a return signal.

In this embodiment, the power supply board 91
Although the return signal generation circuit 970 is provided in 0 to output the return signal to the main board 31 and the payout control board 37, the return signal generation circuit is provided in each of the main board 31 and the payout control board 37. May be.

FIG. 11 shows the CPU 56 in the main board 31.
It is a block diagram showing an example of the circumference. As shown in FIG. 11, the power-off signal from the power-supply monitoring circuit (power-supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. Therefore, CP
U56 can confirm the occurrence of power failure by the non-maskable interrupt process.

The reset IC 651A in the system reset circuit 65A sets the output to the low level for a predetermined time determined by the capacity of the external capacitor when the power is turned on, and sets the output to the high level after the predetermined time has elapsed.
That is, when the reset signal is raised to high level, CP
Enable U56. In addition, reset IC65
1A monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, and the voltage value is below a predetermined value (value lower than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). Output goes low. Therefore, the CPU 56 is reset in the system (that is, returned to the initial state of the system) after performing a predetermined power supply stoppage process in response to the power off signal from the power monitoring circuit.

As shown in FIG. 11, the reset IC 651 is used.
The reset signal from A is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inversion circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. Then, the Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration,
When the power is turned on, a reset signal (low level signal) is given twice to the reset terminal of the CPU 56.
56 reliably starts operation.

Then, for example, the detection voltage of the power supply monitoring circuit mounted on the power supply substrate 910 (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to the low level is + 9V. And In such a configuration, since the power supply monitoring circuit and the system reset circuit 65A monitor the voltage of the same power supply VSL, the timing at which the voltage monitoring circuit outputs the power-off signal and the system reset circuit 65A reset the system. It is possible to reliably set the difference between the timings of outputting the signals in a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop time process to the reliable completion of the power supply stop time process in response to the power off signal from the power supply monitoring circuit. The power supply monitoring circuit and the system reset circuit 6
The voltage of the power supply monitored by 5A may be different.

While the power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board 910, and the power supply to the gaming machine is stopped. The contents are saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65A, so that the CPU 56 returns to the normal operating state. At that time, the necessary data is backup RA
Since it is saved in M, it can be restored to the game state at the time of occurrence of a power failure or the like when the power failure or the like is restored.

In the structure shown in FIG. 11, the reset signal (low level signal) is applied twice to the reset terminal of the CPU 56 when the power is turned on. When using the released CPU, reference numerals 941 to 949
The circuit element indicated by is unnecessary. In that case, the output of the reset IC 651A is directly connected to the reset terminal of the CPU 56.

Further, as shown in FIG.
Return signal from 0 and reset signal from system reset circuit 65A (specifically, output of AND circuit 949)
Is input to the AND circuit 161, and the output of the AND circuit 161 is input to the reset terminal (reset signal input section) of the CPU 56.

FIG. 12 is a timing chart for explaining the operation of counter 971 in return signal generating circuit 970. As shown in FIG. 12A, when the power supply voltage drops and the voltage value of VSL drops to the power cutoff signal output level (+ 22V in this example), a power cutoff signal is generated. Specifically, the power-off signal goes low. Then, as will be described later, the CPU 31 of the main board 31 and the payout control CPU 371 start execution of the power supply stop time process,
When the processing is completed, a loop state (standby state) in which no control is performed is entered.

The counter 971 starts counting when the power-off signal goes low, but the count-up value is VSL after the power-off signal goes low.
Is set to be equal to or longer than the time required for the voltage value of 1 to drop to the voltage capable of generating Vcc. That is, at least the power supply voltage is set to be longer than or equal to the time for which the control operation is disabled. Since the counter 971 operates using Vcc as a power source, the count-up value is set to a value equal to or greater than the value corresponding to the operable period of the counter 971. Therefore, in general,
Before the counter 971 counts up and the return signal is output, the counter 971 and other circuit components do not operate.

When the power source is momentarily cut off or the like, as shown in FIG. 12B, the voltage level of VSL is reduced for a short period of time and then restored. When the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level and the power supply stop processing is started. Then, the CPU 56 and the payout control CPU 371 enter the loop state after the end of the power supply stop process. The loop processing cannot be exited without any control. In this case, the counter 971 counts up and a return signal is generated.

On the main board 31, the return signal is AND
It is input to the reset terminal of the CPU 56 via the circuit 161. Therefore, the CPU 56 is reset. As a result, the CPU 56 can get out of the loop state. Further, as will be described later, the payout control board 3
In 71, the return signal is input to the reset terminal of the payout control CPU 371 via the AND circuit 385 (see FIG. 40). Therefore, the payout control CPU 371 is reset. As a result, C for payout control
The PU 371 can get out of the loop state.

13 and 14 are explanatory views showing the allocation of output ports in this embodiment. Figure 1
As shown in FIG. 3, the output port 0 is an output port of the INT signal of the control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1,
The 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2, and the 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. And in FIG.
As shown in, the 8-bit data of the sound control command sent to the sound control board 70 is output from the output port 4.

Also, from the output port 5, the information output circuit 6
Various information output signals reaching the information terminal board 34 and the terminal board 160 via 4, that is, output data of information relating to control are output. Then, from the output port 6, a solenoid 16 for opening / closing the variable winning ball device 15, a solenoid 21 for opening / closing the opening / closing plate 2 of the special winning opening, and a solenoid 21 for switching a path in the special winning opening.
The drive signal for A is output.

As shown in FIG. 14, the payout control board 37,
An output port for outputting each INT signal (payout control signal INT, display control signal INT, lamp control signal INT, and voice control signal INT) output to the pattern control board 80, the lamp control board 35, and the sound control board 70 ( The output port 0) and the output ports (output ports 1 to 4) for outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 and the sound control signals CD0 to CD7 are different ports. Is.

Therefore, when the INT signal is output, the payout control signals CD0 to CD7 and the display control signals CD0 to CD0 are mistakenly output.
The possibility of changing the CD7, the lamp control signals CD0 to CD7, and the audio control signals CD0 to CD7 is reduced. Also, when the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 or the voice control signals CD0 to CD7 are output, the I
The possibility of changing the NT signal is reduced. As a result, the command to the electric component control board from the game control means of the main board 31 is more reliably transmitted. Further, since each INT signal is configured to be output from the output port 0, I of the game control means.
The load of NT signal output processing is reduced.

FIG. 15 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 15, bits 0 to 7 of the input port 0 are respectively connected to the winning opening switches 33a, 39a, 29a, 30a,
Detection signals of the gate switch 32a, the starting opening switch 14a, the count switch 23, and the V winning switch 22 are input. In addition, the detection signals of the prize ball count switch 301A, the full tank switch 48, the ball cut switch 187, the count switch short circuit signal, and the detection signal of the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. In this way, the detection signal of the clear switch 921, that is, the operation input of the operating means, is the input port to which the detection signal of the switch for detecting the game ball is input (8-bit input section).
Bit in the same input port as (input port circuit)
Has been entered in.

Next, the operation of the gaming machine will be described. Figure 1
6 is a flowchart showing main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main processing, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the top address of the stack area is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, initialization of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) (step S
After performing 5), the RAM is set to the accessible state (step S6).

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, the CTC has two external clock / timer trigger inputs CLK / TRG2,3.
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has an RST instruction (1 byte) or a CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode to always fly to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the internal device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it becomes possible to easily process the interrupt request from each built-in device, and the interrupt processing can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input through the input port 1 only once (step S7). If ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level (see FIG. 15). Further, for example, the game shop clerk uses the clear switch 92.
By starting power supply to the gaming machine while turning on 1 (for example, turning on the power switch 914), the initialization process can be easily executed. That is, the RAM clear or the like can be performed.

If the clear switch 921 is not in the ON state, data protection processing of the backup RAM area (for example, processing when power supply is stopped such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. When such a protection process is performed, backup is made. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area during the power supply stop process. In this example, as shown in FIG. 17, if "55H" is set in the backup flag area, it means that there is backup (on state), and if a value other than "55H" is set, there is no backup (off). State).

After confirming that there is a backup, the CPU 5
6 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Further, the number of checksum calculations corresponding to the number of checksum target data is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The data after inversion is used as the checksum.

In the power supply stop process, the checksum is calculated by the same process as the above process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If the power is restored after an unexpected power outage such as a power outage, backup RA
Since the data in the M area should have been saved, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply was stopped. In such a case, since the internal state cannot be returned to the state when the power supply was stopped, the initialization process that is executed when the power is turned on, not when the power supply is restored from the stop, is executed.

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply was stopped (step S10). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored.

In this way, if "backup is present" is not confirmed by the state of the backup flag, the initialization process described below is performed without performing the game state recovery process described below, so the backup data It is possible to prevent the game state restoration process from being executed even though there is no, and it is possible to return the control state to the initial state by the initialization process.

Further, when the check result using the check data is not normal, the initialization process described below is performed without performing the game state restoration process described below, so that the power supply is stopped. It is possible to prevent the game state restoration process from being executed based on the backup data having different contents, and it is possible to return the control state to the initial state by the initialization process.

The CPU 56 uses the backup flag and the check data such as the checksum to perform the backup R.
Check whether the data in the AM area is saved.
That is, when the power supply is restored, a plurality of restoration conditions for determining whether to restore the control state before the power supply is stopped (in this example, the backup flag is stored normally) If all the checksums are normal), a recovery process for recovering the control state is executed based on the stored contents stored in the variable data storage means, and at least one of the plurality of recovery conditions is set. When the condition is not satisfied, it is possible to execute the initialization process for initializing the storage contents of the fluctuation data storage means. By using a plurality of recovery conditions, it is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved.

When the operation signal is output from the operation means, the initialization process is executed regardless of the plurality of restoration conditions (step S7). Further, in this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used.
That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

In the initialization processing, the CPU 56 first executes R
AM clear processing is performed (step S11). RA
The predetermined data (for example, the data of the count value of the counter for generating the big hit determination random number) may be left as it is without initializing the entire area of M. For example, when the data of the count value of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by an unauthorized means. It is difficult to aim at a timing when the count value of the counter coincides with the jackpot determination value. Further, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol process flag, a payout command storage pointer, an award ball flag, a ball out flag, a payout. Work area setting processing for setting an initial value to a flag such as a stop flag for selectively performing processing according to the control state is performed (step S12).

Further, the CPU 56 determines whether or not a predetermined payout prohibition condition is satisfied (step S13).
a), if the payout prohibition condition is not satisfied, a payout permission state designation command (hereinafter referred to as a payable state designation command) for instructing that the payout from the ball payout device 97 is possible is given to the payout control board 37. A process of transmitting the same is performed (step S13b). If the payout prohibition condition is satisfied, the control state of the main board 31 is set to the payout prohibition state.

In this embodiment, the out-of-ball flag is set to the out-of-ball state (on state), and the full tank flag is set to the down-bottom full tank state (on state). Set the control state to the withdrawal prohibition state.
The payout prohibition condition is, for example, when the ball is out of stock or when the bottom plate is full, and there is a possibility that the game ball to be paid out cannot be paid out or the game ball is paid out. Applies if not appropriate. Therefore, in step S13a, for example, the out-of-ball switch 1
The confirmation of the detection state by 87 and the confirmation of the detection state by the full tank switch 48 are performed. Note that step S13a
Since the timer interrupt setting to be described later has not been made at the stage when the determination processing of (1) is executed, a monitoring time (for example, 2 ms) is created by a wait processing by a software timer and the like, and processing for monitoring the state of the switch described later is performed. By executing the same process, the states of the out-of-ball switch 187 and the full-fill switch 48 may be monitored at each monitoring time to determine whether the switch is turned on.

Further, the CPU 56 is another sub board (lamp control board 35, sound control board 70, symbol control board 80).
A process of transmitting an initialization command for initializing the sub board to each sub-board is executed (step S14). As the initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and the prize ball lamp 5
1 and a command (to the lamp control board 35) for instructing to turn off the out-of-bulb lamp 52.

In the initialization processing, a payable state designation command is transmitted to the payout control board 37 when the payout prohibition condition is not satisfied, and a payout prohibition state designation command is sent when the payout prohibition condition is satisfied. Is not sent. Even if the state of the gaming machine is a state in which the payout from the ball payout device 97 is not possible (a state in which the payout prohibition condition is satisfied), the payout prohibition state in the initialization process in the payout control board 37. It should be set to, so there is no problem. In the process of transmitting the payable state designation command and the initialization command to other sub-boards, for example, the address of the table (ROM area) in which each command is set is set in the pointer, and the command setting process described later (Fig. 32)).

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S15). That is,
A value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Specifically, one of the control registers (for example, CH3) provided for each of a plurality of timers (for example, four timers) has a timer interrupt set value (in this example, A7).
(H): Set interrupt enable, reset, etc., and then set time constant data (count value, 2E (H) in this example) according to 2 ms in the control register.

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number updating process and the initial value random number updating process are executed, the interrupt disabled state is set (step S16), and when the display random number updating process and the initial value random number updating process are completed, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining the symbol displayed on the variable display device 9, and the display random number updating process is a process of updating the count value of the counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random numbers. The initial value random number is a random number for determining an initial value of a count value of a counter (big hit determination random number generation counter) for generating a random number for determining whether or not to make a big hit. In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, the initial value is set to the counter.

Note that, when the display random number updating process is executed, the interrupt prohibited state is set because the display random number updating process is also executed in the timer interrupt process described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt prohibition state is set during the process of step S17.

FIG. 18 is a flow chart showing an example of the game state restoration processing. In the game state recovery process, C
The PU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (a stack pointer save buffer in a work area where power is backed up) in a power supply stop process which will be described later in detail. Therefore,
In step S81, the value of the RAM area is set in the stack pointer to restore the value. Note that the area pointed to by the restored stack pointer (that is, the read destination in the stack area that stores the return address etc. when the subroutine is called: more specifically, a plurality of areas after that) is the area when the power supply is stopped. Register values and program counter (PC) values are saved.

Then, the CPU 56 transmits a display control command for restoring the display state of the special symbol on the variable display device 9 when the power supply is stopped (step S82).

Further, the prize ball count value stored in the backup RAM is reflected in the total prize ball number storage buffer and the prize ball information counter for outputting the prize ball information to the outside of the gaming machine (step S84). The prize ball count value corresponds to the number of payout balls detected in the power supply stoppage process described later. In step S84, the CPU 56 performs processing of subtracting the prize ball count value from the value stored in the total prize ball number storage buffer and adding the prize ball count value to the count value of the prize ball information counter. Then, the prize ball count value is cleared.

Next, the CPU 56 unconditionally transmits to the payout control means a payout control command (payable state designation command) (step S85).

Since the payout control means always receives the payout control command from the game control means when the power supply is restored, it is possible to immediately recognize that the game control means has normally started up. In reality, even if the supply ball shortage or the surplus ball receiving tray 4 is full, the payout prohibition state designation command is transmitted to the payout control means in the prize ball processing, so that the supply ball shortage or Even if the surplus ball tray 4 is full, the payout control will not be continued. Further, instead of sending the payable state designation command, the payout control command transmitted last before the power supply is stopped may be sent. That is, the recovery command does not always have to be the same command. Further, a payout control command for designating the number of prize balls may be transmitted. In that case, the payout control means is also performing the control state restoration process, but after performing the control state restoration process, control such as ignoring the contents specified by the payout control command received within the predetermined time To do.

In this embodiment, the game control means restores the stack pointer in the game state restoration process executed when the power supply is restored, and then restores the control state to the payout control board 37. Unconditionally transmitting a payable state designation command as a recovery command indicating that the operation is to be performed. Next, a timer interrupt setting and a register restoration process described later are performed. By configuring to send the recovery command unconditionally to the payout control board 37,
The game control means does not need to perform extra confirmation processing (confirmation of whether or not payout is possible). As will be described later, the payout control means mounted on the payout control board 37 sets the timer interrupt and registers on the condition that the recovery command is received in the payout state recovery process executed when the power supply is restored. Then, the payout control is restarted.

In this embodiment, the game control means unconditionally transmits a payout possible state designation command as a recovery command, but it is confirmed whether or not the game balls can be paid out. However, if it is possible, the payout possible state designation command may be transmitted as a recovery command, and if it is not possible, the payout prohibition state designation command may be transmitted as a recovery command. The state in which the gaming balls cannot be paid out is, for example, a state in which the supply balls are insufficient or the surplus ball tray 4 is full. When the payout prohibition state designation command is transmitted as the recovery command, when the game balls are ready to be paid out in the game control process executed after the game state recovery process is finished, the game control means is , Send the payable state designation command.

In the game state restoration processing, even if it is confirmed whether or not the payout of the game balls is possible before the restoration command is transmitted, the payout control means is provided when the power supply is restored. Since the recovery command is always received from the game control means, it is possible to immediately recognize that the game control means has normally started up. Therefore, even when the game control means and the payout control means are configured to start at the same time when the power supply start is restored, the payout control by the payout control means is controlled by the game control means (for example,
It is synchronized with the game ball payout monitoring control).

The recovery command transmitted in the game state recovery process is the same as the command relating to payout control transmitted in the game control process. That is,
The payout possible state designation command for instructing the payout possible or the payout prohibited state designation command for instructing the payout prohibition transmitted in the game control process is used as the recovery command in the game state recovery process. Therefore, even if the recovery command is transmitted in the game state recovery process, the number of types of payout control commands does not increase.

After that, a timer interrupt setting process for setting the timer interrupt process so that a timer interrupt is taken every 2 ms is executed (step S86). For example, a plurality (for example, 4
One) of the control registers (for example, CH3) among the control registers provided for each of the certain timers, the timer interrupt set value (A7 (H) in this example: interrupt enable or reset). Settings, etc.), then 2
Time constant data (count value, 2E (H) in this example) according to ms is set in the control register. Also, CPU
56 clears the backup flag (step S
87) That is, the flag indicating that the predetermined memory protection process has been executed at the time of the previous power supply stop is reset.
Therefore, it is possible to prevent unnecessary information from remaining after the control state is restored.

Furthermore, the saved values of various registers are read from the stack area, and the various registers (IX register, H
The L register, the DE register, and the BC register) are set (step S88). That is, register restoration processing is performed. The value of the stack pointer is decremented each time each register is restored. That is, the value of the stack pointer is updated to point to the address immediately before the stack area. Further, the parity flag is restored from the stack area, and the interrupt flag (interrupt state flag) is restored according to the contents (step S89). The interrupt flag is
This is an internal flag of the CPU 56 and indicates whether it is in the interrupt permission state or the prohibition state. In this case, the interrupt flag indicates whether the state before the power supply was stopped was the interrupt permitted state or the prohibited state.

Then, when the parity flag is not turned on, the interrupt enable state is set (step S9).
1, S92). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S93).

Then, the RET instruction is executed. RET
When the instruction is executed, the CPU 56 realizes the return operation of the program by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state recovery processing. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S89, the stack pointer pointing to the stack area is NM.
It indicates the area where the address of the program being executed when the power supply stop processing by I was started is saved. That is, the return address stored in the stack area pointed to by the restored stack pointer is
This is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, the next RET instruction in step S92 returns to the address where the NMI occurred when the power supply was stopped.

As described above, in this embodiment, the game control is restarted based on the address data (program address data) saved in the stack area.

When a timer interrupt occurs, the CPU 56
After performing the register saving process (step S20), the game control process of steps S21 to S32 shown in FIG. 19 is executed. In the game control process, the CPU 56 first
Via the switch circuit 58, the detection signals of the switches such as the gate switch 32a, the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a are input to determine their states (switch processing: Step S21).

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used for game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

Further, the CPU 56 carries out special symbol process processing (step S26). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S27). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. And the value of the normal symbol process flag,
It is updated during each process according to the game state.

Next, the CPU 56 performs a process of sending a display control command by setting a display control command relating to a special symbol in a predetermined area of the RAM 55 (special symbol command control process: step S28). In addition, the display control command relating to the normal symbol is set in a predetermined area of the RAM 55 and a process of transmitting the display control command is performed (normal symbol command control process: step S29).

Further, the CPU 56 performs an information output process for outputting data such as big hit information, starting information, probability variation information, etc. supplied to the hall management computer (step S30).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). In order to open or close the variable winning ball device 15 or the opening / closing plate 20 or to switch the game ball passage in the special winning opening, the solenoid circuit 59 drives the solenoids 16, 21, 21A according to the drive command. To do.

Then, the CPU 56 causes the winning opening switch 2
A prize ball process is performed for setting the number of prize balls based on the detection signals of 9a, 30a, 33a and 39a (step S32). Specifically, the winning opening switches 29a, 30
The payout control command indicating the number of prize balls is output to the payout control board 37 in response to the winning detection based on the turning on of a, 33a, and 39a. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in response to a payout control command indicating the number of prize balls. afterwards,
The contents of the register are restored (step S33), and the interrupt enabled state is set (step S34).

According to the above control, in this embodiment, the game control process is activated every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set,
The game control process may be executed in the main process.

Next, a specific example of the switch process (step S21) in the game control process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch is certainly turned on, and the process corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 20, the switch timers are provided by the number n of detection signals (excluding the detection signal of the clear switch 921). In this embodiment, n = 13. Further, in the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 15).

FIG. 21 is a flow chart showing a processing example of the switch processing of step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs the data input to the input port 0 (step S101). Then
The number of processes is set to "8" (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, the switch check processing subroutine is called (step S104).

FIG. 22 is a flow chart showing a switch check processing subroutine as an input processing routine. In the switch check processing subroutine, C
The PU 56 sets the port input data, in this case, the input data from the input port 0 as the “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, while loading the switch timer pointed by the pointer (the address of the switch timer is set) (step S123),
The comparison value is shifted to the right (direction from the higher bit to the lower bit) (step S124). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after addition becomes 0, the added value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in the off state, clear data is set in the switch timer (step S126). That is, if the switch is in the off state, the value of the switch timer returns to 0.

Thereafter, the CPU 56 adds 1 to the pointer (address of the switch timer) (step S130) and subtracts 1 from the number of processes (step S13).
1). If the number of processes is not 0, step S122
Return to. Then, the processing of steps S122 to S132 is repeated.

The processes of steps S122 to S132 are repeated by the number of processes, that is, eight times, and during that time, the switch detection signals input to the 8 bits of the input port 0 are sequentially turned on or off. If the check process is performed and the switch is on, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes step S of the switch processing.
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S107). Then, the switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is executed, steps S122 to S122
The processing of 132 is repeated for the number of processings, that is, four times, and during that time, with respect to the detection signal of the switch input to the 4 bits of the input port 1, the check processing of whether it is in the on state or the off state is performed sequentially. If it is on, the value of the corresponding switch timer is incremented by one.

In this embodiment, the game control process is activated every 2 ms, so the switch process is also performed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

23 to 25 are flowcharts showing an example of the prize ball process of step S32 in the game control process. In the present embodiment, in the prize ball processing, the prize winning hole switches 33a, 39a, 29a, which are targets of prize ball payout,
30a, count switch 23 and starting opening switch 1
4a is surely turned on, and when turned on, the payout control command indicating the number of prize balls is controlled to be sent to the payout control board 37, and the full tank switch 48 and the out-of-ball switch 187 are controlled. Whether or not it is surely turned on is determined, and when it is turned on, processing such as controlling to send a predetermined payout control command to the payout control board 37 is performed.

In the prize ball process, the CPU 56 sets "1" as the offset of the input determination value table (step S150) and "9" as the offset of the switch timer address (step S151). The offset “1” in the input determination value table (see FIG. 27) is
This means that the second data “50” in the input determination value table is used. Further, each switch timer is shown in FIG.
Since they are arranged in the same order as the bit order of the input ports shown in FIG. 3, the offset "9" of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input judgment value table is set with a judgment value for each switch, which is used to judge that the switch is surely turned on when the number of times the switch is continuously turned on is set.
It is the M region. An example of the structure of the input judgment value table is shown in FIG. As shown in FIG. 27, in the input determination value table, “2”, “50”, “250”, “30”,
The determination values of "250" and "1" are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the switch timer value determined by the start address of the switch timer and the offset value, and they match. In that case, the switch-on flag is set, for example.

An example of the switch-on check routine is shown in FIG. In the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the full-tank switch 48 matches the full-tank switch-on determination value "50" (step S153), so the full-tank flag is set. (Step S
154). Although not clearly shown in FIG. 23, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

Further, the CPU 56 sets "2" as the offset of the input judgment value table (step S15).
5), "0A (H)" is set as the offset of the switch timer address (step S156). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “0A (H)” is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S157).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
58), the out-of-ball flag is set (step S15).
9). Although not clearly shown in FIG. 23, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when the value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 confirms whether or not the payout is prohibited (step S160). The payout prohibition state is a state after the payout prohibition state designation command, which is a payout control command for instructing the payout control board 37 to be in a state in which the payout should be stopped, specifically, the work area. The payout stop flag in is set. If it is not in the payout prohibition state, it is confirmed whether or not the above-mentioned out-of-ball state flag or full tank flag is turned on (step S161).

When any of them changes to the ON state,
The payout stop flag is set (step S16).
2) The command transmission table relating to the payout prohibition state designation command is set (step S163), and the command setting process is called (step S164). In step S163, a command transmission table (RO that stores the payout control command of the payout prohibition state designation command).
The start address of M) is set as the address of the command transmission table. The command transmission table relating to the payout prohibition state designation command includes INT data, which will be described later,
Data of the first byte of the payout control command and data of the second byte of the payout control command are set. In step S161, when one of the flags is already in the on state and the other flag is in the on state, steps S162 to S16.
The process of 4 is not performed.

If the payout is prohibited, it is confirmed whether the out-of-ball flag and the full tank flag are both turned off (step S165). When both are in the off state (when the release condition described later is satisfied), the payout stop flag is reset (step S166), and the command transmission table relating to the payable state designation command is set (step S167). The set process is called (step S168). In step S167, the head address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payable state designation command, INT data, which will be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

The cancel condition is a condition for canceling the payout prohibition state and is satisfied when it is no longer necessary to maintain the payout prohibition state. In this embodiment, the release condition is that the surplus ball receiving tray 4 is not in the full tank state or in the ball out state when the payout forbidden state is set.

Further, the CPU 56 sets "0" as the offset of the input judgment value table (step S16).
9), "0" is set as the offset of the switch timer address (step S170). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “0” specifies the switch timer corresponding to the winning opening switch 33a. Means Also, "4" is set as the number of repetitions (step S171).
Then, the switch-on check routine is called (step S172).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 27) (step S281). And
An offset is added to the address (step S28
2) The switch-on determination value is loaded from the added address (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the added address (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, the switch-on flag is set (step 228).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value "2", the switch-on flag is set (step S1).
73). Then, the switch check-on routine is executed for the number of repetitions set initially (steps S176, S177) while the address offset of the switch timer is updated (step S178).
After all, the winning opening switch 33a, 39a, 29a, 30a
For, the value of the corresponding switch timer is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" as the number of prize balls to be paid out is set in the ring buffer (step S174). Then, 10 is added to the value stored in the total prize ball number storage buffer (unpaid amount data) (step S175). When data is written in the ring buffer, the write pointer is incremented, and when data is written in the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball numbers instructed to the payout control means (however, it is subtracted when the payout is made).
It is formed in the backup RAM. In this embodiment, when the data is written in the ring buffer, addition processing is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, addition processing of the number of prize balls corresponding to the payout control command to be output may be performed on the stored value of the total prize ball storage buffer.

Next, the CPU 56 sets "0" as the offset of the input determination value table (step S17).
9), "5" is set as the offset of the switch timer address (step S180). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset "5" specifies the switch timer corresponding to the starting port switch 14a. Means Then, the switch-on check routine is called (step S
181).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a matches the switch-on determination value "2", the switch-on flag is set (step S182). When the switch-on flag is set, "6" as the number of prize balls to be paid out is set in the ring buffer (step S183). In addition, the value stored in the total prize ball storage buffer is 6
Is added (step S184).

Next, the CPU 56 sets "0" as the offset of the input determination value table (step S18).
5), "6" is set as the offset of the switch timer address (step S186). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the offset "6" of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S
187).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value "2", the switch-on flag is set (step S188). When the switch-on flag is set, "15" as the number of prize balls to be paid out is set in the ring buffer (step S189). In addition, 15 is added to the value stored in the total prize ball storage buffer (step S190).

If data exists in the ring buffer (step S191), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S192), and the value of the read pointer is updated (in the ring buffer). It is updated to point to the next area (step S193), the command transmission table regarding the number of prize balls is set (step S194), and the command setting process is called (step S195). The operation of the command set process will be described later in detail.

In step S194, the start address of the command transmission table (ROM) in which the payout control command relating to the number of prize balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of prize balls includes INT data (01
(H)), the first byte of the payout control command (F
0 (H)), and the data of the second byte of the payout control command are set. However, "80 (H)" is set as the second byte of data.

As described above, when the payout control command for instructing the number of prize balls is output from the game control means to the payout control board 37, the address setting of the command transmission table regarding the number of prize balls and the setting of the transmission buffer are performed. Is done. Then, by the command setting process, the payout control command is sent to the payout control board 37 based on the command transmission table regarding the number of prize balls and the setting contents of the transmission buffer. In step S191, it is possible to confirm whether or not there is data by the difference between the write pointer and the read pointer. You may confirm whether or not.

Then, the content of the total prize ball number storage buffer is 0.
If not, that is, if there is still a prize ball left, C
The PU 56 turns on the prize ball payout flag (step S
196, S197).

When the award ball payout flag is on (step S198), the CPU 56 monitors the number of award balls actually paid out from the ball payout device 97 and stores the total award ball storage buffer. The number of prize balls subtraction processing for subtracting the value is performed (step S199). When the prize-ball paying-out flag changes from on to off, the lamp control board 3
5, a lamp control command for instructing lighting of the prize ball lamp 51 is transmitted.

Upon receipt of the payout prohibition state designation command, the payout control means stops both the ball payout as a prize ball and the ball payout as a ball lend. When the payable state designation command is received, both the ball payout as a prize ball and the ball payout as a ball lend are made possible. However, from the game control means to the payout control means, a payout control command for stopping or restarting ball payout as a prize ball and a payout control command for stopping or restarting ball payout as a ball lending are different control commands. You may make it transmit as.

Further, in this embodiment, the processing of steps S169 to S195 is executed even in the payout prohibition state (steps S160 and S165). That is, the game control means can send a payout control command for instructing the number of prize balls even in the payout prohibited state. That is, the command for instructing the number of prize balls is
Even in the payout prohibition state, it is transmitted to the payout control means, and when the payout prohibition state is released, the prize ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of prize balls based on the winning in the payout prohibition state.

Further, in this embodiment, the processing of steps S169 to S195 is executed regardless of the payout status of the game medium. That is, the game control means can send a payout control command for instructing a new prize ball number, regardless of whether or not the specified number of prize balls has been paid out up to the previous time. Therefore, it is possible to reduce the processing load related to the payout of the game control means, and to quickly perform the prize ball payout processing.

Next, a method of sending a control command from the game control means to each electric component control means will be described. When the control command is to be output from the game control means to another electric component control board (sub board), the start address of the command transmission table is set. Figure 2
FIG. 8A is an explanatory diagram showing a configuration example of a command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the 1st byte.
The MODE data of the first byte of the control command is set in the command data 1 of the second byte. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set with data for designating the address of the table in which the EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, command data 2 is EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
In this embodiment, if the work area reference bit is 1, it indicates that the content of the transmission buffer is used as the EXT data. If the work area reference bit is 1, the other 7 bits can be configured to indicate that the other 7 bits are an offset for designating the address of the table in which the EXT data is stored.

FIG. 28B is an explanatory diagram showing a structural example of INT data. Bit 0 in INT data
Indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, CPU5
6 is, for example, prize ball processing (step S32 of the main processing)
In, the INT data is set to "01 (H)".
Bit 1 in the INT data indicates whether or not a display control command should be sent to the symbol control board 80.
If bit 1 is "1", it indicates that the display control command should be sent. Therefore, the CPU 56, for example, special symbol command control processing (step S2 of the main processing
In 8), "02 (H)" is set to the INT data.

Bits 2 and 3 of the INT data are bits indicating whether or not to send a lamp control command and a sound control command, respectively, and the CPU 56 outputs a special command at the timing to send these commands. In the symbol process processing or the like, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When sending those commands, the corresponding bit of the INT data is set to "1", and the command data 1 and the command data 2 are MOD.
E data and EXT data are set.

In this embodiment, a ring buffer and a transmission buffer are prepared for the payout control command, as shown in FIG. 28 (C). Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. Also, when sending the payout control command regarding the number of prize balls,
One data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 28C, the ring buffer can store data corresponding to 12 payout control commands. That is, there are 12 buffers. The number of buffers in the ring buffer may be any number corresponding to the number of winning openings for generating prize balls. This is because even if the simultaneous winnings occur, it is possible to store the payout control command data based on the respective winnings.

FIG. 29 is an explanatory diagram showing an example of the command form of the control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always "1", and the first bit (bit 7) of the EXT data is always "0". As described above, the control command, which is a command to the electric component control board, is composed of a plurality of data, and can be distinguished by the leading bit. Note that the command form shown in FIG. 29 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used. Further, although FIG. 29 illustrates the payout control command sent to the payout control board 37,
The control commands sent to the other electric component control boards have the same configuration.

FIG. 30 shows 8-bit control signals CD0 to CD forming a control command for each electric component control means.
7 is a timing diagram showing the relationship between 7 and the INT signal. As shown in FIG. 30, when the period indicated by A elapses after the MODE or EXT data is output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data. INT which is a signal
Set the signal to high level (on data). When the period indicated by B elapses, the INT signal is set to low level (off data). Furthermore, if there is data to be sent next, that is, after sending the MODE data, the data of the second byte is sent to the output port after a period indicated by C. Regarding the data of the second byte, the periods A and B are the same as the case of the first byte.
In this way, the capture signal is output for each of MODE and EXT data.

The period A is a period for the CPU 56 to prepare for sending a command, that is, a period required for setting a sending command in the buffer, and a period for stabilizing the data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal as a capture signal is output after a predetermined period (period of A: part of the off output period) has elapsed. Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the OFF output period) is a period in which the electric component control unit is set so that the data can be reliably fetched. In the period of B and C,
The data on the signal line does not change. That is, the data output is maintained until the B and C periods elapse.

In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal for the first byte to the start of the transmission of the data of the second byte, is longer than the reception processing time in the electric component control means that takes the longest time for the command reception processing. Is also set to be long.

Each electric component control means detects that the INT signal has risen, and starts fetching 1-byte data by, for example, interrupting.

Since the period of B and C is longer than the reception processing time in the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing to each electric component control means by the common module. However, any electric component control means can surely receive the control command from the game control means.

The CPU 56 is ready to send the next data when a predetermined period of time elapses after executing the INT signal output processing, but during the predetermined period (B and C periods), the IN
It is longer than the period (period A) from the transmission of data before the T signal output process to the start of output of the INT signal. As described above, the period A is the stabilization period in the command signal line, and the periods B and C are the periods for ensuring the time required for the receiving side to take in the data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can surely receive the command, and the transmission of one command is completed. There is also an effect that the period required for is shortened.

FIG. 31 is an explanatory diagram showing an example of the contents of the payout control command. In this embodiment, a plurality of types of payout control commands are used to execute the payout control. In the example shown in FIG. 31, MODE = FF
(H), EXT = 00 (H) command FF00 (H)
Is a payout control command (payable state designation command) for instructing that the payout is possible. MODE = FF
(H), EXT = 01 (H) command FF01 (H)
Is a payout control command (payout prohibition state designation command) for instructing that the payout should be stopped. Also, the command F0XX (H) of MODE = F0 (H)
Is a payout control command (payout number designation command) for designating the number of prize balls. “XX”, which is EXT, indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the prize ball payout and the ball lending are stopped, and FF00.
When the payout control command (H) is received, prize balls can be paid out and balls can be lent. Further, when the payout control command for designating the number of prize balls is received, the prize ball payout control according to the number designated by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the level of the INT signal changes, and “recognitionally being sent only once” means that in this example, the payout control signal is sent to each of the first byte and the second byte. Accordingly, the INT signal is output only once in a pulse shape (rectangular wave shape).

A control command for each electric component control board is
When outputting to the corresponding output port (output ports 1 to 4), one of the bits 0 to 3 of the output port 0 becomes "1" (high level) for a predetermined period. And the bit array in the output port 0 correspond to each other. Therefore, when the control command is sent to each electric component control board, the INT signal can be easily output based on the INT data.

FIG. 32 is a flow chart showing an example of the command set processing (steps S164, S168, S195). The command set process is a process including a command output process and an INT signal output process. In the command setting process, the CPU 56 first saves the address of the command transmission table (contents of the pointer as the transmission signal instruction means) to the stack or the like (step S3).
31). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore,
The address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sends the command data 1
Is read out and is set to the argument 2 (step S334).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S335).

FIG. 33 is a flow chart showing the command transmission processing routine. In the command transmission processing routine, after turning on the command transmission flag (step S350), the CPU 56 sets the data set in the argument 1, namely INT data, in the work area determined as the comparison value (step S351). ).
The command transmitting flag is a flag indicating whether or not the command transmitting process is being performed, and is stored in a predetermined area of the RAM 55. Next, the CPU 56 sets the number of transmissions = 4 in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of the output port for outputting the payout control signal. Also, ports 2-4
Is the address of the output port for outputting the display control signal, the lamp control signal, and the voice control signal.

Next, the CPU 56 shifts the comparison value right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S355). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S3
56). When the first shift processing is performed, the address of port 1 is set as the IO address, so the MODE data of the payout control command is set to port 1 at that time.
Is output to.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the processing number (step S358). When the port 1 is shown before the addition, the address of the port 2 is set to the IO address by the addition process for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0,
It returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not the lamp control command and the sound control command should be sent. In this way, when each shift process is performed, the IO address has the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process. It is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
A control command is sent to. That is, one common module can perform a process of sending a control command to each electric component control means.

Further, in this way, since the control command to which the control command should be output is determined only by the shift processing, it is determined to which electric component control means the control command should be output. Processing has been simplified.

Next, the CPU 56 reads the content of the argument 1 in which the INT data before the shift processing is started (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is a port for outputting the INT signal for each control signal, and bit 0 of port 0
4 to 4 are the payout control INT signal and the display control IN, respectively.
It is a port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and decrements by 1 until the value becomes 0 (steps S363, S36).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S36).
5) output the data to port 0 (step S3)
66). Therefore, the INT signal becomes low level. Further, a predetermined value is set in the wait counter (step S3
62), and subtracts 1 by 1 until the value becomes 0 (steps S368 and S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time that is generated in steps S367 to S369 and the subsequent processing time (if MODE data is output at this time, the time required for control until the EXT data is output). ) Is the period added. By setting the period of C in this way,
Even when the commands are continuously sent, a predetermined period of time elapses after the output of one command is completed and before the sending of the next command is started, and the electric component control means for receiving the command. On the side of, the command delimiters can be easily identified and each command is reliably received.

Therefore, the value set in the wait counter in step S367 is such that the period of C is a period sufficient for surely performing the command reception process by all the electric component control means which are the control command reception targets. Value. The value set in the wait counter is
The value is longer than the time (corresponding to the period A) required for the processes of steps S357 to S359. In addition, A
If it is desired to lengthen the period A, a wait process for creating the period A (for example, a process of setting a predetermined value in the wait counter and performing subtraction until the value of the wait counter becomes 0) is performed.

When the value of the wait counter becomes 0 (Y in step S369), the CPU 56 turns off the command transmission flag (step S370).

As described above, the 1st byte MODE data of the control command is transmitted. Therefore, CPU5
In step S336 shown in FIG. 32, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S338). If not 0, the contents of the transmission buffer are loaded into the argument 2 (step S339). If the extended data is used when the value of the work area reference bit is "1", the start address of the command extended data address table is set in the pointer and the command data is set in the pointer. The address is calculated by adding the values of bit 6 to bit 0 of 2. Then, the data of the area pointed to by the address is loaded into the argument 2.

Since the data capable of specifying the number of prize balls is set in the transmission buffer, the data is set in the argument 2. If the extended data is used when the value of the work area reference bit is “1”, the command extended data address table contains
EXT data that can be sent to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table according to the content of the command data 2 is loaded into the argument 2.

Next, the CPU 56 calls the command transmission processing routine (step S340). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent out.

As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte structure is transmitted to the corresponding electric component control means. The electric component control means starts the control command fetching process when the rising edge of the INT signal is detected. However, the wait period (step S367 to step S369
Since a new signal is not output until the period specified by the process of (part of the period of C) elapses, for any electric component control means, the game control is performed before the capture process is completed. No new signal from the means is output to the signal line. That is, a reliable command reception process is performed in each electric component control means. It should be noted that each electric component control means may start the control command acquisition process at the fall of the INT signal. Also,
The polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, in the prize ball processing, when the prize ball payout condition is satisfied, the data capable of specifying the number of prize balls is stored in the ring buffer capable of storing a plurality of data at the same time. When the payout control command designating the is sent, the data in the area of the ring buffer pointed by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of prize ball payout conditions are satisfied at the same time, the data capable of specifying the number of prize balls based on the satisfaction of those conditions is stored in the ring buffer, so that the command output process based on the satisfaction of each condition does not pose a problem. To be executed.

Further, in this embodiment, both the payout prohibition state designating command or the payout possible state designating command and the command indicating the number of prize balls can be sent in one award ball process. That is, 1 is activated every 2 ms
Multiple commands can be sent within one control period. Further, in this embodiment, since a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, payout control command) to each control means, for example, When data capable of specifying the control command is set in the ring buffer of the control command, the lamp control command, and the sound control command, a plurality of display control commands, lamp control commands, and sound control commands can be performed by one command control process. Can also be configured to deliver. That is, a plurality of control commands can be sent at the same time (meaning in the activation cycle of the game control process, that is, the 2 ms timer interrupt process). Since the transmission timings of those control commands occur at the same time in the progress of the game production, it is convenient to have such a configuration. However, since the payout control command is generated regardless of the progress of the game effect, in general, the display control command,
It is not sent at the same time as the lamp control command and the sound control command.

FIG. 34 is a flow chart showing an example of the award ball number subtracting process. In the process of subtracting the number of prize balls, C
The PU 56 first loads the value stored in the total prize ball number storage buffer (step S381). Then, it is confirmed whether the stored value is 0 (step S382). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the loaded value is compared with the ON determination value (in this case, "2") (step S384). If they match (step S38)
5) Assuming that the prize ball count switch 301A is turned on, that is, one game ball is certainly one ball payout device 9
The value stored in the total prize ball number storage buffer is decremented by 1 assuming that the payout is made from 7 (step S386).

Also, the value of the prize ball information counter is incremented by 1 (step S387). When the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information counter is incremented by 1 (step S389),
The value of the prize ball information counter is decremented by 10 (step S39).
0). The value of the prize ball information counter is the information output process (step S3) in the game control process shown in FIG.
0), and if the value is 1 or more, one pulse is output as the prize ball signal (bit 7 of the output port 5: see FIG. 14). Therefore, in this embodiment, each time 10 game balls are paid out as prize balls, one prize ball signal is output to the outside of the gaming machine.

Then, when the value stored in the total prize ball number storage buffer becomes 0 (step S391), the prize ball payout flag is cleared (step S392) to notify that there is no remaining prize ball number. After the command data indicating that the prize ball lamp 51 is turned off is set in the command transmission table for the lamp control command (step S393), the lamp control command sending process is executed (step S394).

35 to 37 are flowcharts showing a processing example of the non-maskable interrupt processing (power supply stop processing) executed in response to the power-off signal from the power supply board 910. The non-maskable interrupt process is an interrupt process that cannot be prohibited. When a non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 uses the stack pointer as the address of the program being executed at the time of the non-maskable interrupt (specifically, the next address after completion of execution). It is saved in the stack area pointed to by and the value of the stack pointer is increased. That is, the value of the stack pointer is updated to point to the next address in the stack area.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) to a predetermined backup RAM area (specifically, stack area) (step S451). Also, the interrupt flag is copied to the parity flag (step S45).
2) Save the contents to the stack area (step S
453). Also, the BC register, the DE register, the HL register, and the IX register are saved in the stack area (steps S454 to S457). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag.

Next, the CPU 56 causes the clear data (0
0) is set in an appropriate register (step S45
9), the number of processes (“7” in this example) is set in another register (step S460). Further, the address of the output port 0 is set in the IO pointer (step S46).
1). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S46).
2), the value of the IO pointer is incremented by 1 (step S46
3) The value of the number of processes is subtracted by 1 (step S464).
In the processes of steps S462 to S464, the value of the number of processes is 0.
Is repeated (step S465). As a result, clear data is set in all output ports 0 to 6 (see FIGS. 14 and 15). 14 and 15
As shown in, in this example, "1" is in the ON state,
Since the clear data "00" is set to each output port, all the output ports are turned off.

As described above, since each output port is turned off, it is possible to surely prevent the occurrence of a situation inconsistent with the saved game state. That is, in a gaming machine that has a variable winning ball device, such as a pachinko gaming machine,
Due to the mounting, the position of the variable winning opening in the variable winning ball device and the installation position of the winning opening switch for detecting the winning must be separated to some extent. If you do not immediately turn off the output port, especially the output port that outputs the signal to open the variable winning ball device, when the power supply is stopped, even if you win the variable winning port, even if the power supply is stopped A situation may occur in which execution of the process is started and the winning opening switch is not detected. In that case, the fact that the variable winning a prize has been won is not saved. That is, the actually occurring game state (there is a prize) and the saved game state do not match. However, in this embodiment, since the output port is cleared and the variable winning ball device is closed, it is possible to reliably prevent the occurrence of a situation inconsistent with the saved game state.

Further, since the output port can be cleared during the power supply stoppage process executed before the electric components cannot be driven, the electric components cannot be driven. Before that, each electric component controlled by the game control means can be put into an appropriate operation stopped state. For example, after closing the open special winning opening and closing the open variable winning ball device 15, the operation of the electric components is disabled after the operation of the electric components is stopped. be able to. Therefore, it becomes possible to wait for the restoration of the power supply in an appropriate stop state.

Furthermore, since the operation of each electric component is stopped during the power supply stop process, electric power is not consumed to drive each electric component, and the signal output from the output port is not performed. Since the used electric current is cut off, it is possible to suppress the power consumption though it is a small amount.

Furthermore, in this embodiment, the detection signal of the prize ball count switch 301A is checked for a predetermined period (hereinafter referred to as the payout confirmation period). When the prize ball count switch 301A is turned on, the prize ball count value is set to 1
increase.

In this embodiment, a payout confirmation period measuring counter is used to measure the payout confirmation period. The value of the payout confirmation period measurement counter is the initial value m.
From the loop of the switch detection processing described below (S4
It is assumed that the payout confirmation period ends when the loop (starting from 67 and returning to S467) is decremented by 1 each time the value becomes 0. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore, a time m times the time required for one round of the loop is substantially equivalent to the payout confirmation period.

To measure the payout confirmation period, the CPU 5
A built-in timer of 6 may be used. That is, a predetermined value (corresponding to the payout confirmation period) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the payout confirmation period has ended. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program.

The payout confirmation period is from the time when the game ball drops from the ball payout device 97 (for example, when the game ball is sent to the ball passages 293a and 293b below the sprocket 292 shown in FIG. 5). It is set to be longer than the time required to reach 301A. When the distance from the ball payout device 97 to the prize ball count switch 301A is L, the fall time t during that time is t = √ (2L / g) (g:
Because of the acceleration due to gravity, the payout confirmation period is set longer than that. The specific value of the payout confirmation period varies depending on the value of the distance L and how much margin is provided from the fall time t, but is, for example, about 100 [ms] to 150 [ms].

Even when the game control means detects the payout of the loan ball, the payout confirmation period is set in the same manner. That is, from the time when the game ball falls from the ball payout device 97 (for example, when the game ball is delivered to the ball passages 293a and 293b below the sprocket 292 shown in FIG. 5) to the ball lending count switch 301B or more. Is set to. Therefore, if the distance from the ball payout device 97 to the ball lending count switch 301B is L, the fall time t during that time is still t = √ (2L / g) (g: gravity acceleration). It is set higher than that. Also in this case, the specific value of the payout confirmation period varies depending on the value of the distance L and how much margin is provided from the fall time t, but for example, 100 [ms] to 150 [m]
s]. In addition, when the distance from the ball payout device 97 to the prize ball count switch 301A and the distance to the loan ball count switch 301B are different, the payout confirmation is performed based on the distance of the switch away from the ball payout device 97. The period should be set.

At least during the payout confirmation period in which the switch detection processing is executed, the prize ball count switch 301A
(Or the prize ball count switch 301A and the ball lending count switch 301B) must be in a state where the game ball can be detected. Therefore, in this embodiment, as shown in FIG.
As shown in FIG. 5, a capacitor 923 as an auxiliary drive power source having a relatively large capacity is connected to the input side of the converter IC 920 on the power source board 910. Therefore, even when the power supply to the gaming machine is stopped, +1 for a certain period
The 2V power supply voltage is maintained within a switchable range, and the prize ball count switch 301A (or prize ball count switch 301A and ball lend count switch 301B)
Becomes operational. The capacity of the capacitor 923 is determined so that the period is equal to or longer than the payout confirmation period.

Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 920, they can be operated for a relatively long period even when the power supply is stopped.

As described above, in this example, the initial value m is set in the payout confirmation period measuring counter (step S4).
66). Also, in step S467, the 2 ms measurement counter is set to the initial value n corresponding to the time of 2 ms. Then, the value of the 2 ms measurement counter is decremented by 1 until the value of the 2 ms measurement counter becomes 0 (step S468) (step S469).

When the value of the 2 ms measurement counter becomes 0,
The input of the detection signal of the prize ball count switch 301A is checked. That is, a process similar to the switch process of step S21 is performed. Specifically, the data input to the input port 1 is input (step S470). Then, "1" is set as the number of processes (step S47).
1) Set the address of the switch timer for the prize ball count switch 301A in the pointer (step S
472). Then, the switch check processing subroutine is called (step S473).

When the value of the switch timer is 2 (step S479), the prize ball count value (in the backup RAM area) is incremented by 1 (step S480).
Next, the value of the payout confirmation period measuring counter is decremented by 1 (step S481), and if the value is not 0, the process returns to step S467 (step S482).

Through the above processing, if the prize ball count switch 301A is turned on within the payout confirmation period, the prize ball count value is incremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the prize ball count value is always incremented by 1 for the prize balls that have been paid out. The power supply to the gaming machine was stopped,
After that, when the game state is restored, in step S84 in the game state restoration process (see FIG. 18), the CPU 56 subtracts the prize ball count value from the value stored in the total prize ball number storage buffer, and the prize ball count value is the prize ball information counter. Is added to the count value of. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. That is, the gaming balls paid out are not actually undetected.

In this embodiment, the prize ball count value addition process is performed in the power supply stop process, but when the prize ball count switch 301A is turned on, the stored value of the total prize ball number storage buffer is set to -1. At the same time, the count value of the prize ball information counter may be incremented by one. In such a case, the process of step S84 in the game state recovery process is unnecessary.

In the above input processing, timer processing using a detection period counter is performed. That is, 2 ms
The detection signal of the prize ball count switch 301A is checked every time, and when the ON signal is detected twice consecutively, it is considered that the prize ball count switch 301A is surely turned ON. That is, a predetermined game medium detection determination period (a period for determining whether or not a game medium (here, a prize ball paid out in the power supply stop process) is detected. In this embodiment, a period of 2 ms or more ) Is continuously detected twice before and after, it is considered that the payout of one prize ball is completed. As described above, in this embodiment, the game medium detection determination period is the normal game medium detection determination period (a period for determining the presence or absence of a game medium in the normal game state, which is not the process in the power supply stop process). In this embodiment, the period is 2 ms or more, which is determined by the switch-on determination value (see FIG. 33) described later, and is the same period as the period used in the determination in step S188 in FIG. Therefore, it is possible to determine whether or not the prize ball count switch 301A is turned on under the same condition as the normal control.

Further, since it is determined whether or not the prize ball count switch 301A is turned on under the same conditions and the same processing as the normal control, the switch detection input processing routine in the power supply stop processing, The input processing routine for switch detection in normal control (switch check processing subroutine shown in FIG. 22) can be commonly used. That is, the switch detection input processing routine in the normal control can be used in the switch detection in the power supply stop processing. Therefore, the program amount of the power supply stop processing is reduced.

In this embodiment, the switch detection processing is performed only for the prize ball count switch 301A, but the same applies to the switch for the starting winning opening and the V winning switch 22 and the counting switch related to the special winning opening. Switch detection processing may be performed. Further, similar switch detection processing may be performed for other prizes. When such an on-check is also performed, even if a power failure occurs immediately after the game ball has won the winning opening, the winning is surely detected and reflected in the saved game state.

When the payout confirmation period has elapsed (step S4)
86), that is, when the value of the payout confirmation period measuring counter becomes 0, the backup designated value (in this example, “5
5H ”) is stored in the backup flag (step S487). Backup flag is backup RAM
Is formed in the area. Next, parity data is created (steps S488 to S497). That is, first, clear data (00) is set in the checksum data area (step S488), and the checksum calculation start address is set in the pointer (step S48).
9). Also, the number of checksum calculations is set (step S490).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S491). The calculation result is stored in the checksum data area (step S49).
2), increment the pointer value by 1 (step S493),
The value of the checksum calculation count is subtracted by 1 (step S4
94). The processes of steps S491 to S494 are repeated until the value of the checksum calculation count becomes 0 (step S495).

When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S496). Then, the inverted data is stored in the checksum data area (step S497). This data becomes the parity data that is checked when the power is turned on. Next, after the contents of the stack pointer are saved in the backup RAM area (step S498), the access prohibition value is set in the RAM access register (step S499). After that, the built-in RAM 55 cannot be accessed.

Then, when the access prohibition value is set in the RAM access register, the CPU 56 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

As described above, the game control means performs the register save processing, the input processing of the detection signal from the prize ball count switch 301A as the payout game medium detecting means, the stack pointer save processing, and the execution in the power supply stop processing. Each process is executed in the order of the process of saving the confirmation information (the backup flag and the checksum data in this example) and the process of prohibiting the RAM access.

That is, in the power supply stop process, first, the registers except the stack pointer are saved, then the detection signal of the prize ball count switch 301A is input, and the backup flag is set. After setting the checksum data (storing the execution confirmation information), stack pointer save processing is executed, and finally RAM access is prohibited. Since the register saving process is executed first, the register contents are saved more reliably.

In this embodiment, the power supply stoppage process is executed according to the NMI, but the power-off signal is changed to C
You may connect to the maskable terminal of PU56 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In the above example, the output port clearing process is performed before the switch detection process is executed (step S466).
Before). During the execution of the power supply stop process, the CPU 56 and the switches are connected to the capacitors 923 and 92.
It will be driven by the charging power of 4 or the like. Since the output port clearing process is performed before the switch detection process is executed, even if the special winning opening, the variable winning device, etc. are configured to be driven by electric parts such as solenoids, they must be driven. Not a capacitor (especially capacitor 92
The charging power and the like in 4) can be effectively used for the processing at the time of power supply stop.

In the above example, when the V winning switch 22 is detected after the power is cut off, the solenoid 21 (the member for guiding the special winning opening to the V winning switch is operated). It is preferable to clear the output port of the device (1) after the execution of the switch detection processing. By doing so, when a power outage occurs in a state where the V winning that is the condition of continuation right is not generated, the game ball that has entered the special winning opening immediately before the power outage is placed in the V winning switch 22.
Can be guided to the side. Therefore, it is possible to prevent the unjustified extinction of the continuation right. In this case, the period corresponding to the above-mentioned payout confirmation period is a predetermined period of time or more until the gaming ball that has won the special winning opening reaches the V winning switch 22. When a latch type solenoid is used, it is not necessary to clear the output port.

Even if the special winning opening is closed by clearing the output port, it is possible that there is a game ball in the special winning opening. Therefore, in the switch detection process executed in response to the power-off signal, the count switch 23 It is desirable to detect The above-mentioned exceptional processing is the same not only in the type 1 pachinko gaming machine but also in the type 2 pachinko gaming machine and the type 3 pachinko gaming machine.

FIG. 38 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power off signal: power supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of the monitoring voltage (voltage input to the power supply monitoring IC 902) of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to + 22V, the power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (becomes a low level).

The power-off signal is introduced to the electric component control board (in this embodiment, the main board 31 and the payout control board 37), and the CPU 56 and the payout control CPU 371 receive N signals.
It is input to the MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the system reset circuit mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 And the payout control CPU 371 enters the system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stoppage process before being brought into the system reset state.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, at least on the main board 31 and the payout control board 37, the processing at the time of power supply stop is executed, and
56 and the payout control CPU 371 are in the system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Generates a voltage drop signal (power cut detection signal). As shown in FIG. 38, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stoppage process.

Here, the power supply monitoring circuit monitors the voltage branched from the highest power supply VSL of the DC voltage used in the game machine, but the timing of generating the power supply cutoff signal is the IC drive voltage. The voltage to be monitored does not have to be the highest voltage of the power supply VSL, as long as the operation time for the electric component control means operating in (3) secures the operation time for performing the predetermined power supply stop processing. That is, if at least a voltage higher than the drive voltage of the IC or the solenoid is monitored, the power-off signal is generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. be able to. In this example, the voltage branched from the power supply VSL is used as the drive voltage of the solenoid or the like, but unlike the line to which the monitored voltage is supplied, a large-capacity capacitor 924 is provided in the line that supplies the drive voltage to the solenoid or the like. Since they are connected, the power-off signal can be generated at a timing when a predetermined period in which the supply of the drive voltage to the solenoid etc. can be continued is secured.

When a voltage other than the highest power source VSL is set as the monitored voltage, it is preferable that the monitored voltage is a voltage that can also prevent erroneous switch-on detection when the power supply is stopped, as described above. That is, the voltage supplied to various switches of the gaming machine (switch voltage: for example, prize ball count switch 301A, ball lending count switch 301
Since B) is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

FIG. 39 is a timing chart showing an example of how the detection signal input processing (switch detection processing) from the payout detection means is executed. In this embodiment, the power-off signal is input to the main board 31 and the payout control board 37, and the CPU 56 of the main board 31 and the payout control CPU 3 are provided.
71 to the NMI terminal. CPU5 of main board 31
The non-maskable interrupt process 6 executes the above-described power supply stop process.

As shown in FIG. 39, when the prize-ball payout is executed when the power-off signal is turned on (changes from the high level to the low level in this example), the detection signal input process from the payout detection means ( The prize ball count switch 301A is turned on within the payout confirmation period in which the switch detection process) is executed. Therefore, the ball payout executed when the power-off signal is turned on can be reflected in the prize ball count value when the power supply stop time process is executed.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the signal from the reset IC 651 input to the main board 31 becomes low level, and the CPU 56 enters the system reset state. Become. The CPU 56 completes the power supply stoppage process before the system is reset.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, in the main board 31, the power supply stop processing is executed, and the CPU 56 is in the system reset state.

The payout control CPU 371 of the payout control board 37 also enters the system reset state after similarly performing the power supply stop time process.

Next, the operation of the payout control means will be described. FIG. 40 is a block diagram showing a configuration example around the payout control CPU 371. As shown in FIG. 40, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is supplied to the payout control CPU via the buffer circuit 980.
It is connected to an unmaskable interrupt terminal (XNMI terminal) 371. Therefore, the payout control CPU 371 can confirm the occurrence of power failure by the non-maskable interrupt process.

In this embodiment, the reset IC 651B in the system reset circuit 65B sets the output to the low level for a predetermined time determined by the capacity of the external capacitor when the power is turned on, and sets the output to the high level after the predetermined time elapses. . Further, the reset IC 651B monitors the power supply voltage of VSL and sets the output to the low level when the voltage value becomes a predetermined value (for example, + 9V) or less. Therefore, when the power supply to the gaming machine is stopped, the signal from the reset IC 651B becomes low level, so that the payout control CPU 3
71 is system reset.

The predetermined value for the reset IC 651B to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the payout control CPU 371 can operate for a while. Further, the reset IC 651B is a CP for payout control.
Since it is configured to monitor a voltage higher than the voltage required by the U371 (+ 5V in this example), the monitoring range can be expanded with respect to the voltage required by the payout control CPU 371. Therefore, more precise monitoring can be performed.

While the power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, so that a power failure or the like occurs. Contents are saved even when power supply to the gaming machine is stopped. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65B, so that the payout control CPU 371 returns to the normal operating state. At that time, since necessary data is backed up, at the time of recovery from a power failure or the like, the payout control state at the time of power failure can be restored.

In the structure shown in FIG. 40, system reset circuit 65B outputs a low level for a period determined by the capacitance of the capacitor when the power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
Similarly to the case of 1, the circuit configuration in which the reset release timing occurs a plurality of times may be used. Further, in the electric component control boards other than the payout control board 37, the circuit for generating the reset signal is configured as shown in FIG.

In addition, a return signal from the power supply board 910,
What is the reset signal from the system reset circuit 65B?
It is input to the ND circuit 385, and the output of the AND circuit 385 is input to the reset terminal of the payout control CPU 371.
When the return signal is output when the payout control CPU 371 performs the power supply stoppage process and is in the loop state (standby state), the payout control CPU 371 is reset. As a result, the payout control CPU 371 can get out of the loop state.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. Then, when the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt will occur in response to the input of the INT signal. The INT signal is a signal that means that a payout control command has been sent from the game control means to the payout control means. The payout control CPU 371 starts the payout control command reception process by an interrupt generated in response to the input of the INT signal.

FIG. 41 is an explanatory diagram showing output port allocation in this embodiment. As shown in FIG. 41, the output port C (address 00H) is connected to the payout motor 2
89 is an output port for driving signals and the like output to 89. Further, the output port D (address 01H) is an output port of a display control signal output to the error display LED 374 which is a 7-segment LED. And output port E
(Address 02H) is the drive signal output to the distribution solenoid 310 and the EX to the card unit 50.
It is an output port for outputting the S signal and the PRDY signal.

FIG. 42 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 42, the input port A (address 06H) is an input port for taking in the 8-bit payout control signal of the payout control command sent from the main board 31. Further, the detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Detection signal is input. In this way, the detection signal of the clear switch 921, that is, the operation input of the operating means is a bit at the same input port as the input port (the input unit having the 8-bit configuration) to which the detection signal of the switch for detecting the game ball is input. (Input port circuit).

FIG. 43 shows the payout control means (payout control CP.
7 is a flowchart showing a main process of U371 and peripheral circuits such as ROM and RAM. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and the top address of the stack area is set to the stack pointer (step S703). Further, the payout control CPU 371
Initializes the internal device register (step S
704), initialization of CTC and PIO (step S7
After performing 05), the RAM is set to the accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the built-in device register setting processing of step S704 and the processing of step S705, register setting for setting the channel to be used in timer mode, register setting for permitting interrupt generation, and register for setting interrupt vector Settings are made. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set in the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, payout control process is executed.

Also, another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means, and that channel is used. Is used in counter mode. Therefore, in the built-in device register setting processing of step S704 and the processing of step S705, in order to set the register setting for setting the channel to be used in the counter mode, the register setting for permitting interrupt generation, and the interrupt vector. Register setting is performed.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set the interrupt processing start address according to the interrupt vector sent by the CTC.

The interruption based on the count-up of the channel 2 (CH2) of the CTC is an interruption which occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as the specific register
An initial value "1" is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rising or falling of the signal input to the CLK / TRG2 terminal. You can make a choice. In this embodiment, the timer counter register CLK / TRG is output at the rising edge of the signal input to the CLK / TRG2 terminal.
The count value of 2 is set to -1.

[0289] The CTC channel 3 (CH3) count-up interrupt is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes "0". 2m
s Used as a timer interrupt. Specifically, CPU3
A clock obtained by dividing the operation clock of 71 is given to the CTC, the value of the register is subtracted by the input of the clock, and when the value of the register becomes 0, a timer interrupt is generated.
For example, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the CH3 register.

An interrupt based on the count-up of CTC CH2 has a higher priority than an interrupt based on the count-up of CH3. Therefore, when count-ups occur at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process is prioritized.

Next, the payout control CPU 371 confirms the state of the output signal of the clear switch 921 input via the input port B (see FIG. 42) only once (step S707). When ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S714). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 372, the on state of the clear switch signal is high level. Also, for example,
The game store staff can easily execute the initialization process by starting power supply to the gaming machine (for example, turning on the power switch 914) while turning on the clear switch 921. That is, the RAM clear or the like can be performed.

Note that, like the CPU 56 of the main substrate 31, the payout control CPU 371 also determines that the ON state is at least 2 when the ON detection of the switch detection signal is performed.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms) does not continue, it is not considered to be switch-on, but when the clear switch 921 is detected to be on, ON / OFF is determined by the ON determination. That is, it is determined whether or not the clear switch 921 as the operating means is in a predetermined operating state.
The initialization request detection determination period for U371 to determine is
The period is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detecting means has detected the game medium.

If the clear switch 921 is not turned on, the payout control CPU 371 confirms whether or not backup data exists in the payout control backup RAM area (step S708). For example, similar to the processing of the CPU 56 of the main board 31, whether or not backup data exists is determined by whether or not the backup flag that is set when the power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

When it is confirmed that there is a backup, the payout control CPU 371 performs a data check of the backup RAM area (parity check in this example). When the power is restored after the power supply is stopped due to an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, it is not possible to return the internal state to the state at the time of stopping the power supply, so the initialization process executed when the power is turned on is executed instead of when the power is restored from an insufficient power failure.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state at the time of stopping the power supply (step S710). Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area.

The payout control CPU 371 confirms whether or not the data in the backup RAM area is stored using the backup flag and the check data such as the checksum. That is, when the power supply is restored,
All of the multiple restoration conditions (in this example, the backup flag was saved normally and the checksum was normal) that determine whether to restore the control state before the power supply was stopped When the condition is satisfied, the recovery process for recovering the control state is executed based on the stored contents stored in the variable data storage means, and the variable data storage is performed when at least one condition among the plurality of recovery conditions is not satisfied. It is possible to execute an initialization process for initializing the stored contents of the means. By using multiple recovery conditions,
It is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. When the operation signal is output from the operation means, the initialization process is executed regardless of the plurality of restoration conditions (step S70).
7). In this embodiment, the backup RAM is used by using both the backup flag and the check data.
Although it is confirmed whether or not the data of the area is stored, only one of them may be used. That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

In the initialization processing, the payout control CPU 371
First performs a RAM clear process (step S71).
1). Then, the CTC provided in the payout control CPU 371 so that a timer interrupt is periodically applied every 2 ms.
The register is set (step S712). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Further, in this embodiment, the payout control CPU 371 sets the payout prohibition state as an initial state (step S713). When setting the payout prohibition state, the payout control CP is set.
The U 371 controls, for example, driving of the payout motor 289 and sets an internal flag (payment stopped flag) indicating that the payout is prohibited. That is,
In step S713, data indicating that the payout is prohibited (the set payout suspension flag)
Is stored in a predetermined storage area. Since the interrupt is prohibited in step S701 of the initialization process, the interrupt is permitted before the initialization process is completed (step S714). In addition, the payout suspension flag is reset on condition that the payable state designation command is received from the game control means (see step S753e in FIG. 51).

In this embodiment, the payout control CPU 3
71 built-in CTCs are set to repeatedly generate timer interrupts. In this embodiment, the repetition period is 2
Set to ms. And when a timer interrupt occurs,
As shown in FIG. 44, a timer interrupt flag indicating that there is a timer interrupt is set (step S792).
Then, in the main process, when it is detected that the timer interrupt flag is set (step S715), the timer interrupt flag is reset (step S715).
751), payout control process (steps S751 to S76)
0) is executed.

In the timer interruption, as shown in FIG. 44, the interruption permission state is first set (step S79).
1). Therefore, during the timer interrupt process, the interrupt enable state is set, and the payout control command reception process based on the input of the INT signal can be preferentially executed.

In the payout control process, the payout control CPU
371: First, the prize ball count switch 301A and the ball lending count switch 3 input to the input port 372b.
It is determined whether a switch such as 01B is turned on (switch process: step S752).

Next, the payout control CPU 371 sets the payout prohibition state when the payout prohibition state designation command is received from the main board 31, and releases the payout prohibition state when the payout possible state designation command is received. (Payout prohibited state setting process: step S753). Further, it analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S754). Further, prepaid card unit control processing is performed (step S755).

Next, the payout control CPU 371 controls the payout of the lent balls in response to the ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the prize ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the 72c and the relay board 72 to perform payout motor control processing for rotating the payout motor 289 for a predetermined number of rotations (step S758). .

In this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control process, eight types of excitation pattern data are repeatedly output to the payout motor 289. Further, in this embodiment, each excitation pattern data is output by 4 ms.

Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

The output port C shown in FIG. 41 has a payout motor control process (step S75) in the payout control process.
Accessed in 8). Further, the output port D is accessed by the error processing in the payout control processing (step S759). Then, the output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

[0307] FIG. 45 is a flow chart showing an example of the payout state recovery process of step S710. In the payout state recovery process, the payout control CPU 371 first sets the payout prohibition state as a state related to payout (step S721). When the payout prohibition state is set, the payout control CPU 371 performs, for example, control for stopping the driving of the payout motor 289 and an internal flag indicating that the payout prohibition state is set (payout stop flag).
Set. That is, in step S721, a process of storing data indicating that the payout is prohibited (a set payout suspension flag) in a predetermined storage area is executed.

Then, the interrupt-enabled state is set (step S
722). Since the game control means transmits a recovery command in the power supply stop process and the payout control means receives the payout control command by the interrupt process, the game control means is set to the interrupt permitted state. Then, it waits for the recovery command to be received (step S723). When the recovery command is received by the interrupt process, it is stored in the received command buffer. Further, if the recovery command is not received even after the lapse of a predetermined time, the process may proceed to step S711 (initialization process). When the recovery command is received, the payout control CPU 371 performs a stack pointer recovery process (step S731). The value of the stack pointer is saved in a predetermined RAM area (backup RAM area whose power is backed up) in a power supply stoppage process described later. Therefore, step S7
At 31, the value in the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the read destination in the stack area: more specifically, a plurality of areas), the register value and the program counter (PC) value when the power supply is stopped are saved. There is.

When the payable state designation command is received as the recovery command, the payout suspended flag is reset.

Next, the prize ball count value stored in the backup RAM is reflected in the total number memory (step S733). The prize ball count value corresponds to the number of prize ball payout balls detected in the power supply stoppage process described later. In step S733, payout control CPU 371
Performs a process of subtracting the prize ball count value from the stored value in the total number memory. Then, the prize ball count value is cleared.
In addition, the lent ball count value stored in the backup RAM is reflected in the lent ball number storage (step S73).
4). The ball lending count value corresponds to the number of ball lending and paying balls detected in the power supply stoppage process described later. In step S734, the payout control CPU 371 performs a process of subtracting the lent ball count value from the stored value of the lent ball number storage. Then, the rental ball count value is cleared.

Thereafter, a timer interrupt setting process for setting the timer interrupt process so that a timer interrupt is taken every 2 ms is executed (step S735). For example, one of the control registers (for example, CH3) provided for each of a plurality of timers (for example, four) has a timer interrupt set value (A7 (H): Interrupt enable and reset settings), and then
Time constant data (count value, 2E (H) in this example) corresponding to 2 ms is set in the control register. Further, the payout control CPU 371 clears the backup flag (step S736), that is, resets the flag indicating that a predetermined storage protection process has been executed at the previous power supply stop.

Further, the saved values of various registers are read from the stack area, and various registers (IX register, H
The L register, the DE register, and the BC register) are set (step S737). That is, register restoration processing is performed. The value of the stack pointer is decremented each time each register is restored. That is, the value of the stack pointer is updated to point to the address immediately before the stack area. Also, the parity flag is restored from the stack area, and the interrupt flag is restored according to the contents (step S738). Interrupt flag is CP for payout control
It is an internal flag of U371 and indicates whether it is in the interrupt permission state or the prohibition state.

If the parity flag is not on, the interrupt enable state is set (steps S739, S).
740). Finally, the AF register (register for accumulator and flag) is restored from the stack area (step S741).

Then, the RET instruction is executed, but the return destination here is not the portion that called the payout state recovery processing. This is because the stack pointer restoration process is performed in step S731, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred at the time of the previous power supply stop in the program. Therefore, the next RET instruction in step S740 returns to the address where the NMI occurred when the power supply was stopped. That is, the payout control is restarted based on the address saved in the stack area.

FIG. 46 is an explanatory diagram showing a usage example of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number memory (for example, 2 bytes) and a rental ball number memory are formed.
The total number storage stores the total number of prize ball payout numbers instructed from the main board 31 side. The loaned ball number storage is for storing the number of unpaid lent balls. In addition,
The backup RAM area is not limited to the area for storing the above-mentioned information regarding the number of game balls, and various kinds of flags such as a flag indicating an error state such as a payout stop flag, an award ball path error flag, and a backup flag, which will be described later, for example. An area for storing flags, an area for storing various buffers such as a reception command buffer, and the like are also formed. Further, the RAM area in which the data used in the payout control process is stored may be backed up by power supply.

Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in the prize ball control process (step S757), for example, the contents are stored in the total number memory. To increase. In addition, in the ball lending control process (step S756), the content is increased to the lending ball number storage by one unit (for example, 25) each time the ball lending request signal is received from the card unit 50. Further, the payout control CPU 3
71 is the prize ball count switch 3 in the prize ball control processing.
When 01A detects the payout of one prize ball, the value of the total number of balls stored is decremented by 1. When the ball lending count switch 301B detects the payout of one ball, the value of the stored number of lent balls is decremented by 1.

Therefore, the number of unpaid prize balls and the number of lent balls are backup RAs capable of holding the contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply interruption such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the stored contents of the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is made based on the number of unpaid prize balls and the number of lent balls when the power supply is stopped, and is given to the player. The disadvantage can be reduced.

FIG. 47 is an explanatory diagram showing a configuration example of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type reception buffer that can store six 2-byte payout control commands is used. Therefore, the reception buffer is composed of 12-byte areas of the reception command buffers 1 to 12. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter takes a value of 0-11.

FIG. 48 is a flow chart showing the payout control command receiving process by the interrupt process. The payout control INT signal from the main board 31 is sent to the payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted and the payout control command reception process shown in FIG. 48 is started. In addition, CP for payout control
The U371 is a CPU having a structure in which, when an interrupt occurs, no further maskable interrupt occurs unless the interrupt is permitted by software.

Although the command receiving process of the payout control means will be described here, the same command receiving process is executed by the display control means, the lamp control means and the sound control means. In this embodiment, CLK /
Although the initial setting was made such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the TRG2 terminal rises, that is, the initial setting is made such that an interrupt occurs at the rising edge of the INT signal. CLK / TRG
When the input of 2 terminals falls, timer counter register C
Initialization may be performed such that the value of LK / TRG2 is decremented by one. In other words, the initialization may be performed so that an interrupt occurs at the falling edge of the INT signal.

That is, if the interrupt is configured to occur at the level change timing (edge) of the pulse (rectangular wave) INT signal as the capture signal, the edge may be a rising edge or a falling edge. It may be. In any case, the interrupt is configured to occur at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the acquisition signal. By doing so, it becomes possible to receive the command promptly at the stage when the command acquisition is instructed. In addition, the period of A (Fig. 3
Since the output of the INT signal is waited until the time (see 0) has elapsed, the control signals CD0 to CD7 are output when the INT signal is output.
The output state of the command data on the line is stable. Therefore, the payout control command is properly received by the payout control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
Data is read from 72a (see FIG. 8) (step S
851). Then, it is confirmed whether or not the read data is within the rule (step S851a). Whether or not the data is within the rule is determined by checking whether or not the structure or content of the received data conforms to a predetermined rule. For example, when the received data has a different number of bytes from the regular command, or when the content of the data is a content that cannot be a regular command, the data is out of the rule. Is determined. If the read data is the data within the rule, it is confirmed whether or not it is the first byte of the payout control command having a 2-byte structure (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is "1". The head bit is “1” in the MODE byte (first byte) of the payout control command having a 2-byte structure (see FIG. 29). Therefore, the payout control CPU 371
If the first bit is "1", it is determined that the valid first byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter in the reception buffer area (step S853).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

If the first byte has already been received,
It is confirmed whether the first bit of the received 1 byte is "0". If the first bit is "0",
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The head bit is "0" in the EXT byte (second byte) of the payout control command having a 2-byte structure (see FIG. 29). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not "0". If it is determined as "N" in step S854, the process of step S856 is not performed, so the command received next is stored in the buffer area where the command received this time should have been stored. It

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether the command reception counter is 12 or more (step S857), and if it is 12 or more, the command reception number counter is cleared (step S858). After that, the saved registers are restored (step S859),
Finally, the interrupt permission is set (step S860).

During the command reception interrupt process, the interrupt is disabled. As described above, since the interrupt is enabled during the 2ms timer interrupt process, if a command reception interrupt occurs during the 2ms timer interrupt process, the command reception interrupt process is executed with priority. It Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since the other interrupt processing is not executed during the command receiving processing, the maximum time required for the command receiving processing is determined. If the other interrupt processing can be executed during the command receiving processing, it is difficult to estimate the maximum time required for the command receiving processing. Since the maximum time required for the command reception process is determined, the period C in the command transmission process of the game control means (see FIG. 30)
Can be accurately determined. More specifically, since the maximum time required for the command reception process is determined, it is possible to accurately determine what the value of the wait counter set in step S367 should be.

The payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX
It is configured so that it can be immediately distinguished from T) on the receiving side.
That is, the receiving side can immediately detect whether the data as MODE or the data as EXT is received by the first bit. Therefore, as described above, it is possible to easily determine whether or not proper data has been received.

Next, a specific example of the switch process (step S752) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch is certainly turned on, and the process corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 49, the switch timer displays a detection signal (prize ball count switch 301A).
The number of ball lending count switches 301B) is set to two. In the RAM, the address of each switch timer is in the bit arrangement order of the input port B (see FIG. 42).
They are arranged in the same order as the order from top to bottom shown in.

FIG. 50 is a flow chart showing an example of the switch process of step S752. In the switch process, the payout control CPU 371 inputs the data input to the input port B (step S651).
Then, "2" is set as the number of processes (step S65).
2) Set the address of the switch timer for the prize ball count switch 301A in the pointer (step S
653). Then, the switch check processing subroutine is called (step S654). The switch check processing subroutine can be configured in the same manner as the switch check processing subroutine in the game control means (see FIG. 22).

Then, the value of the switch timer corresponding to the prize ball count switch 301A is checked (step S
655), if the value is 2, it is determined that one prize ball has been paid out. When it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball unpaid counter (the number of prize balls stored in the total number memory: unpaid amount data) by -1. (Step S65
6).

[0331] Next, the ball lending count switch 301B
The value of the switch timer corresponding to is checked (step S657), and if the value is 2, it is determined that one loan ball has been paid out. When it is determined that one ball has been paid out, the payout control CPU 371
Decrements the unpaid sphere unpaid number counter (loan sphere number stored in the lent ball number storage): unpaid number data (step S658).

FIG. 51 is a flow chart showing an example of the payout prohibition state setting process of step S753. In the payout prohibition state setting process, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S753a). If there is a receive command in the receive buffer, it is confirmed whether or not the received payout control command is a payout prohibition state designation command (step S).
753b). If it is a payout prohibition state designation command, the payout control CPU 371 sets the payout prohibition state (step S753c).

When it is confirmed in step S753b that the received command is not the payout prohibition state designation command, it is confirmed whether or not the received payout control command is the payout possible state designation command (step S753d). If it is the payable state designation command, the payout prohibited state is canceled (step S753e).

When setting the pay-out prohibited state,
The payout control CPU 371 controls, for example, driving of the payout motor 289, and sets an internal flag (payout stopped flag) indicating that the payout is prohibited. When the payout prohibition state is released, the driving of the payout motor 289 is restarted and the payout stop flag is reset. That is, in step S753c,
A process of storing data indicating that the payout is prohibited (a set payout suspended flag) in a predetermined storage area is executed, and in step S753e,
A process of storing data indicating that the payout is permitted (reset payout suspended flag) in a predetermined storage area is executed.

The discontinuation flag is stored in, for example, the backup RAM area. The payout suspension flag has a 1-byte structure including bits D0 to D7, for example. In this case, for example, if D0 is "1", the payout prohibition state is set, and if D1 is "1", the payout prohibition state is released.

When the payout prohibiting state is set, the payout motor 289 may be stopped immediately, but the payout motor 289 is not controlled in such a manner but is cut off at a good cutting position.
May be stopped. For example, the payout of the game balls may be executed in units of 25, and the payout motor 289 may be stopped when the payout of one unit is completed, and the internal state may be set to the payout prohibited state. As mentioned above,
Since the ball break switch 187 is installed at a position where it can detect that there are 27 to 28 gaming balls in the payout ball passage, even if the game control means of the main board 31 detects the ball breaking. From that point on, at least 25 payouts are possible. Therefore, there is no problem even if the payout prohibition state is set at the time when the payout of one unit is completed. Further, if the payout prohibition state is set for each unit, the control at the time of restarting the payout becomes easy.

FIG. 52 is a flow chart showing an example of the command analysis execution processing of step S754. In the command analysis execution processing, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S754a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for designating the number of prize balls (step S7).
54b). The payout control CPU 371 makes a determination in step S754b for the received command stored at the address in the receive buffer pointed to by the read pointer as the command instruction means. After the determination, the value of the read pointer is incremented by +1. When the address pointed to by the read pointer exceeds the address of the receive command buffer 12 (see FIG. 47), the value of the read pointer is updated to point to the receive command buffer 1.

If the received payout control command is a payout control command for designating the number of prize balls, the number instructed by the payout control command is added to the total number storage (step S754c). That is, the payout control CPU 371
Stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

If necessary, the payout control CPU 371 performs the subtraction of the command reception number counter and the reception command shift processing in the reception buffer. Further, the payout prohibition state setting process and the command analysis execution process may be configured to be repeated until the value of the read pointer and the latest command storage position in the reception buffer match. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands, but the repeated processing is executed until they match. , There are no outstanding received commands. That is, all the received commands stored in the reception buffer are read and processed in one process.

FIG. 53 is a flow chart showing an example of the prepaid card unit control process of step S755. In the prepaid card unit control process, the payout control CPU 371 confirms whether or not the VL signal input from the card unit control microcomputer is detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Further, the payout control CPU 37
1 confirms whether or not the value of the VL signal non-detection counter is 125 in this embodiment (step S755).
c). If the value of the VL signal non-detection counter is 125,
The payout control CPU 371 stops the output of the emission control signal to the emission control board 91 and stops the drive motor 94 (step S755d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) When the OFF of the VL signal is continuously detected, the ball firing prohibition state is set.

When the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output control signal output is stopped (step S755f), the payout control CPU 371 starts the output control signal output to the discharge control board 91 to put the drive motor 94 into an operable state (step S755g). .

54 and 55, step S756 is executed.
It is a flow chart which shows an example of the ball lending control processing of.
In addition, in this embodiment, the maximum value of the continuous payout number is one unit (for example, 25) of the lending sphere, but the maximum value of the continuous payout number may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is suspended (step S510). If it is stopped, the process ends.
Whether or not the ball lending is stopped is confirmed by whether or not the payout stopped flag which is set in the payout prohibition state setting process shown in FIG. 51 is turned on.

If the ball lending is not stopped, the payout control CP
The U371 confirms whether or not the lending of balls is in progress (step S511). If the lending of balls is in progress, the process proceeds to the process of lending balls shown in FIG. 55. In addition, whether or not the lent-out of the lent-out sphere is being performed is determined by the state of the lent-out-of-ball-lending flag described later. If the loan balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S512). Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending balls nor the prize balls are being paid out, the payout control CPU 371 confirms whether or not there is a ball lending request from the card unit 50 (step S5).
13). When there is a request, the ball lending processing flag is turned on (step S514), and 25 (one unit of ball lending: 100 yen here) is set in the backup RAM area storage of the number of lending balls (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout control CPU 371 sets the motor rotation time for paying out the 25 game balls, or determines the number of output pulses corresponding to the motor rotation time. Then, the payout motor 289 is turned on (step S51
8), and shifts to the processing during ball lending shown in FIG.

Turning on the payout motor 289 is as follows.
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the acceptance. The ball lending processing flag is set in the backup RAM area.

FIG. 55 is a flowchart showing the processing during ball lending in the payout control processing by the payout control CPU 371. In the ball lending process, the payout motor 289 is turned on if it is not turned on. In addition, in this embodiment,
In the switch processing of step S751, it is confirmed whether or not the game balls have been paid out based on the detection signal of the ball lending count switch 301B. Therefore, in the ball lending control processing, the storage of the number of loaned balls is not subtracted.

In the ball lending control processing, the payout control CP
U371 confirms whether or not it is in the waiting time for passing the loan ball (step S519). If it is not during the waiting time for passing the rental ball, the rental ball is paid out (step S520),
It is confirmed whether or not the driving of the payout motor 289 should be ended (whether one unit of payout operation is ended) (step S52).
1). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522).
The lending ball passage waiting time is set (step S52).
3).

If it is in the lending ball passage waiting time in step S519, the payout control CPU 371 confirms whether or not the lending ball passage waiting time has ended (step S52).
4). The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all of the one unit of lending balls have been paid out, so that it is possible to indicate to the card unit 50 that the next ball lending request can be accepted. The EXS signal is turned off (step S525). The distribution solenoid is turned off (step S5).
26), turn off the ball lending processing flag (step S5)
27). If the last payout ball has not passed the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. Also,
In this embodiment, prize balls and ball lending are performed by the same payout device.

If the BRQ signal which is the ball lending request signal is turned on again within a predetermined period after turning off the EXS signal indicating acceptance of the ball lending request, the ball lending is performed without turning off the distribution solenoid and the payout motor. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be continuously executed.

The content of the number of rented balls is stored by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the game machine is stopped. Therefore, when the power supply is restored within the predetermined period, the payout control CPU 371 can continue the ball lending process based on the content of the loan ball number storage.

56 and 57, step S757 is executed.
It is a flow chart which shows an example of the prize ball control processing. In addition, in this example, the maximum value of the continuous payout amount is set to the same number as one unit of the lending sphere (for example, 25), but the maximum value of the continuous payout amount may be another number.

In the prize ball control processing, the payout control CPU
The 371 first confirms whether or not the prize ball is stopped (step S530). If it is stopped, the process ends. Whether or not the prize balls are stopped is confirmed by whether or not the payout stopped flag which is set in the payout prohibited state setting process shown in FIG. 51 is turned on.

If the prize ball is not stopped, the payout control CPU
The 371 confirms whether or not the lending balls are being paid out (step S531), and if the lending balls is being paid out, the process is ended. In addition, whether or not the lent ball is being paid out is determined by the state of the ball lending processing flag. If the payout of the rented balls is not in progress, it is confirmed whether or not the prize ball payout processing has already been started, that is, whether or not the prize balls are being paid out (step S53).
2). If it is in the prize ball, the processing shifts to the process in the prize ball shown in FIG. Whether or not a prize ball is in play is determined by the state of a prize ball processing flag, which will be described later.

If the prize balls are not being paid out, the payout control CPU
371 confirms whether the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number memory is 2.
It is confirmed whether it is 5 or more (step S536). The prize ball processing flag is set in the backup RAM area.

When the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 instructs the payout motor 289 to rotate the payout motor 289 until the 25 game balls are paid out. In order to output the drive signal by the operation, the 25-piece dispensing operation is set (step S53
7). Specifically, the motor rotation time for paying out the 25 game balls is set, and the number of output pulses corresponding to the motor rotation time is determined.

If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 rotates the payout motor 289 until the game balls corresponding to the number stored in the total number memory are paid out. In order to output the drive signal so as to perform the above operation, the all-pieces payout operation is set (step S538). Specifically, the motor rotation time for paying out the game balls is set, and the number of output pulses corresponding to the motor rotation time is determined. Next, the payout motor 289 is turned on (step S539). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the prize ball side. Then, the process shifts to the process of paying out prize balls in the prize ball control process shown in FIG.

FIG. 57 is a flow chart showing an example of a prize ball process in the payout control process by the payout control CPU 371. In the prize ball control processing, the payout motor 289
If is not on, turn it on. In this embodiment, in the switch processing of step S751, it is confirmed whether or not the game balls have been paid out by the detection signal of the prize ball count switch 301A. Is not done.

In the process of winning a prize ball, the payout control CPU
The 371 confirms whether or not it is during the prize ball waiting time (step S540). If it is not during the prize ball passage waiting time, whether or not the prize balls should be paid out (step S541) and the driving of the payout motor 289 should be ended (whether the payout operation of 25 or a predetermined number of less than 25 has ended). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the prize ball passage waiting time (step S544). The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

If it is during the prize ball passage waiting time in step S540, the payout control CPU 371 confirms whether or not the prize ball passage waiting time is over (step S545).
When the prize ball waiting time is over, step S537
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
If the award ball passage waiting time has ended, the award ball processing flag is turned off (step S546). If the last payout ball has not passed the prize ball count switch 301A before the prize ball passage waiting time has elapsed, a prize ball path error is determined.

In this embodiment, step S5
11, the ball lending is prioritized over the prize ball processing according to the determination in step S531, but the prize ball processing may be prioritized over the ball lending.

The contents of the total number storage and the number of rented balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored within a predetermined period, the payout control C
The PU 371 can continue the payout process based on the content of the total number storage.

Although the payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number memory, the prize ball number is stored for each prize ball number (for example, 15, 10, 6, 6).
Individual). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. Then, when the prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, the subtraction process is performed in the payout control process). Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored within a predetermined period, the payout control CPU
The 371 can continue the prize ball payout process based on the contents of the respective number counters.

In this embodiment, the payout control means detects that the INT signal relating to the payout control signal has risen, and starts the process of fetching 1-byte data by, for example, an interrupt process. Since a receiving ring buffer (a receiving buffer in this example) capable of storing a plurality of payout control commands is provided, after the payout control command is received, the next payout control command is issued before the control based on the command is started. The receipt of the command does not mean that the command is not received by the payout control means.

In the payout control means, the interrupt process is activated even in the payout prohibition state, so that the payout control means can receive the payout control command even in the payout prohibition state. Then, in the payout prohibition state, the payout processing according to the received payout control command is stopped, but since a receiving ring buffer capable of storing a plurality of payout control commands is provided, it is sent from the game control means. The payout control command does not disappear in the payout control means.

Then, in the payout control means, a command reception number counter is used as an address designating means for indicating in which area in the reception ring buffer the transmission command is to be stored. Therefore, it is easy to determine which area should be used.

In the above embodiment, the case where the RAM is used as the fluctuation data storage means is shown. However, as the fluctuation data storage means, any electrically rewritable storage means other than RAM can be used. You may use.

Further, in the above-described embodiment, the power supply monitoring means is provided on the power supply board 910 and the circuit for generating the signal for system reset is provided on the electric part control board. It may be provided on the substrate.

58 to 60 are non-maskable interrupt processing (N) executed in response to a power-off signal from the power supply board 910.
It is a flow chart which shows the example of processing of MI processing: processing at the time of power supply stop. In this example, the process at the time of stopping the power supply is executed according to the NMI, but a power-off signal is sent to the payout control C
You may connect to the maskable terminal of PU371 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In the non-maskable interrupt process, the payout control CPU 371 sets the AF register to a predetermined backup R.
The data is saved in the AM area (specifically, the stack area) (step S801). Further, the interrupt flag is copied to the parity flag (step S802), and the contents are saved in the stack area (step S803). The interruption flag is an internal flag of the payout control CPU 371 and indicates whether the interruption permission state or the prohibition state is set. The BC register, DE register, HL register, and IX register are saved in the stack area (step S8).
04-807). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag.

Next, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S809), and sets the number of processes (“2” in this example) in another register (step S810). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S811). Another register is used as the IO pointer.

Then, clear data is set to the address pointed to by the IO pointer (step S81).
2), the value of the IO pointer is incremented by 1 (step S81
3), 1 is subtracted from the value of the number of processes (step S814).
In the processes of steps S812 to S814, the value of the number of processes is 0.
Is repeated (step S815). As a result, clear data is set in the output port C and the output port D (see FIG. 41). As shown in FIG. 41, in this example, “1” is in the ON state, and clear data “00” is set in each output port, so all the ports of the output port C and the output port D are turned off. It becomes a state. In this example, since the output port E is not cleared, the output port of the distribution solenoid 310 is not turned off. The clearing process may be performed on the output ports other than the output port of the distribution solenoid 310 in the output port E.

In addition, in this embodiment, the payout motor 2
As 89, a stepping motor that is rotated by a pulse signal (drive signal) from the payout control CPU 371 is used. Therefore, by stopping the output of the pulse signal to the payout motor 289, the ball payout device 9
The driving of 7 is stopped.

After that, in this embodiment, a prize ball count switch 301A (corresponding to the prize game medium detection means) and a ball lending count switch 301B as payout detection means for a predetermined period (hereinafter referred to as "payout confirmation period").
Check the detection signal (corresponding to the rental game medium detection means). When the prize ball count switch 301A is turned on, the prize ball count value is incremented by 1. When the ball lending count switch 301B is turned on, the ball lending count value is incremented by 1.

In this embodiment, the payout confirmation period measuring counter is used to measure the payout confirmation period. The value of the payout confirmation period measurement counter is the initial value m.
From the loop of the switch detection processing described below (S8
It is assumed that the payout confirmation period ends when the loop starting from 17 and returning to S817) is performed by -1 each time the value becomes 0. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore, a time m times the time required for one round of the loop is substantially equivalent to the payout confirmation period.

The built-in timer of the payout control CPU 371 may be used to measure the payout confirmation period. That is, a predetermined value (corresponding to the payout confirmation period) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the payout confirmation period has ended. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program. Also, during the payout confirmation period, the game ball is the ball payout device 9
Award ball count switch 301 from the time of dropping from 7
It is set to be equal to or longer than the time required to reach A or the ball lending count switch 301B.

At least the payout confirmation period in which the switch detection processing is executed (the period from the time when the game ball falls from the ball payout device 97 to the time when it reaches the prize ball count switch 301A or the ball lending count switch 301B).
For example, about 100 [ms] to 150 [ms]. ), The prize ball count switch 301A and the ball lending count switch 301B must be in a state where the game ball can be detected. Therefore, in this embodiment, as shown in FIG. 9, the converter IC 9 in the power supply board 910 is
A capacitor 923 as an auxiliary driving power source having a relatively large capacity is connected to the input side of 20. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained within the switchable range for a certain period of time, and the prize ball count switch 301A and the ball lending count switch 3
01B becomes operational. The capacity of the capacitor is determined so that the period is longer than the payout confirmation period. The longer the payout confirmation period is, or the longer the switchable period is longer than the payout confirmation period, the larger the capacity of the capacitor that is needed.Therefore, the payout confirmation period can be set shorter and the switch can be driven. It is advisable not to allow too much margin for a certain period.

Input port and payout control CPU
Since the 371 is also driven by the + 5V power source created by the converter IC 920, it can be operated for a relatively long period even when the power supply is stopped.

Furthermore, in this embodiment, the distribution solenoid 310 is used to switch between the prize ball path and the rental ball path. Therefore, the capacitor 92 shown in FIG.
The capacity of No. 4 is such that the distribution solenoid 310 can be driven at least during the above-mentioned payout confirmation period. The capacitor 924 is connected to a line for supplying electric power to each electric component (a line on the input side of the connector 915), but the game control means is operated by another solenoid (large winning opening) in response to the power-off signal. Since the drive signals (for opening and closing, etc.) are in the OFF state, the capacitor 924 needs only to drive only the distribution solenoid 310 among the solenoids after the power-off signal is generated.

The capacitors 923 and 924 used in this embodiment are examples of the auxiliary driving power source, but other auxiliary driving power sources may be used. At least during the above payment confirmation period,
Prize ball count switch 301A, ball lending count switch 301B, sorting solenoid 310 and payout control C
As long as the payout control means such as the PU 371 can be driven, an auxiliary drive power source of another aspect can be used.

In the input processing of the detection signal from the payout detecting means (switch detection processing), the payout control CPU 371.
First, the value m corresponding to the payout confirmation period is set in the payout confirmation period measuring counter (step S816). Further, in step S817, an initial value n corresponding to a time of 2 ms is set in the 2 ms measurement counter. Then, the value of the 2 ms measurement counter is decremented by 1 (step S819) until the value of the 2 ms measurement counter becomes 0 (step S818).

When the value of the 2 ms measurement counter becomes 0,
The input of the detection signals of the prize ball count switch 301A and the ball lending count switch 301B is checked. That is, a process similar to the switch process of step S752 is performed. Specifically, the data input to the input port B is input (step S820). Next, "2" is set as the number of processes (step S821), and the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S822). Then, the switch check processing subroutine is called (step S823).

When the value of the switch timer corresponding to the prize ball count switch 301A is 2, it is determined that the prize ball count switch 301A is turned on (step S82).
5), the prize ball count value (in the backup RAM area) is incremented by 1 (step S826). When the value of the switch timer corresponding to the ball lending count switch 301B is 2, the ball lending count switch 301B
If is turned on (step S827), the ball rental count value (in the backup RAM area) is incremented by 1 (step S828). Next, the value of the payout confirmation period measuring counter is decremented by 1 (step S829), and if the value is not 0, the process returns to step S817 (step S83).
0).

With the above processing, when the prize ball count switch 301A and the ball lending count switch 301B are turned on within the payout confirmation period, the prize ball count value and the ball lending count value are incremented by one. Since the process for saving the contents of the backup RAM is performed after such a switch detection process, the prize ball count value or the ball lending count value is always incremented by 1 for the game ball that has been paid out.
When the power supply to the gaming machine is stopped and then restored, in step S733 in the gaming state restoration processing (see FIG. 45), the payout control CPU 371 subtracts the prize ball count value from the stored value of the total number storage. Further, the lent ball count value is subtracted from the stored value of the lent ball number storage. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent.

Further, since it is determined whether or not the prize ball count switch 301A or the ball lending count switch 301B is turned on under the same condition and the same process as the normal control, the switch detection in the power supply stop process is performed. The input processing routine (1) and the input processing routine for switch detection in normal control (switch check processing subroutine called by the switch processing shown in FIG. 50) can be commonly used. That is, the switch detection input processing routine in the normal control can be used in the switch detection in the power supply stop processing. Therefore, the program amount of the power supply stop processing is reduced.

[0387] When the payout confirmation period elapses (step S8)
30), the payout control CPU 371 stores the designated value with backup (“55H” in this example) in the backup flag (step S835). The backup flag is formed in the backup RAM area. Then, the same processing as the processing of the CPU 56 of the main board 31 is performed to create parity data and save it in the backup RAM area (steps S836 to S845). Then, after the contents of the stack pointer are saved in the backup RAM area (step S846), an access prohibition value is set in the RAM access register (step S847). After that, the built-in RAM cannot be accessed.

When the access prohibition value is set in the RAM access register, the payout control CPU 371 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the RAM area in which the data used in the payout control process is stored is backed up by power supply. Therefore, the checksum generation process indicating whether the contents are correctly stored, and R for preventing the contents from being rewritten
The AM access prevention process corresponds to the process for storing the payout control state.

As described above, in this embodiment, as shown in FIG.
As shown in the conceptual diagram of 1, the game control means 56A mounted on the main board 31 can execute a game control process, a power supply stop time process, and a recovery process, and the payout control board 3
The payout control means 371A mounted on the No. 7 can execute payout control processing, power supply stoppage processing, and recovery processing. Then, the game control means 56A performs a restoration command transmission process in the restoration process, and performs a timer interrupt setting process and a register restoration process. After that, when the recovery process is completed, the game control process is executed again.

In the recovery processing, the game control means always sends a recovery command to the payout control means. Then, the payout control means performs the timer interrupt setting process and the register restoring process on the condition that the recovery command is received,
The control of the ball payout device 97 as the payout means is restarted. That is, if the condition for ball payout is satisfied, the ball payout device 97
Is driven to enter the state of paying out the game balls.

After transmitting the restoration command, the game control means returns to the state where the game control is possible by performing the timer interruption setting processing and the register restoration processing, and the payout control means performs the timer interruption setting processing after receiving the restoration command. Since register return processing is performed to return to a state in which payout control is possible, the timings of restarting game control and restarting payout control are substantially the same,
A gap between the game control and the payout control is prevented from occurring. That is, the difference between the timing when the game control means restarts control and the timing when the payout control means restarts payout control can be reduced, and the payout of the game ball between the game control means and the payout control means can be made. It is possible to prevent the deviation of the state recognition regarding.

When the payout control means receives the payout prohibition state designation command as the recovery command, it keeps the internal state in the payout prohibition state.

Further, in the above-mentioned embodiment, the payout control means is configured to confirm whether or not the prize ball count switch 301A and the ball lending count switch 301B are turned on in the power supply stop process.
A configuration for confirming the state of either switch may be adopted.

As described above, in this example, the output port other than the output port of the distribution solenoid 310 is cleared before the switch detection process is executed (before step S762). During execution of the power supply stop process, the payout control CPU 371 and switches are connected to the capacitor 92.
It will be driven by the charging power of 3,924 or the like. In this example, since the output port clearing process is performed before the switch detection process is executed, the capacitor charging power and the like can be efficiently used for the power supply stop process.

In this example, when a power-off signal is generated due to a momentary power failure or the like, the power-supply voltage is restored to the normal value and the gaming machine returns to a controllable state. When such a situation occurs, a return signal is supplied from the power supply board 910 to the payout board 37. When the return signal is input, the payout control CPU 371 is reset. Therefore, the payout control CPU 371 can start execution of the main processing shown in FIG. At that time, since the game state is saved when the power-off signal is output, the payout state recovery process is executed in the process of step S710, and the payout control returns to the state at the time of the power-off signal and the state The payout control is continued from.

In addition, the process at the time of stopping the power supply (see FIGS. 35 to 3).
7, FIG. 58 to FIG. 60), until the detection maintaining period elapses, the power board 910 uses the electric power charged in the capacitors 923 and 924 to cause the prize ball count switch 301A and the ball lending count switch. 301B
Is supplied with electric power capable of driving, the distribution solenoid 310 supplies driving power for maintaining the state of the distribution member 311, and the game control means is a prize ball count switch 30.
1A detection signal input processing, that is, switch detection processing (steps S466 to S473) is performed, and the payout control means inputs detection signals from the prize ball count switch 301A and the ball lending count switch 301B, that is, switch detection processing (steps). Since S816 to step S828) are configured to be performed, in the power supply stop process, the prize game medium paid out (the game medium paid out as a prize based on the winning in the winning area) or the rental game medium (from the player) It is possible to reliably detect the game medium rented out in response to the lending request. That is, according to the above-mentioned gaming machine, since it is possible to reliably detect the paid-out game medium in the power supply stop process, it is possible to accurately grasp the number of unpaid game media. become.

Also, in the switch detection processing executed in the power supply stop processing, the same subroutine as the switch detection processing executed in the game control processing in the game control means and the main processing in the payout control means is used, It is possible to reduce the program capacity of the processing when the power supply is stopped.

Further, as described above, in the case where the power supply is not stopped even though the standby state after the power supply stop processing is continuously executed, the operation for recovering from the standby state is performed. Since the return signal is output to the CPU 56 and the payout control CPU 371, the return signal enables the CPU 56 and the payout control CPU 371 to return from the standby state to the control execution state. Therefore, it is possible to prevent the control from being disturbed even if the power supply is interrupted for a very short time.

That is, when the game control means and the payout control means having the memory holding means (for example, backup RAM) are in the standby state waiting for the system reset after performing the power supply stop time processing in response to the power-off signal, the power supply When the return signal is output according to the restoration, the game control means and the payout control means restart the operation from the first part of the program. At this time, the control state saved in the power supply stop process is restored, so that the game continues as if nothing happened to the player.

Further, when the electric part control means operates the operation means (clear switch 921) even when the control state saved in the power supply stop processing remains when the power supply is started. In this case, the initialization process is executed without executing the state recovery process. Therefore, the game store staff or the like can easily clear the saved state, and it is possible to improve the convenience in operating the game machine at the game store. In other words, in the game store, the storage contents of the backup storage means can be initialized when it is not necessary to perform the state recovery processing of the game machine, and thus the profit which should not be originally given to other players is given. Can be easily prevented,
As a result, it is possible to improve the convenience in operating the gaming machine in the gaming shop.

As described above, until the detection maintaining period elapses, the power supply substrate 910 supplies the distribution solenoid 310 with electric power capable of driving the distribution member 311. Therefore, the drive state of the distribution solenoid 310 as the passage switching means can be electrically maintained. Therefore, the power supply board 910 is equipped with an operating state holding means for supplying electric power for maintaining the state of the distribution member 311 until the detection maintaining period elapses. The state of the distribution member 311 is maintained until the detection maintaining period elapses, and the distribution member 311 does not operate, so the distribution member 311 is not operated.
It is possible to prevent the game ball from being sandwiched between and the walls inside the ball passages 293a and 293b.

Further, as described above, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the ball payout device 97
Is stopped, the input process (switch detection process) of the detection signal from the payout detection means (prize ball count switch 301A or ball lending count switch 301B) is executed for a predetermined detection maintaining period, and then the payout control is performed. Processing is performed to save the state. Therefore, the game balls that were in the process of being paid out at the time of the power failure are surely reflected in the saved contents of the backup RAM. Therefore, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent a contradiction or the like from occurring between the stored control state and the actual control state. it can.

Further, as described above, means capable of outputting a return signal (for example, means composed of the counter 971 or the like:
Since the standby state returning unit is configured to be mounted on the power supply board 910, it is not necessary to provide the standby state returning unit for each control board, and the standby state can be returned with a simple configuration. .

As described above, the power supply monitoring means (for example, the power supply monitoring IC 902) has the highest voltage among the DC power supplies supplied to the electric component control means (CPU 56, payout control CPU 371, etc.). Power source (eg V
Since it is configured to monitor SL (+ 30V), it is possible to detect the voltage drop at an early stage.

Further, as described above, the power supply monitoring means (for example, the power supply monitoring IC 902) supplies power to each electric component control means (the CPU 56, the payout control CPU 371, etc.) (for example, the power supply board 910). ), The power supply monitoring means can be arranged near the supply source of the monitoring power supply, and the power supply monitoring means can appropriately monitor the state of the power supply. . Further, with the above configuration, the power supply monitoring means can be replaced by simply changing the power supply board.

Further, as described above, the predetermined period (delay period) in which the power-off process is not executed is configured to include at least the period until the voltage supplied to the predetermined voltage (for example, 22V) or higher rises. Therefore, it is possible to prevent the power-off process from being executed in an unstable state. In particular, in the above-described embodiment, the power-off process is executed when the voltage becomes equal to or lower than the predetermined voltage. Therefore, the above configuration prevents the power-off process from being erroneously executed at the time of rising. can do.

Further, as described above, when power supply is started, payout control means (payout control CPU 371).
However, since the game ball payout process is not executed unless the payable state designation command is received from the game control means (CPU 56), the game ball is not controllable by the game control means. It is possible to prevent the payment of money. Therefore, the game control means can surely receive the detection signals of the prize ball count switch 301A and the ball lending count switch 301B for detecting the paid game balls. Therefore, it is possible to prevent a discrepancy between the contents of the information grasped by the game control means and the payout control means regarding the number of unpaid gaming balls, and the game control means and the payout control means are sure to do so. It is possible to achieve control matching.

Also, the detection signal from the prize ball count switch 301A is inputted to both the game control means and the payout control means, and the detection signal from the ball lending count switch 301B is inputted only to the payout control means. Therefore, it is possible to perform reliable management according to each of the prize game medium and the rental game medium.

When the return signal is not generated in power supply board 910, the timer processing can be performed by software to return from the standby state to the control state, but the timer processing may be performed by hardware.

FIG. 62 is a block diagram showing an example of a configuration in which the timer process is performed by hardware when the return signal is not generated in the power supply board. In this example, the main board 31 is provided with a counter (watchdog timer circuit) 162 that functions as a watchdog timer. The watchdog timer circuit 162 counts the output pulses of the oscillation circuit 164, and when counting up, generates one high-level pulse as the Q output. The pulse signal is logically inverted by the inversion circuit 163 and input to the AND circuit 161 as a return signal. The AND circuit 161 calculates the logical product of the reset signal and the return signal to obtain C.
It is supplied to the reset terminal of the PU 56. The CPU 56
May be set to output a system clock or a divided clock thereof, and the clock may be used as an input clock signal of the watchdog timer circuit 162.

The count-up value is set to be longer than the time required for the voltage value of VSL to drop to the voltage at which Vcc can be generated after the power-off signal goes low. Since the watchdog timer circuit 162 operates using Vcc as a power source, the count-up value is set to a value equal to or greater than the operable period of the watchdog timer circuit 162. Therefore, when the power supply to the gaming machine is stopped, the watchdog timer circuit 162 and other circuit components generally do not operate before the watchdog timer circuit 162 counts up and the return signal is output.

When the CPU 56 is performing game control, a clear pulse is periodically given to the watchdog timer circuit 162. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 162 counts up. Therefore, no pulse appears in the Q output of the watchdog timer circuit 162 while the CPU 56 is performing normal game control.

FIG. 63 shows the watchdog timer circuit 16
It is the flowchart which shows the 2ms timer interruption processing of the game control expedient when 2 is provided. As shown in FIG. 63, in the game control process (steps S21 to S32a), the watchdog timer clear process (step S3)
2a) is executed. Therefore, the watchdog timer clear process is executed every 2 ms.

In the watchdog timer clear process (step S32a), a process of outputting one pulse to the output port reaching the clear terminal of the watchdog timer circuit 162 is performed. Therefore, during the execution of the game control process, the watchdog timer circuit 162 is periodically provided with a clear pulse, so that it does not count up.

When the supply voltage to the gaming machine is lowered and the power-off signal is output, the non-maskable interrupt processing as shown in FIGS. 21 to 23 is started. During the processing, the clear pulse is not output to the watchdog timer circuit 162. Therefore, when the power supply voltage is restored and the watchdog timer circuit 162 is operating until it counts up, the return signal is output.

FIG. 64 is a timing chart showing the output timing of the return signal when the return signal is generated by the software timer processing or the watchdog timer circuit 162 described above. FIG. 64A illustrates an example in which the power supply to the game machine is stopped. The software timer process is started after the process at the time of power supply stop is completed and a standby state is set. Further, since the clear pulse is not output to the watchdog timer circuit 162 in the non-maskable interrupt processing, the watchdog timer circuit 16
Are substantially activated from the start of the power supply stop process. In either case, the time-up value (count-up value) is set so as not to time-up until the power supply voltage becomes smaller than the Vcc-producible voltage value, so that no return signal is generated.

When the power supply is momentarily cut off, as shown in FIG. 64 (B), the voltage level of VSL is lowered and then restored. Also in that case, when the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the power supply stoppage process is started. And CP
U56 enters the loop state after the power supply stop process is completed.
Without any control, the loop processing cannot be exited. In this case, the watchdog timer circuit 162 counts up and a return signal is generated.

As shown in FIG. 62, in the main board 31, the return signal is sent to the CPU via the AND circuit 161.
It is input to the reset terminal 56. Therefore, the CPU 56
Requires a system reset. As a result, the CPU 56
Can get out of standby.

FIG. 65 is a block diagram showing an example of a configuration in which the timer processing is performed by the hardware of the payout control board 37 when the return signal is not generated in the power supply board. In this example, the payout control board 37 is provided with a counter (watchdog timer circuit) 386 that functions as a watchdog timer. The watchdog timer circuit 386 counts the output pulses of the oscillation circuit 388, and when counting up, generates one high-level pulse as the Q output. The pulse signal is logically inverted by the inversion circuit 387 and input to the AND circuit 385 as a return signal. The AND circuit 385 calculates the logical product of the reset signal and the return signal and supplies the logical product to the reset terminal of the CPU 56.

The count-up value is set to be equal to or longer than the time required for the voltage value of VSL to drop to the voltage at which Vcc can be generated after the power-off signal becomes low level. Since the watchdog timer circuit 386 operates using Vcc as a power supply, the count-up value is set to a value equal to or greater than the operable period of the watchdog timer circuit 386. Therefore, in general, the watchdog timer circuit 386 and other circuit components do not operate before the watchdog timer circuit 386 counts up and the return signal is output. When the payout control CPU 371 is performing payout control, a clear pulse is periodically given to the watchdog timer circuit 386. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 386 counts up. Therefore, CP for payout control
No pulse appears in the Q output of the watchdog timer circuit 386 when U371 is performing normal game control.

FIG. 66 shows the watchdog timer circuit 38.
It is a flowchart which shows a part of main processing of the payout control means when 6 is provided. The process shown in FIG. 66 is executed subsequent to the processes of steps S701 to S714 shown in FIG. In this case, the watchdog timer clearing process (step S76) is executed in the payout control process loop (steps S715, S751 to S761).
1) is executed. Therefore, the watchdog timer clear process is executed every 2 ms.

In the watchdog timer clear process (step S761), a process of outputting one pulse to the output port reaching the clear terminal of the watchdog timer circuit 386 is performed. Therefore, since the clear pulse is periodically given to the watchdog timer circuit 386 during execution of the payout control process, it does not count up.

When the supply voltage to the gaming machine is lowered and the power-off signal is output, the non-maskable interrupt process shown in FIGS. 47 to 49 is started. During the processing, the clear pulse is not output to the watchdog timer circuit 386. Therefore, when the power supply voltage is restored and the watchdog timer circuit 386 is operating until it counts up, the return signal is output.

As shown in FIG. 65, the payout control board 3
7, the return signal is sent via the AND circuit 385.
It is input to the reset terminal of the payout control CPU 371.
Therefore, the payout control CPU 371 is reset. As a result, the payout control CPU 371 can exit the standby state.

As described above, in the main board 31 and the payout control board 37, the watchdog timer circuits 162, 3 are provided.
If 86 is provided, the return signal can be generated by hardware. Moreover, not only when the power supply voltage drops, but for some reason, the CPU 5
6 or even when the control of the payout control CPU 371 enters an infinite loop, the loop state can be exited.

The count-up value of the watchdog timer circuit 162 of the main board 31 is preferably larger than the count-up value of the watchdog timer circuit 386 of the payout control board 37. If the count-up value of the watchdog timer circuit 162 is larger, the return signal is supplied to the payout control means before the game control means. Therefore, the payout control means does not stand up first and miss the payout control command from the game control means.

Further, for example, the watchdog timer circuit 162 may be installed only on the main board 31, and the return signal from the watchdog timer circuit 162 may be supplied to the CPU 56 and the payout control board 37. With such a configuration, the overall circuit configuration scale can be reduced. Further, in the case of such a configuration, it is preferable to place a delay circuit between the watchdog timer circuit 162 and the reset terminal of the CPU 56 so that the payout control means can be activated first.

Furthermore, the watchdog timer circuit 16
The return signal of 2,386 may be input to the input port instead of being connected to the reset terminal of the CPU. In that case, the input port is monitored in the standby state in the power supply stop process, and when it is detected that the return signal is turned on, the process jumps to the beginning of the main process. Further, watchdog timer circuits 162 and 386
Alternatively, the return signal may be input to the CTC terminal of the CPU. In that case, the CTC interrupt is set in advance in accordance with the input of the return signal. Also, the interrupt permission is set in the standby state. Then, when the CTC interrupt is applied, the process jumps to the beginning of the main process.

Further, in the above embodiment, the power supply stoppage process is executed in the payout control board 37 in accordance with the NMI. However, the power-off signal is connected to the maskable terminal of the payout control CPU 371, and masking is performed. The power supply stop process may be executed by the possible interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

Further, in each of the above-described embodiments, the infinite loop is used as the standby state, but the present invention is not limited to this, and by using the HALT (halt) command or the like at the end of the power supply stop process of the control program, the control means is controlled. The control state of the (CPU 56, the payout control CPU 371) may be a standby state (a standby state in which an interrupt can be accepted). In this case, the signal input to the interrupt terminal becomes valid, and the control state can be restored by the signal input trigger to the interrupt terminal, and the standby state restoration means can be configured with a simple configuration. it can.

In each of the above embodiments, R
The means for supplying the backup power to the AM may be provided for each control means (CPU 56, payout control CPU 371). That is, backup RA
A means for supplying backup power may be provided for each RAM including the M area. Further, the number and mounting positions of such means (whether or not they are mounted on the control board or the power supply board) may be configured in any manner.

Further, in each of the above-described embodiments, the power supply from the power supply board 910 to the prize ball count switch 301A is performed through the main board 31, but is performed through the payout control board 37. Good. Further, the power may be directly supplied from the power supply board 910.

In each of the above-described embodiments, the power supply from the power supply board 910 to the ball lending count switch 301B is performed through the payout control board 37.
It may be performed via the main board 31 (for example, when the detection signal of the ball lending count switch 301B is input to the game control means as described later). Further, the power may be directly supplied from the power supply board 910.

In each of the above-described embodiments, the auxiliary power supply means supplies power to at least the prize ball count switch 301A and the ball lending count switch 301B after the detection signal from the power supply monitoring means is output. As long as it is a prize ball count switch 301A and a ball lend count switch 301B, it may also supply power to something other than the prize ball count switch 301B (a prize detection switch, etc.). It may be one that supplies electric power only. If power is supplied only to the prize ball count switch 301A and the ball lending count switch 301B, the power consumption (charging capacity) of the auxiliary power supply means can be reduced.

Further, in each of the above-mentioned embodiments, the auxiliary power supply means is each electric component control means (CPU 56,
It may be provided for each payout control CPU 371).

Further, in each of the above-mentioned embodiments, the detection signal of the ball lending count switch 301B is the payout control means (the payout control CPU 371 provided in the payout control board 37).
Although it is configured to be input only to, it may be configured to be input to the game control means (CPU 56 included in the main board 31), or may be configured to be input to both the payout control means and the game control means. Then, the game control means inputs the detection signal of the ball lending count switch 301B (ball lending count switch detection process) in the game control process (specifically, the switch process of step S21 described above) and the power supply stop process. May be configured to perform. In this case, RAM55 of game control means
A buffer for storing data indicating the number of unpaid spheres (loan sphere number storage buffer) is provided in the power supply backup area of, and the process of inputting the detection signal of the prize ball count switch 301A is performed during the power supply stop process ( A process similar to the prize ball count switch detection process) may be executed as a ball lending count switch detection process. Also,
In the game control process, the same process as the award ball number subtraction process (see FIG. 34) described above may be executed as a subtraction process of the number of lent balls. In such a configuration, the game control means is provided with a function of executing processing relating to signal exchange with the prepaid card unit 50 in the payout control means, and there is a lending request using the payout control command. It suffices to perform a process of transmitting information regarding the number of lent balls to the payout control means.

With the above arrangement, the game control means can manage the number of lent balls. In particular, when the detection signal of the ball lending count switch 301B is configured to be input to both the payout control means and the game control means, both the game control means and the payout control means can execute the management of the number of loan balls. Therefore, it becomes possible to manage the number of lent balls more accurately.

When the detection signal of the ball lending count switch 301B is input to the game control means, the + 12V power supply voltage can be switch-driven at least during the payout confirmation period or more when the power supply to the gaming machine is stopped. Maintained in range, ball lending count switch 301B
(Or the prize ball count switch 301A and the ball lending count switch 301B) can be operated,
The capacity of the capacitor 923 is determined.

It should be noted that the input processing module for the switch detection processing in the power supply stop processing and the input processing module for the switch detection processing in the normal control are made to be a common module as described above. When the detection signal of 301B is input to the game control means, it can be applied to the ball lending count switch detection processing executed by the game control means.

Further, in each of the above-described embodiments, the recording medium used in the recording medium processing device (prepaid card unit 50) is a magnetic card (prepaid card), but the recording medium is not limited to a magnetic card, and a non-contact type. Alternatively, a contact type IC card may be used. Further, when the recording medium processing device is configured to be able to specify the record information based on the identification code, the recording medium can read at least the information such as the identification code that can specify the record information by the recording medium processing device. It may be something that can be recorded on. Further, the recording medium may be readablely printed with a predetermined information recording symbol such as a barcode. The shape of the recording medium is not limited to the card shape, and may be any shape such as a disc shape, a spherical shape, or a chip shape.

In each of the above embodiments, the power supply monitoring means (for example, the power supply monitoring IC 902) outputs the power off signal when the power supply voltage reaches a predetermined value (for example, 22V). , For example, AC power supply (eg A
The AC signal related to C24V) may be digitally converted into a digital signal, and a power-off signal may be output when the digital signal is interrupted for a predetermined period.

Further, in each of the above embodiments, the power-off processing is executed when the power supply monitoring means (for example, the power supply monitoring IC 902) detects that the power supply voltage has reached a predetermined value (for example, 22V). The system is reset when the system reset means (for example, the system reset circuit 65) detects that the power supply voltage reaches a predetermined value (for example, 9 V). However, after the power-off processing is started, The system may be automatically reset after a lapse of a predetermined period. According to this structure, when the power supply monitoring means detects that the power supply voltage has reached a predetermined value (for example, 22V), the system reset means does not detect the power supply voltage thereafter. You will be able to reset the system.

The pachinko game machine of each of the above embodiments is
Mainly, a predetermined game value can be given to the player when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols.
Although it was a kind of pachinko machine, a kind of pachinko machine that can give a predetermined game value to the player if there is a prize in the predetermined area of the electric role to open based on the start prize, and a start prize Even if it is a third-class pachinko game machine, a predetermined right is generated or continues when there is a prize for a predetermined electric accessory that is released when a stop symbol of the symbols variably displayed based on the above is a combination of predetermined symbols The present invention can be applied.

Furthermore, the present invention is applicable not only to a pachinko gaming machine in which the game medium is a game ball, but also to a slot machine or the like, provided that an electric component for paying out the game medium is provided.

[0446]

As described above, in the invention according to claim 1, after the game control means of the gaming machine has transmitted the restoration command indicating the restoration of the control state to the payout control means in the restoration processing, the gaming machine is periodically operated. The timer interrupt setting process that is automatically activated is executed, and the register restoration process that restores the contents of the register is performed and control is restarted, and the payout control means restores by the restoration process. Since the control is restarted by performing the timer interrupt setting process and the register restoring process on the condition that the command is received, the game control means can manage the restart of the payout control means, and the game control means There is an effect that it is possible to prevent a discrepancy between the recognition of the payout of the game medium and the payout control means.

According to the second aspect of the present invention, in both cases where the payout control means performs the restoration process when the power supply is started and when the initialization process is performed when the power supply is started, the game medium Since a flag indicating that the payout is prohibited is set and the flag is reset on the condition that a predetermined command is received from the game control means, the payout control means is started when the power supply is started. Is definitely in a payout prohibition state.

According to the third aspect of the present invention, the game control means can transmit a payout amount designation command indicating a payout game medium payout amount when a predetermined prize game medium payout condition is satisfied, and the payout number is designated as a recovery command. Since the designated command is transmitted, even if the recovery command is provided, the types of commands transmitted from the game control means to the payout control means do not increase.

In the invention according to claim 4, the game control means and the payout control means, in the recovery process, an interrupt indicating whether the state before the power supply is stopped is the interrupt permitted state or the prohibited state. Since the flag is reset, the state related to the interrupt can be surely returned to the state before the power supply was stopped.

According to the fifth aspect of the present invention, the game control means and the payout control means, when the power supply is restored, a plurality of means for determining whether or not to restore the control state before the power supply is stopped. The recovery process is executed when all the recovery conditions of are satisfied, and the initialization process is executed when at least one of the plurality of recovery conditions is not satisfied. This prevents the control state from being restored.

In the invention according to claim 6, the game control means prohibits the payout of the game medium based on the establishment of a predetermined payout prohibition condition after the power supply is started and the initialization process or the recovery process is executed. Since it is configured to transmit a payout prohibition state designation command instructing, and to send a payout permission state designation command permitting the payout of the game medium based on the cancellation of the payout prohibition condition,
The payout control means can recognize whether or not the payout prohibition condition is satisfied.

According to the seventh aspect of the invention, the game control means transmits a payout prohibition state designation command when any one of the plurality of payout prohibition conditions is satisfied, and the payout prohibition condition is released. When the payout prohibition condition is not satisfied, a common payout permission state indicating that the payout of the game medium is permitted regardless of which of the plurality of payout prohibition conditions is satisfied. Since the designated command is transmitted, the load related to the information transmission from the game control means to the payout control means is further reduced.

According to the eighth aspect of the present invention, a storage state detecting means for detecting whether or not a predetermined amount or more of the game medium is stored in the storage portion for storing the paid-out game medium is provided. Since the prohibition condition is configured to include a condition that is satisfied when the storage state detection means stores a predetermined amount or more of the game medium, the storage unit stores the predetermined amount or more of the game medium. However, it is possible to prevent the payout control means from executing the game medium payout process.

According to the ninth aspect of the invention, the game medium out detecting means for detecting whether or not a predetermined amount or more of the game medium supplied to the payout means is secured is included, and the payout prohibition condition is the game medium out. Since the detecting means is configured to include the condition that is satisfied when it is detected that the predetermined amount or more of the game medium is not secured, the game medium supplied to the payout means is not secured in the predetermined amount or more. Nevertheless, it is possible to prevent the payout control unit from executing the game medium payout process.

In the invention according to claim 10, since the game control means is configured to use the payout prohibition state designation command or the payout permission state designation command as the recovery command, even if the recovery command is provided, the game control is performed. The types of commands transmitted from the means to the payout control means do not increase.

In the eleventh aspect of the present invention, the game control means uses the program address data relating to the address of the control program as the data necessary for restoring the control state in the power supply stop processing, the variable data storage means. It is configured to perform the process of saving in the power saving process and to resume the control based on the program address data saved in the fluctuation data storage means in the recovery process, so that it is executed when the power supply is stopped. It is possible to reliably return to control.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is a front view showing the front surface of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine viewed from the back side.

FIG. 4 is a rear view of a mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a front view showing an exposed portion of a power supply board installed on the game board.

FIG. 7 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 8 is a block diagram showing a circuit configuration example of a payout control board.

FIG. 9 is a block diagram showing a circuit configuration example of a power supply board.

FIG. 10 is a block diagram showing a configuration example of a reset management circuit.

FIG. 11 is a block diagram showing an example of the configuration around a CPU.

FIG. 12 is a timing chart for explaining the operation of a counter which is an example of timer means.

FIG. 13 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 14 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 15 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 16 is a flowchart showing main processing executed by a CPU on a main board.

FIG. 17 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state recovery process.

FIG. 18 is a flowchart showing a game state recovery process.

FIG. 19 is a flowchart showing a 2 ms timer interrupt process.

FIG. 20 is an explanatory diagram showing a formation example of a switch timer in a RAM.

FIG. 21 is a flowchart showing an example of a switch process.

FIG. 22 is a flowchart showing an example of a switch check process.

FIG. 23 is a flowchart showing an example of prize ball processing.

FIG. 24 is a flowchart showing an example of prize ball processing.

FIG. 25 is a flowchart showing an example of prize ball processing.

FIG. 26 is a flowchart showing a switch-on check process.

FIG. 27 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 28 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 29 is an explanatory diagram showing an example of a command form of a control command.

FIG. 30 is a timing diagram showing a relationship between an 8-bit control signal forming a control command and an INT signal.

FIG. 31 is an explanatory diagram showing an example of contents of a payout control command.

FIG. 32 is a flowchart showing a processing example of command set processing.

FIG. 33 is a flowchart showing a command transmission processing routine.

FIG. 34 is a flowchart showing an example of award ball number subtraction processing.

FIG. 35 is a flowchart showing a non-maskable interrupt process (power supply stop process).

FIG. 36 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 37 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 38 is a power supply drop or N when power supply to a game machine is stopped.
It is a timing diagram which shows a mode of MI signal.

FIG. 39 is a timing chart showing an example of how a detection signal input process is executed.

FIG. 40 is a block diagram showing a configuration example around a payout control CPU.

FIG. 41 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 42 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 43 is a flowchart showing a main process executed by a CPU in a payout control board.

FIG. 44 is a flowchart showing a 2 ms timer interrupt process.

FIG. 45 is a flowchart showing a payout state recovery process.

FIG. 46 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 47 is an explanatory diagram showing a configuration example of a reception command buffer.

FIG. 48 is a flowchart showing an example of command reception processing of the payout control CPU.

FIG. 49 is an explanatory diagram showing a formation example of a switch timer in the RAM of the payout control means.

FIG. 50 is a flowchart showing an example of switch processing.

FIG. 51 is a flowchart showing an example of payout stop state setting processing.

FIG. 52 is a flowchart showing an example of command analysis execution processing.

FIG. 53 is a flowchart showing an example of prepaid card unit control processing.

FIG. 54 is a flowchart showing an example of ball lending control processing.

FIG. 55 is a flowchart showing an example of ball lending control processing.

FIG. 56 is a flowchart showing an example of prize ball control processing.

FIG. 57 is a flowchart showing an example of prize ball control processing.

FIG. 58 is a flowchart showing another example of non-maskable interrupt processing (power supply stop processing).

FIG. 59 is a flowchart showing another example of the non-maskable interrupt process (power supply stop process).

FIG. 60 is a flowchart showing another example of unmaskable interrupt processing (power supply stop processing).

FIG. 61 is a conceptual diagram showing an outline of the present invention.

FIG. 62 is a block diagram showing a part of another configuration example of the game control means.

FIG. 63 is a flowchart showing another example of the 2 ms timer interrupt process executed by the CPU on the main board.

FIG. 64 is a timing chart for explaining the operation of the software timer and the watchdog timer circuit.

FIG. 65 is a flowchart showing another example of the power supply stoppage process in the game control means.

FIG. 66 is a flowchart showing another example of the power supply stop processing in the payout control means.

[Explanation of symbols]

1 Pachinko machine 31 Game control board (main board) 37 Discharge control board 56 CPU 65 System reset circuit (power supply monitoring means) 97 Ball dispensing device 301A prize ball count switch 301B ball lending count switch 310 Sorting solenoid 311 Sorting member 371 CPU for payout control 910 Power board 902 Power supply monitoring IC (power supply monitoring means) 914 power switch 921 clear switch 923,924 capacitors

Claims (11)

[Claims] 1. A game machine which can play a predetermined game using a game medium, and which pays out the game medium based on satisfaction of a predetermined payout condition. Payout means, game control means for controlling the progress of the game, payout control means for controlling the payout means based on a command from the game control means, and a predetermined period even if the power supply to the gaming machine is stopped Is a variable data storage means capable of holding the stored contents and the state of a predetermined power source used in the gaming machine, and detects a detection signal when the detection condition related to the stop of the power supply to the gaming machine is satisfied. Power supply monitoring means for outputting, and the game control means and the payout control means, respectively, with data necessary to restore the control state according to the detection signal from the power supply monitoring means. The data including the contents of the register is stored in the fluctuation data storage means on the condition that the power supply is stopped and the predetermined restoration condition is satisfied. An initialization process for executing a restoration process for restoring the control state to the state before the power supply is stopped based on the stored contents, and for initializing the control state when the predetermined restoration condition is not satisfied. It is possible to execute, the game control means, in the recovery processing, after transmitting a recovery command indicating the recovery of the control state to the payout control means, of the timer interrupt processing that is regularly activated. The timer interrupt setting process for setting is performed, the register return process for restoring the register contents is performed, and the control is restarted. Gaming machine, characterized in that to resume control of the reception of the command to condition the performing timer interruption setting processing and the register restoration process. 2. The payout control means prohibits the payout of the game medium regardless of whether the power supply is started and the recovery process is executed or the power supply is started and the initialization process is executed. Set the flag that indicates,
The game machine according to claim 1, wherein the flag is reset on the condition that a predetermined command is received from the game control means. 3. The game control means can transmit a payout amount designation command indicating a payout game medium payout amount when a predetermined prize game medium payout condition is satisfied, and transmits the payout amount designation command as a recovery command. The gaming machine according to claim 1 or 2. 4. The game control means and the payout control means restore the interrupt state flag indicating whether the state before the power supply was stopped was the interrupt permitted state or the prohibited state in the restoration process. The gaming machine according to any one of claims 1 to 3. 5. The game control means and the payout control means all satisfy a plurality of restoration conditions for deciding whether or not to restore the control state before the power supply is stopped when the power supply is restored. 5. The recovery process is executed when the above condition is satisfied, and the initialization process is executed when at least one condition among the plurality of recovery conditions is not satisfied.
A gaming machine according to any one of the above. 6. The payout prohibition state in which the game control means instructs to prohibit the payout of the game medium based on the establishment of a predetermined payout prohibition condition after the power supply is started and the initialization process or the recovery process is executed. The gaming machine according to any one of claims 1 to 5, which transmits a designated command, and transmits a payout permission state designation command which permits payout of a game medium based on the cancellation of the payout prohibition condition. . 7. The game control means sends a payout prohibition state designation command when any one of the plurality of payout prohibition conditions is satisfied, the payout prohibition condition is canceled, and any payout prohibition condition is satisfied. A request to send a common payout permission state designation command indicating that the payout of the game medium is permitted regardless of which of the plurality of payout prohibition conditions has been satisfied A gaming machine according to Item 6. 8. A storage state detecting means for detecting whether or not a predetermined amount or more of the game medium is stored in a storage portion in which the paid-out game medium is stored, and the payout prohibition condition is the storage. The gaming machine according to claim 6 or 7, including a condition that is satisfied when a predetermined amount or more of the game medium is stored in the storage section by the state detection means. 9. A game medium out detection unit for detecting whether or not a predetermined amount or more of the game medium supplied to the payout unit is secured, and the payout prohibition condition is the game medium out by the game medium out detection unit. The gaming machine according to any one of claims 6 to 8, including a condition that is satisfied when it is detected that a predetermined amount or more is not secured. 10. The gaming machine according to claim 6, wherein the game control means uses a payout prohibition state designation command or a payout permission state designation command as a recovery command. 11. The game control means performs processing for saving program address data related to the address of the control program in the variation data storage means as data necessary for restoring the control state in the power supply stop processing. ,
The game machine according to any one of claims 1 to 10, wherein in the restoration process, control is restarted based on the program address data stored in the fluctuation data storage means.