JP2003169905A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform a process for recovering a game state. <P>SOLUTION: In the game state-recovering process, a CPU performs the returning process of a stack pointer first. Then, if the state is not a put-out prohibited state, a command-transmitting table regarding a put-out available state designating command is set, and the command setting process is called. Also, a command-transmitting table regarding a display-controlling command for recovering the display state of a special pattern in a variably displaying device when a power supply is stopped is set, and the command setting process is called. Then, a process for setting retracting values for various kinds of registers and so forth is performed for various kinds of registers, and then, a RET command is performed. Since the process to transmit the command is performed after the stack point has been returned, the process to transmit the command can be performed using a sub-routine, and the process for recovering the game state can be efficiently performed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game.

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Furthermore, a variable display unit whose display state can be changed is provided,
There is one configured to give a predetermined game value to the player when the display result of the variable display section becomes a predetermined specific display mode.

The gaming value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who easily wins a hit ball, or is advantageous for the player. To generate the right to pay for the prize, and to make it easier for the conditions for paying out prize balls to be met.

In the pachinko gaming machine, it is usually called a "big hit" that the display result of the variable display section for displaying the special symbol is a combination of predetermined specific display modes.
When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which a hit ball is easy to win is entered. Then, in each opening period, when a predetermined number (for example, 10) of winning holes are won, the winning holes are closed. The number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied when the special winning opening is closed, the jackpot gaming state ends.

Further, in the variable display device, the symbols other than the symbol which is the final stop symbol (for example, the middle symbol of the left and right middle symbols) continue for a predetermined time, and stop and swing in a state in which it matches the specific display mode. , Scaled or deformed state, or multiple symbols fluctuate synchronously in the same symbol, or the position of the displayed symbol is swapped, the possibility of a big hit before the final result is displayed The effect that is performed in a state in which the above is continued (hereinafter, these states are referred to as the reach state) is referred to as the reach effect. A variable display including a reach effect is called a reach variable display. By changing the variation pattern in the reach state from the variation pattern in the normal state, the interest of the game is enhanced. When the display result of the symbols variably displayed on the variably display device does not satisfy the condition for reaching the reach state, the result is “out”, and the variably display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game on the gaming machine is controlled by the game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display unit are controlled by a video display processor (VDP) that generates image data according to an instruction from the microcomputer and transfers the image data to the variable display unit side. The program capacity required by the microcomputer is large.

Therefore, it is not possible to control the identification information and the like displayed on the variable display portion by the microcomputer of the game control means having a limited memory capacity for storing the program, which is different from the microcomputer of the game control means. A pattern control board on which display control means such as a microcomputer for display control is mounted is installed. The game control means for controlling the progress of the game needs to send a command for display control to the display control means.

When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game proceeds to the game mounted on the main board. Since it is controlled by the control means, the number of prize balls based on the winning is determined by the game control means and transmitted to the payout control board. On the other hand, rental of game media is
Since it has nothing to do with the progress of the game, it is generally controlled by the payout control means without passing through the game control means.

As described above, the game machine is equipped with various control means in addition to the game control means. Then, the game control means for controlling the progress of the game sends each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the game control means and other control means may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

[0010]

As described above, the game machine is equipped with various electric component control means including the game control means. Generally, each electric component control means is configured to include a microcomputer. Such electric component control means generally performs an initialization process when the power supply voltage rises, and starts control from an initial state. Then, an unexpected power failure such as a power failure occurs, and then the power returns to the initial state when the power is restored, which may cause a problem that the gaming value or the like obtained by the player disappears. In order to prevent such a problem from occurring, the game control is interrupted in response to a predetermined signal that accompanies the decrease in the power supply voltage value, and the control state at that time is stopped by the power supply to the game machine. In particular, the power may be stored in the storage means that is backed up (backup storage means) and controlled so as to wait until the power supply is completely stopped. In such a gaming machine, if the power supply is restarted while the game state is stored in the storage means, the game is restarted based on the stored control state, which is disadvantageous to the player. Is prevented.

However, in the case where the game is restarted based on the control state saved as described above,
The game control means needs to execute various processes such as transmitting a command for restoring the control state at the time of stopping the power supply to other electric component control means. As described above, since the game control means has a limited memory capacity for storing the program, it is preferable to minimize the capacity of the program used for executing the processing for restoring the game state. To that end, it is desired to be able to more efficiently execute the processing for restoring the gaming state.

Therefore, an object of the present invention is to provide a gaming machine capable of efficiently executing a process for restoring a gaming state.

[0013]

A gaming machine according to the present invention comprises:
A game machine that allows a player to play a predetermined game, and electric parts provided on the game machine (for example, ball payout device 97, variable display device 9, and electric part 802 shown in FIG. 65).
For controlling the electric component (for example, payout control means including payout control CPU 371, display control CPU
Display control means including 101, CPU 351 for lamp control
To the gaming machine, a lamp control means including the electric component control means 801 shown in FIG. 65), a game control means for controlling the progress of the game (for example, a game control means including the CPU 56, a game control means 561 shown in FIG. 65). Fluctuation data storage means capable of holding the stored contents for a predetermined period even when the power supply of the device is stopped (for example, the RAM 55 of the main board 31 with power backup and the RAM of the payout control board 37 with power backup, FIG. The fluctuation data storage means 551) shown in FIG. 65 and a state of a predetermined power source used in the gaming machine are monitored, and a detection condition (for example, a voltage of VSL (+ 30V) which is a monitoring voltage) related to stop of power supply to the gaming machine is monitored. Value is +
Power supply monitoring means (for example, power supply monitoring IC 9) that outputs a detection signal (for example, a power supply cutoff signal, the detection signal shown in FIG. 65) when a condition that is satisfied when the voltage drops to 22V is satisfied.
02, and power supply monitoring means 910a) shown in FIG.
The game control means executes a command transmission program (for example, a program for executing command set processing) for transmitting a command to the electric component control means, and transmits a command according to the progress of the game (for example, command transmission means 65 has a game control means including the CPU 56 and a command transmission means 562 shown in FIG. 65, and is used for data necessary for restoring the control state according to the detection signal from the power supply monitoring means (for example, the CPU 56 and the payout control CPU 371). Power supply stop processing for storing the data of the register to be stored in the fluctuation data storage means (for example, FIGS. 23 to 25).
And the power supply stoppage process of step S450 shown in FIG. 65) and a restoration process for restoring the control state to the state before the power supply was stopped based on the stored contents stored in the fluctuation data storage means ( For example, the game state restoration process shown in FIG. 21 and the restoration process of step S100 shown in FIG. 65) are executed, and the command transmission means sends a command called by a subroutine (for example, a subroutine for executing the command set process) call in the restoration process. A process of transmitting a command for restoring the control state before the power supply is stopped to the electric component control means by executing the program (for example, step S82 to step S85, the command transmission process of step S562a shown in FIG. 65). And the variable data storage means has a subroutine call (for example, Step S84) stack area for saving the program address data associated with the address of the control program which has been executed in accordance with (e.g., Fig. 6
5, the game control means stores the data to be read next among the addresses saved in the stack area by the address indicated by the stack pointer (for example, the stack pointer 563 shown in FIG. 65). The specified address is specified, and the stack address data related to the address indicated by the stack pointer is saved in the fluctuation data storage means in the power supply stop process (for example, step S458,
Perform the evacuation process of step S450a shown in FIG.
In the restoration process, before the command transmitting means first transmits a command (for example, step S82 to step S85).
Before), the stack pointer is set by the stack address data (for example, stack address data 552a shown in FIG. 65) saved in the fluctuation data storage means in the power supply stop process (for example, step S81, FIG. 65).
The stack pointer setting process in step S100a shown in FIG.

The game control means, the power supply is restored and a predetermined restoration condition (for example, the conditions of step S7 to step S9)
If the predetermined recovery condition is not satisfied, the recovery process is executed when the condition is satisfied, and the initialization process is performed to initialize the storage content held in the variable data storage means (for example, step S11 to step S15). May be configured to perform.

The electric component control means includes a payout control means for controlling the payout means for paying out the game medium, and the payout control means prohibits the payout of the game medium when power supply is started. (For example, step S732), the payout prohibition state may be canceled (for example, step S753e) in response to the reception of a predetermined command (for example, a payable state designation command) from the game control means.

A command sending means specifies a payout state designating command (for example, a payable state designating command) for designating whether or not to permit the payout of the game medium in the recovery process.
To the payout control means (for example, step S8
3, step S84), the payout control means may be configured to cancel the payout prohibition state when the payout state designating command permits the payout of the game medium.

With respect to the start of the power supply to the gaming machine, the time when the game control means becomes the state in which the control related to the game can be performed is more than the time when the electric part control means becomes the state in which the electric parts can be controlled. It may be configured to include a starting order regulation unit (for example, a delay circuit 960) that regulates the activation timing to be late.

In the variable display device, the electric component control means controls the variable display device (for example, the variable display device 9) that variably displays the identification information (for example, the display control device including the display control CPU 101). Starting prize winning memory number display control means (for example, a display including the display control CPU 101) for controlling the starting winning prize memory number display means (for example, the starting memory indicator 18) that displays the starting winning prize memory number that indicates the number of times of variable display of the identification information. Control means, CPU for lamp control
The lamp control means including 351), and the command transmission means, in the restoration process, a start winning prize memory number designating command (for example, starting winning prize memory number lamp designating command) for designating the starting prize winning memory number. It may be configured to transmit to the display control means.

The electric component control means includes a display control means (for example, a display control means including the display control CPU 101) for controlling a variable display device (for example, the variable display device 9) that variably displays the identification information, and the gaming machine is , It is possible to control to a specific game state (eg, big hit game state) advantageous to the player on condition that the display result of the identification information displayed on the variable display device becomes a particular display form (eg, big hit display state). Together with the special game, the identification information can be controlled to a special game state (for example, a probability change state) that tends to be in a specific display mode, and the command transmission means, in the restoration process, specifies whether or not the special game state. The state designation command (for example, the probability variation state designation command) may be configured to be transmitted to the display control means.

The electric component control means includes a display control means for controlling the variable display device that variably displays the identification information, and the command transmission means causes the variable display device at a time related to the stop of the power supply in the restoration process. The identification information designating command for designating the display result of the identification information to be displayed in (for example, each designating command designating each of the left, middle, and right symbols) may be transmitted to the display control means.

The game control means performs a predetermined control according to a timer interrupt generated every predetermined period, and in the restoration process, after transmitting a command to the electric component control means by the command transmitting means, the timer interrupt is executed. The setting may be performed (for example, step S87) so as to generate the interruption every predetermined period (for example, every 2 ms).

The game control means may be configured to execute a processing (for example, step S498) of prohibiting access to the fluctuation data storage means in the power supply stop processing.

The game control means is provided with an output port for outputting an output signal (for example, the output port shown in FIGS. 16 and 17), and the game control means performs output power stop processing to the output port. May be configured to perform a process for clearing the output signal by outputting a clear signal (for example, step S459 to step S465).

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of a pachinko gaming machine as seen from the front, and FIG. 2 is a front view showing the front surface of the gaming board. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine and can be applied to, for example, an image-type gaming machine or a slot machine.

The pachinko gaming machine 1 is composed of an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a frame-shaped glass door frame 2 that is provided in the game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanical parts and the like are attached, and various parts attached to them (excluding a game board described later). It is a structure including and.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply plate (upper plate) 3. Below the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball feed tray 3 and a hitting ball operation handle (operation knob) 5 for firing the hit ball. Glass door frame 2
A game board 6 is detachably attached to the back surface of the. The game board 6 is a structure including a plate-shaped body that constitutes the game board 6 and various parts attached to the plate-shaped body. A game area 7 is formed on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display device (special symbol display device) 9 including a plurality of variable display portions for variably displaying symbols as identification information is provided. The variable display device 9 includes, for example, “left”, “middle”,
There are three "right" variable display parts (symbol display areas).
A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the starting winning opening 14 is guided to the rear surface of the game board 6 and detected by the starting opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the starting winning opening 14. Variable winning ball device 1
The solenoid 5 is opened by the solenoid 16.

At the bottom of the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). Opening plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 (V winning area)
The entered winning balls are detected by the V winning switch 22, and the winning balls from the opening / closing plate 20 are detected by the count switch 23. On the back surface of the game board 6, a solenoid 21A for switching the route inside the special winning opening is also provided. In addition, in the lower part of the variable display device 9, a special symbol starting memory display (hereinafter, referred to as starting memory display) 18 by four LEDs for displaying the number of effective winning balls that have entered the starting winning opening 14, that is, the number of starting memories. Is provided. Each time there is an effective start prize, the start memory indicator 18 increases the number of LEDs to be turned on by one.
Then, each time the variable display of the variable display device 9 is started,
Decrease the number of lit LEDs by 1.

When the game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the display of the normal symbol display 10 is started. In this embodiment, the left and right lamps (the pattern can be visually recognized when turned on) are alternately turned on to perform variable display. For example, when the variable display ends, the right lamp is turned on. And when the stop symbol on the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. Normal symbol display 10
The number of winning balls that entered the gate 32 is displayed near 4
A normal symbol start-up memory display 41 having a display section with two LEDs is provided. Every time there is a prize in the gate 32, the normal symbol starting memory display 41 turns on the LED that is turned on by 1
increase. Then, each time the variable display of the normal symbol display device 10 is started, the number of LEDs to be turned on is reduced by 1.

The game board 6 has a plurality of winning openings 29, 30,
33, 39 are provided, and the winning openings 29, 30, 3 for gaming balls
The prizes for 3 are prize winning opening switches 29a, 30 respectively.
a, 33a, 39a. Each prize hole 2
Reference numerals 9, 30, 33, and 39 form a winning area provided on the game board 6 as an area for accepting a game medium and allowing a prize. It should be noted that the starting winning opening 14 that accepts the game medium and allows the winning, and the special winning opening also constitute the winning area. Decorative lamps 25 that are displayed blinking during the game are provided around the left and right sides of the game area 7, and there is an outlet 26 at the bottom for absorbing hit balls that have not been won. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b and a right frame lamp 28
c is provided. Further, a decorative LED is installed around each structure (a special winning opening, etc.) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of the decorative light-emitting body provided in the game machine.

In this example, the prize ball lamp 51 that lights up when there is a remaining number of prize balls near the left frame lamp 28b.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the top frame lamp 28a.
As described above, the pachinko gaming machine 1 of this example is provided with lamps and LEDs as light-emitting bodies at various places. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming machine 1,
A card unit that allows you to lend a ball by inserting a prepaid card (prepaid card unit)
50 is also shown.

The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and a connecting stand direction indicator indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to. 153, a card insertion indicator lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The game ball shot from the hitting ball launching device enters the game area 7 through the hit ball rail, and then descends from the game area 7. When the ball hits the starting winning opening 14 and is detected by the starting opening switch 14a, if the variable display of the symbol can be started, the variable display device 9 starts the variable display (variation) of the special symbol. If it is not in a state where variable display of symbols can be started, the number of starting memories is increased by 1.

The variable display of the special symbol on the variable display device 9 is stopped when a certain time has elapsed. If the special symbol combination at the time of stop is a big hit symbol (specific display result), the big hit game state is entered. That is, the opening / closing plate 2
0 is released until a fixed time elapses or a predetermined number (for example, 10) of hit balls are won. Then, when the hit ball enters the V winning area while the opening / closing plate 20 is open and is detected by the V winning switch 22, the continuation right is generated and the opening / closing plate 20
Is released again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

A combination of special symbols in the variable display device 9 at the time of stop is a big hit symbol with probability variation (probability variation symbol)
In the case of the combination of, the probability of the next big hit is high. That is, the state of probability change is more advantageous for the player.

When the hit ball wins the gate 32, the normal symbol display 10 is in a state in which the normal symbol is variably displayed. Further, when the stop symbol in the normal symbol display device 10 is a predetermined symbol (hit symbol), the variable winning ball device 15
Remains open for a predetermined time. Furthermore, in the probable state,
The probability that the stop symbol in the normal symbol display 10 will be a winning symbol is increased, and the opening time and the number of times of opening the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probability variation symbol, and the like, and from a disadvantageous state for the player. Change to an advantageous state. In addition, increasing the number of times of opening is a concept including changing from a closed state to an open state.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a rear view of the gaming machine viewed from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

As shown in FIG. 3, on the back side of the game machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board (mainly a game control microcomputer, etc.) is mounted. Substrate) 31 is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decorations L provided on the game board 6
ED, starting memory indicator 18 and normal symbol starting memory indicator 41, decoration lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 28c, prize ball lamp 51 and ball out lamp provided on the frame side. There is also provided a lamp control board 35 on which a lamp control means for controlling lighting of 52 is mounted, and a sound control board 70 on which a sound control means for controlling sound generation from the speaker 27 is mounted. In addition, DC3
A power supply board 910 and a firing control board 91 on which a power supply circuit for creating 0V, DC21V, DC12V and DC5V is mounted are provided.

On the back side of the game machine, a terminal board 160 having terminals for outputting various information to the outside of the game machine is installed above. Terminal board 160
At least, the terminal for ball breakage for introducing the output of the ball breakage detection switch and outputting it externally, the terminal for prize balls for externally outputting the prize ball number signal and the external output for the ball lending number signal A ball lending terminal is provided. Further, in the vicinity of the center, an information terminal board (information output board) 34 provided with each terminal for outputting various information from the main board 31 to the outside of the gaming machine is installed.

The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. 4, the curve gutter 1
After 86, the ball payout device covered with the prize ball case 40A is reached. At the upper part of the ball payout device, a ball break switch 187 is provided as a game medium cut detection means. When the out-of-ball switch 187 detects out-of-ball, the payout operation of the ball payout device is stopped. The out-of-ball switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage, but the out-of-ball detection switch 167 that detects a shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail 39 (the storage tank 38). (Provided near). When the out-of-ball detection switch 167 detects a shortage of game balls, the supply mechanism provided on the game machine installation island supplies game balls to the game machine.

A large number of game balls as prizes based on prizes and game balls based on ball lending requests are paid out, and the hitting ball supply plate 3 is filled up. Finally, after the game balls reach the contact port 45, further game balls are provided. When paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In that state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the launching device is also stopped.

As shown in FIG. 4, a ball passage 191 extending from the curve gutter 186 to the discharge port 192 at the lower portion of the game machine is formed on the side of the ball payout device. Ball passage 19
1 is provided with a ball removing lever 193, and when the ball removing lever 193 is operated by a game store clerk or the like, a game ball passage from the guide rail 39 to the ball removing passage 191 is formed and stored in the storage tank 38. The played game ball is discharged from the discharge port 192 to the outside of the game machine.

FIG. 5 is an exploded perspective view showing a structural example of the ball payout device 97. In this example, a ball payout device 97 is formed inside the three cases 140, 141, 142 as the prize ball case 40A. Holes 170, 171 communicating with the ball passage at the bottom of the ball break switch 187 are provided in the upper part of the cases 140, 141, and the game ball has holes 170, 171.
It flows into the ball payout device 97 from 171.

The ball payout device 97 includes a payout motor (eg, stepping motor) 289 serving as a drive source. The rotational force of the dispensing motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the dispensing motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls flowing in from the holes 170 and 171 are dropped one by one into the ball passages 293a and 293b below the sprocket 292 by the recesses of the sprocket 292.

Sphere passage (an example of a game medium payout passage) 293
The a and 293b are provided with a distribution member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and at the time of paying out a prize ball, one of the downflow paths (ball path 2) in the ball paths 293a and 293b.
93a: An example of a prize game medium passage) falls down so that a game ball flows down, and at the time of lending a ball, a game ball flows down the other downflow path (ball passage 293b: an example of a rental game medium path) of the ball passages 293a and 293b. To fall. The payout motor 289 and the solenoid 310 are controlled by the payout control CPU mounted on the payout control board 37. In addition, the payout control CPU controls the payout motor 289 and the solenoid 310 in accordance with a command from the game control CPU mounted on the main board 31.

A prize ball sensor (prize ball count switch) 301A for detecting the game balls paid out by the ball payout device is provided below the downflow path selected at the time of paying out prize balls.
A ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by a ball payout device is provided below the flow-down path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals. In addition, prize ball count switch 301
The detection signal A is also input to the CPU of the main board 31.
Power supply board 91 for ball lending count switch 301B
The power supply from 0 is performed through the payout control board 37. Although power is supplied from the power supply board 910 to the prize ball count switch 301A through the main board 31, it may be supplied through the payout control board 37. In addition, a plurality of prize ball sensors and ball lending sensors may be provided respectively. Moreover, as the prize ball sensor, one for the main board 31 and one for the payout control board 37 may be provided separately.

Incidentally, on the peripheral portion of the gear 291, there is formed a protrusion forming a payout motor position sensor. The protrusion allows the light from the light emitting body (not shown) to pass through or shield the light receiving unit (not shown) of the payout motor position sensor in accordance with the rotation of the gear 291 or the rotation of the payout motor 289. To do. The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

The ball payout device may be configured to perform both prize ball payout and ball lending, but a ball payout device for paying a prize ball and a ball payout device for lending a ball are separately provided. It may be. Further, for example, the rotation direction of the sprocket may be changed to divide the prize ball payout and the ball lending, and the ball payout device having any structure other than the ball payout device 97 exemplified in the present embodiment. The present invention can also be applied by using.

FIG. 6 is a front view showing an exposed portion of the power supply substrate 910 installed on the mechanism plate constituting the game frame. As shown in FIG. 6, most of the power supply board 910 overlaps with the main board 31, but there is an exposed portion that is visible from the outside without overlapping with the main board 31. In this exposed portion, a power switch 914 for executing or cutting off power supply to the gaming machine 1 and each board (main board 31
And a payout control board 37) included in the storage content holding means (for example, a backup RAM capable of holding the content even when power supply is stopped) as a clear switch 92 as an operation means for clearing the backup data.
1 and are provided. In this way, the power switch 91
4 and the clear switch 921 are arranged close to each other, the operation of the clear switch 921 becomes easy.

FIG. 7 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 7 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the firing control board 91, and the symbol control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
Control circuit 53, a gate switch 32a, a starting opening switch 14a, a V winning switch 22, a count switch 23, winning opening switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for giving the signal from 21 to the basic circuit 53
8 and a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening / closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching the path in the special winning opening according to a command from the basic circuit 53 are mounted.

Although not shown in FIG. 7, the count switch short circuit signal is also transmitted to the basic circuit 53 through the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Switches such as the prize ball count switch 301A may be called a sensor. That is, a game medium detecting means capable of detecting a game ball (a game ball detecting means in this example)
If so, the name does not matter. In particular, each of the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a for performing the winning detection is also a winning detection means. The winning detection means may be one that collectively detects each of the gaming balls that have been won separately in a plurality of winning openings. Further, even if a passing gate such as the gate switch 32a is used for paying out prize balls, entering a game ball into the passing gate is a prize, and a switch provided in the passing gate (for example, The gate switch 32a) serves as a winning detection means.

Further, according to the data given from the basic circuit 53, the big hit information indicating the occurrence of the big hit, the effective starting information indicating the number of starting winning balls used to start the variable display of the symbols on the variable display device 9, and the probability variation. An information output circuit 64 that outputs an information output signal such as probability variation information indicating that it has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 is a ROM 54 for storing a game control program and the like, and R as a storage means (means for storing variation data) used as a work memory.
AM55, CPU5 which controls according to the program
6 and I / O port section 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. Note that the 1-chip microcomputer only needs to have at least the RAM 55 built therein, and
The OM 54 and the I / O port unit 57 may be external or built-in.

Further, a part or all of the RAM (which may be a CPU built-in RAM) 55 is a backup RAM backed up by a backup power source created in the power source board 910. In other words, even if the power supply to the gaming machine is stopped, the RAM remains for a predetermined period.
The contents of part or all of 55 are saved.

In this embodiment, the power supply board 910 also inputs to the main board 31 a reset signal whose low level indicates a reset state, a low active return signal, and a low active power off signal. The reset signal and the return signal are input to the AND circuit 161, and the AND circuit 1
The output of 61 is input to the reset terminal of the CPU 56.
Further, the power-off signal is a non-maskable interrupt (N
MI) terminal.

A hitting ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on a launching control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 controls the ball to be fired at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 includes the starting memory indicator 18, the normal symbol starting memory indicator 41 and the decorative lamp 25 provided on the game board. In addition to performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the out-of-ball lamp 52 provided on the frame side is performed. Further, the display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the ordinary symbol is the symbol control board 80.
The display control means mounted on the.

FIG. 8 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full tank switch 48 is transmitted via the relay substrate 71 to the main substrate 3.
1 is input to the I / O port unit 57. The detection signal from the ball break switch 187 is also input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates the full state, a payout control command instructing that the payout should be stopped is sent. When receiving the payout control command instructing that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid award ball.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port (output port 0) 570 outputs a 1-bit INT signal. The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is
Input a payout control command through the O port 372a,
The ball payout device 97 is driven in accordance with the payout control command to perform prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a built-in RAM.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A lent ball number signal indicating the number of lent balls is output to the terminal board 160 via 72c. Furthermore, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signals from the ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually loaned ball. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the distribution solenoid 3 is used.
The drive signal to 10 is transmitted to the distribution solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a usable indicator lamp 151, a connecting stand direction indicator 153, a card insertion indicator lamp 154 and a card insertion slot 155 (see FIG. 1). To the balance display board 74, a frequency display LED, a ball lending switch and a return switch, which are provided in the vicinity of the hitting ball supply tray 3, are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. As described above, the balance display board 74 and the card unit 50 are connected to each other via the payout control board 37 without being directly connected. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BR).
The Q signal), the ball lending completion signal (EXS signal) and the pachinko machine operation signal (PRDY signal) are exchanged via the input port 372b and the output port 372e. In addition, between the card unit 50 and the payout control board 37,
An interface board (not shown) is interposed, and signals such as connection signals (VL signals) are exchanged via the interface board.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

Then, the payout control C of the payout control board 37 is used.
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. After that, if the BRDY signal from the card unit 50 is not on,
The prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a reset signal, a return signal and a power-off signal are also input from the power supply board 910 to the payout control board 37. The reset signal and the return signal are input to the AND circuit 385, and the output of the AND circuit 385 is input to the reset terminal of the payout control CPU 371. Further, the power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. further,
RAM existing in the payout control board 37 (RAM with built-in CPU
May be ) Is at least partially
It is backed up by the backup power supply created at 0. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is saved for a predetermined period.

In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. May be. Further, the present invention can be applied even in the case where a game ball corresponding to the amount of coins is lent out according to the coin insertion.

FIG. 9 shows the circuit configuration in the symbol control board 80, an LCD (liquid crystal display device) 82 which is an example of realizing the variable display device 9, an ordinary symbol display device 10, an output port of the main substrate 31 (port 0). , 2) 570 and 572 and output buffer circuits 620 and 62A.
8-bit data is output from the output port (output port 2) 572, and a 1-bit strobe signal (INT signal) is output from the output port 570.

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and when the INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, the display control command is received via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. If the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls the display of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP (video display processor) 103. The VDP 103 is the character RO
Read the required data from M86. VDP103 is
Image data to be displayed on the LCD 82 is generated according to the input data, and the R, G, B signals and the synchronization signal are set to L.
Output to CD82.

FIG. 9 also shows a reset circuit 83 for resetting the VDP 103, an oscillating circuit 85 for giving an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image including characters, figures, symbols, or the like displayed on the LCD 82.

The input buffer circuits 105A and 105B are
The signal can be passed only in the direction from the main board 31 to the symbol control board 80. Therefore, the pattern control board 8
There is no room for signals to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute an irreversible information input means together with the input ports. Even if the circuit in the symbol control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

Noise filter 10 for cutting off high frequency signals
For example, a 3-terminal capacitor or a ferrite bead is used as 7, but the presence of the noise filter 107 eliminates the influence of noise on the display control command between the substrates. A noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 10 is a block diagram showing signal transmitting / receiving portions of the main board 31 and the lamp control board 35. In this embodiment, the point frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c provided on the outside of the game area 7 and the decoration lamp 25 provided on the game board are turned on / off, and the prize ball lamp is provided. A lamp control command indicating turning on / off of 51 and the out-of-bulb lamp 52 is output from the main board 31 to the lamp control board 35. Further, a lamp control command indicating the number of lighting of the starting memory display 18 and the normal symbol starting memory display 41 is also output from the main board 31 to the lamp control board 35.

As shown in FIG. 10, the lamp control command relating to the lamp control is the output port (output port 0, 3) 570 of the I / O port unit 57 in the basic circuit 53.
It is output from 573. Output port (output port 3) 5
73 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. Lamp control board 35
, The control command from the main board 31 is sent to the lamp control CP via the input buffer circuits 355A and 355B.
Input to U351. The lamp control CPU 351
Does not include an I / O port, the input buffer circuits 355A and 355B and the lamp control CPU 351.
An I / O port is provided between and.

In the lamp control board 35, the lamp control CPU 351 follows the lighting / extinguishing patterns of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25 defined according to each control command. A lighting / extinguishing signal is output to the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25. The lighting / extinguishing signal is output to the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25. In addition, the lighting / extinguishing pattern is the CP for lamp control
It is stored in the built-in ROM of U351 or the external ROM.

On the main board 31, the CPU 56 controls the RA
When there is an unpaid remaining number of award balls in the stored contents of M55, a control command for instructing lighting of the award ball lamp 51 is output, and the out-of-ball switch 187 (which is installed upstream of the award ball passage on the back surface of the game board). When the game ball is not detected (see FIG. 3), a control command for instructing lighting of the out-of-ball lamp 52 is output. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. Lamp control CPU
351 turns on / off the prize ball lamp 51 and the out-of-ball lamp 52 according to these control commands. In addition,
The lighting / extinguishing pattern is stored in the built-in ROM or the external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a lighting / extinguishing signal to the starting memory indicator 18 and the normal symbol starting memory indicator 41 in response to the control command.

The input buffer circuits 355A and 355B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 35
5A and 355B are the main board 31 and the lamp control board 35.
The signal can only be passed in the direction towards. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if the circuit in the lamp control board 35 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

On the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside the 70 and 573. The buffer circuits 620 and 63A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. With such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the lamp control board 35 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 11 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31,
Design control board 80, sound control board 70, lamp control board 3
5 and the payout control board 37 and other electric part control boards are installed independently of each other, and each electric part control board in the gaming machine and the voltage used by the mechanical parts are generated. In this example, AC2
4V, VSL (DC + 30V), DC + 21V, DC + 1
Generates 2V and DC + 5V. Further, the backup power source, that is, the capacitor 916 serving as a memory holding unit,
It is charged from DC + 5V, that is, from the line of the power supply that drives the ICs on each substrate. Note that VSL is a rectifier circuit 912.
At, the rectifying element rectifies and boosts AC 24V. VSL serves as a solenoid drive power source.

The power supply board 910 is provided with a power supply switch 914 for executing or cutting off power supply to each electric part control board and mechanical parts in the game machine. The transformer 911 converts the AC voltage from the AC power supply into 24V. The AC 24V voltage is output to the connector 915.
The rectifier circuit 912 also generates a DC voltage of + 30V from AC 24V and outputs the DC voltage to the DC-DC converter 913 and the connector 915. DC-DC converter 913
Has one or more converter ICs 920 (only one is shown in FIG. 11) and is +21 based on VSL.
V, + 12V and + 5V are generated and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 920. Therefore,
When the power supply to the game machine from the outside is stopped,
DC voltages such as + 30V, + 12V, and + 5V drop relatively slowly. Also, on the input side of the connector 915,
A relatively large-capacity capacitor 924 is connected. Therefore, the + 30V DC voltage output to the connector 915 drops more gently than other DC voltages. As a result, the capacitors 923 and 924 serve as an auxiliary drive power source, which will be described later. The connector 915 is connected to, for example, a relay board, and the relay board supplies electric power of a required voltage to each electric component control board and mechanical components.

However, the power supply board 910 may be provided with each connector reaching each electric component control board, and each voltage may be supplied from the power supply board 910 to each board without the relay board. Further, although one connector 915 is representatively shown in FIG. 11, the connector is provided for each electric component control board.

+ 5V from the DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the game machine is stopped (RAM whose power is backed up, that is, backup storage means that can be in a storage content holding state even when the power supply is stopped).
It becomes a backup power supply that supplies electric power so that the memory state can be maintained. In addition, a diode 9 for preventing backflow is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, the backup + 5V is applied to the main board 31 and the payout control board 3
7 is supplied.

A battery that can be charged from a + 5V power source may be used as the backup power source. When a battery is used, a rechargeable battery is used which loses its capacity when the power is not supplied from the + 5V power source for a predetermined time. Further, instead of the capacitors 923 and 924 described above, a battery that can be charged from a + 30V power source may be used.
When a battery is used instead of the capacitor 923, a rechargeable battery that can supply power to the prize ball count switch 301A and the ball lending count switch 301B for a period equal to or longer than a payout confirmation period described later is used. Also, the capacitor 924
When a battery is used instead of the rechargeable battery, a rechargeable battery that can supply power to the distribution solenoid 310 for a period equal to or longer than a payout confirmation period described later is used. The above-mentioned battery does not have to have a charging function and, for example, a battery such as a nicad battery, an alkaline battery, a manganese battery or the like is used.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, it is determined that the power supply is stopped, and a power-off signal is output. Therefore, it is possible to start the power supply stop process when the prize ball count switch 301A is effectively detecting the prize ball. Therefore, the prize ball can be detected for a while after the power supply stop processing is started without depending on the auxiliary drive power supply, and the capacity of the capacitor 923 as the auxiliary drive power supply can be small. The power supply voltage to be monitored is the power supply voltage of the circuit element mounted on each electric component control board (in this example, +
It is preferable that the voltage is higher than 5 V). In this example, VSL, which is the voltage immediately after conversion from AC to DC, is used. The power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of the power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Further, VSL (+ 30V) is used as the monitoring voltage.
In the case of using, since the voltage supplied to the various switches of the gaming machine is + 12V, it can be expected to prevent erroneous detection of switch-on at the moment of power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in + 12V generated after + 30V is generated, before the voltage starts to drop. When the voltage of the + 12V power supply drops, the switch output starts to turn on. However, if the + 30V power supply voltage that drops earlier than + 12V is monitored and it is recognized that the power supply has stopped, the power supply will turn on before the switch output turns on. It is possible to enter a state of waiting for restoration and enter a state in which no switch output is detected.

Further, VSL (+ 30V) as a monitoring voltage
Unlike the input line to the power supply monitoring IC 902, VSL (+
A large-capacity capacitor 924 is connected to the input line to the connector (915) of 30V. Therefore, VSL (+ 30V) as the monitoring voltage is the large-capacity capacitor 92.
VSL output to connector 915 to which 4 is connected
It drops faster than (+ 30V). That is, even after VSL (+ 30V) as the monitoring voltage starts to drop, the supply state of VSL (+ 30V) as the voltage supplied to the solenoid and the motor is maintained for a predetermined period. After that, VSL as the voltage supplied to the solenoid, motor, etc.
(+ 30V) gradually decreases. Therefore, even when VSL (+30 V) as the monitoring voltage starts to drop, the solenoid, the motor, etc. can be driven for a predetermined period. Further, the stop of the power supply can be recognized before the VSL (+ 30V) output to the connector 915 starts to drop.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric part control board, the power supply cutoff circuit can supply a power-off signal to the plurality of electric part control boards. Even if there are any number of electrical component control boards that require a power-off signal, one power source monitoring means may be provided, so that even if each electrical component control means in each electrical component control board performs recovery control described below. , The cost of gaming machines does not rise so much.

In the configuration shown in FIG. 11, the detection signal (power-off signal) of the power supply monitoring IC 902 is transmitted through the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control board). Although it is transmitted to the substrate 37), for example, one detection signal may be transmitted to the relay substrate and the same signal may be distributed from the relay substrate to each electric component control substrate. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, the main substrate 31
Regarding the power-off signal output to the payout control board 37, the monitoring voltage of the power-source monitoring circuit that outputs the power-off signal may be different.

As shown in FIG. 11, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the like via the connector 915. Also,
If the clear switch 921 is not pressed, a high level (off state) signal is output.

The clear switch 921 may have a structure other than the push button structure. Figure 12
It is a block diagram which shows the other structural example of the clear switch 921. The clear switch 921 shown in FIG.
It has a switching operation unit 921a for performing selective switching of "F", "ON", and "clear". Switching operation unit 921
When “OFF” is selected by a, no signal is generated. When "ON" is selected, a high level signal is output. The clear switch 92
1 may also serve as a switch for switching on / off the power supply to the gaming machine 1. In that case, "OF
When "F" is selected, the power supply to the gaming machine 1 is stopped (the gaming machine is powered off). "O
When "N" or "clear" is selected, the game machine 1 is supplied with power (the game machine is powered on). Also, when "clear" is selected, a low level clear switch signal is output.

In this embodiment, the clear switch 92
Since 1 is mounted on the power board 910, even if the power board 910 is used as it is for the game board 6 after replacement when the game board 6 is replaced, etc., the game board 6 after replacement remains unchanged. It is possible to execute a game state restoration process and the like. That is, the power supply board 910 can be reused. Note that the clear switch 921 may be mounted at another location instead of the power supply board 910. As another place, for example, the clear switch 9
The switch board on which 21 is mounted and the clear switch 92
1 and a power switch 914 may be mounted on the terminal board.

A reset management circuit 940 for supplying a reset signal and a return signal to each board is mounted on the power supply board 910. The reset management circuit 940 is an implementation example of the boot order control means.

FIG. 13 is a block diagram showing a configuration example of the reset management circuit 940. In the reset management circuit 940, the reset IC 651 in the reset circuit 65
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level when the predetermined time elapses. That is, the reset signal is raised to the high level to bring the CPU 56 into the operable state. Further, the reset IC 651 is a power monitoring IC 9
The power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by 02, is monitored, and when the voltage value becomes equal to or lower than a predetermined value (a value lower than the power supply voltage value at which the power supply monitoring circuit outputs the power-off signal), the output is turned low To level. Therefore, the CPU 56 and the payout control CPU 371 perform system resetting (that is, return to the initial state of the system) after performing predetermined power supply stoppage processing in response to the power off signal from the power monitoring IC 902. .

As shown in FIG. 13, the reset IC 651 is used.
The externally attached capacitor has a reset IC 65
1 is a line branched from the power supply voltage line for introducing the monitoring voltage. This capacitor is provided in order to delay that the monitoring voltage introduced to the reset IC 651 becomes a value equal to or higher than the predetermined value when power supply is started. Therefore, when the power supply is started, the voltage introduced to the reset IC 651 reaches a predetermined value that causes the reset signal to rise to a high level after a predetermined period has elapsed since the power supply was started. It will be. This predetermined period is determined by the capacity of the capacitor, and the larger the capacity, the longer the period can be.

The output of the reset IC 651 is output through the circuits 941 to 949 in the reset signal circuit 950.
It is supplied to the buffer circuits 961 to 964 and the delay circuit 960. The output of the delay circuit 960 is the buffer circuit 965.
To enter. Then, the buffer circuits 961 to 965 are supplied as reset signals to the electric component control boards. Therefore, when the output of the reset IC 651 becomes high level, the CPU in each electric component control board becomes operable.

As shown in FIG. 13, the reset IC 651 is used.
The reset signal from is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level.
Then, the Q5 output of the counter IC 941 is the NOT circuit 9
It is input to the NAND circuit 947 via 45 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The NAND circuit 9 is connected to the other input of the OR circuit 949.
The output of 47 is introduced via the NOT circuit 948. The output of the OR circuit 949 is the buffer circuits 961 to 961.
It is supplied to each CPU via 965. With such a configuration, since the reset signal (low level signal) is applied twice to the reset terminal of each CPU when the power is turned on, each CPU reliably starts its operation.

Then, for example, the detection voltage of the power supply monitoring circuit (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to the low level is set to + 9V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 have the same power supply VSL.
Since the voltage is monitored, the difference between the timing when the voltage monitoring circuit outputs the power-off signal and the timing when the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop time process to the reliable completion of the power supply stop time process in response to the power off signal from the power supply monitoring circuit.

The power supply voltages monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.
The system reset circuit 65 corresponds to the second power supply monitoring means.

In this example, the detection condition for the power supply monitoring means to output a detection signal is + 30V when the power supply voltage is +22.
It means that the reset IC 651 outputs the low level which is the reset level because the power supply voltage has dropped to V and the + 30V power supply voltage has dropped to + 9V. However, the voltage value used here is an example, and another value may be used.

However, although the monitoring range is narrowed, it is also possible to use the + 5V power supply voltage as the monitoring voltage of the power supply monitoring means and the reset IC 651. Also in that case, the detection voltage of the power supply monitoring circuit is set higher than the detection voltage of the reset IC 651.

+5 which is the drive power source for the CPU 56 of the main board 31 and the payout control CPU 371 of the payout control board 37.
While power is not being supplied from the V power supply, at least part of the RAM is backed up by the backup power supply supplied from the power supply board 910, and the contents are saved even when the power supply to the gaming machine is cut off. Then, when the power is restored, the reset signal from the reset management circuit 940 becomes high level, so the CPU 56 and the payout control CPU
371 returns to the normal operating state. At that time, because the necessary data is stored in the backup RAM,
It is possible to return to the gaming state at the time of power failure at the time of recovery from power failure.

FIG. 13 shows a configuration in which the reset signal (low level signal) is applied twice to the reset terminal of the CPU of each electric component control board when the power is turned on.
When using a CPU that is surely released from reset even if the reset signal rises only once, the circuit elements indicated by reference numerals 941 to 949 are unnecessary. In such a case, the circuit elements denoted by reference numerals 941 to 949 may be omitted. In this case, the output of the reset IC 651 is directly connected to the buffer circuits 961 to 964 and the delay circuit 960.

In the above example, the reset circuit 65 is provided on the power board 910 to output the reset signal and the return signal to each board such as the main board 31 and the payout control board 37. A reset circuit may be provided on each of the substrates such as 31 and the payout control substrate 37.

In this embodiment, when the power is turned on, the reset IC 651 in the reset circuit 65 delays the rise of the reset signal supplied to the CPU of each electric component control board for a predetermined time determined by the capacitance of the external capacitor. Let That is, if the capacity of the external capacitor of the reset IC 651 is selected to a value that produces a predetermined delay time, the output becomes low level for a predetermined time determined by the capacity of the external capacitor, and when the predetermined time elapses. The output goes high.

Therefore, when the power is turned on, the timing at which the reset signal rises to the high level is delayed so that the reset signal rises to the high level after the power-off signal (NMI signal) from the power supply monitoring circuit rises to the high level. It is possible to prevent the power-off signal from being output when the reset state is released and the power-off process being executed when the power supply is restarted and restored. it can.

Further, in this embodiment, the power supply board 91
When the reset signal is supplied from 0 to the CPU of each electric component control board, the delay circuit 960 causes the CP of the main board 31 to operate.
Delay the rise of the reset signal to U56.
Therefore, when the power is turned on, the input signal of the reset terminal included in the CPU 56 of the main board 31 rises later than when the reset signal supplied to the CPU of another electric component control board rises.

For example, when the CPU 56 of the main board 31 outputs a control command to another electric component control board,
Since the CPUs in the other electric component control boards have already started up, the control command is surely received by the CPU of the electric part control board on the receiving side.

Further, the power supply board 910 is equipped with a counter 971 which is an example of a return signal output means for measuring a standby period and outputting a return signal. Counter 971
Counts the clock signal from the oscillator 943 when the power-off signal goes low and the clear is released.
Then, upon counting up, one high-level pulse is generated as the Q output. The pulse signal is logically inverted by the inverting circuit 972 and input to the buffer circuit 973 and the delay circuit 974. The delay circuit 974 delays the input signal for a predetermined period and inputs it to the buffer circuit 975.

The output of the buffer circuit 973 serves as a return signal to the payout control board 37. In addition, the buffer circuit 975
Output becomes a return signal to the main board 31. The buffer circuits 973 and 975 may be provided on the payout control board 37 and the main board 31.

FIG. 14 shows the CPU 56 in the main board 31.
It is a block diagram showing an example of the circumference. As shown in FIG. 14, the power-off signal from the power-supply monitoring circuit (power-supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. As described above, the power supply monitoring circuit is a circuit that monitors the voltage of one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value becomes equal to or lower than a predetermined value, a low level power-off signal is generated. VSL is the maximum DC voltage in the gaming machine, and is + 30V in this example. Therefore, the CPU 56 can confirm the occurrence of power failure by the interrupt processing.

As shown in FIG. 14, the power supply board 91
The reset signal and the return signal from 0 are AND circuits 161
And the output of the AND circuit 161 is input to the reset terminal (reset signal input section) of the CPU 56.

FIG. 15 is a timing chart for explaining the operation of counter 971. As shown in FIG. 15A, when the power supply voltage drops and the voltage value of VSL drops to the power cutoff signal output level (+ 22V in this example), a power cutoff signal is generated. Specifically, the power-off signal goes low. Then, as will be described later, the CPU 3 of the main board 31
1 and the payout control CPU 371 start execution of the power supply stop process, and when the process ends, enter the loop state (standby state) in which no control is performed.

The counter 971 starts counting when the power-off signal goes low, but the count-up value is VSL after the power-off signal goes low.
Is set to be equal to or longer than the time required for the voltage value of 1 to drop to the voltage capable of generating Vcc. That is, at least the power supply voltage is set to be longer than or equal to the time for which the control operation is disabled. Since the counter 971 operates using Vcc as a power source, the count-up value is set to a value equal to or greater than the value corresponding to the operable period of the counter 971. Therefore, in general,
Before the counter 971 counts up and the return signal is output, the counter 971 and other circuit components do not operate.

When the power supply is momentarily cut off, as shown in FIG. 15B, the voltage level of VSL is reduced for a short period of time and then restored. When the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level and the power supply stop processing is started. Then, the CPU 56 and the payout control CPU 371 enter the loop state after the end of the power supply stop process. The loop processing cannot be exited without any control. In this case, the counter 971 counts up and a return signal is generated.

As shown in FIGS. 7 and 8, in the main board 31 and the payout control board 371, the return signal is
It is input to the reset terminals of the CPU 56 and the payout control CPU 371 via the AND circuits 161 and 385.
Therefore, the system reset is applied to the CPU 56 and the payout control CPU 371. As a result, the CPU 56 and the payout control CPU 371 can get out of the loop state.

Note that the counter 971 is shown in FIG.
Although the case where the return signal is output immediately after the count-up is performed, the power supply board 910 has the delay circuit 974 as shown in FIG.
The supply timing of the return signal to the PU 56 is delayed from the supply timing of the return signal to the payout control CPU 371. That is, the reset release timing of the game control means is delayed with respect to the reset release timing of the payout control means, as in the case where the reset signal is given at the start of normal power supply. Therefore, even when the control operation is restored by the return signal, the game control means will be activated later than the other electric component control means.

FIG. 16 and FIG. 17 are explanatory views showing the allocation of output ports in this embodiment. Figure 1
As shown in FIG. 6, the output port 0 is an output port for the INT signal of the control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1,
The 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2, and the 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. And in FIG.
As shown in, the 8-bit data of the sound control command sent to the sound control board 70 is output from the output port 4.

Also, from the output port 5, the information output circuit 6
Various information output signals reaching the information terminal board 34 and the terminal board 160 via 4, that is, output data of information relating to control are output. Then, from the output port 6, a solenoid 16 for opening / closing the variable winning ball device 15, a solenoid 21 for opening / closing the opening / closing plate 2 of the special winning opening, and a solenoid 21 for switching a path in the special winning opening.
The drive signal for A is output.

As shown in FIG. 17, the payout control board 37,
An output port for outputting each INT signal (payout control signal INT, display control signal INT, lamp control signal INT, and voice control signal INT) output to the pattern control board 80, the lamp control board 35, and the sound control board 70 ( The output port 0) and the output ports (output ports 1 to 4) for outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 and the sound control signals CD0 to CD7 are different ports. Is.

Therefore, when the INT signal is output, the payout control signals CD0 to CD7 and the display control signals CD0 to CD0 are mistakenly output.
The possibility of changing the CD7, the lamp control signals CD0 to CD7, and the audio control signals CD0 to CD7 is reduced. Also, when the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7 or the voice control signals CD0 to CD7 are output, the I
The possibility of changing the NT signal is reduced. As a result, the command to the electric component control board from the game control means of the main board 31 is more reliably transmitted. Further, since each INT signal is configured to be output from the output port 0, I of the game control means.
The load of NT signal output processing is reduced.

FIG. 18 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 18, the bits 0 to 7 of the input port 0 are respectively connected to the winning opening switches 33a, 39a, 29a, 30a,
Detection signals of the gate switch 32a, the starting opening switch 14a, the count switch 23, and the V winning switch 22 are input. In addition, the detection signals of the prize ball count switch 301A, the full tank switch 48, the ball cut switch 187, the count switch short circuit signal, and the detection signal of the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. In this way, the detection signal of the clear switch 921, that is, the operation input of the operating means, is the input port to which the detection signal of the switch for detecting the game ball is input (8-bit input section).
Bit in the same input port as (input port circuit)
Has been entered in.

Next, the operation of the gaming machine will be described. Figure 1
9 is a flowchart showing main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main processing, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the stack pointer designated address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). After initializing CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) (step S5), the RAM is set to the accessible state (step S6).

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, the CTC has two external clock / timer trigger inputs CLK / TRG2,3.
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode to always fly to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the internal device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it becomes possible to easily process the interrupt request from each built-in device, and the interrupt processing can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 confirms only once the state of the output signal of the clear switch 921 input through the input port 1 (step S7). If ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 1, the on state of the clear switch signal is high level (see FIG. 18). Further, for example, the game shop clerk uses the clear switch 92.
By starting power supply to the gaming machine while turning 1 on, the initialization process can be easily executed. That is, the RAM clear or the like can be performed.

If the clear switch 921 is not in the ON state, the data protection processing of the backup RAM area (for example, processing when power supply is stopped such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. When such a protection process is performed, backup is made. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area during the power supply stop process. In this example, as shown in FIG. 20, if “55H” is set in the backup flag area, it means that there is backup (on state), and if a value other than “55H” is set, there is no backup (off). State).

After confirming that there is a backup, the CPU 5
6 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Further, the number of checksum calculations corresponding to the number of checksum target data is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The data after inversion is used as the checksum.

In the power supply stop process, the checksum is calculated by the same process as the above process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If the power is restored after an unexpected power outage such as a power outage, backup RA
Since the data in the M area should have been saved, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply was stopped. In such a case, since the internal state cannot be returned to the state when the power supply was stopped, the initialization process that is executed when the power is turned on, not when the power supply is restored from the stop, is executed.

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply was stopped (step S10). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored.

As described above, the backup RA is backed up using the backup flag and the check data such as the checksum.
By checking whether or not the data in the M area is saved, it is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

Further, if "backup is present" is not confirmed by the state of the backup flag, the initialization process described below is performed without performing the game state recovery process described below, so backup data exists. It is possible to prevent the game state restoration process from being executed despite not doing so, and it is possible to return the control state to the initial state by the initialization process.

Further, when the check result using the check data is not normal, the initialization process described below is performed without performing the game state restoration process described below, so that the power supply is stopped. It is possible to prevent the game state recovery process from being executed based on the backup data that has become different contents,
By the initialization processing, the control state can be returned to the initial state.

In the initialization process, the CPU 56 first executes R
AM clear processing is performed (step S11). Further, a predetermined work area (for example, a random number counter for normal symbol determination, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
Work area setting processing for setting an initial value to a prize ball flag, out-of-ball flag, payout stop flag, or other flag for selectively performing processing according to the control state is performed (step S1).
2).

Further, the CPU 56 determines whether or not a predetermined payout prohibition condition is satisfied (step S13).
a), if the payout prohibition condition is not satisfied, a payout permission state designation command (hereinafter referred to as a payable state designation command) for instructing that the payout from the ball payout device 97 is possible is given to the payout control board 37. A process of transmitting the same is performed (step S13b). If the payout prohibition condition is satisfied, the control state of the main board 31 is set to the payout prohibition state. In this example, the out-of-ball flag is set to the out-of-ball state (on state), and the full tank flag is set to the down-bottom full tank state (on state), so that the control state of the main board 31 is prohibited. Set to state. Withdrawal prohibition conditions are
For example, it is established when there is a possibility that the game ball that should be paid out cannot be paid out, or when it is not appropriate to pay out the game ball, such as when the ball is out or the bottom plate is full To do. Therefore, step S13
In a, for example, confirmation of the detection state by the out-of-ball switch 187 and confirmation of the detection state by the full tank switch 48 are performed. At the stage where the determination process of step S13a is executed, the timer interrupt described later is not set, so the monitoring time (for example, 2 ms) is created by the wait process by the software timer, and the state of the switch described later is set. By executing the same processing as the processing to be monitored (steps S150 to S159), the out-of-ball switch 187 and the full-tank switch 48 are monitored every monitoring time.
It is only necessary to monitor the state of and determine whether or not the switch is turned on.

Further, the CPU 56 is another sub board (lamp control board 35, sound control board 70, symbol control board 80).
A process of transmitting an initialization command for initializing the sub board to each sub-board is executed (step S14). As the initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and the prize ball lamp 5
1 and a command (to the lamp control board 35) for instructing to turn off the out-of-bulb lamp 52.

In the initialization processing, a payable state designation command is transmitted to the payout control board 37 when the payout prohibition condition is not satisfied, and is issued when the payout prohibition condition is satisfied. (Hereinafter, referred to as a payout prohibition state designation command.) Is not transmitted. Even if the state of the gaming machine is the state in which the payout from the ball payout device 97 is not possible (the state in which the payout prohibition condition is satisfied), the payout is prohibited by the initialization process in the payout control board 37. It should be set to the state, so there is no problem. In the process of transmitting the payable state designation command and the initialization command to other sub-boards, for example, the address of the table (ROM area) in which each command is set is set in the pointer, and the command setting process described later (Fig. 42)).

Then, the register of the CTC provided in the CPU 56 is set so that the timer interrupt is periodically applied every 2 ms (step S15). That is,
A value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number updating process and the initial value random number updating process are executed, the interrupt disabled state is set (step S16), and when the display random number updating process and the initial value random number updating process are completed, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining the symbol displayed on the variable display device 9, and the display random number updating process is a process of updating the count value of the counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random numbers. The initial value random number is a random number for determining an initial value of a count value of a counter (big hit determination random number generation counter) for generating a random number for determining whether or not to make a big hit. In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, the initial value is set to the counter.

The interrupt-prohibited state is set when the display random number updating process is executed, because the display random number updating process is also executed in the timer interrupt process described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt prohibition state is set during the process of step S17.

The update value in the display random number update processing is
For example, the value specified by the refresh register (R register) is used. The R register is a register used as a refresh counter when the dynamic RAM is used, and the CPU 56 uses such R register.
It has a built-in register. The R register is the CPU
It is incremented each time 56 fetches an instruction.
In this case, the CPU 56 refers to the value (1 byte) of the R register when updating the random number for determining the fluctuation pattern and the like,
A predetermined upper bit is masked, and the remaining lower bit data is used as an updated value (value added to the count value of the counter for generating the display random number). Specifically, when the random number for updating the left symbol is updated in the range of 0 to 11, when the numerical value in the range of 0 to 7 is used as the updated value to be added, for the left symbol updating When updating the random number of, the lower 3 bits of data of the R register are used. Depending on the lower 3 bits of data in the R register,
Since a random value of 0 to 7 can be obtained, the random value can be used as the update value with a simple configuration. Further, since the instruction fetch timing and the display random number update processing execution timing are not synchronized, the count value of the counter for generating the display random number is randomized by using the lower bit of the R register as the update value of the random number. It can be set to any value, and it is possible to improve the randomness of the display pattern and the variation pattern that appear. Further, since the function of the R register is used, the program configuration is simplified,
It will be possible to flexibly respond to model changes. further,
Since the upper bits are masked and used, it is possible to deal with updating random numbers in a plurality of update ranges by changing the masked range.

FIG. 21 is a flow chart showing an example of the game state restoration processing. In the game state recovery process, C
The PU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (a stack pointer save buffer in a work area where power is backed up) in a power supply stop process which will be described later in detail. Therefore,
In step S81, the value of the RAM area is set in the stack pointer to restore the value. Specifically, data indicating the address of the stack area saved in the RAM area (stack address data) is set in the stack pointer. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the CPU 56 confirms whether or not the payout is prohibited (step S82). Whether or not the payout is prohibited is determined by the RAM whose power is backed up.
Predetermined work area stored in the area (for example, random symbol for normal symbol determination, normal symbol determination buffer, special symbol left middle right symbol buffer, special symbol process flag,
The payout stop flag as the payout state data in the payout command storage pointer, the probability change flag, the award ball flag, the out-of-ball flag, the full tank flag, the payout stop flag, etc.) is confirmed. The payout stop flag is turned on when either the out-of-ball flag or the full tank flag is turned on, and is turned off when both the out-of-ball flag and the full tank flag are turned off. If it is in the payout prohibition state, the control state of the main board 31 is set to the payout prohibition state. In this example, the out-of-ball flag is set to the out-of-ball state (on state), and the full tank flag is set to the down-bottom full tank state (on state), so that the control state of the main board 31 is prohibited. Set to state.

If it is not in the payout prohibition state, a command transmission table relating to a payout control command (payout possible state designation command) for instructing the payout control means that the payout is possible is set (step S83). A command set process is called (step S84). In step S83, the command transmission table (RO
The start address of M) is set as the address of the command transmission table. The command transmission table relating to the payable state designation command includes INT data, which will be described later,
Data of the first byte of the payout control command and data of the second byte of the payout control command are set. In addition, according to the call instruction of step S84,
The stack pointer restored at 81 is incremented, and the address data (program address data) of the program being executed is saved in the stack area pointed to by the stack pointer. Then, when the command set processing based on the call instruction is completed, it returns to the address at the time of calling the command set processing based on the address data (program address data) saved in the stack area pointed to by the stack pointer.

When the payout prohibition state is determined in step S82, the payout control command (payout prohibition state designation command) for instructing the stop of the payout is not transmitted, but the recovery process in the payout control board 37 (see FIG. 50). There should be no problem because it is supposed to be in the payout prohibition state in).

Since the payout control means cannot recognize the shortage of the supply balls and the full capacity of the surplus ball receiving tray 4, the game control means must notify the shortage of the supply ball or the surplus ball receiving tray 4 when the power is restored. There is a risk that the game ball payout process will be started despite the fact that it is a ton. However, in this embodiment, when the supply ball is insufficient or the surplus ball receiving tray 4 is not full, a payout control command instructing that the payout is possible in the game state recovery process is transmitted, and the payout control command is issued. Since the payout control means does not execute the payout processing unless it receives a message, the payout control means starts the payout processing for the game balls even if the supply balls are insufficient or the surplus ball receiving tray 4 is full. There is no end. The processing executed by the payout control means will be described later in detail.

Then, the CPU 56 sets a command transmission table relating to a display control command for restoring the display state according to the display state of the special symbol on the variable display device 9 when the power supply is stopped (step S85). ), And a command set process is called (step S86). In step S85, the head address of the command transmission table (ROM) that stores the display control command for restoring the display state is set as the address of the command transmission table. In the command transmission table regarding the display control command for restoring the display state, INT data, the first byte data of the payout control command, and the second byte data of the payout control command are set, which will be described later.

The display control commands set in step S85 include a symbol designating command for left, middle and right for designating a special symbol to be displayed on the variable display device 9 after restoration.
For example, if the special symbol is fluctuating when the power supply is stopped, the command transmission table for the symbol designating command that designates the final stop symbol after the fluctuation is set, and, for example, when the power supply is halted. If the special symbol is stopped, the command transmission table regarding the symbol designating command for designating the final stopped symbol in the previous symbol fluctuation is set. Display control CPU 10
1, when receiving the symbol designating command of the left middle right after the power supply is started, when the display state during symbol variation is restored, depending on the symbol designating command received after the symbol variation ends Display the finalized design (final stop design). In addition, when the display is restored while the symbols are stopped,
A fixed symbol (determined symbol in the last symbol change) corresponding to the symbol designating command received at a predetermined display timing is displayed. As mentioned above, when the power supply is started,
The display state of the variable display device 9 can be restarted from the state before the power supply was cut off.

Further, the display control command set in step S85 includes a display control command (for example, a probability variation state designation command) for notifying the symbol display board 80 of the probability variation state. For example, if the backed up probability variation flag is in the ON state, the command transmission table relating to the display control command indicating the probability variation state is set in step S85. The probability variation flag is turned on when being controlled to a high probability state (a state in which a big hit is likely to occur), and is set to a normal state (a state where the probability of a big hit is not a high probability). This flag is turned off and is stored in the backup RAM area. CP for display control
Upon receiving the probability variation state designation command, the U 101 performs display control of the variable display device 9 so as to display in the display mode at the time of the probability variation (for example, the background color is changed to the color at the time of the probability variation). As described above, when the power supply is started, the display state of the variable display device 9 can be restarted from the state before the power was turned off.

Next, the CPU 56 sets the register of the CTC provided in the CPU 56 so that the timer interrupt is periodically applied every 2 ms (step S87). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). in this way,
Since the timer interrupt is set immediately after transmitting the command for restoring the control state to the sub-board, it becomes easy to synchronize the main board 31 and the sub-board.

After that, the CPU 56 clears the backup flag (step S88), that is, resets the flag indicating that a predetermined storage protection process has been executed at the previous power supply stop. Therefore, it is possible to prevent unnecessary information from remaining after the control state is restored.
Also, the saved values of various registers are read from the stack area, and various registers (IX register, HL register, D
Set to E register, BC register) (step S8)
9). That is, register restoration processing is performed. The value of the stack pointer is decremented each time each register is restored. That is, the value of the stack pointer is updated to point to the address immediately before the stack area. Then, when the parity flag is not turned on, the interrupt permission state is set (steps S90 and S91). Finally, AF
The registers (accumulator and flag registers) are restored from the stack area (step S92).

Then, the RET instruction is executed. RET
When the instruction is executed, the CPU 56 realizes the return operation of the program by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state recovery processing. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S92, the stack pointer pointing to the stack area is NM.
It indicates the area where the address of the program being executed when the power supply stop processing by I was started is saved. That is, the return address stored in the stack area pointed to by the restored stack pointer is
This is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, the next RET instruction in step S92 returns to the address where the NMI occurred when the power supply was stopped. That is, in this example, the recovery control is executed based on the address data (program address data) saved in the stack area.

As described above, since the stack pointer is restored before transmitting the control command for restoring the game state, the process for transmitting the command (command set process) should be a subroutine. It is possible to perform the transmission process of the control command for restoring the game state by calling the subroutine.

In the state before the stack pointer is restored, the stack pointer has a predetermined value (for example, 0000 (H) or FFFF (H)) set when the power is turned on. Therefore, if the call instruction of the subroutine is executed without returning the stack pointer, and if the value of the stack pointer is pointing to the maximum possible value (eg FFFF (H)), the contents of the stack pointer based on the call instruction are changed. A problem that the increment cannot be performed may occur. Also, the stack pointer does not always point to the address of the stack area (ROM
(There is a possibility that it is pointing to the area of 54)), so that the problem that the contents of the program counter cannot be stacked may occur. Further, by stacking the contents of the program counter on the basis of the call command, the data backed up and stored in the RAM 55 may be erased (erased by overwriting).

However, in this example, since the stack pointer is restored before executing the processing for transmitting the command as described above, the transmission processing of the control command for restoring the game state by the subroutine processing is performed. Can be executed. Therefore, the program capacity used for game control can be reduced, and the required capacity of the ROM 54 can be reduced. In addition, the CPU 56
It becomes possible to efficiently perform the game state restoration processing.

When a timer interrupt occurs, the CPU 56
After performing the register save process (step S20), the game control process of steps S21 to S32 shown in FIG. 22 is executed. In the register saving processing in step S20,
A process of saving the address data (program address data) of the program being executed to the stack area pointed to by the stack pointer is also executed. Then, the register restoration process after executing the game control process (step S3
At 3), based on the address data saved in the stack area, the address at the time when the timer interrupt occurred is restored. In the game control process, the CPU 56 first causes the gate switch 32 via the switch circuit 58.
The detection signals of switches such as a, the starting port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input, and their states are determined (switch processing: step S21).

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used for game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

Further, the CPU 56 carries out special symbol process processing (step S26). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S27). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. And the value of the normal symbol process flag,
It is updated during each process according to the game state.

Next, the CPU 56 performs a process of setting a display control command relating to a special symbol in a predetermined area of the RAM 55 and transmitting a display control command (special symbol command control process: step S28). In addition, the display control command relating to the normal symbol is set in a predetermined area of the RAM 55 and a process of transmitting the display control command is performed (normal symbol command control process: step S29).

Further, the CPU 56 performs an information output process for outputting data such as big hit information, start information, probability variation information, etc. supplied to the hall management computer (step S30).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). In order to open or close the variable winning ball device 15 or the opening / closing plate 20 or to switch the game ball passage in the special winning opening, the solenoid circuit 59 drives the solenoids 16, 21, 21A according to the drive command. To do.

Then, the CPU 56 causes the winning opening switch 2
A prize ball process is performed for setting the number of prize balls based on the detection signals of 9a, 30a, 33a and 39a (step S32). Specifically, the winning opening switches 29a, 30
The payout control command indicating the number of prize balls is output to the payout control board 37 in response to the winning detection based on the turning on of a, 33a, and 39a. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in response to a payout control command indicating the number of prize balls. afterwards,
The CPU 56 restores the contents of the register (step S
33), and the interrupt permission state is set (step S34).

According to the above control, in this embodiment, the game control process is activated every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set,
The game control process may be executed in the main process.

23 to 25 are flowcharts showing a processing example of the non-maskable interrupt processing (power supply stop processing) which is executed in response to the power-off signal from the power supply substrate 910. The non-maskable interrupt process means a process in which the interrupt prohibition is not applied. When a non-maskable interrupt occurs,
The interrupt control mechanism built in the CPU 56 saves the address of the program being executed when the non-maskable interrupt occurs (specifically, the next address after the completion of execution) in the stack area pointed to by the stack pointer. , Increase the stack pointer value. That is, the value of the stack pointer is updated to point to the next address in the stack area.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Also, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register and the stack pointer are saved in the backup RAM area (steps S454 to S458). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag. Although the stack pointer is saved in S458, more specifically, data indicating the address of the stack area set in the stack pointer (stack address data) is saved in the backup RAM area.

Next, the CPU 56 causes the clear data (0
0) is set in an appropriate register (step S45
9), the number of processes (“7” in this example) is set in another register (step S460). Further, the address of the output port 0 is set in the IO pointer (step S46).
1). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S46).
2), the value of the IO pointer is incremented by 1 (step S46
3) The value of the number of processes is subtracted by 1 (step S464).
In the processes of steps S462 to S464, the value of the number of processes is 0.
Is repeated (step S465). As a result, clear data is set to all output ports 0 to 6 (see FIGS. 16 and 17). 16 and 17
As shown in, in this example, "1" is in the ON state,
Since the clear data "00" is set to each output port, all the output ports are turned off.

As described above, since each output port is turned off, it is possible to surely prevent the occurrence of a situation inconsistent with the saved game state. That is, in a gaming machine that has a variable winning ball device, such as a pachinko gaming machine,
Due to the mounting, the position of the variable winning opening in the variable winning ball device and the installation position of the winning opening switch for detecting the winning must be separated to some extent. If you do not immediately turn off the output port, especially the output port that outputs the signal to open the variable winning ball device, when the power supply is stopped, even if you win the variable winning port, even if the power supply is stopped A situation may occur in which execution of the process is started and the winning opening switch is not detected. In that case, the fact that the variable winning a prize has been won is not saved. That is, the actually occurring game state (there is a prize) and the saved game state do not match. However, in this embodiment, since the output port is cleared and the variable winning ball device is closed, it is possible to reliably prevent the occurrence of a situation inconsistent with the saved game state.

In addition, since the output port can be cleared during the power supply stoppage processing executed before the electric components cannot be driven, the electric components cannot be driven. Before that, each electric component controlled by the game control means can be put into an appropriate operation stopped state. For example, after closing the open special winning opening and closing the open variable winning ball device 15, the operation of the electric components is disabled after the operation of the electric components is stopped. be able to. Therefore, it becomes possible to wait for the restoration of the power supply in an appropriate stopped state.

Further, since the operation of each electric component is stopped during the power supply stop process, no electric power is consumed to drive each electric component, and a signal is output from the output port. Since the used electric current is cut off, it is possible to suppress the power consumption though it is a small amount.

Further, in this embodiment, the detection signal of the prize ball count switch 301A is checked for a predetermined period (hereinafter referred to as the payout confirmation period). When the prize ball count switch 301A is turned on, the content of the total prize ball count buffer is decremented by one.

In this embodiment, a payout confirmation period measuring counter is used to measure the payout confirmation period. The value of the payout confirmation period measurement counter is the initial value m.
From the loop of the switch detection processing described below (S4
It is assumed that the payout confirmation period ends when the loop (starting from 67 and returning to S467) is decremented by 1 each time the value becomes 0. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore, a time m times the time required for one round of the loop is substantially equivalent to the payout confirmation period.

In order to measure the payout confirmation period, the CPU 5
A built-in timer of 6 may be used. That is, a predetermined value (corresponding to the payout confirmation period) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the payout confirmation period has ended. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program.

In the payout confirmation period, the game ball is dropped from the ball payout device 97 (for example, when the game ball is sent to the ball passages 293a and 293b below the sprocket 292 shown in FIG. 5). It is set to be longer than the time required to reach 301A. When the distance from the ball payout device 97 to the prize ball count switch 301A is L, the fall time t during that time is t = √ (2L / g) (g:
Because of the acceleration due to gravity, the payout confirmation period is set longer than that. The specific value of the payout confirmation period varies depending on the value of the distance L and how much margin is provided from the fall time t, but is, for example, about 100 [ms] to 150 [ms].

Even when the game control means detects the payout of the loan ball, the payout confirmation period is set in the same manner. That is, from the time when the game ball falls from the ball payout device 97 (for example, when the game ball is delivered to the ball passages 293a and 293b below the sprocket 292 shown in FIG. 5) to the ball lending count switch 301B or more. Is set to. Therefore, if the distance from the ball payout device 97 to the ball lending count switch 301B is L, the fall time t during that time is still t = √ (2L / g) (g: gravity acceleration). It is set higher than that. Also in this case, the specific value of the payout confirmation period varies depending on the value of the distance L and how much margin is provided from the fall time t, but for example, 100 [ms] to 150 [m]
s].

The distance from the ball payout device 97 to the prize ball count switch 301A and the loan ball count switch 3
If the distance to 01B is different, the ball payout device 97
The payout confirmation period may be determined based on the distance of the switch away from.

At least during the payout confirmation period in which the switch detection process is executed, the prize ball count switch 301A must be in a state where it can detect a game ball. Therefore,
In this embodiment, as shown in FIG. 11, a relatively large-capacity capacitor 923 as an auxiliary drive power supply is connected to the input side of converter IC 920 in power supply substrate 910. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained within a switchable range for a certain period of time, and the prize ball count switch 301
A becomes operational. The capacity of the capacitor 923 is determined so that the period is equal to or longer than the payout confirmation period.

Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 920, they can be operated for a relatively long period even when the power supply is stopped.

As described above, in this example, the payout confirmation period measuring counter is set to the initial value m (step S4).
66). Also, in step S467, the 2 ms measurement counter is set to the initial value n corresponding to the time of 2 ms. Then, the value of the 2 ms measurement counter is decremented by 1 until the value of the 2 ms measurement counter becomes 0 (step S468) (step S469).

When the value of the 2 ms measurement counter becomes 0,
The input check of the detection signal of the prize ball count switch 301A is performed. That is, a process similar to the switch process and the switch check process described later is performed. Specifically, the data input to the input port 1 is input (step S470). Then, clear data (0
0) is set (step S471). Further, the port input data, in this case, the input data from the input port 1 is set as the "comparison value" (step S472).
Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S473).

Then, the switch timer pointed by the pointer (the address of the switch timer is set) is loaded (step S474), and the comparison value is shifted to the right (direction from the upper bit to the lower bit) (step S475). ). The data of the input port 1 is set as the comparison value. Then, in this case, the detection signal of the prize ball count switch 301A is pushed out to the carry flag.

If the value of the carry flag is "1" (step S476), that is, the prize ball count switch 30.
If the 1A detection signal is on, the switch timer value is incremented by 1 (step S477). If the value of the carry flag is "0", that is, if the detection signal of the prize ball count switch 301A is in the off state, clear data is set in the switch timer (step S478).
That is, if the switch is in the off state, the value of the switch timer returns to 0.

When the value of the switch timer reaches 2 (step S479), the value stored in the total prize ball number storage buffer is decremented by 1 (step S480), and the value of the prize ball information counter is incremented by 1 (step S480). Step S481).
If the value of the prize ball information counter is 10 or more (step S482), the value of the prize ball information output counter is incremented by 1 (step S483), and the value of the prize ball information counter is decreased by -10 (step S484).

Next, the value of the payout confirmation period measuring counter is decremented by 1 (step S485), and if the value is not 0, the process returns to step S467.

Through the above processing, when the prize ball count switch 301A is turned on within the payout confirmation period, the value of the total prize ball number storage buffer is decremented by one. Since the process for saving the contents of the backup RAM is performed after such a switch detection process,
The total prize ball number storage buffer is always decremented by one. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the switch detection process, since the prize ball information output frequency counter for outputting the prize ball information to the outside of the gaming machine is also calculated, the prize ball information output to the outside and the actual number of payout prize balls are inconsistent. It doesn't happen.

Further, in the above switch detection processing, timer processing using a detection period counter is performed. That is, the detection output of the prize ball count switch 301A is checked every 2 ms, and when the ON detection is performed twice in succession, it is considered that the prize ball count switch 301A is surely turned on. That is, a predetermined game medium detection determination period (a period for determining whether or not a game medium (here, a prize ball paid out in the power supply stop process) is detected. In this example, a period of 2 ms or more) When the ON detection is performed twice consecutively before and after, it is considered that the payout of one prize ball is completed. As described above, in this example, the game medium detection determination period is the normal game medium detection determination period (a period for determining the presence or absence of the game medium in the normal game state, which is not the process in the power supply stop process. Then, 2 ms determined by the switch-on determination value (see FIG. 35) described later.
In the above period, step S18 of FIG.
It is used in the judgment of 8. ) And the same period.
Therefore, it is possible to determine whether or not the prize ball count switch 301A is turned on under the same condition as the normal control. Further, it is determined whether or not the prize ball count switch 301A is turned on by the same processing under the same conditions as in the normal control, so that the switch detection processing module in the power supply stop processing and the normal control The switch detection processing module (the processing module of step S21 of FIG. 22 including the processing of FIG. 29 and the processing of FIG. 30) can be a common processing module. That is, the switch detection processing module in the normal control can be used for the switch detection in the power supply stop processing. The game medium detection determination period may be different from the normal game medium detection determination period. As described above, when the ON detection is performed twice consecutively, the prize ball count switch 301A is considered to be surely turned ON. Therefore, the switch ON detection is prevented from being erroneously performed, and the payout is prevented. It is possible to reliably detect the prize ball that has been put out.

In this embodiment, the switch detection processing is performed only for the prize ball count switch 301A, but the same applies to the start winning opening switch, the V winning switch 22 related to the special winning opening, and the count switch. Switch detection processing may be performed. Further, similar switch detection processing may be performed for other prizes. When such an on-check is also performed, even if a power failure occurs immediately after the game ball has won the winning opening, the winning is surely detected and reflected in the saved game state.

When the payout confirmation period elapses (step S4
86), that is, when the value of the payout confirmation period measuring counter becomes 0, the backup designated value (in this example, “5
5H ”) is stored in the backup flag (step S487). Backup flag is backup RAM
Is formed in the area. Next, parity data is created (steps S488 to S497). That is, first, clear data (00) is set in the checksum data area (step S488), and the checksum calculation start address is set in the pointer (step S48).
9). Also, the number of checksum calculations is set (step S490).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S491). The calculation result is stored in the checksum data area (step S49).
2), increment the pointer value by 1 (step S493),
The value of the checksum calculation count is subtracted by 1 (step S4
94). The processes of steps S491 to S494 are repeated until the value of the checksum calculation count becomes 0 (step S495).

When the value of the checksum calculation frequency becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S496). Then, the inverted data is stored in the checksum data area (step S497). This data becomes the parity data that is checked when the power is turned on. Then R
An access prohibition value is set in the AM access register (step S498). After that, the built-in RAM 55 cannot be accessed.

When the access prohibition value is set in the RAM access register, the CPU 56 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the RAM area in which the data used in the game control processing is stored is backed up by power supply. Therefore, the checksum generation process indicating whether or not the contents are correctly saved, and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for saving the game state.

In this embodiment, the power supply stoppage process is executed according to the NMI.
You may connect to the maskable terminal of PU56 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In this embodiment, the register saving process is performed at the beginning of the process activated in response to the power-off signal. However, when the register is not used in the switch detecting process, the switch detecting process is performed. The register saving process can be performed after the execution, that is, before the process of setting the backup flag and calculating the checksum. In that case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as the power supply stop process. Further, even when some registers are used in the switch detection process, the register saving process can be performed on the unused registers before the backup flag setting and the checksum calculation process.

In the above example, the output port clearing process is performed before the switch detection process is executed (step S466).
Before). During the execution of the power supply stop process, the CPU 56 and the switches are connected to the capacitors 923 and 92.
It will be driven by the charging power of 4 or the like. Since the output port clearing process is performed before the switch detection process is executed, even if the special winning opening, the variable winning device, etc. are configured to be driven by electric parts such as solenoids, they must be driven. Not a capacitor (especially capacitor 92
The charging power and the like in 4) can be effectively used for the processing at the time of power supply stop.

In the above example, when the V winning switch 22 is detected after the power is cut off, the solenoid 21 (the member for guiding the special winning opening to the V winning switch is operated). The output port of () is cleared after the switch detection processing is executed. By doing so, when a power outage occurs in a state where the V winning that is the condition of continuation right is not generated, guide the game ball that entered the special winning opening just before the power outage to the V winning switch 22 side. You can Therefore, it is possible to prevent the unjustified extinction of the continuation right. In this case, the period corresponding to the above-mentioned payout confirmation period is a predetermined period of time or more until the gaming ball that has won the special winning opening reaches the V winning switch 22. When a latch type solenoid is used, it is not necessary to clear the output port.

Even if the special winning opening is closed by clearing the output port, it is possible that there is a game ball in the special winning opening. Therefore, in the switch detection process executed in response to the power-off signal, the count switch 23 It is desirable to detect The above-mentioned exceptional processing is the same not only in the type 1 pachinko gaming machine but also in the type 2 pachinko gaming machine and the type 3 pachinko gaming machine.

FIG. 26 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power off signal: power supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of the monitoring voltage (voltage input to the power supply monitoring IC 902) of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to + 22V, the power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (becomes a low level).

The power-off signal is introduced to the electric component control board (in this embodiment, the main board 31 and the payout control board 37), and the CPU 56 and the payout control CPU 371 receive N signals.
It is input to the MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the system reset circuit mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 And the payout control CPU 371 enters the system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stoppage process before being brought into the system reset state.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, at least on the main board 31 and the payout control board 37, the processing at the time of power supply stop is executed, and
56 and the payout control CPU 371 are in the system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Generates a voltage drop signal (power cut detection signal). As shown in FIG. 26, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stoppage process.

Here, the power supply monitoring circuit monitors the voltage branched from the highest power supply VSL among the DC voltage used in the gaming machine, but the timing of generating the power supply cutoff signal is the IC drive voltage. The voltage to be monitored does not have to be the highest voltage of the power supply VSL, as long as the operation time for the electric component control means operating in (3) secures the operation time for performing the predetermined power supply stop processing. That is, if at least a voltage higher than the drive voltage of the IC or the solenoid is monitored, the power-off signal is generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. be able to. In this example, the voltage branched from the power supply VSL is used as the drive voltage of the solenoid or the like, but unlike the line to which the monitored voltage is supplied, a large-capacity capacitor 924 is provided in the line that supplies the drive voltage to the solenoid or the like. Since they are connected, the power-off signal can be generated at a timing when a predetermined period in which the supply of the drive voltage to the solenoid etc. can be continued is secured.

When a voltage other than the highest power source VSL is used as the monitoring target voltage, it is preferable that the monitoring target voltage is a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped, as described above. That is, the voltage supplied to various switches of the gaming machine (switch voltage: for example, prize ball count switch 301A, ball lending count switch 301
Since B) is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

FIG. 27 is a timing chart showing an example of how the process of inputting the detection signal from the payout detecting means is executed. In this embodiment, the power-off signal is the main board 31.
And the payout control board 37, and the CP of the main board 31.
It is input to the N56 terminal of the U56 and the payout control CPU 371. The CPU 56 of the main board 31 executes the above-described power supply stop processing by the non-maskable interrupt processing.

As shown in FIG. 27, when the prize-ball payout is executed when the power-off signal turns on (in this example, changes from the high level to the low level), the input processing of the detection signal from the payout detection means is performed. The prize ball count switch 301A is turned on within the payout confirmation period (detection maintaining period) to be executed. Therefore, the ball payout executed when the power-off signal is turned on can be reflected in the total prize ball number buffer when the power supply stop process is executed.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the signal from the reset IC 651 input to the main board 31 becomes low level, and the CPU 56 enters the system reset state. Become. The CPU 56 completes the power supply stoppage process before the system is reset.

When the voltage value of VSL further decreases and falls below a voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, in the main board 31, the power supply stop processing is executed, and the CPU 56 is in the system reset state.

The payout control CPU 371 in the payout control board 37 also enters the system reset state after performing the power supply stop time process.

Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch is certainly turned on, and the process corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 28, switch timers are provided by the number N of detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 13. Further, in the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 18).

FIG. 29 is a flow chart showing a processing example of the switch processing of step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs the data input to the input port 0 (step S101). Then
The number of processes is set to "8" (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, the switch check processing subroutine is called (step S104).

FIG. 30 is a flow chart showing the switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0 as the "comparison value" (step S121). In addition, clear data (00) is set (step S1
22). Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S).
124). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after addition becomes 0, the added value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in the off state, clear data is set in the switch timer (step S126). That is, if the switch is in the off state, the value of the switch timer returns to 0.

Thereafter, the CPU 56 increments the pointer (address of the switch timer) by 1 (step S130) and decrements the processing number by 1 (step S13).
1). If the number of processes is not 0, step S122
Return to. Then, the processing of steps S122 to S132 is repeated.

The processing of steps S122 to S132 is repeated for the number of processings, that is, eight times, and during that time, the switch detection signal input to the 8 bits of the input port 0 is sequentially turned on or off. If the check process is performed and the switch is on, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes step S of the switch processing.
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S107). Then, the switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is executed, steps S122 to S122
The processing of 132 is repeated for the number of processings, that is, four times, and during that time, with respect to the detection signal of the switch input to the 4 bits of the input port 1, the check processing of whether it is in the on state or the off state is performed sequentially. If it is on, the value of the corresponding switch timer is incremented by one.

In this embodiment, the game control process is activated every 2 ms, so the switch process is also performed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

31 to 33 are flowcharts showing an example of the prize ball process of step S32 in the game control process. In the present embodiment, in the prize ball processing, the prize winning hole switches 33a, 39a, 29a, which are targets of prize ball payout,
30a, count switch 23 and starting opening switch 1
4a is surely turned on, and when turned on, the payout control command indicating the number of prize balls is controlled to be sent to the payout control board 37, and the full tank switch 48 and the out-of-ball switch 187 are controlled. Whether or not it is surely turned on is determined, and when it is turned on, processing such as controlling to send a predetermined payout control command to the payout control board 37 is performed.

In the prize ball processing, the CPU 56 sets "1" as the offset of the input determination value table (step S150) and "9" as the offset of the switch timer address (step S151). The offset “1” in the input determination value table (see FIG. 35) is
This means that the second data “50” in the input determination value table is used. Further, each switch timer is shown in FIG.
Since they are arranged in the same order as the bit order of the input ports shown in FIG. 3, the offset "9" of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input judgment value table is set with a judgment value for judging whether the switch is surely turned on when the number of times the switch is turned on is detected for each switch.
It is the M region. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 35, in the input determination value table, “2”, “50”, “250”, “30”,
The determination values of "250" and "1" are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the switch timer value determined by the start address of the switch timer and the offset value, and they match. In that case, the switch-on flag is set, for example.

An example of the switch-on check routine is shown in FIG. In the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the full-tank switch 48 matches the full-tank switch-on determination value "50" (step S153), so the full-tank flag is set. (Step S
154). Although not clearly shown in FIG. 31, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

Further, the CPU 56 sets "2" as the offset of the input judgment value table (step S15).
5), "0A (H)" is set as the offset of the switch timer address (step S156). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 18, the switch timer address offset “0A (H)” is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S157).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
58), the out-of-ball flag is set (step S15).
9). Although not shown in FIG. 31, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when the value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 confirms whether or not the payout is prohibited (step S160). The payout prohibition state is a state after the payout prohibition state designation command, which is a payout control command for instructing the payout control board 37 to be in a state in which the payout should be stopped, specifically, the work area. The payout stop flag in is set. If it is not in the payout prohibition state, it is confirmed whether or not the above-mentioned out-of-ball state flag or full tank flag is turned on (step S161).

[0240] When any of them changes to the ON state,
The payout stop flag is set (step S16).
2) The command transmission table relating to the payout prohibition state designation command is set (step S163), and the command setting process is called (step S164). In step S163, a command transmission table (RO that stores the payout control command of the payout prohibition state designation command).
The start address of M) is set as the address of the command transmission table. The command transmission table relating to the payout prohibition state designation command includes INT data, which will be described later,
Data of the first byte of the payout control command and data of the second byte of the payout control command are set. In step S161, when one of the flags is already in the on state and the other flag is in the on state, steps S162 to S16.
The process of 4 is not performed.

If it is in the payout prohibition state, it is confirmed whether or not both the out-of-ball state flag and the full tank flag are turned off (step S165). When both are in the off state (when the release condition described later is satisfied), the payout stop flag is reset (step S166), and the command transmission table relating to the payable state designation command is set (step S167). The set process is called (step S168). In step S167, the head address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payable state designation command, INT data, which will be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

The cancellation condition is a condition for canceling the payout prohibition state and is satisfied when it is no longer necessary to maintain the payout prohibition state. In this example, the cancellation condition is that the surplus ball receiving tray 4 is used when the payout prohibition state is set.
Is said to be in a state that is not full and is not out of ball.

Further, the CPU 56 sets "0" as the offset of the input judgment value table (step S16).
9), "0" is set as the offset of the switch timer address (step S170). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 18, the switch timer address offset “0” specifies the switch timer corresponding to the winning opening switch 33a. Means Also, "4" is set as the number of repetitions (step S171).
Then, the switch-on check routine is called (step S172).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 35) (step S281). And
An offset is added to the address (step S28
2) The switch-on determination value is loaded from the added address (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the added address (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 18, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, the switch-on flag is set (step 228).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value "2", the switch-on flag is set (step S1).
73). Then, the switch check-on routine is executed for the number of repetitions set initially (steps S176, S177) while the address offset of the switch timer is updated (step S178).
After all, the winning opening switch 33a, 39a, 29a, 30a
For, the value of the corresponding switch timer is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" as the number of prize balls to be paid out is set in the ring buffer (step S174). Then, 10 is added to the value stored in the total prize ball number storage buffer (unpaid amount data) (step S175). When data is written in the ring buffer, the write pointer is incremented, and when data is written in the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball numbers instructed to the payout control means (however, the value is subtracted when the payout is made).
It is formed in the backup RAM. In this embodiment, when the data is written in the ring buffer, addition processing is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, addition processing of the number of prize balls corresponding to the payout control command to be output may be performed on the stored value of the total prize ball storage buffer.

Next, the CPU 56 sets "0" as the offset of the input judgment value table (step S17).
9), "5" is set as the offset of the switch timer address (step S180). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 18, the offset "5" of the address of the switch timer specifies the switch timer corresponding to the starting port switch 14a. Means Then, the switch-on check routine is called (step S
181).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a matches the switch-on determination value "2", the switch-on flag is set (step S182). When the switch-on flag is set, "6" as the number of prize balls to be paid out is set in the ring buffer (step S183). In addition, the value stored in the total prize ball storage buffer is 6
Is added (step S184).

Next, the CPU 56 sets "0" as the offset of the input determination value table (step S18).
5), "6" is set as the offset of the switch timer address (step S186). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 18, the offset “6” of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S
187).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value "2", the switch-on flag is set (step S188). When the switch-on flag is set, "15" as the number of prize balls to be paid out is set in the ring buffer (step S189). In addition, 15 is added to the value stored in the total prize ball storage buffer (step S190).

If data exists in the ring buffer (step S191), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S192), and the value of the read pointer is updated (in the ring buffer). It is updated to point to the next area (step S193), the command transmission table regarding the number of prize balls is set (step S194), and the command setting process is called (step S195). The operation of the command set process will be described later in detail.

In step S194, the start address of the command transmission table (ROM) in which the payout control command relating to the number of prize balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of prize balls includes INT data (01
(H)), the first byte of the payout control command (F
0 (H)), and the data of the second byte of the payout control command are set. However, "80 (H)" is set as the second byte of data.

As described above, when the payout control command for instructing the number of prize balls is output from the game control means to the payout control board 37, the address setting of the command transmission table regarding the number of prize balls and the setting of the transmission buffer are performed. Is done. Then, by the command setting process, the payout control command is sent to the payout control board 37 based on the command transmission table regarding the number of prize balls and the setting contents of the transmission buffer. In step S191, it is possible to confirm whether or not there is data by the difference between the write pointer and the read pointer. You may confirm whether or not.

Then, the content of the total prize ball number storage buffer is 0.
If not, that is, if there is still a prize ball left, C
The PU 56 turns on the prize ball payout flag (step S
196, S197).

When the prize ball payout flag is on (step S198), the CPU 56 monitors the number of prize balls actually paid out from the ball payout device 97 and stores the total prize ball number storage buffer. The number of prize balls subtraction processing for subtracting the value is performed (step S199). When the prize-ball paying-out flag changes from on to off, the lamp control board 3
5, a lamp control command for instructing lighting of the prize ball lamp 51 is transmitted.

Upon receipt of the payout prohibition state designation command, the payout control means stops both the ball payout as a prize ball and the ball payout as a ball lend. When the payable state designation command is received, both the ball payout as a prize ball and the ball payout as a ball lend are made possible. However, from the game control means to the payout control means, a payout control command for stopping or restarting ball payout as a prize ball and a payout control command for stopping or restarting ball payout as a ball lending are different control commands. You may make it transmit as.

Further, in this embodiment, even when the payout is stopped (steps S160 and S165), the step S is performed.
The processing of 169 to S195 is executed. That is, the game control means can send a payout control command for instructing the number of prize balls even in the payout prohibited state.
That is, the command for instructing the number of prize balls is transmitted to the payout control means even in the payout prohibited state, and when the payout prohibited state is released, the prize ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of prize balls based on the winning in the payout prohibition state.

Further, in this embodiment, the processing of steps S169 to S195 is executed regardless of the payout status of the game medium. That is, the game control means can send a payout control command for instructing a new prize ball number, regardless of whether or not the specified number of prize balls has been paid out up to the previous time. Therefore, it is possible to reduce the processing load related to the payout of the game control means, and to quickly perform the prize ball payout processing.

Next, a method of sending a control command from the game control means to each electric component control means will be described. When the control command is to be output from the game control means to another electric component control board (sub board), the start address of the command transmission table is set. Figure 3
FIG. 6A is an explanatory diagram showing a configuration example of a command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the 1st byte.
The MODE data of the first byte of the control command is set in the command data 1 of the second byte. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

The EXT data itself may be set in the area of the command data 2, but the command data 2
May be set with data for designating the address of the table in which the EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, command data 2 is EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
In this embodiment, if the work area reference bit is 1, it indicates that the content of the transmission buffer is used as the EXT data. If the work area reference bit is 1, the other 7 bits can be configured to indicate that the other 7 bits are an offset for designating the address of the table in which the EXT data is stored.

FIG. 36B is an explanatory diagram showing a structural example of INT data. Bit 0 in INT data
Indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, CPU5
6 is, for example, prize ball processing (step S32 of the main processing)
In, the INT data is set to "01 (H)".
Bit 1 in the INT data indicates whether or not a display control command should be sent to the symbol control board 80.
If bit 1 is "1", it indicates that the display control command should be sent. Therefore, the CPU 56, for example, special symbol command control processing (step S2 of the main processing
In 8), "02 (H)" is set to the INT data.

Bits 2 and 3 of the INT data are bits indicating whether or not to send a lamp control command and a sound control command, respectively, and the CPU 56 outputs a special command at the timing to send these commands. In the symbol process processing or the like, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When sending those commands, the corresponding bit of the INT data is set to "1", and the command data 1 and the command data 2 are MOD.
E data and EXT data are set.

In this embodiment, for the payout control command, a ring buffer and a transmission buffer are prepared as shown in FIG. 36 (C). Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. Also, when sending the payout control command regarding the number of prize balls,
One data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 36C, the ring buffer can store data corresponding to 12 payout control commands. That is, there are 12 buffers. The number of buffers in the ring buffer may be any number corresponding to the number of winning openings for generating prize balls. This is because even if the simultaneous winnings occur, it is possible to store the payout control command data based on the respective winnings.

FIG. 37 is an explanatory diagram showing an example of the command form of the control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always "1", and the first bit (bit 7) of the EXT data is always "0". As described above, the control command, which is a command to the electric component control board, is composed of a plurality of data, and can be distinguished by the leading bit. Note that the command form shown in FIG. 37 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used. Further, although FIG. 37 exemplifies the payout control command sent to the payout control board 37,
The control commands sent to the other electric component control boards have the same configuration.

FIG. 38 is an 8-bit control signal CD0-CD forming a control command for each electric component control means.
7 is a timing diagram showing the relationship between 7 and the INT signal. As shown in FIG. 38, when the period indicated by A has elapsed since the MODE or EXT data was output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data. INT which is the signal
Set the signal to high level (on data). When the period indicated by B elapses, the INT signal is set to low level (off data). Furthermore, if there is data to be sent next, that is, after sending the MODE data, the data of the second byte is sent to the output port after a period indicated by C. Regarding the data of the second byte, the periods A and B are the same as the case of the first byte.
In this way, the capture signal is output for each of MODE and EXT data.

The period A is a period during which the CPU 56 prepares to send a command, that is, a period required to set a send command in the buffer, and is a period for stabilizing data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal as a capture signal is output after a predetermined period (period of A: part of the off output period) has elapsed. Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the OFF output period) is a period in which the electric component control unit is set so that the data can be reliably fetched. In the period of B and C,
The data on the signal line does not change. That is, the data output is maintained until the B and C periods elapse.

In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal for the first byte to the start of the transmission of the data of the second byte, is longer than the reception processing time in the electric component control means that takes the longest time for the command reception processing. Is also set to be long.

Note that each electric component control means detects that the INT signal has risen, and starts the processing of fetching 1-byte data by interrupt processing, for example.

Since the periods B and C are longer than the reception processing time in the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing to each electric component control means by the common module. However, any electric component control means can surely receive the control command from the game control means.

The CPU 56 is ready to send the next data when a predetermined period of time has elapsed after executing the INT signal output process, but during the predetermined period (B and C periods), the IN
It is longer than the period (period A) from the transmission of data before the T signal output process to the start of output of the INT signal. As described above, the period A is the stabilization period in the command signal line, and the periods B and C are the periods for ensuring the time required for the receiving side to take in the data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can surely receive the command, and the transmission of one command is completed. There is also an effect that the period required for is shortened.

FIG. 39 is an explanatory diagram showing an example of the contents of the payout control command. In this example, a plurality of types of payout control commands are used to execute the payout control. Figure 3
In the example shown in FIG. 9, MODE = FF (H), EX
The command FF00 (H) of T = 00 (H) is a payout control command (payable state designation command) for instructing that the payout is possible. MODE = FF (H), EX
The command FF01 (H) of T = 01 (H) is a payout control command (payout prohibition state designation command) for instructing that the payout should be prohibited. Also, MODE
The command F0XX (H) of = F0 (H) is a payout control command (payout number designating command) for designating the number of prize balls. “XX”, which is EXT, indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout ball payout and the ball lending are stopped, and FF00.
When the payout control command (H) is received, prize balls can be paid out and balls can be lent. Further, when the payout control command for designating the number of prize balls is received, the prize ball payout control according to the number designated by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the level of the INT signal changes, and “recognitionally being sent only once” means that in this example, the payout control signal is sent to each of the first byte and the second byte. Accordingly, the INT signal is output only once in a pulse shape (rectangular wave shape).

A control command for each electric component control board is
When outputting to the corresponding output port (output ports 1 to 4), one of the bits 0 to 3 of the output port 0 becomes "1" (high level) for a predetermined period. And the bit array in the output port 0 correspond to each other. Therefore, when the control command is sent to each electric component control board, the INT signal can be easily output based on the INT data.

FIG. 40 is an explanatory diagram showing an example of the contents of the display control command sent to the symbol control board 80. In the example shown in FIG. 40, commands 8000 (H) -80
XX (H) (X = any value of 4 bits) is a display control command that specifies a variation pattern of the special symbol in the variable display device 9 that variably displays the special symbol. The command for designating the variation pattern also serves as a variation start instruction.

Commands 8F00 (H) and 8F01
(H) is a special symbol power-on designation command (an example of an initial display mode command) and a normal symbol power-on designation command (an example of an initial display mode command) that are sent out when the power is turned on. The initial display mode command is a command for instructing the mode (initial display mode) of the identification information to be displayed on the variable display device 9 at the start of power supply, and for instructing the display of the initial display mode. Specifically, the initial display mode command is, for example, that data indicating the initial display mode is stored in a predetermined area of the character ROM 86, and data indicating the initial display mode is read from the predetermined area of the character ROM 86. This is a command for instructing the variable display device 9 to display. In addition,
The initial display mode command is, for example, a command instructing that the initial display mode is a special symbol of “7”, “8”, and “9” and that the initial display mode is displayed on the variable display device 9. May be said. The normal symbol power-on time designation command is used when the display control means performs the normal symbol variation control, and the normal symbol display device 1
When 0 is controlled by the lamp control means, it is not sent to the symbol control board 80. When the display control means receives the special symbol power-on time designation command, it starts the control for initial display.

Commands 91XX (H), 92XX (H)
And 93XX (H) is a display control command for designating the left middle right stop symbol of the special symbol. Also, command A
000 (H) is a display control command (decision command) for instructing to stop the variable display of special symbols.

The command BXXX (H) is a display control command sent from the start of the big hit game to the end of the big hit game. The command B1XX (H) is a display control command for designating the display of the number of times of opening the special winning opening (the number of rounds) during the big hit game. Command B2
00 (H) is a display control command for designating a display indicating the start of the big hit game when the big hit game is started. Command B2XX (H) (XX = 01 or more)
Is a display control command for designating a display before the opening of the special winning opening (for example, a display notifying what round the round to be executed is) during the big hit game. The command B400 (H) is a command to be transmitted a predetermined number of times (for example, a timing at which a big hit symbol is displayed during each round, the number of rounds-1 times) at a predetermined timing during a big hit game. It is a display control command (big hit symbol display command) for designating the display of symbols. Command B500 (H) is
It is a display control command for designating a display indicating that the non-specific big hit (indeterminate big hit) has ended. The command B501 (H) is a display control command for designating a display indicating that the specific big hit (probable variation big hit) has ended. Further, the command CXXX (H) is a display control command concerning the display state of the variable display device 9 which is not related to the variation of the special symbol and the big hit game. Then, the commands D000 (H) to D400 (H) are display control commands related to the variation pattern of the normal symbols.

When the display control means of the symbol control board 80 receives the above-mentioned display control command from the game control means of the main board 31, the variable display device 9 and the ordinary symbol display device 10 according to the contents shown in FIG. Change the display status.

FIG. 41 is an explanatory diagram showing an example of the contents of the lamp control command sent from the main board 31 for controlling the game to the lamp control board 35. The lamp control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 41, the command 80XX (X = any value of 4 bits) is a lamp control command for designating a lamp / LED display control pattern corresponding to the variation pattern of the special symbol in the variable display device 9. Also, the command A0X
X (H) is the lamp / L when the variable display of special symbols is stopped
The ED display control pattern is a lamp control command, and the command BXXX (H) is a lamp / LED display control pattern instruction from the big hit game start to the big hit game end. The command 9001 (H) is a lamp control command for instructing the lamp / LED display control pattern at the customer waiting demonstration.

It should be noted that the commands 8XXX (H), 9XXX
(H), AXXX (H), BXXX (H) and CXX
X (H) is a lamp control command sent from the game control means according to the game progress status. When the lamp control means receives the above-mentioned lamp control command from the game control means of the main board 31, it changes the display state of the lamp / LED according to the contents shown in FIG. In addition, command 8
XXX (H), 9XXX (H), AXXX (H), BX
XX (H) and CXXX (H) are commonly used with a display control command and a voice control command, for example, in a common control state.

The command E0XX (H) is a lamp control command indicating the number of lighting of the start memory indicator 18. For example, the lamp control means turns on the number of displays designated by “XX (H)” in the start memory display 18. Further, the command E1XX (H) is a lamp control command indicating the number of lights of the normal symbol starting memory display 41. For example, the lamp control means normally turns on the number of display devices designated by "XX (H)" in the symbol starting memory display device 41. That is, those commands are commands for instructing the control of the light-emitting body provided for notifying the information of the number of holdings. The command regarding the number of lighting of the starting memory display 18 and the normal symbol starting memory display 41 may be configured to indicate the increase or decrease of the number of lighting.

Commands E200 (H) and E201
(H) is a lamp control command relating to the display state of the prize ball lamp 51, and includes commands E300 (H) and E3.
01 (H) is a lamp control command related to the display state of the out-of-bulb lamp 52. The lamp control means is the main board 3
When the lamp control command of "E201 (H)" is received from the game control means of No. 1, the display state of the prize ball lamp 51 is changed to a predetermined display state when there is a prize ball remaining, and the lamp of "E200 (H)" is displayed. When the control command is received, the display state of the prize ball lamp 51 is changed to a predetermined display state as when there is no prize ball remaining. When the lamp control command of "E300 (H)" is received from the game control means of the main board 31, the display state of the out-of-ball lamp 52 is changed to the display state with a ball, and the lamp control command of "E301 (H)" is issued. When it is received, the display state of the out-of-ball lamp 52 is changed to the in-bulb display state. That is, the command E2
00 and E201 (H) are commands indicating that a light emitting body provided for notifying a player or the like that there is a non-prize game ball, and a command E300.
(H) and E301 (H) are commands indicating that the light emitters provided for notifying the player or the game clerk that the supply ball has run out are controlled.

FIG. 42 is a flow chart showing a processing example of the command set processing (steps S164, S168, S195). The command set process is a process including a command output process and an INT signal output process. In the command setting process, the CPU 56 first saves the address of the command transmission table (contents of the pointer as the transmission signal instruction means) to the stack or the like (step S3).
31). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore,
The address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sends the command data 1
Is read out and is set to the argument 2 (step S334).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S335).

FIG. 43 is a flow chart showing the command transmission processing routine. In the command transmission processing routine, the CPU 56 sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). In addition,
The command transmission flag is a flag indicating whether or not command transmission processing is in progress, and is stored in a predetermined area of the RAM 55. Next, the CPU 56 sends the number of transmissions = 4.
Is set in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of the output port for outputting the payout control signal. Further, the addresses of the ports 2 to 4 are the addresses of the output ports for outputting the display control signal, the lamp control signal and the voice control signal.

Next, the CPU 56 shifts the comparison value right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S355). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S3
56). When the first shift processing is performed, the address of port 1 is set as the IO address, so the MODE data of the payout control command is set to port 1 at that time.
Is output to.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the processing number (step S358). When the port 1 is shown before the addition, the address of the port 2 is set to the IO address by the addition process for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0,
It returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not the lamp control command and the sound control command should be sent. In this way, when each shift process is performed, the IO address has the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process. It is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
A control command is sent to. That is, one common module can perform a process of sending a control command to each electric component control means.

Further, in this way, since it is judged which electric component control means the control command should be outputted only by the shift processing, it is judged which electric part control means the control command should be outputted to. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 in which the INT data before the shift processing is started (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is a port for outputting the INT signal for each control signal, and bit 0 of port 0
4 to 4 are the payout control INT signal and the display control IN, respectively.
It is a port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and decrements by 1 until the value becomes 0 (steps S363, S36).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S36).
5) output the data to port 0 (step S3)
66). Therefore, the INT signal becomes low level. Further, a predetermined value is set in the wait counter (step S3
62), and subtracts 1 by 1 until the value becomes 0 (steps S368 and S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time that is generated in steps S367 to S369 and the subsequent processing time (if MODE data is output at this time, the time required for control until the EXT data is output). ) Is the period added. By setting the period of C in this way,
Even when the commands are continuously sent, a predetermined period of time elapses after the output of one command is completed and before the sending of the next command is started, and the electric component control means for receiving the command. On the side of, the command delimiters can be easily identified and each command is reliably received.

Therefore, the value set in the wait counter in step S367 is such that the period C is a period sufficient for surely performing the command receiving process by all the electric component control means which are the control command receiving targets. Value. The value set in the wait counter is
The value is longer than the time (corresponding to the period A) required for the processes of steps S357 to S359. In addition, A
If it is desired to lengthen the period A, a wait process for creating the period A (for example, a process of setting a predetermined value in the wait counter and performing subtraction until the value of the wait counter becomes 0) is performed.

As described above, the 1st byte MODE data of the control command is transmitted. Therefore, CPU5
42. In step S336 shown in FIG. 42, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S338). If not 0, the contents of the transmission buffer are loaded into the argument 2 (step S339). If the extended data is used when the value of the work area reference bit is "1", the start address of the command extended data address table is set in the pointer and the command data is set in the pointer. The address is calculated by adding the values of bit 6 to bit 0 of 2. Then, the data of the area pointed to by the address is loaded into the argument 2.

Since data capable of specifying the number of prize balls is set in the transmission buffer, the data is set in the argument 2. If the extended data is used when the value of the work area reference bit is “1”, the command extended data address table contains
EXT data that can be sent to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table according to the content of the command data 2 is loaded into the argument 2.

Next, the CPU 56 calls the command transmission processing routine (step S340). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent out.

As described above, the 2-byte control command (payout control command, display control command, lamp control command, sound control command) is transmitted to the corresponding electric component control means. The electric component control means starts the control command fetching process when the rising edge of the INT signal is detected. However, the wait period set to end after the command receiving process in each electric component control means (step S367 to step S369
Since a new signal is not output until the period specified by the process of (part of the period of C) elapses, for any electric component control means, the game control is performed before the capture process is completed. No new signal from the means is output to the signal line. That is, a reliable command reception process is performed in each electric component control means. It should be noted that each electric component control means may start the control command acquisition process at the fall of the INT signal. Also,
The polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, in the award ball processing, when the award ball payout condition is satisfied, data capable of specifying the number of award balls is stored in the ring buffer capable of storing a plurality of data at the same time, and When the payout control command designating the is sent, the data in the area of the ring buffer pointed by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of prize ball payout conditions are satisfied at the same time, the data capable of specifying the number of prize balls based on the satisfaction of those conditions is stored in the ring buffer, so that the command output process based on the satisfaction of each condition does not pose a problem. To be executed.

Furthermore, in this embodiment, both the payout prohibition state designation command or the payout possible state designation command and the command indicating the number of prize balls can be sent in one prize ball process. That is, 1 is activated every 2 ms
Multiple commands can be sent within one control period. Further, in this embodiment, since a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, payout control command) to each control means, for example, When data capable of specifying the control command is set in the ring buffer of the control command, the lamp control command, and the sound control command, a plurality of display control commands, lamp control commands, and sound control commands can be performed by one command control process. Can also be configured to deliver. That is, a plurality of control commands can be sent at the same time (meaning in the activation cycle of the game control process, that is, the 2 ms timer interrupt process). Since the transmission timings of those control commands occur at the same time in the progress of the game production, it is convenient to have such a configuration. However, since the payout control command is generated regardless of the progress of the game effect, in general, the display control command,
It is not sent at the same time as the lamp control command and the sound control command.

FIG. 44 is a flow chart showing an example of the award ball number subtracting process. In the process of subtracting the number of prize balls, C
The PU 56 first loads the value stored in the total prize ball number storage buffer (step S381). Then, it is confirmed whether the stored value is 0 (step S382). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the load value and the ON determination value (in this case, "2") are compared (step S384). If they match (step S38)
5) Assuming that the prize ball count switch 301A is turned on, that is, one game ball is certainly one ball payout device 9
The value stored in the total prize ball number storage buffer is decremented by 1 assuming that the payout is made from 7 (step S386).

Also, the value of the prize ball information counter is incremented by 1 (step S387). When the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information output counter is incremented by 1 (step S38).
9), the value of the prize ball information counter is decremented by 10 (step S
390). The value of the prize ball information output counter is shown in FIG.
Referred to in the information output process (step S30) in the game control process shown in, and if the value is 1 or more, it is set as 1 as a prize ball signal (bit 7 of output port 5: see FIG. 17).
A pulse is output. Therefore, in this embodiment, 1
Each time 0 game balls are paid out as a prize ball, one prize ball signal is output to the outside of the gaming machine.

When the value stored in the total prize ball number storage buffer becomes 0 (step S391), the prize ball payout flag is cleared (step S392) to notify that there is no remaining prize ball number. After the command data indicating that the prize ball lamp 51 is turned off is set in the command transmission table for the lamp control command (step S393), the lamp control command sending process is executed (step S394).

Next, the payout control means will be described as an example of the electric component control means other than the game control means. Figure 45
FIG. 3 is a block diagram showing a configuration example around a payout control CPU 371. As shown in FIG. 45, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 980. There is.
Therefore, the payout control CPU 371 can confirm the occurrence of power failure by the non-maskable interrupt process. The reset signal and the return signal from the power supply board 910 are input to the AND circuit 385, and the output of the AND circuit 385 is input to the reset terminal of the payout control CPU 371.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. Then, when the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt will occur in response to the input of the INT signal. The INT signal is a signal that means that a payout control command has been sent from the game control means to the payout control means. The payout control CPU 371 starts the payout control command reception process by an interrupt generated in response to the input of the INT signal.

FIG. 46 is an explanatory diagram showing output port allocation in this embodiment. As shown in FIG. 46, the output port C (address 00H) is connected to the payout motor 2
89 is an output port for driving signals and the like output to 89. Further, the output port D (address 01H) is an output port of a display control signal output to the error display LED 374 which is a 7-segment LED. And output port E
(Address 02H) is the drive signal output to the distribution solenoid 310 and the EX to the card unit 50.
It is an output port for outputting the S signal and the PRDY signal.

FIG. 47 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 47, the input port A (address 06H) is an input port for taking in the 8-bit payout control signal of the payout control command sent from the main board 31. Further, the detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Detection signal is input.

FIG. 48 is a payout control means (CP for payout control).
7 is a flowchart showing a main process of U371 and peripheral circuits such as ROM and RAM. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and the stack pointer designated address is set to the stack pointer (step S703). Further, the payout control CPU 37
1 initializes built-in device registers (step S704), and initializes CTC and PIO (step S704).
After performing 705), the RAM is set to the accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the built-in device register setting processing of step S704 and the processing of step S705, register setting for setting the channel to be used in timer mode, register setting for permitting interrupt generation, and register for setting interrupt vector Settings are made. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set in the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, payout control process is executed.

Further, another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving the payout control command from the game control means, and that channel is used. Is used in counter mode. Therefore, in the built-in device register setting processing of step S704 and the processing of step S705, in order to set the register setting for setting the channel to be used in the counter mode, the register setting for permitting interrupt generation, and the interrupt vector. Register setting is performed.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set the interrupt processing start address according to the interrupt vector sent by the CTC.

The interrupt based on the count-up of the channel 2 (CH2) of the CTC is an interrupt that occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as the specific register
An initial value "1" is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rising or falling of the signal input to the CLK / TRG2 terminal. You can make a choice. In this embodiment, the timer counter register CLK / TRG is output at the rising edge of the signal input to the CLK / TRG2 terminal.
The count value of 2 is set to -1.

The interrupt based on the count-up of the CTC channel 3 (CH3) is an interrupt that occurs when the register value becomes "0" by counting down the internal clock (system clock) of the CPU, and will be described later. 2m
s Used as a timer interrupt. Specifically, CPU3
A clock obtained by dividing the operation clock of 71 is given to the CTC, the value of the register is subtracted by the input of the clock, and when the value of the register becomes 0, a timer interrupt is generated.
For example, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the CH3 register.

An interrupt based on CTC CH2 count-up has a higher priority than an interrupt based on CH3 count-up. Therefore, when count-ups occur at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process is prioritized.

Next, the payout control CPU 371 confirms the state of the output signal of the clear switch 921 input via the input port B (see FIG. 47) only once (step S707). When ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S714). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 372, the on state of the clear switch signal is high level. Further, the payout control means does not have to make the determination in step S707.

Note that, like the CPU 56 of the main board 31, the payout control CPU 371 also determines that the ON state is at least 2 when the ON detection of the switch detection signal is performed.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms) does not continue, it is not considered to be switch-on, but when the clear switch 921 is detected to be on, ON / OFF is determined by the ON determination. That is, it is determined whether or not the clear switch 921 as the operating means is in a predetermined operating state.
The initialization request detection determination period for U371 to determine is
The period is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detecting means has detected the game medium.

If the clear switch 921 is not turned on, the payout control CPU 371 confirms whether or not backup data exists in the payout control backup RAM area (step S708). For example, similar to the processing of the CPU 56 of the main board 31, whether or not backup data exists is determined by whether or not the backup flag that is set when the power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

When it is confirmed that there is a backup, the payout control CPU 371 performs a data check of the backup RAM area (parity check in this example). When the power is restored after the power supply is stopped due to an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, it is not possible to return the internal state to the state at the time of stopping the power supply, so the initialization process executed when the power is turned on is executed instead of when the power is restored from an insufficient power failure.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state at the time of stopping the power supply (step S710). Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
First performs a RAM clear process (step S71).
1). Then, the CTC provided in the payout control CPU 371 so that a timer interrupt is periodically applied every 2 ms.
The register is set (step S712). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Further, in this example, the payout control CPU 371 sets the payout prohibition state as an initial state (step S713). When the payout prohibition state is set, for example, the driving of the payout motor 289 is stopped and an internal flag (payout stoppage flag) indicating that the payout is stopped is set. That is, in step S713, a process of storing data indicating that the payout is prohibited (a set payout suspension flag) in a predetermined storage area is executed. The payout suspension flag will be described in detail later. Since the interrupt is prohibited in step S701 of the initialization process, the interrupt is permitted before the initialization process is completed (step S714).

In this embodiment, the payout control CPU 3
71 built-in CTCs are set to repeatedly generate timer interrupts. In this embodiment, the repetition period is 2
Set to ms. And when a timer interrupt occurs,
As shown in FIG. 49, a timer interrupt flag indicating that there is a timer interrupt is set (step S792).
Then, in the main process, when it is detected that the timer interrupt flag is set (step S715), the timer interrupt flag is reset (step S715).
751), payout control process (steps S751 to S76)
0) is executed.

In the timer interruption, as shown in FIG. 49, the interruption permission state is first set (step S79).
1). Therefore, during the timer interrupt process, the interrupt enable state is set, and the payout control command reception process based on the input of the INT signal can be preferentially executed.

In the payout control process, the payout control CPU
371: First, the prize ball count switch 301A and the ball lending count switch 3 input to the input port 372b.
It is determined whether a switch such as 01B is turned on (switch process: step S752).

Next, the payout control CPU 371 sets the payout prohibited state when the payout prohibited state designation command is received from the main board 31, and releases the payout prohibited state when the payable state designation command is received. (Payout prohibited state setting process: step S753). Further, it analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S754). Further, prepaid card unit control processing is performed (step S755).

Next, the payout control CPU 371 controls the payout of the lent balls in response to the ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the prize ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the 72c and the relay board 72 to perform payout motor control processing for rotating the payout motor 289 for a predetermined number of rotations (step S758). .

Incidentally, in this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control process, eight types of excitation pattern data are repeatedly output to the payout motor 289. Further, in this embodiment, each excitation pattern data is output by 4 ms.

Next, error detection processing is performed, and a predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

The output port C shown in FIG. 46 has a payout motor control process (step S75) in the payout control process.
Accessed in 8). Further, the output port D is accessed by the error processing in the payout control processing (step S759). Then, the output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 50 is a flow chart showing an example of the payout state recovery process of step S710. In the payout state recovery process, the payout control CPU 371 first performs a stack pointer return process (step S73).
1). The value of the stack pointer is saved in a predetermined RAM area (power source is backed up) in the power supply stoppage process described later. Therefore, step S7
At 31, the value in the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the payout control CPU 371 sets the payout prohibition state in this example as the state related to the payout to be restored (step S732). When the payout prohibition state is set, for example, the driving of the payout motor 289 is stopped and an internal flag (payout stoppage flag) indicating that the payout is stopped is set. That is, in step S732, a process of storing the data indicating that the payout is prohibited (the set payout suspension flag) in a predetermined storage area is executed. The payout suspension flag will be described in detail later.

Further, the payout control CPU 371 clears the backup flag (step S733), that is, resets the flag indicating that a predetermined storage protection process has been executed at the previous power supply stop. Further, the save values of various registers are read from the stack area and set in the various registers (step S734). That is, register restoration processing is performed. Then, when the parity flag is not turned on, the interrupt enable state is set (step S7).
35, S736). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S737).

Then, the RET instruction is executed, but the return destination here is not the portion that called the payout state recovery processing. This is because the stack pointer restoration process is performed in step S731, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred at the time of the previous power supply stop in the program. Therefore, the next RET instruction in step S737 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

51 to 53 are non-maskable interrupt processing (N) executed in response to a power-off signal from the power supply board 910.
It is a flow chart which shows the example of processing of MI processing: processing at the time of power supply stop. In this example, the process at the time of stopping the power supply is executed according to the NMI, but a power-off signal is sent to the payout control C
You may connect to the maskable terminal of PU371 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

In the non-maskable interrupt process, the payout control CPU 371 sets the AF register to a predetermined backup R.
It is saved in the AM area (step S801). Also, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, IX register and stack pointer are saved in the backup RAM area (steps S804-8).
08). When the power is restored, the register contents are restored based on the saved contents, and the interrupt enable / disable state is internally set according to the contents of the parity flag.

In this example, as the payout motor 289, a stepping motor that is rotated by a pulse signal (drive signal) from the payout control CPU 371 is used. Therefore, the driving of the ball payout device 97 is stopped by stopping the output of the pulse signal to the payout motor 289.

Next, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S809), and sets the number of processes (“2” in this example) in another register (step S810). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S811). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S81).
2), the value of the IO pointer is incremented by 1 (step S81
3), 1 is subtracted from the value of the number of processes (step S814).
In the processes of steps S812 to S814, the value of the number of processes is 0.
Is repeated (step S815). As a result, clear data is set in the output port C and the output port D (see FIG. 46). As shown in FIG. 46, in this example, “1” is in the ON state and clear data “00” is set in each output port, so that all the output ports C and D are off. It becomes a state. In this example, since the output port E is not cleared, the output port of the distribution solenoid 310 is not turned off. Clear processing may be performed on output ports other than the output port of the distribution solenoid 310 in the output port E.

Thereafter, in this embodiment, a prize ball count switch 301A (corresponding to prize game medium payout detection means) and a ball lending count switch 301B as payout detection means for a predetermined period (hereinafter referred to as "payout confirmation period").
The detection signal (corresponding to the rental game medium payout detection means) is checked. When the prize ball count switch 301A is turned on, the content of the total number memory is decremented by 1. When the ball lending count switch 301B is turned on, the content of the number of lent balls is reduced by one.

In this embodiment, a payout confirmation period measuring counter is used to measure the payout confirmation period. The value of the payout confirmation period measurement counter is the initial value m.
From the loop of the switch detection processing described below (S8
It is assumed that the payout confirmation period ends when the loop starting from 17 and returning to S817) is performed by -1 each time the value becomes 0. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore, a time m times the time required for one round of the loop is substantially equivalent to the payout confirmation period.

The built-in timer of the payout control CPU 371 may be used to measure the payout confirmation period. That is, a predetermined value (corresponding to the payout confirmation period) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the payout confirmation period has ended. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program. Also, during the payout confirmation period, the game ball is the ball payout device 9
Award ball count switch 301 from the time of dropping from 7
It is set to be equal to or longer than the time required to reach A or the ball lending count switch 301B.

At least the payout confirmation period in which the switch detection processing is executed (the period from the time when the game ball falls from the ball payout device 97 to the time when it reaches the prize ball count switch 301A or the ball lending count switch 301B).
For example, about 100 [ms] to 150 [ms]. ), The prize ball count switch 301A and the ball lending count switch 301B must be in a state where the game ball can be detected. Therefore, in this embodiment, as shown in FIG. 11, the converter IC in the power supply board 910 is
A capacitor 923 serving as an auxiliary drive power source having a relatively large capacity is connected to the input side of 920. Therefore, even when the power supply to the gaming machine is stopped, + 12V for a certain period
The power supply voltage is maintained within a switchable range, and the prize ball count switch 301A and the ball lending count switch 301B become operable. The capacity of the capacitor is determined so that the period is longer than the payout confirmation period. The longer the payout confirmation period is, or the longer the switchable period is longer than the payout confirmation period, the larger the capacity of the capacitor that is needed.Therefore, the payout confirmation period can be set shorter and the switch can be driven. It is advisable not to allow too much margin for a certain period.

The input port and the payout control CPU
Since the 371 is also driven by the + 5V power source created by the converter IC 920, it can be operated for a relatively long period even when the power supply is stopped.

Further, in this embodiment, the distribution solenoid 310 is used to switch between the prize ball path and the rental ball path. Therefore, the capacitor 9 shown in FIG.
The capacity of 24 is such that the distribution solenoid 310 can be driven at least during the above-mentioned payout confirmation period. The capacitor 924 is connected to a line for supplying electric power to each electric component (a line on the input side of the connector 915), but the game control means is operated by another solenoid (large winning opening) in response to the power-off signal. Since the drive signals (for opening and closing, etc.) are in the OFF state, the capacitor 924 needs only to drive only the distribution solenoid 310 among the solenoids after the power-off signal is generated.

The capacitors 923 and 924 used in this embodiment are examples of auxiliary driving power supplies, but other auxiliary driving power supplies may be used. At least during the above payment confirmation period,
Prize ball count switch 301A, ball lending count switch 301B, sorting solenoid 310 and payout control C
As long as the payout control means such as the PU 371 can be driven, an auxiliary drive power source of another aspect can be used.

In the input processing of the detection signal from the payout detecting means (switch detection processing), the payout control CPU 371.
First, the value m corresponding to the payout confirmation period is set in the payout confirmation period measuring counter (step S816). Then, the payout control CPU 371 decrements the value of the payout confirmation period measurement counter by 1 (step S817), and confirms the value of the payout confirmation period measurement counter (step S81).
8). If the value is 0, the switch detection process is terminated and the process proceeds to a process for saving the control state.

If the value of the payout confirmation period measuring counter is not 0, it is confirmed whether or not the prize ball count switch is on (step S819). This confirmation is performed by confirming the state of the flag for turning on the prize ball count switch, which will be described later. If the prize ball count switch ON flag is set, it is determined that the prize ball count switch is ON, the value of the detection period counter is decremented by 1 (step S820), and then the value of the detection period counter is set to 0. It is confirmed whether or not (step S821). If it is 0, prize ball count switch 3 via the input port
If the detection signal of 01A is confirmed (step S822) and it is in the ON state, it is determined that the prize ball count switch 301A is surely turned on and the value of the total number memory is decremented by 1 (step S823).

In step S819, if it is confirmed that the prize ball count switch is not on (the prize ball count switch ON flag is not set), the detection signal of the prize ball count switch 301A is confirmed via the input port. (Step S824) If it is in the on state, the prize ball count switch ON flag is set (step S825), and the initial value n is set in the detection period counter (step S826).

As a result of the above processing, if the prize ball count switch 301A is turned on within the payout confirmation period, the value of the total number stored is decremented by one. Since the processing for storing the contents of the backup RAM is performed after such a switch detection processing, the total number of stored prize balls is always -1. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the above switch detection processing, timer processing using a detection period counter is performed. That is, once the prize ball count switch 301A is detected to be on, a predetermined time (from S817 to S821, S8
If n is not detected even after elapse of n times the processing time in the loop returning to 17: game medium detection determination period), it is not considered to be switch on. In other words, after the first ON detection, when the ON detection is performed after the lapse of a predetermined game medium detection determination period, it is considered that one prize ball has been paid out. Therefore, erroneous switch-on detection can be prevented.

In this case, for example, if n is set so that the game medium detection determination period becomes approximately 2 ms, the game medium detection determination period is set to the normal game medium detection determination period (not the power supply stop process, the normal The period for determining the presence or absence of the game medium in the game state of. In this example, a period of 2 ms or more until it is confirmed that the value of the prize ball count switch on flag is 2 in 751c in FIG. It is possible to have the same period as. According to this structure, it is possible to determine whether or not the prize ball count switch 301A is turned on under substantially the same conditions as in the normal control.

In the normal switch process (step S752 in FIG. 48), the timer process for preventing erroneous detection is also performed. Therefore, you may make it call such a switch process at the time of normal. Although the timer process using the detection period counter is performed here, the CPU built-in timer may be used in the case of measuring the payout confirmation period, as in the switch detection process. You may implement | achieve a timer process.

When the prize ball count switch is not on and the prize ball count switch 301A cannot be detected to be in the ON state, switch detection processing is performed for the ball lending count switch 301B. That is, C for payout control
The PU 371 confirms whether or not the ball lending count switch is on (step S827). If it's on,
After decrementing the detection period counter value by 1 (step S8)
28), it is confirmed whether or not the value of the detection period counter has become 0 (step S829). If it is 0, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S830). The value stored in the number is reduced by 1 (step S831).

In step S827, if it is confirmed that the ball lending count switch is not turned on, the detection signal of the ball lending count switch 301B is confirmed through the input port (step S832), and if it is in the ON state, the ball lending count switch is turned on. The count switch ON flag is set (step S833), and the detection period counter is set to the initial value n.
Is set (step S834).

By the above processing, when the ball lending count switch 301B is turned on within the payout confirmation period, the value of the number of lent balls memorized is decremented by one. The processing for saving the contents of the backup RAM is performed after such a switch detection processing, so that the number of lent balls is always -1 for the lent balls that have been paid out. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the above switch detection processing,
Timer processing using a detection period counter is performed. That is, unless the ball lending count switch 301B is turned on for a predetermined time (game medium detection determination period) or more, it is not considered to be switched on. That is, as in the case of detecting the payout of a prize ball, it is considered that the payout of one loan ball is completed when the ON detection is performed after a predetermined game medium detection determination period has elapsed after the first ON detection. Therefore, erroneous switch-on detection can be prevented.

Further, as in the case of the prize ball payout detection, for example, if n is set so that the game medium detection determination period is approximately 2 ms, the game medium detection determination period is set to the normal game medium detection determination period (power). A period for determining the presence / absence of a game medium in the normal game state, which is not the process at the time of supply stop.In this example, it is confirmed that the value of the ball lending count switch on flag is 2 at 751h in FIG. It is possible to set the same period as the period of 2 ms or more). According to this structure, it is possible to determine whether or not the ball lending count switch 301B is turned on under substantially the same conditions as in the normal control.

When the payout confirmation period has elapsed (step S8)
18), the payout control CPU 371 stores the designated value with backup (“55H” in this example) in the backup flag (step S835). The backup flag is formed in the backup RAM area. Then, the same processing as the processing of the CPU 56 of the main board 31 is performed to create parity data and save it in the backup RAM area (steps S836 to S845). And RA
An access prohibition value is set in the M access register (step S846). After that, the built-in RAM cannot be accessed.

In this embodiment, the RAM area in which the data used in the payout control process is stored is backed up by power supply. Therefore, the checksum generation process indicating whether the contents are correctly stored, and R for preventing the contents from being rewritten
The AM access prevention process corresponds to the process for storing the payout control state.

As described above, in this embodiment, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the ball payout device 97 is stopped, and then the payout confirmation period and the payout detection means are operated. The detection signal input process is executed, and then the process for saving the payout control state is performed. Therefore, the game balls that were being paid out when the power failure occurred are also reflected in the saved contents of the backup RAM.

That is, in this embodiment, in the case where the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent the control contradiction from occurring.

Further, in this embodiment, when the game medium detecting means detects the ON state twice consecutively before and after the predetermined game medium detection determination period, the payout of one prize ball or loan ball is completed. Therefore, it is possible to prevent erroneous switch-on detection. Therefore, it is possible to optimize the control when the power is off.

As described above, in this example, the clearing process of the output ports other than the output port of the distribution solenoid 310 is performed before the switch detection process is executed (before step S762). During execution of the power supply stop process, the payout control CPU 371 and switches are connected to the capacitor 92.
It will be driven by the charging power of 3,924 or the like. In this example, since the output port clearing process is performed before the switch detection process is executed, the capacitor charging power and the like can be efficiently used for the power supply stop process.

When the access prohibition value is set in the RAM access register, the payout control CPU 371 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

In this example, when a power-off signal is generated due to a momentary power-off or the like, the power-supply voltage is restored to the normal value and the gaming machine returns to a controllable state. When such a situation occurs, a return signal is supplied from the power supply board 910 to the payout board 37. When the return signal is input, the payout control CPU 371 is reset. Therefore, the payout control CPU 371 can start execution of the main processing shown in FIG. At that time, since the game state is saved when the power-off signal is output, the payout state recovery process is executed in the process of step S710, and the payout control returns to the state at the time of the power-off signal and the state The payout control is continued from.

Here, the prize ball count switch 3 is used.
Timer (counter for detection period) when the detection signal of 01A or ball lending count switch 301B indicates the ON state
Is set, and if the detection signal shows the ON state even when the timer times out, it is determined that the switch is surely turned ON. However, like the CPU 56 of the main board 31,
The detection signal may be determined each time the ms timer (2 ms measurement counter) times out.

Also in this embodiment, the register saving process is performed at the beginning of the process started in response to the power-off signal, but if the register is not used in the switch detecting process, the switch detecting process The register saving process can be performed after the execution, that is, before the process of setting the backup flag and calculating the checksum. In that case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as the power supply stop process. Further, even when some registers are used in the switch detection process, the register saving process can be performed on the unused registers before the backup flag setting and the checksum calculation process.

FIG. 54 is an explanatory diagram showing a usage example of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number memory (for example, 2 bytes) and a rental ball number memory are formed.
The total number storage stores the total number of prize ball payout numbers instructed from the main board 31 side. The loaned ball number storage is for storing the number of unpaid lent balls. In addition,
The backup RAM area is not limited to the area for storing the above-mentioned information regarding the number of game balls, and various kinds of flags such as a flag indicating an error state such as a payout stop flag, an award ball path error flag, and a backup flag, which will be described later, for example. An area for storing flags, an area for storing various buffers such as a reception command buffer, and the like are also formed. Further, the RAM area in which the data used in the payout control process is stored may be backed up by power supply.

Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in the prize ball control process (step S757), for example, the specified number of contents is stored in the total number memory. To increase. In addition, in the ball lending control process (step S756), the content is increased to the lending ball number storage by one unit (for example, 25) each time the ball lending request signal is received from the card unit 50. Further, the payout control CPU 3
71 is the prize ball count switch 3 in the prize ball control processing.
When 01A detects the payout of one prize ball, the value of the total number of balls stored is decremented by 1. When the ball lending count switch 301B detects the payout of one ball, the value of the stored number of lent balls is decremented by 1.

Therefore, the number of unpaid prize balls and the number of lent balls are backup RAs that can retain their contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply interruption such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the stored contents of the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is made based on the number of unpaid prize balls and the number of lent balls when the power supply is stopped, and is given to the player. The disadvantage can be reduced.

FIG. 55 is an explanatory diagram showing an example of the structure of a reception buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type reception buffer that can store six 2-byte payout control commands is used. Therefore, the reception buffer is composed of 12-byte areas of the reception command buffers 1 to 12. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter takes a value of 0-11.

FIG. 56 is a flow chart showing the payout control command receiving process by the interrupt process. The payout control INT signal from the main board 31 is sent to the payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted and the payout control command reception process shown in FIG. 56 is started. In addition, CP for payout control
The U371 is a CPU having a structure in which, when an interrupt occurs, no further maskable interrupt occurs unless the interrupt is permitted by software.

Although the command receiving process of the payout control means will be described here, the same command receiving process is executed by the display control means, the lamp control means and the sound control means. In this embodiment, CLK /
Although the initial setting was made such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the TRG2 terminal rises, that is, the initial setting is made such that an interrupt occurs at the rising edge of the INT signal. CLK / TRG
When the input of 2 terminals falls, timer counter register C
Initialization may be performed such that the value of LK / TRG2 is decremented by one. In other words, the initialization may be performed so that an interrupt occurs at the falling edge of the INT signal.

That is, if the interrupt is generated at the level change timing (edge) of the pulse (rectangular wave) INT signal as the capture signal, the edge may be a rising edge or a falling edge. It may be. In any case, the interrupt is configured to occur at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the acquisition signal. By doing so, it becomes possible to receive the command promptly at the stage when the command acquisition is instructed. In addition, the period of A (Fig. 3
Since the output of the INT signal is waited until the time (see 8) has elapsed, the control signals CD0 to CD7 are output when the INT signal is output.
The output state of the command data on the line is stable. Therefore, the payout control command is properly received by the payout control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
Data is read from 72a (see FIG. 8) (step S
851). Then, it is confirmed whether or not the read data is within the rule (step S851a). Whether or not the data is within the rule is determined by checking whether or not the structure or content of the received data conforms to a predetermined rule. For example, when the received data has a different number of bytes from the regular command, or when the content of the data is a content that cannot be a regular command, the data is out of the rule. Is determined. If the read data is the data within the rule, it is confirmed whether or not it is the first byte of the payout control command having a 2-byte structure (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is "1". The first bit is "1" in the MODE byte (first byte) of the payout control command having a 2-byte structure (see FIG. 37). Therefore, the payout control CPU 371
If the first bit is "1", it is determined that the valid first byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter in the reception buffer area (step S853).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

If the first byte has already been received,
It is confirmed whether the first bit of the received 1 byte is "0". If the first bit is "0",
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The head bit is “0”, which is supposed to be the EXT byte (second byte) of the payout control command having a 2-byte structure (see FIG. 37). If the confirmation result in step S854 has already received the first byte, the process ends if the first bit of the data received as the second byte is not "0". If it is determined as "N" in step S854, the process of step S856 is not performed, so the command received next is stored in the buffer area where the command received this time should have been stored. It

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether the command reception counter is 12 or more (step S857), and if it is 12 or more, the command reception number counter is cleared (step S858). After that, the saved registers are restored (step S859),
Finally, the interrupt permission is set (step S860).

During the command reception interrupt process, the interrupt is disabled. As described above, since the interrupt is enabled during the 2ms timer interrupt process, if a command reception interrupt occurs during the 2ms timer interrupt process, the command reception interrupt process is executed with priority. It Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since the other interrupt processing is not executed during the command receiving processing, the maximum time required for the command receiving processing is determined. If the other interrupt processing can be executed during the command receiving processing, it is difficult to estimate the maximum time required for the command receiving processing. Since the maximum time required for the command receiving process is determined, the period C in the command sending process of the game control means (see FIG. 38)
Can be accurately determined. More specifically, since the maximum time required for command reception processing is determined, it is possible to accurately determine what the value of the weight counter set in step S367 should be.

The payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX
It is configured so that it can be immediately distinguished from T) on the receiving side.
That is, the receiving side can immediately detect whether the data as MODE or the data as EXT is received by the first bit. Therefore, as described above, it is possible to easily determine whether or not proper data has been received.

FIG. 57 is a flow chart showing an example of the switch process of step S752. In the switch processing, the payout control CPU 371 confirms whether or not the prize ball count switch 301A is in the ON state (step S751a). If it is in the ON state, the payout control CPU 371 increments the prize ball count switch ON counter by 1 (step S751b). The prize ball count switch on counter is the prize ball count switch 30.
This is a counter for counting the number of times the ON state of 1A is detected.

Then, the value of the prize ball count switch ON counter is checked (step S751c), and if the value is 2, it is determined that one prize ball has been paid out. When it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball unpaid counter (the number of prize balls stored in the total number memory: unpaid amount data) by -1. (Step S751d).

If it is confirmed in step S751a that the prize ball count switch 301A is not in the on state, the payout control CPU 371 clears the prize ball count switch ON counter (step S751e). And in this embodiment, the ball lending count switch 3
It is confirmed whether or not 01B indicates the ON state (step S751f). If it is in the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by 1 (step S751g). Ball lending count switch ON counter is ball lending count switch 301
This is a counter for counting the number of times the ON state of B is detected.

Then, the value of the ball lending count switch on counter is checked (step S751h), and if the value is 2, it is determined that one ball has been paid out. When it is determined that one loan ball has been paid out, the payout control CPU 371 causes the loan ball unpaid number counter (the number of loan balls stored in the loan ball number storage:
The unpaid amount data) is decremented by 1 (step S751i).

When it is confirmed in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch ON counter (step S751j).

FIG. 58 is a flow chart showing an example of payout prohibition state setting processing in step S753. In the payout prohibition state setting process, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S753a). If there is a receive command in the receive buffer, it is confirmed whether or not the received payout control command is a payout prohibition state designation command (step S).
753b). If it is a payout prohibition state designation command, the payout control CPU 371 sets the payout prohibition state (step S753c).

When it is confirmed in step S753b that the received command is not the payout prohibition state designation command, it is confirmed whether or not the received payout control command is the payout possible state designation command (step S753d). If it is the payable state designation command, the payout prohibited state is canceled (step S753e).

When setting the payout prohibition state,
For example, the driving of the payout motor 289 is stopped, and an internal flag (payment stopped flag) indicating that the payout is stopped is set. Further, when the payout prohibition state is released, the driving of the payout motor 289 is restarted and the payout stop flag is reset. That is, in step S753c, data indicating that payout is prohibited (set payout suspension flag)
Is being executed in the predetermined storage area, and in step S753e, the processing for storing the data indicating that the payout is permitted (the reset payout suspension flag) in the predetermined storage area is executed. It is running.

The discontinuation flag is stored in, for example, the backup RAM area. The payout suspension flag has a 1-byte structure including bits D0 to D7, for example. In this case, for example, if D0 is "1", the payout prohibition state is set, and if D1 is "1", the payout prohibition state is released. Further, D2 is used, for example, to indicate that it is in a waiting state for return after the payout prohibition state is released. Note that D3 to D7 are unused areas.

Here, the state of the payout suspension flag in the process of FIG. 58 will be specifically described. Step S753c
In the process of, the payout control CPU 371 sets D0 of the payout suspension flag to “0” and sets D1 to “1”. In the process of step S753e, the payout control CPU 371 sets D0 of the payout suspension flag to “1”, sets D1 to “0”, and sets D2 to “1”. When D2 is set to "1", the payout control CPU 371 sets D2 to "0" after a predetermined period (for example, 1 [s]) has elapsed. In this example, the payout suspension flag indicates that when D0 is "0" and D1 is "1",
Indicates that the payout is prohibited. Further, when D0 is “1” and D1 is “0”, it indicates that the payout permission state (the payout prohibition state is released). Note that the payout suspension flag may have a configuration other than the 1-byte configuration, and each bit may be used in another manner (for example, by using only D0, D0 is " The payout prohibited state may be indicated if "0", and the payout permitted state may be indicated if D0 is "1".

When the pay-out prohibited state is set, the pay-out motor 289 may be stopped immediately, but the pay-out motor 289 is not controlled in such a way, but at a good cutting point.
May be stopped. For example, the payout of the game balls may be executed in units of 25, and the payout motor 289 may be stopped when the payout of one unit is completed, and the internal state may be set to the payout prohibited state. As mentioned above,
Since the ball break switch 187 is installed at a position where it can detect that there are 27 to 28 gaming balls in the payout ball passage, even if the game control means of the main board 31 detects the ball breaking. From that point on, at least 25 payouts are possible. Therefore, there is no problem even if the payout prohibition state is set at the time when the payout of one unit is completed. Further, if the payout prohibition state is set for each unit, the control at the time of restarting the payout becomes easy.

FIG. 59 is a flow chart showing an example of the command analysis execution processing of step S754. In the command analysis execution processing, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S754a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for designating the number of prize balls (step S7).
54b). The payout control CPU 371 makes a determination in step S754b for the received command stored at the address in the receive buffer pointed to by the read pointer as the command instruction means. After the determination, the value of the read pointer is incremented by +1. When the address pointed to by the read pointer exceeds the address of the reception command buffer 12 (see FIG. 55), the value of the read pointer is updated to point to the reception command buffer 1.

If the received payout control command is the payout control command for designating the number of prize balls, the number designated by the payout control command is added to the total number memory (step S754c). That is, the payout control CPU 371
Stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

If necessary, the payout control CPU 371 performs the subtraction of the command reception number counter and the reception command shift processing in the reception buffer. Further, the payout prohibition state setting process and the command analysis execution process may be configured to be repeated until the value of the read pointer and the latest command storage position in the reception buffer match. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands, but the repeated processing is executed until they match. , There are no outstanding received commands. That is, all the received commands stored in the reception buffer are read and processed in one process.

60 and 61, step S756 is executed.
It is a flow chart which shows an example of the ball lending control processing of.
In addition, in this embodiment, the maximum value of the continuous payout number is one unit (for example, 25) of the lending sphere, but the maximum value of the continuous payout number may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is suspended (step S510). If it is stopped, the process ends.
Whether or not the ball lending is stopped is confirmed by whether or not the payout stopped flag which is set in the payout prohibition state setting process shown in FIG. 58 is turned on.

If the ball lending is not stopped, the payout control CP
The U371 confirms whether or not the lending of balls is in progress (step S511), and if the lending of balls is in progress, the process proceeds to the process of lending balls shown in FIG. 61. In addition, whether or not the lent-out of the lent-out sphere is being performed is determined by the state of the lent-out-of-ball-lending flag described later. If the loan balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S512). Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending ball is paying out nor the prize ball is paying out, the payout control CPU 371 confirms whether or not there is a ball lending request from the card unit 50 (step S5).
13). When there is a request, the ball lending processing flag is turned on (step S514), and 25 (one unit of ball lending: 100 yen here) is set in the backup RAM area storage of the number of lending balls (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout control CPU 371 sets the motor rotation time for paying out the 25 game balls, or determines the number of output pulses corresponding to the motor rotation time. Then, the payout motor 289 is turned on (step S51
8), and shifts to the processing during ball lending shown in FIG.

Note that the payout motor 289 is turned on by
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the acceptance. The ball lending processing flag is set in the backup RAM area.

FIG. 61 is a flow chart showing the processing during ball lending in the payout control processing by the payout control CPU 371. In the ball lending process, the payout motor 289 is turned on if it is not turned on. In addition, in this embodiment,
In the switch processing of step S751, it is confirmed whether or not the game balls have been paid out based on the detection signal of the ball lending count switch 301B. Therefore, in the ball lending control processing, the storage of the number of loaned balls is not subtracted.

In the ball lending control processing, the payout control CP
U371 confirms whether or not it is in the waiting time for passing the loan ball (step S519). If it is not during the waiting time for passing the rental ball, the rental ball is paid out (step S520),
It is confirmed whether or not the driving of the payout motor 289 should be ended (whether one unit of payout operation is ended) (step S52).
1). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522).
The lending ball passage waiting time is set (step S52).
3).

[0407] If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 confirms whether or not the lending ball passage waiting time has ended (step S52).
4). The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all of the one unit of lending balls have been paid out, so that it is possible to indicate to the card unit 50 that the next ball lending request can be accepted. The EXS signal is turned off (step S525). The distribution solenoid is turned off (step S5).
26), turn off the ball lending processing flag (step S5)
27). If the last payout ball has not passed the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. Also,
In this embodiment, prize balls and ball lending are performed by the same payout device.

After turning off the EXS signal indicating acceptance of the ball lending request, if the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period, the ball lending is performed without turning off the distribution solenoid and the payout motor. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be continuously executed.

The content of the number of rented balls is stored by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the game machine is stopped. Therefore, when the power supply is restored within the predetermined period, the payout control CPU 371 can continue the ball lending process based on the content of the loan ball number storage.

62 and 63, step S757 is executed.
It is a flow chart which shows an example of the prize ball control processing. In addition, in this example, the maximum value of the continuous payout amount is set to the same number as one unit of the lending sphere (for example, 25), but the maximum value of the continuous payout amount may be another number.

In the prize ball control processing, the payout control CPU
The 371 first confirms whether or not the prize ball is stopped (step S530). If it is stopped, the process ends. Whether or not the prize ball is stopped is confirmed by whether or not the payout stopped flag set in the payout prohibited state setting process shown in FIG. 58 is turned on.

If the prize ball is not stopped, the payout control CPU
The 371 confirms whether or not the lending balls are being paid out (step S531), and if the lending balls is being paid out, the process is ended. In addition, whether or not the lent ball is being paid out is determined by the state of the ball lending processing flag. If the payout of the rented balls is not in progress, it is confirmed whether or not the prize ball payout processing has already been started, that is, whether or not the prize balls are being paid out (step S53).
2). If it is in the prize ball, the process moves to the process in the prize ball shown in FIG. Whether or not a prize ball is in play is determined by the state of a prize ball processing flag, which will be described later.

If the prize ball is not being paid out, the payout control CPU
371 confirms whether the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number memory is 2.
It is confirmed whether it is 5 or more (step S536). The prize ball processing flag is set in the backup RAM area.

When the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 instructs the payout motor 289 to rotate the payout motor 289 until the 25 game balls are paid out. In order to output the drive signal by the operation, the 25-piece payout operation is set (step S53).
7). Specifically, the motor rotation time for paying out the 25 game balls is set, and the number of output pulses corresponding to the motor rotation time is determined.

If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 rotates the payout motor 289 until the game balls corresponding to the number stored in the total number memory are paid out. In order to output the drive signal so as to perform the above operation, the all-pieces payout operation is set (step S538). Specifically, the motor rotation time for paying out the game balls is set, and the number of output pulses corresponding to the motor rotation time is determined. Next, the payout motor 289 is turned on (step S539). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the prize ball side. Then, the process shifts to the process of paying out prize balls in the prize ball control process shown in FIG.

FIG. 63 is a flow chart showing an example of a prize ball process in the payout control process by the payout control CPU 371. In the prize ball control processing, the payout motor 289
If is not on, turn it on. In this embodiment, in the switch processing of step S751, it is confirmed whether or not the game balls have been paid out by the detection signal of the prize ball count switch 301A. Is not done.

In the process of winning a prize ball, the payout control CPU
The 371 confirms whether or not it is during the prize ball waiting time (step S540). If it is not during the prize ball passage waiting time, whether or not the prize balls should be paid out (step S541) and the driving of the payout motor 289 should be ended (whether the payout operation of 25 or a predetermined number of less than 25 has ended). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the prize ball passage waiting time (step S544). The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

If it is during the prize ball passage waiting time in step S540, the payout control CPU 371 confirms whether or not the prize ball passage waiting time is over (step S545).
When the prize ball waiting time is over, step S537
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
If the award ball passage waiting time has ended, the award ball processing flag is turned off (step S546). If the last payout ball has not passed the prize ball count switch 301A before the prize ball passage waiting time has elapsed, a prize ball path error is determined.

In this embodiment, step S5
11, the ball lending is prioritized over the prize ball processing according to the determination in step S531, but the prize ball processing may be prioritized over the ball lending.

The contents of the total number storage and the number of rented balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored within a predetermined period, the payout control C
The PU 371 can continue the payout process based on the content of the total number storage.

Although the payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number memory, the prize ball number is calculated for each prize ball number (for example, 15, 10, 6).
Individual). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, the subtraction process is performed in the payout control process).
Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored within the predetermined period, the payout control CP
The U371 can continue the prize ball payout process based on the contents of the respective number counters.

In this embodiment, the payout control means detects that the INT signal related to the payout control signal has risen, and starts the process of fetching 1-byte data by, for example, an interrupt process. Since a receiving ring buffer (a receiving buffer in this example) capable of storing a plurality of payout control commands is provided, after the payout control command is received, the next payout control command is issued before the control based on the command is started. The receipt of the command does not mean that the command is not received by the payout control means.

In the payout control means, the interrupt process is activated even in the payout prohibited state, so that the payout control means can receive the payout control command even when the payout is stopped. Then, while the payout is stopped, the payout process according to the received payout control command is stopped, but since a receiving ring buffer capable of storing a plurality of payout control commands is provided, it is sent from the game control means. The payout control command does not disappear in the payout control means.

Then, in the payout control means, a command reception number counter is used as an address designating means for indicating in which area in the reception ring buffer the transmission command is stored. Therefore, it is easy to determine which area should be used.

In the above embodiment, the case where the RAM is used as the fluctuation data storage means has been shown, but as the fluctuation data storage means, any electrically rewritable storage means other than RAM can be used. You may use.

Further, in the above-described embodiment, the power supply monitoring means is provided on the power supply board 910 and the circuit for generating the signal for system reset is provided on the electric part control board. It may be provided on the substrate.

Next, an example of processing when the gaming machine of this embodiment starts paying out game balls after power supply is started will be described. FIG. 64 is a ball payout device 97 by the payout control CPU 371 for transmitting the payable state designation command by the CPU 56 at the start of power supply.
It is a timing chart showing an example of a processing timing such as a payout process of a game ball using. In addition, also in FIG.
By appropriately selecting the capacity of the external capacitor of the reset IC 651 in the system reset circuit 65 mounted on the power supply board 910 and the capacity of the external capacitor of the power monitoring IC 902, the power monitoring I
The voltage value (+22 in this embodiment) that causes the power-off signal output from C902 to rise to a high level.
An example is shown in which the reset signal rises after the VSL power supply voltage reaches V).

When the gaming machine is powered on and the VSL power supply voltage rises and reaches a predetermined value (+ 9V in this embodiment), the CPU 5 of the main board 31 is set as shown in FIG.
6 starts operation after the CPU of another electric component control board (in this embodiment, the payout control CPU 371 of the payout control board 37) starts its operation and the time delayed by the delay circuit 960 elapses. . When the operation is started, the CPU 56 of the main board 31 transmits a payable state designation command when the control state related to the payout to be restored is not the payout prohibited state when the control state is restored (see steps S83 and S84). . In the case of initialization, the CPU 56 transmits a payable state designation command if the payout prohibition condition is not satisfied (step S1).
See 3b).

The CPU 56 of the main board 31 controls the payout control board 3
The fact that the payable state designation command can be output to 7 means that the CPU 56 of the main board 31 has already started up. Therefore, the CPU 56 of the main board 31 is ready to receive the detection signal of the prize ball count switch 301A.

Upon receipt of the payable state designation command,
The payout control CPU 371 cancels the payout prohibition state set in the above-described step S713 in the initial setting or the above-described step S732 in the recovery process (see step S753e), and if there is an unpaid gaming ball, it is a ball. The payout device 97 is used to execute a payout process for gaming balls. Then, the paid game balls are detected by the prize ball count switch 301A. The detection signal of the prize ball count switch 301A indicates that the CPU 56 which has started the operation.
And the payout control CPU 371, respectively.

FIG. 65 is a block diagram showing a structure of a characteristic part in the above-mentioned gaming machine of this example. As shown in FIG. 65, the gaming machine of this example is a gaming machine that allows a player to play a predetermined game, and an electric component control means for controlling an electric component 802 provided in the gaming machine. 801,
A game control means 561 for controlling the progress of the game, a variable data storage means 551 capable of retaining the stored contents for a predetermined period even if the power supply to the game machine is stopped, and a predetermined power source used in the game machine. And a power supply monitoring means 910a for outputting a detection signal when a detection condition relating to stop of supply of electric power to the gaming machine is satisfied, and the game control means 561 sends a command to the electric component control means 801. Command transmitting means 56 for transmitting a command according to the progress of the game by executing the command transmitting program for transmitting
2, the power supply stop processing (step S450) for storing the data necessary for restoring the control state in the fluctuation data storage means 551 according to the detection signal from the power supply monitoring means 910a, and the fluctuation data. Based on the stored contents stored in the storage unit 551, a restoration process (step S100) for restoring the control state to the state before the power supply is stopped is executed, and the command transmission unit 562 performs the restoration process (step S100). By executing the command transmission program called by the subroutine call, the process of transmitting a command for restoring the control state before the power supply is stopped to the electric component control means 801 (step S562a) is executed, and the variation data Storage means 55
1 includes a stack area 552 for saving the program address data related to the address of the control program being executed in response to the subroutine call, and the game control means 561 causes the stack pointer 563.
Among the data saved in the stack area 552 by the address indicated by, the address where the data to be read next is stored is specified, and in the power supply stop processing (step S450), the stack pointer 56
The stack address data 552a associated with the address indicated by 3 is saved in the variable data storage means 551 (step S450a), and the command transmission means 56 is executed in the restoration processing (step S100).
Before the second first transmits the command, the fluctuation data storage means 551 is processed in the power supply stop process (step S450).
The stack address data 552a saved in
Set the stack pointer 563 (step S100
It is characterized by a).

As described above, since the stack pointer is restored (step S81) before the control command for restoring the game state is transmitted (steps S83 to S86), the command is transmitted. The process (command set process) can be a subroutine, and by calling the subroutine, it becomes possible to execute the control command transmission process for restoring the game state. Therefore, the program capacity used for game control can be reduced, and the ROM
The required capacity of 54 can be reduced. Also, CP
U56 can efficiently execute the game state recovery process. That is, since the game state recovery process is executed by a small-capacity program that uses a subroutine,
The game state recovery process is an efficient process with no waste in terms of program configuration.

As described above, when the payout possible state designating command is transmitted in the recovery process, the subroutine (step S84) is used. Therefore, the payout possible state designating command is transmitted in the game state recovery process. The processing can be performed efficiently.

Further, as described above, when the display control command for restoring the display state of the variable display device 9 is transmitted, the subroutine (step S86) is used, so that the display in the game state restoration process is performed. It is possible to efficiently perform the process of transmitting the display control command for restoring the state. Specifically, in the game state restoration process, a subroutine (step S86) is used to transmit a symbol designating command for restoring the information relating to the fixed symbol, so the display control means recognizes it before the power is turned off. It is possible to efficiently perform the transmission process of the display control command for restoring the stored state of the information regarding the fixed symbol that has been used. Further, when the game is restarted, it is possible to reliably inform the player of information relating to the fixed symbol. In the game state restoration process, a subroutine (step S
86) is used to send the probability variation state restoration specification command for recovering the display state related to the probability variation state, so that the display control command for restoring the display state indicating the probability variation state before power off is restored. The transmission process can be performed efficiently. Further, when the game is restarted, it is possible to surely inform the player whether or not the state is the probability change state.

Further, as described above, in the game state restoration process, immediately after the process of transmitting the command for restoring the control state is performed, the timer interrupt is set (step S8).
Since it is configured to perform 7), it becomes easy to synchronize the game control means and the other electric component control means.

Further, as described above, the capacitors 923 and 9 are connected until the detection maintaining period elapses in the power supply stop process (see FIGS. 23 to 25 and 51 to 53).
The power supply board 910 supplies electric power capable of driving the prize ball count switch 301A and the ball lending count switch 301B by using the electric power charged in 24, and the solenoid 310 holds the state of the distribution member 311. Drive power is supplied, and the game control means inputs the detection signal from the prize ball count switch 301A (step S4).
66 to step S486), and the payout control means (payout control CPU 371) causes the prize ball count switch 301A.
Since the input processing of the detection signal from the ball lending count switch 301B (step S816 to step S834) is performed, the paid game game medium (based on the winning of the winning area in the power supply stop processing). It is possible to reliably detect a game medium to be paid out as a prize) and a lending game medium (a game medium to be lent out in response to a lending request from a player). That is, according to the above-mentioned gaming machine, it is possible to reliably execute the detection of the game medium paid out in the power supply stop process, so that the number of unpaid game media can be accurately grasped. become.

As described above, the power supply board 910 keeps the solenoid 31 until the detection maintaining period elapses.
Since the electric power that can drive the distribution member 311 is supplied to 0, the driving state of the solenoid 310 as the passage switching unit can be maintained by the electric configuration. With the above-described configuration, the power supply substrate 910 functions as an operating state holding unit that supplies electric power for maintaining the state of the distribution member 311 until the detection maintaining period elapses. There is.
Further, since the configuration is as described above, the state of the distribution member 311 is maintained until the detection maintaining period elapses, and the distribution member 311 does not operate. It is possible to prevent the game ball from being caught between the walls inside the passages 293a and 293b.

Also, as described above, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the ball payout device 97
In order to save the payout control state after the driving of the is stopped, the detection signal is input from the payout detecting means (prize ball count switch 301A or ball lending count switch 301B) for a predetermined detection maintaining period. Is processed. Therefore, the game balls that were in the process of being paid out at the time of the power failure are surely reflected in the saved contents of the backup RAM. Therefore, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped,
It is possible to prevent inconsistency between the saved control state and the actual control state.

Further, as described above, in the case where the power supply is not stopped even though the standby state after the power supply stop processing is continuously executed, the operation for recovering from the standby state is performed. Since the return signal is output to the CPU 56 and the payout control CPU 371, the return signal enables the CPU 56 and the payout control CPU 371 to return from the standby state to the control execution state. Therefore, it is possible to prevent the control from being disturbed even if the power supply is interrupted for a very short time.

That is, in the above-described embodiment, the game control means and the payout control means having the storage holding means (for example, backup RAM) perform the power supply stop time processing in response to the power-off signal and wait for the system reset. When the return signal is output in response to the power restoration in the state, the game control means and the payout control means restart the operation from the first part of the program. At this time, the control state saved in the power supply stop process is restored, so that the game continues as if nothing happened to the player.

Also, as described above, means capable of outputting a return signal (for example, means constituted by the counter 971 or the like:
Since the standby state returning unit is mounted on the power supply board 910, it is not necessary to provide the standby state returning unit for each control board, and the standby state can be restored with a simple configuration. .

Further, as described above, when the electric component control means starts the electric power supply and the control state saved in the electric power supply stop processing remains, the operating means (clear switch 921) operates. If it is operated, the initialization process is executed without executing the state recovery process. Therefore, it is possible for a game shop employee or the like to easily clear the saved state, and it is possible to improve the convenience of operating the game machine in the game shop.

In the embodiment described above, in the game state restoration process, a symbol designating command for restoring the information relating to the fixed symbol and the display state relating to the probability variation state are restored using the subroutine (step S86). Although the probability variation state restoration designation command is transmitted, other display control commands for restoring the display state of the variable display device 9 may be transmitted.

Further, in the above-mentioned embodiment, the number of stored winning prizes is displayed by using the starting memory indicator 18. However, the number of stored winning prizes is displayed in the display area of the variable display device 9. Good. In this case, the variable display device 9 is provided with, for example, four special symbol starting memory display areas (starting memory display area) for displaying the number of effective winning balls that have entered the starting winning opening 14, that is, the starting memory number. Change the display color each time there is (for example, change from blue display to red display)
It is sufficient to increase the number and reduce the display area for starting memory number, in which the display color is changed each time the variable display of the variable display device 9 is started, by 1 (that is, the display color is returned to the original one). Even if the symbol display area and the starting memory display area are divided, the starting memory display area may be provided in a part of the symbol display area. When the start memory display area is provided in a part of the symbol display area, the display of the start memory number may be interrupted during the variable display.

Further, in the above-mentioned embodiment, the maximum value of the number of memory for winning the winning prize is set to 4, but the maximum value may be any number. In particular, when the number of stored winning awards is displayed in the display area of the variable display device 9, even if the maximum value of the number of awarded winning winnings is set to a large value, it is possible to easily deal with it.

Further, in the above-described embodiment, the total number memory, the number of lent balls, and the like are stored in the backup RAM area so that the payout control board 37 backs up various data. The substrate 37 may be configured not to back up various data. In this case, the number of unpaid prize balls and the number of lent balls are backed up and stored in the main board 31, and when the power supply is restarted, the number of unpaid prize balls and the number of lent balls are indicated from the main board 31. The payout control command may be transmitted to the payout control board 37. According to the above-mentioned configuration, even if the payout control board 37 is configured not to back up various data, the payout control CPU 371 detects the unpaid prize balls or loan balls after the power supply is restarted. It becomes possible to perform payout processing.

Further, in the above-mentioned embodiment, the payout control command and the display control command are transmitted by using the subroutines (step S84, step S86) in the game state recovery processing, but the lamp, LED, etc. A lamp control command may be transmitted to restore the control state of the light emitter, and a sound control command may be transmitted to restore the voice output state from the speaker 27. For example, in the game state restoration process, the display state of the start memory indicator 18 may be restored by transmitting a start prize winning memory number lamp designation command using a subroutine. According to the above-mentioned configuration, since the starting prize winning memory number lamp designating command is transmitted using the subroutine, it is possible to efficiently perform the lamp control command transmitting process for restoring the display state of the starting memory indicator 18. Further, when the game is restarted, the player can be surely informed of the number of starting winning prizes stored. When the starting memory indicator 18 is configured to be controlled by the display control means, a subroutine may be used to send a starting winning memory number lamp designation command as a display control command.

Further, in the above-mentioned embodiment, the payout control means performs the prize ball count switch 301A and the ball lending count switch 301B in the power supply stop process.
Although it is configured to confirm whether or not each switch is turned on, the configuration may be configured to confirm the state of either one of the switches.

66 to 68 are non-maskable interrupt processing (NMI) executed in response to a power-off signal from the power supply board 910 in the case of confirming the state of one of the switches as described above. It is a flowchart which shows the example of a process of a process: power supply stop process. In addition, FIG.
Detailed description of the processes already described with reference to FIGS. 1 to 53 will be omitted.

In the non-maskable interrupt process, the payout control CPU 371 executes steps S801 to S808.
After performing the process of step S809 to step S8
The output port clear process shown in 15 is performed. After that, in this embodiment, a detection signal of a prize ball count switch 301A (corresponding to prize game medium payout detection means) or a ball lending count switch 301B (corresponding to rental game media payout detection means) for a predetermined period (detection maintaining period) Check.
In this example, the detection signal is checked only for the switches that may detect the game ball. When the switch that may be detected is the prize ball count switch 301A, the prize ball count switch 301A is checked, and when it is turned on, the content of the total number storage is decremented by one. Also,
If the switch that may be detected is the ball lending count switch 301B, the ball lending count switch 3
If 01B is checked and turned on, the content of the number of lent balls is reduced by 1.

In this example, the payout control CPU 371 is
It is confirmed whether or not the award ball processing flag is turned on (step S847). If the award ball processing flag is turned on, it means that the award ball processing switch 301A may detect the award ball. To determine. If the prize ball processing flag is not on, the payout control CPU 371 confirms whether the ball lending processing flag is on (step S8).
48) If it is ON, it is determined that the ball lending count switch 301B may detect the ball lending because the ball lending process is being performed.

In this example, in order to measure the payout confirmation period, whichever switch is checked,
A payout confirmation period measuring counter is used. When the prize ball count switch 301A is checked, the value of the payout confirmation period measuring counter is changed from the initial value m to a loop of prize ball count switch detection processing described below (S817).
It is assumed that the payout confirmation period ends when the loop) that starts from step S817 and returns to S817 is incremented by one each time the value becomes 0. In addition, ball lending count switch 301B
When the check is made, the value of the payout confirmation period measuring counter is changed from the initial value m to the loop of the ball lending count switch detection processing described below (starting from S817a to S
It is assumed that the payout confirmation period has ended when the value of the loop (returning to 817a) is incremented by 1 every time it is executed once and becomes 0. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore, a time m times the time required for one round of the loop is substantially equivalent to the payout confirmation period. The internal timer of the payout control CPU 371 may be used to measure the payout confirmation period.

If the award ball processing flag is turned on in step S847, the payout control CPU 371 executes an input process of the detection signal from the award ball count switch 301A (award ball count switch detection process). In the prize ball count switch detection process, the payout control CPU 371 first sets a value m corresponding to the payout confirmation period in the payout confirmation period measurement counter (step S816). And
The payout control CPU 371 decrements the value of the payout confirmation period measurement counter by 1 (step S817), and confirms the value of the payout confirmation period measurement counter (step S818). If the value is 0, the prize ball count switch detection process is terminated and the process proceeds to the power supply stop process which is a process for storing the control state.

If the value of the payout confirmation period measuring counter is not 0, the same as in FIG. 54 described above, step S8.
The processing of 19 to step S826 is performed. However, in the prize ball count switch detection processing, if the value of the detection period counter is not 0 in step S821, if the prize ball count switch 301A does not indicate the ON state in step S824, in step S826. In any case where the detection period counter is set to the initial value n, the processing returns to step S817 after the processing. By the above processing, if the prize ball count switch 301A is turned on within the payout confirmation period, the value of the total number memory is decremented by one.

If the ball lending processing in-progress flag is on in step S848, the payout control CPU 371 executes input processing of a detection signal from the ball lending count switch 301B (ball lending count switch detection processing). In the ball lending count switch detection processing, the payout control CPU 371
First, the payout confirmation period measuring counter is set to a value m corresponding to the payout confirmation period (step S816a).
Then, the payout control CPU 371 decrements the value of the payout confirmation period measurement counter by 1 (step S817a), and confirms the value of the payout confirmation period measurement counter (step S8).
18a). If the value is 0, the ball lending count switch detection process is terminated, and the process proceeds to the power supply stop process which is a process for saving the control state.

If the value of the payout confirmation period measuring counter is not 0, as in the case of FIG. 52 described above, step S8.
The processing from 27 to step S834 is performed. However, in the ball lending count switch detection processing, if the value of the detection period counter is not 0 in step S829, if the ball lending count switch 301B is not in the ON state in step S832, in step S834. In any case where the detection period counter is set to the initial value n, the process returns to step S817a after those processes. By the above process, when the ball lending count switch 301B is turned on within the payout confirmation period, the value of the number of lent balls memorized is decremented by one.

Also, steps S847 and S84.
If both the prize ball processing flag and the ball lending processing flag are not turned on at 8, the prize ball count switch 301A
Since there is no possibility of turning on both the ball lending count switch 301B and the ball lending count switch 301B, the payout control CPU 371 performs processing such as saving the contents of the backup RAM similar to the processing of FIG. After performing steps S835 to S846, a standby state (loop state) is entered.

As described above, when there is no possibility that a game ball is detected, neither the prize ball count switch 301A nor the ball lending count switch 301B is detected. This can be omitted, and the processing at the time of stopping the power supply (FIGS. 66 to 68) can be performed quickly.

Further, as described above, among the prize ball count switch 301A or the ball lending count switch 301B, only the switch in which the game ball may be detected is selectively configured to check the detection state. Therefore, useless processing can be omitted. Further, since the processing period of the switch detection loop processing shown in FIG. 66 and the like is shorter than that of the switch detection processing loop processing shown in FIG. 52, even if the value set in the predetermined time measurement counter is the same, Also, since there is a difference in the processing period in the final loop processing, with the above configuration, the power supply stop processing (FIGS. 66 to 68) can be quickly performed. Therefore, the capacities of the capacitors 923 and 924 can be reduced as compared with the case where the power supply stop processing shown in FIG. 51 and the like is executed.

In the above example, when the award ball processing flag is not on, the state of the ball lending processing flag is checked. However, if the award ball processing flag is not on, the ball lending count is immediately calculated. The switch detection process may be executed. Further, the state of the ball lending processing flag may be confirmed without checking the prize ball processing flag, and the prize ball count switch detection processing may be executed immediately if the ball lending processing flag is not on. According to this structure, it is possible to quickly confirm the state of the switch that has a possibility of being detected.

In the above example, neither the detection state of the prize ball count switch 301A nor the ball lending count switch 301B is confirmed, or the detection state of either the prize ball count switch 301A or the ball lending count switch 301B is checked. Although the confirmation is performed, both the prize ball count switch 301A and the ball lending count switch 301B may be confirmed. With this configuration, it is possible to recognize whether the prize ball or the loan ball is detected when the detection signal is input, without checking which switch the detection signal is from. be able to. For example, if the detection signal from the count switch is input after confirming that the prize ball processing flag is turned on, the payout control CPU
It suffices that the 371 recognize that the detection signal from the prize ball count switch 301A has been input. Therefore, if configured as described above, whether the detected game ball is a prize ball or a loan ball even if the game ball paid out by one count switch for prize balls and ball lending is detected Can be accurately determined.

Further, in each of the above-mentioned embodiments, the distribution member 311 is arranged to fall so that the game ball flows down to the ball lending side / prize ball side in accordance with the turning on / off of the solenoid 310. The configuration may be such that the position where the distribution member 311 falls down is controlled by a motor, and the distribution member 311 alternates between the ball lending side and the prize ball side every time the motor is turned on. In this configuration, the distribution member 311 will continue to maintain the current state unless the motor is newly turned on. Therefore, by configuring as described above, the distribution member 3 has a mechanical structure in the power supply stop process regardless of the voltage state of the drive power source of the motor.
The state of 11 can be maintained. In the case of the above configuration, the distribution member 311 is subjected to the restoration process or the initialization process after the power supply is started.
It suffices to execute a process of returning the state of 1 to the initial state (for example, the state where the game ball flows down to the ball lending side). Each time a predetermined process is performed, the allocating member 3 is alternately switched to the ball lending side / prize ball side.
A member other than the motor (for example, a latch-type solenoid) may be used as long as 11 can be tilted. In the case of the above-described configuration, the motor that controls the position where the distributing member 311 falls down functions as the passage switching means, and the distribution that has a mechanism that can maintain the current state unless there is a drive signal from the motor. The member 311 will function as an operation state holding means. Further, the mechanism of the distribution member 311 capable of maintaining the state of the ball lending side / prize ball side functions as a holding mechanism capable of holding the state of the passage switching means until the detection maintaining period elapses. Become.

In each of the above embodiments, n is set so that the game medium detection determination period (the period measured by the detection period counter) is approximately 2 ms (step S826).
Or step S834) may be set. However, for example, a predetermined delay period (step S817) may be set after step S817 so that the loop process of returning from step S817 to step S817 is executed every 2 ms. 2m
(A period obtained by subtracting the period required for normal loop processing from s)
It may be configured to perform a process of delaying until elapse. The delay period may be measured by, for example, a software timer. Note that step S817a
The same applies to the loop processing that returns from step S817a to step S817a. Further, the period may be other than 2 ms.

In each of the above embodiments, in the power supply stop process, it is monitored whether or not the game balls have been paid out, and when the game balls have been paid out, it is stored as the number of unpaid game balls. Although the process of subtracting the stored value (step S480, step S823, step S831) was performed, the process of subtracting the stored value of the unpaid amount is not performed, and the prize ball count switch 301A and the ball lending count switch 30 are executed.
The configuration may be such that it is confirmed whether or not the 1B is turned on, and the confirmation result is stored in the RAM whose power is backed up. In this case, in the recovery process (see FIGS. 21 and 50) after the power supply is started, the prize ball count switch 301A and the ball are switched while the power supply stop process is being executed based on the stored contents of the RAM whose power is backed up. If it is confirmed that the lending count switch 301B is turned on, a process of subtracting the stored value of the unpaid amount may be performed. As described above, when the prize ball count switch 301A or the ball lending count switch 301B is turned on in the power supply stop process, the prize ball count switch 301A or the ball lending count switch 301B is used without updating the unpaid amount. If the configuration is such that the result of the input processing of the detection signal of is saved and the number of unpaid payments is updated according to the saved result of the input processing at the time of restoration, it is stored as the number of unpaid payments in the power supply stop processing. Since it is not necessary to perform the process to change the value (unpaid amount data), the power supply stop process is quicker than when the power supply stop process is executed to change the unpaid amount data. In order to be able to more reliably complete the processing executed to manage the number of unpaid gaming balls before the power supply is stopped. It made.

Further, in each of the above-mentioned embodiments, the ball payout device 97 pays out the prize balls and the lending balls, and the sorting solenoid 31 is used.
By the distribution member 311 driven by 0, the prize ball downflow path (prize game medium path) and the rental ball downflow path (rental game medium path) were switched. However, a payout device for paying a prize ball and a payout device for lending a ball may be separately provided.

Further, in each of the above embodiments, the return signal from the power supply board 910 is sent to the CPU 5 on the main board 31.
6 was input to the reset terminal, but I / O port 57
May be input to the input port of.

In the case of such a configuration, in the non-maskable interrupt process (power supply stop process) of the game control means, steps S451 to S shown in FIGS.
In the standby state waiting for the system reset after the processing of 498, detection of ON of the return signal is executed through the input port, and when the return signal is turned ON, FIG.
The process may jump to step S1 of the main process shown in FIG. When the execution of the main process is started, the game state is stored when the power-off signal is output, so the game state restoration process is executed in the process of step S10, and the game control is performed when the power-off signal is generated. Returning to the state of, the game control is continued from that state.

The return signal is input to, for example, bit 5 of input port 1 (see FIG. 18). Further, in this example, immediately after the turn-on of the return signal is detected, the step S1 is performed.
However, in order to remove noise, etc., the CPU may jump to step S1 when a plurality of consecutive ONs are detected, or jump to step S1 when a ON is detected again after a predetermined period has elapsed after the ON detection. May be. Further, the return signal input to the input port may be detected also in the non-maskable interrupt process of the payout control means.

Further, in each of the above-mentioned embodiments, the return signal is created on the power supply board 910, but it may be created on the electric component control board which requires the return signal. That is, the standby state returning means is the main board 31 or the payout control board 3
It may be configured to be provided on each control board such as No. 7 and the like. The power supply board used when the return signal is generated in each control board is configured not to output the return signal. Further, the reset management circuit may have a configuration in which the return signal generating portion is removed from the circuit configuration shown in FIG.

FIG. 69 is a flow chart showing an example of the non-maskable interrupt processing (power supply stop processing) of the game control means when the return signal is not generated in the power supply board. The flow chart shown in FIG. 69 is shown in FIGS.
Is executed subsequent to the processing of steps S451 to S498 shown in FIG. That is, in this embodiment, after the RAM access prohibition value is set (step S498), the initial value M of the counter is first set in the standby state waiting for the system reset (step S111). While subtracting 1 from the counter value (step S11
2) It is confirmed whether or not the value of the counter has become 0 (step S113).

When the counter value becomes 0, the process jumps to step S1 of the main process shown in FIG. When the execution of the main process is started, the game state is stored when the power-off signal is output, so the game state restoration process is executed in the process of step S10, and the game control is performed when the power-off signal is generated. Returning to the state of, the game control is continued from that state.

The time from setting the initial value M in the counter to counting up (= 0) is [time required for processing in steps S112 and S113] × M. It is set so as to count a time longer than the time from the generation of the disconnection signal until the CPU 56 operating with the Vcc power supply becomes inoperable. Therefore, in general, the CPU 56 does not operate before the counter counts up and jumps to step S1. That is, there is no jump to step S1.

However, if a momentary power interruption occurs, the power supply voltage level is reduced for a short period of time and then restored. Also in that case, when the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the power supply stoppage process is started. Then, the CPU 56 enters a loop state after the processing when the power supply is stopped is completed. Without any control, the loop processing cannot be exited. In this case, the counter can count up and return to the main processing.

That is, the counter in this embodiment corresponds to the software timer for performing the timer process executed in the standby state in the process according to the power-off signal. Then, when the counter counts up, that is, when the elapse of a predetermined period is measured by the timer processing, the CPU 56 as the returning means performs control for returning from the standby state to the game control state.

Even in such a configuration, when the power supply voltage is restored to the normal value even though the power supply cutoff signal is generated due to the momentary power cutoff or the like, the CPU 56 is shown in FIG. The execution of the main process can be resumed. At that time, since the game state is saved when the power-off signal is output, the game state restoration process is executed in the process of step S10, and the game control returns to the state at the time of the power-off signal, and the state The game control is continued from.

Such control can also be executed by the payout control means. FIG. 70 is a flowchart showing an example of the non-maskable interrupt process (power supply stop process) of the payout control means when the return signal is not generated in the power supply board. The flowchart shown in FIG.
Step S8 shown in FIG. 53 or FIGS. 66 to 68
It is executed following the processing of 01 to S846. That is,
In this embodiment, after the RAM access prohibition value is set (step S846), the initial value M of the counter is first set in the standby state waiting for the system reset (step S921). Then, while subtracting 1 from the counter value (step S922), it is confirmed whether or not the counter value has become 0 (step S923).

Then, when the value of the counter becomes 0, the process jumps to step S701 of the main process shown in FIG. When the execution of the main process is started, since the control state is saved when the power-off signal is output, the payout state restoration process is executed in the process of step S710,
The control returns to the state at the time of the power-off signal, and the payout control is continued from that state.

The count-up value handled by the CPU 56 of the main board 31 (M set in S111 in FIG. 69) is preferably larger than the count-up value handled by the payout control CPU 371. If the count-up value handled by the CPU 56 is larger,
The payout control means will be restarted before the game control means. Therefore, the payout control means does not stand up first and miss the payout control command from the game control means.

As described above, when the return signal is not generated in the power supply board, it is possible to return from the standby state to the control state by performing timer processing by software, but the timer processing may be executed by hardware. .

FIG. 71 is a block diagram showing an example of a configuration in which the timer processing is performed by hardware when the return signal is not generated in the power supply board. In this example, the main board 31 is provided with a counter (watchdog timer circuit) 162 that functions as a watchdog timer. The watchdog timer circuit 162 counts the output pulses of the oscillation circuit 164, and when counting up, generates one high-level pulse as the Q output. The pulse signal is logically inverted by the inversion circuit 163 and input to the AND circuit 161 as a return signal. The AND circuit 161 calculates the logical product of the reset signal and the return signal to obtain C.
It is supplied to the reset terminal of the PU 56. The CPU 56
May be set to output a system clock or a divided clock thereof, and the clock may be used as an input clock signal of the watchdog timer circuit 162.

The count-up value is set to be equal to or longer than the time required for the voltage value of VSL to drop to the voltage at which Vcc can be generated after the power-off signal goes low. Since the watchdog timer circuit 162 operates using Vcc as a power source, the count-up value is set to a value equal to or greater than the operable period of the watchdog timer circuit 162. Therefore, when the power supply to the gaming machine is stopped, the watchdog timer circuit 162 and other circuit components generally do not operate before the watchdog timer circuit 162 counts up and the return signal is output.

When the CPU 56 is performing game control, a clear pulse is periodically given to the watchdog timer circuit 162. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 162 counts up. Therefore, no pulse appears in the Q output of the watchdog timer circuit 162 while the CPU 56 is performing normal game control.

FIG. 72 shows the watchdog timer circuit 16
It is the flowchart which shows the 2ms timer interruption processing of the game control expedient when 2 is provided. As shown in FIG. 72, in the game control process (steps S21 to S32a), the watchdog timer clear process (step S3
2a) is executed. Therefore, the watchdog timer clear process is executed every 2 ms.

In the watchdog timer clear process (step S32a), a process of outputting one pulse to the output port reaching the clear terminal of the watchdog timer circuit 162 is performed. Therefore, during the execution of the game control process, the watchdog timer circuit 162 is periodically provided with a clear pulse, so that it does not count up.

When the supply voltage to the gaming machine is lowered and the power-off signal is output, the non-maskable interrupt processing as shown in FIGS. 23 to 25 is started. During the processing, the clear pulse is not output to the watchdog timer circuit 162. Therefore, when the power supply voltage is restored and the watchdog timer circuit 162 is operating until it counts up, the return signal is output.

FIG. 73 is a timing chart showing the output timing of the return signal when the return signal is generated by the software timer processing or the watchdog timer circuit 162 described above. FIG. 73A illustrates an example in which power supply to the game machine is stopped. The software timer process is started after the process at the time of power supply stop is completed and a standby state is set. Further, since the clear pulse is not output to the watchdog timer circuit 162 in the non-maskable interrupt processing, the watchdog timer circuit 16
Are substantially activated from the start of the power supply stop process. In either case, the time-up value (count-up value) is set so as not to time-up until the power supply voltage becomes smaller than the Vcc-producible voltage value, so that no return signal is generated.

When the power supply is momentarily cut off, as shown in FIG. 73 (B), the voltage level of VSL is reduced for a short period of time and then restored. Also in that case, when the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the power supply stoppage process is started. And CP
U56 enters the loop state after the power supply stop process is completed.
Without any control, the loop processing cannot be exited. In this case, the watchdog timer circuit 162 counts up and a return signal is generated.

As shown in FIG. 71, in the main board 31, the return signal is sent to the CPU via the AND circuit 161.
It is input to the reset terminal 56. Therefore, the CPU 56
Requires a system reset. As a result, the CPU 56
Can get out of standby.

FIG. 74 is a block diagram showing an example of a configuration in which the timer processing is performed by the hardware in the payout control board 37 when the return signal is not generated in the power supply board. In this example, the payout control board 37 is provided with a counter (watchdog timer circuit) 386 that functions as a watchdog timer. The watchdog timer circuit 386 counts the output pulses of the oscillation circuit 388, and when counting up, generates one high-level pulse as the Q output. The pulse signal is logically inverted by the inversion circuit 387 and input to the AND circuit 385 as a return signal. The AND circuit 385 calculates the logical product of the reset signal and the return signal and supplies the logical product to the reset terminal of the CPU 56.

The count-up value is set to be equal to or longer than the time required for the voltage value of VSL to drop to the voltage capable of generating Vcc after the power-off signal becomes low level. Since the watchdog timer circuit 386 operates using Vcc as a power supply, the count-up value is set to a value equal to or greater than the operable period of the watchdog timer circuit 386. Therefore, in general, the watchdog timer circuit 386 and other circuit components do not operate before the watchdog timer circuit 386 counts up and the return signal is output. When the payout control CPU 371 is performing payout control, a clear pulse is periodically given to the watchdog timer circuit 386. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 386 counts up. Therefore, CP for payout control
No pulse appears in the Q output of the watchdog timer circuit 3876 when U371 is performing normal game control.

FIG. 75 shows the watchdog timer circuit 38.
It is a flowchart which shows a part of main processing of the payout control means when 6 is provided. The process shown in FIG. 84 is executed subsequent to the processes of steps S701 to S714 shown in FIG. In this case, the watchdog timer clearing process (step S76) is executed in the payout control process loop (steps S715, S751 to S761).
1) is executed. Therefore, the watchdog timer clear process is executed every 2 ms.

In the watchdog timer clear process (step S761), a process of outputting one pulse to the output port reaching the clear terminal of the watchdog timer circuit 386 is performed. Therefore, since the clear pulse is periodically given to the watchdog timer circuit 386 during execution of the payout control process, it does not count up.

When the supply voltage to the gaming machine is lowered and the power-off signal is output, the non-maskable interrupt processing as shown in FIGS. 51 to 53 is started. During the processing, the clear pulse is not output to the watchdog timer circuit 386. Therefore, when the power supply voltage is restored and the watchdog timer circuit 386 is operating until it counts up, the return signal is output.

As shown in FIG. 74, the payout control board 3
7, the return signal is sent via the AND circuit 385.
It is input to the reset terminal of the payout control CPU 371.
Therefore, the payout control CPU 371 is reset. As a result, the payout control CPU 371 can exit the standby state.

As described above, in the main board 31 and the payout control board 37, the watchdog timer circuits 162, 3 are provided.
If 86 is provided, the return signal can be generated by hardware. Moreover, not only when the power supply voltage drops, but for some reason, the CPU 5
6 or even when the control of the payout control CPU 371 enters an infinite loop, the loop state can be exited.

The count-up value of the watchdog timer circuit 162 of the main board 31 is preferably larger than the count-up value of the watchdog timer circuit 386 of the payout control board 37. If the count-up value of the watchdog timer circuit 162 is larger, the return signal is supplied to the payout control means before the game control means. Therefore, the payout control means does not stand up first and miss the payout control command from the game control means.

Further, for example, the watchdog timer circuit 162 may be installed only on the main board 31, and the return signal from the watchdog timer circuit 162 may be supplied to the CPU 56 and the payout control board 37. With such a configuration, the overall circuit configuration scale can be reduced. Further, in the case of such a configuration, it is preferable to place a delay circuit between the watchdog timer circuit 162 and the reset terminal of the CPU 56 so that the payout control means can be activated first.

Further, the watchdog timer circuit 16
The return signal of 2,386 may be input to the input port instead of being connected to the reset terminal of the CPU. In that case, the input port is monitored in the standby state in the power supply stop process, and when it is detected that the return signal is turned on, the process jumps to the beginning of the main process. Further, watchdog timer circuits 162 and 386
Alternatively, the return signal may be input to the CTC terminal of the CPU. In that case, the CTC interrupt is set in advance in accordance with the input of the return signal. Also, the interrupt permission is set in the standby state. Then, when the CTC interrupt is applied, the process jumps to the beginning of the main process.

Further, in each of the above-described embodiments, the process of stopping the power supply is executed in the payout control board 37 according to the NMI, but the power-off signal is sent to the payout control CPU 371.
It is also possible to connect to the maskable terminal and to execute the power supply stop process by the maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

Further, in each of the above-described embodiments, one power supply board 910 is provided with a circuit (reset circuit 65) for generating a reset signal to be supplied to each electric component control means. A circuit for generating a reset signal to be supplied to the CPU 56 and a circuit for generating a reset signal to be supplied to the CPU of another electric component control board may be separately provided.

Further, in the above-described embodiment, one circuit (reset circuit 65) for generating a reset signal to be supplied to each electric component control means is provided on the power supply substrate 910, but each electric component control substrate is provided. A circuit for generating a reset signal may be provided for each.

As described above, when the system reset means (reset circuit 65) is mounted on each electric component control board on which each electric component control means is mounted, the output signal of the system reset means is output. The cable (the cable connecting the system resetting device and the CPU) for transmitting the signal can be shortened, and the influence of noise can be reduced.

In the above-described embodiment, the command output port is cleared in the power supply stop process, but the process of saving the state of the command output port in the RAM backup area before clearing the output port is performed. The power recovery processing may be performed to restore the state of the command output port to the state before the power was turned off. With this configuration, for example, even when the control command is output to the output port, but the power supply is stopped before the INT signal is output, the transmission destination can be reliably transmitted after the power supply is restarted. The control command can be output to.

In the above-described embodiment, the power supply monitoring means (eg, power supply monitoring IC 902) outputs the power supply cutoff signal when the power supply voltage reaches a predetermined value (eg, 22V). For example, a configuration may be adopted in which a digital signal obtained by digitally converting an AC wave related to an AC power supply is monitored, and a power-off signal is output when the digital signal is interrupted for a predetermined period.

Further, in each of the above-described embodiments, the control command is composed of MODE data and EXT data, but the control command may be composed of three or more data, and is composed of one data. May be. Moreover, the control command is not limited to the 2-byte configuration as described above.

Also, in each of the above-mentioned embodiments, INT
Command reception processing in response to signal reception (see FIG. 56)
However, the command receiving process may be performed without using the INT signal. In this case, for example, each electric component control board on the command receiving side monitors the command input port (for example, the input port A shown in FIG. 47) every predetermined period, and the command receiving process is performed according to the state of the port. It may be configured to execute.

In each of the above-mentioned embodiments, the command is transmitted using a plurality of signal lines.
The command may be configured by a serial signal, and serial transmission may be performed using one signal line.

In each of the above embodiments, the payout control means for controlling the ball payout device 97 as an electric part is mainly used as the electric part control means other than the game control, but the present invention is applied. The electric component control means may be control means other than the payout control means.

Further, in the above-mentioned embodiment, if the payout state determination means (a part of the game control means) for determining whether or not the game medium can be paid out detects that the payout is not possible, the cause is determined. Regardless, one type of payout prohibition state designation command (that is, in the present example, the payout prohibition state designation command is common regardless of which of the plural types of conditions for prohibiting payout is satisfied). However, the command used for each cause is divided into commands for different causes (in the above example, a command for indicating a shortage of supply balls and a command for indicating a lower tank full). May be. In this case, when the payout state determination means detects that one of the payout prohibition conditions is not satisfied, a command indicating that the corresponding payout prohibition condition has been canceled (for example, a command indicating elimination of the shortage of the supply balls, A command indicating that the lower plate is full is to be transmitted. In the case of the above configuration, the payout control means disables the payout control when receiving one of the commands provided for each of the causes of the payout prohibition condition and prohibits the payout. Are all canceled (for example, when all the flags provided for each withdrawal prohibition condition are in a state where the condition is not satisfied)
Then, the payout control may be executed.

[0510] Also, when the payout of gaming balls is not possible,
In order to prohibit the continuation of the game, a command instructing to prohibit the launch of the game ball may be transmitted to the payout control board 37. When the payout control means mounted on the payout control board 37 receives a command instructing to prohibit the launch of a game ball, it stops driving the ball striking device. Also,
When the payout of the game ball is not possible, the game control means may directly give the launch control means a signal instructing to prohibit the launch of the game ball. Further, the payout control means may stop the driving of the hit ball launching device when the payout prohibition state designation command is received.

Further, in the above-described embodiment, as the payout motor 289, the stepping motor rotated by the pulse signal (driving signal) from the payout control CPU 371 is used, but a solenoid may be used. In this case, in the power supply stop process, the prize ball count switch 301A and the ball lending count switch 3
Before the process of checking the state of 01B (for example, step S8
16), the process of stopping the driving of the payout motor 289 may be performed. According to this structure, even if the payout motor 289 is configured by using the solenoid, the power consumption can be suppressed.

Further, in each of the above-mentioned embodiments, the payout means has a structure capable of executing both ball lending and prize ball payout, but the mechanism for lending a ball and the mechanism for paying out a prize ball are independent. The present invention can also be applied. In that case, even if the mechanism for performing the ball lending and the mechanism for performing the prize ball payout are independent, as long as the payout control means is configured to control both the mechanisms, as in the above embodiment, A common prize payout that indicates that the game control means prohibits the payout of game media as a prize from the mechanism for paying a prize ball in the payout means, when any of the plurality of prize payout prohibition conditions is satisfied. A prohibition state designation command is transmitted to the payout control means, and it is shown that, regardless of which of the plurality of lending prohibition conditions is satisfied, lending of the game medium from the mechanism for lending a ball in the payout means is prohibited. It can be configured to send a common lending prohibition state designation command to the payout control means.

Further, in each of the above-mentioned embodiments, in the power supply stop process, it is monitored whether or not the game balls have been paid out, and when the game balls have been paid out, it is stored as the number of unpaid game balls. Although the process of subtracting the stored value was performed, it is confirmed whether the prize ball count switch 301A or the ball lending count switch 301B is turned on without performing the process of subtracting the stored value of the unpaid amount, and the confirmation is performed. The result may be stored in the RAM that is backed up by the power supply. In this case, when the power supply is started, the prize ball count switch 301A and the ball lending count switch 301B are turned on during the execution of the power supply stop process based on the stored contents of the RAM whose power is backed up. If it is confirmed, the process of subtracting the stored value of the unpaid amount may be performed. If configured as described above, it is not necessary to change the value stored as the unpaid number in the power supply stop process, so the number of unpaid gaming balls is managed before the power supply is stopped. Therefore, it becomes possible to more surely complete the processing executed.

Further, in each of the above-mentioned embodiments, the payout prohibition condition is satisfied when the ball is out of stock or the lower plate is full, but when it is not desirable to pay other payouts or payout is made, The payout prohibition condition may be satisfied when the payment cannot be performed. For example, when the glass door frame 2 is in the open state, when the count switch short circuit signal is input, and when it is confirmed that the card unit 50 is not connected by the input state of the VL signal, The payout prohibition condition may be established when the ball clogging flag is on or when the lending ball clogging flag is on.

As described in each of the above embodiments, the standby state returning means (the standby state when the power supply to the gaming machine is not stopped in the standby state after the power supply stop process) Means for making it possible to execute the recovery process by returning from the state (meaning that the recovery process does not necessarily have to be executed, and the state of the electric component control means may be reset to recover from the standby state). , Configuration by a single means for returning a plurality of control means (CPU 56, payout control CPU 371) (configuration by a counter 971 provided on a power supply board 910 capable of outputting a return signal)
Alternatively, the game control means and the payout control means are respectively provided (the CPU 56 having the function of resetting the system based on the time-up in the watchdog timer and the payout control CPU 371). However, it may be configured to include a plurality of standby state returning means of different types as described above. In this case, since the functions are duplicated by the plurality of standby state returning means, there is a possibility that a malfunction may occur, so that one of the plurality of standby state returning means of different types is operated with priority, It is desirable that the other one be configured to be operated auxiliary. As a result, even when the function of one of the standby state returning means is stopped due to some trouble, the control means (CPU 5
6. The payout control CPU 371) can surely recover from the standby state.

Further, in each of the above-described embodiments, the infinite loop is used as the standby state, but the present invention is not limited to this, and by using the HALT (HALT) command or the like at the end of the power supply stop process of the control program, the control means is controlled. The control state of the (CPU 56, the payout control CPU 371) may be a standby state (a standby state in which an interrupt can be accepted). In this case, the signal input to the interrupt terminal becomes valid, and the control state can be restored by the signal input trigger to the interrupt terminal, and the standby state restoration means can be configured with a simple configuration. it can.

In each of the above embodiments, R
The means for supplying the backup power to the AM may be provided for each control means (CPU 56, payout control CPU 371). That is, backup RA
A means for supplying backup power may be provided for each RAM including the M area. Further, the number and mounting positions of such means (whether or not they are mounted on the control board or the power supply board) may be configured in any manner.

Further, in each of the above-mentioned embodiments, the power supply from the power supply board 910 to the prize ball count switch 301A is performed through the main board 31, but is performed through the payout control board 37. Good. Further, the power may be directly supplied from the power supply board 910.

Further, in each of the above-described embodiments, the power supply from the power supply board 910 to the ball lending count switch 301B is performed via the payout control board 37.
It may be performed via the main board 31 (for example, when the detection signal of the ball lending count switch 301B is input to the game control means as described later). Further, the power may be directly supplied from the power supply board 910.

In each of the above embodiments, the auxiliary power supply means supplies power to at least the prize ball count switch 301A and the ball lending count switch 301B after the detection signal from the power supply monitoring means is output. As long as it is a prize ball count switch 301A and a ball lend count switch 301B, it may also supply power to something other than the prize ball count switch 301B (a prize detection switch, etc.). It may be one that supplies electric power only. If power is supplied only to the prize ball count switch 301A and the ball lending count switch 301B, the power consumption (charging capacity) of the auxiliary power supply means can be reduced.

Further, in each of the above-mentioned embodiments, the auxiliary power supply means is each electric component control means (CPU 56,
It may be provided for each payout control CPU 371).

Further, in each of the above-described embodiments, the detection signal of the ball lending count switch 301B is the payout control means (the payout control CPU 371 provided in the payout control board 37).
Although it is configured to be input only to, it may be configured to be input to the game control means (CPU 56 included in the main board 31), or may be configured to be input to both the payout control means and the game control means. Then, the game control means is configured to execute the input process of the detection signal of the ball lending count switch 301B in the game control process (specifically, the switch process of step S21 described above) and the power supply stop time process. May be. In this case, in the power supply backup area of the RAM 55 of the game control means, a buffer for storing data indicating the number of unpaid spheres (loan sphere number storage buffer) is provided, and the power supply stop process (FIG. 2).
3 to 25), the same processing as the detection signal input processing of the prize ball count switch 301A shown in steps S467 to S486 described above is executed as the detection signal input processing of the ball lending count switch 301B. You can do this. Also, game control processing (eg, step S
21), the same process as the award ball number subtraction process (see FIG. 44) described above may be executed as a loan ball number subtraction process. Further, in the case of the above configuration, the game control means is provided with a function of executing processing relating to signal exchange with the prepaid card unit 50 in the above-mentioned payout control means, and is lent out using a payout control command. It suffices to perform processing for transmitting information regarding the requested number of lent balls to the payout control means. It should be noted that the ball lending count switch 3 is used in the power supply stop process (FIGS. 23 to 25)
When the input processing of the detection signal of 01B is executed, it may be executed after step S466 and before step S487 (for example, immediately before step S487). With the above configuration, the game control means can manage the number of lent balls. Especially when the detection signal of the ball lending count switch 301B is input to both the payout control means and the game control means,
Both the game control means and the payout control means can execute the management of the number of lent balls, and the management of the number of lent balls can be performed more accurately. In the case of the above configuration, when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained in the switchable range for at least the payout confirmation period, and the ball lending count switch 301B (or the prize) Of course, the capacitance of the capacitor 923 is determined so that the ball count switch 301A and the ball lending count switch 301B) can be operated.

Further, in each of the above-mentioned embodiments, the switch detection process (eg, FIG.
No. 4, processing shown in FIG. 52) and processing of switch detection processing in normal control (processing of step S21 of FIG. 22 including processing of FIG. 29 and processing of FIG. 30, processing of step S752 of FIG. 48). The module and the module can be used as a common processing module (that is, a common subroutine is used). In this case, the contents of the stack pointer are rewritten in the input processing (switch detection processing described above). Therefore, in the case of using the common module, in the game control means, step S
The processing of step 458 may be performed before the processing of step S487, and the payout control means may perform the processing of step S808 before the processing of step S835. It should be noted that the processing module for the switch detection processing in the power supply stop processing and the processing module for the switch detection processing in the normal control are made to be a common processing module as described above by detecting the detection signal of the ball lending count switch 301B. When it is configured to input to the game control means, the ball lending count switch 3 executed by the game control means
This can be applied to the switch detection processing of 01B (detection signal input processing).

In the above-described embodiment, when the power supply is started, step S713 or step S713 is performed.
Although the payout suspension flag is set in 732 to set the payout prohibition state, the output port for outputting a control signal for controlling the ball payout device 97 in step S713 or step S732 (see FIG. 46). The payout prohibited state may be set by clearing the output port C) shown.

In the above-described embodiment, the power supply monitoring means (for example, the power supply monitoring IC 902) outputs the power off signal when the power supply voltage reaches a predetermined value (for example, 22V). For example, an AC power source (for example, A
The AC signal related to C24V) may be digitally converted into a digital signal, and a power-off signal may be output when the digital signal is interrupted for a predetermined period.

Further, in the above-described embodiment, the power-off processing is executed when the power supply monitoring means (eg, power supply monitoring IC 902) detects that the power supply voltage has reached a predetermined value (eg, 22V). Further, the system is configured to be reset when the second power supply monitoring means (for example, the power supply monitoring IC 902) detects that the power supply voltage has reached a predetermined value (for example, 9V). After that, the system may be automatically reset after a lapse of a predetermined period. According to this structure, when the power supply monitoring unit (for example, the power supply monitoring IC 902) detects that the power supply voltage has reached the predetermined value (for example, 22 V), the second power supply monitoring unit (for example, the second power supply monitoring unit) that follows is detected. Even if the detection by the power supply monitoring IC 902) is not made, the system can be surely reset.

Further, in the above-described embodiment, the power-off signal from the power supply board 910 causes the non-maskable interrupt terminal (XNM).
The power supply stop process (FIGS. 23 to 25 and 51 to 53) is executed by the main board 31 and the payout control board 37 in response to the input to I). Alternatively, the main board 31 may output a power-off signal input to the non-maskable interrupt terminal. In this case, the CPU 56 starts the power supply stop processing (FIGS. 23 to 25) in response to the power-off signal from the power supply board 910 being input to the non-maskable interrupt terminal, and also causes the payout control board 37 to operate. Performs processing to output a power-off signal to the non-maskable interrupt terminal. And the payout control CPU 3
When the power-off signal from the main board 31 is input to the non-maskable interrupt terminal 71, the processing 71 is performed when the power supply is stopped (see FIGS. 51 to 5).
3) is started. With this configuration, the power supply board 91
The configuration of 0 can be simplified. In the case of the above configuration, the CPU 56 transmits the command (see FIG. 4).
(2, while executing the processing shown in FIG. 43), when the power-off signal is received, after the command transmission processing is completed,
You may make it perform the process which transmits a power-off signal to the payout control board 37. According to this structure, the payout control board 37 can execute the power supply stop process (FIGS. 51 to 53) after the process related to the reception of the command is completed. Further, in the case of the above configuration, the CPU 56 executes the power supply stop time process toward the payout control board 37 in response to the power-off signal from the power supply board 910 being input to the non-maskable interrupt terminal. The designated payout control command may be transmitted. In this case, when the payout control CPU 371 receives the payout control command designating the execution of the power supply stoppage process, the power supply stoppage process (FIGS. 51 to 53) is started. Further, the sub-boards other than the payout control board 37 (the pattern control board 80, the lamp control board 35, the sound control board 70) may be configured as described above.

In the above-mentioned embodiment, the "specific game state" means a state advantageous to the player to whom a predetermined game value is given. Specifically, the "specific game state" is, for example, a state in which the state of the variable winning ball device is advantageous for a player who is likely to win a hit ball (big hit gaming state), and a right to be a state advantageous for the player. Is a state in which a predetermined game value is given, such as a state in which the game is generated, a state in which the prize game medium payout condition is easily established.

Further, in the above-mentioned embodiment, the "special game state" means a state advantageous to the player who is prone to a big hit. Specifically, "special game state"
Is, for example, a probability variation state in which the probability that the special symbols are arranged in a big jackpot pattern is a high probability state, a time saving state in which the number of fluctuations of the ordinary symbol per unit time is increased, and an opening period and the number of times of opening the variable winning ball device 15 are increased. It is a high-probability state in which the probability of a big hit such as the extended extension state is increased. In the time saving state, since the number of times the variable winning ball device 15 is opened is increased, the number of winnings per unit time is increased, and the number of times the special symbol is variably displayed per unit time is increased. Can be said to have been raised. Similarly, in the extended open state, the number of winnings per unit time is increased because the opening period and the number of times of opening the variable winning ball device 15 are increased, and the number of times the special symbol is displayed variable per unit time is increased. Therefore, it can be said that the probability of being a big hit is increased.

The pachinko game machine of each of the above-mentioned embodiments is
Mainly, a predetermined game value can be given to the player when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols.
Although it was a kind of pachinko machine, a kind of pachinko machine that can give a predetermined game value to the player if there is a prize in the predetermined area of the electric role to open based on the start prize, and a start prize Even if it is a third-class pachinko game machine, a predetermined right is generated or continues when there is a prize for a predetermined electric accessory that is released when a stop symbol of the symbols variably displayed based on the above is a combination of predetermined symbols The present invention can be applied.

Furthermore, the present invention is applicable not only to a pachinko gaming machine in which the game medium is a game ball, but also to a slot machine or the like provided with electric parts for paying out the game medium.

[0532]

As described above, according to the invention described in claim 1, the game control means executes the command transmission program for transmitting the command to the electric component control means, and the game progresses. And a power supply stop processing for storing data necessary for restoring the control state in the variable data storage means in response to a detection signal from the power supply monitoring means. , A command called by the command transmission means by a subroutine call in the restoration processing, which executes restoration processing for restoring the control state to the state before the power supply is stopped based on the stored contents stored in the fluctuation data storage means. By executing the transmission program, the process of transmitting a command to the electrical component control means to restore the control state before the power supply was stopped is executed. , The variable data storage means includes a stack area for saving the program address data related to the address of the control program being executed in response to the subroutine call, and the game control means has the address indicated by the stack pointer. Of the data saved in the stack area, the address where the data to be read next is stored is specified, and the stack address data related to the address indicated by the stack pointer is stored as the variable data in the process when the power supply is stopped. In the restoration process, the stack pointer is set by the stack address data saved in the variable data storage unit in the power supply stop process before the command transmission unit first sends the command in the restoration process. Is characterized by Since the process for transmitting the command in the process can be performed by the subroutine, the capacity of the program for executing the process for restoring the game state can be reduced, and the game state can be restored. This has the effect that the processing of can be efficiently executed in terms of the program configuration.

According to the second aspect of the invention, the game control means executes the restoration process when the power supply is restored and the predetermined restoration condition is satisfied, and when the predetermined restoration condition is not satisfied, the fluctuation occurs. Since the initialization processing for initializing the storage contents held in the data storage means is executed, the control state can be restored only when the restoration condition is satisfied.

According to the third aspect of the invention, the payout control means controls the payout prohibition state in which the payout of the game medium is prohibited when the power supply is started, and the predetermined command is received from the game control means. Since the payout prohibition state is released accordingly, the payout prohibition state can be released after it is confirmed that the game control means has started control, and the game control means can control the state. It is possible to reliably prevent the payout control means from starting the payout process before it happens.

In the invention according to claim 4, the command transmitting means transmits to the payout control means a payout state designating command for designating whether to prohibit or permit the payout of the game medium in the recovery processing, Since the payout control means is configured to cancel the payout prohibition state when the payout state designation command permits the payout of the game medium, the payout control is performed according to the actual state of the gaming machine. The control state of the means can be restored. Further, the processing for transmitting the payout state designation command can be performed by the subroutine.

According to the fifth aspect of the invention, in connection with the start of the power supply to the gaming machine, the electric parts control means controls the electric parts at the time when the game control means becomes in a state where the control related to the game becomes possible. Since the starting order regulation means for regulating the time to be later than the time when the electric power supply is possible is provided, the electric component control means for receiving the command from the game control means at the start of the power supply surely receives the command. The effect is that you can.

According to the sixth aspect of the present invention, the command transmitting means transmits the starting winning memory number designating command for designating the starting winning memory number to the starting winning memory number display control means in the restoration process. Since it is configured, it becomes possible to perform the processing for transmitting the command for specifying the number of memory for starting winning prizes by a subroutine. Further, when the game is restarted, the player can be surely notified of the number of memory for winning the winning prize for starting.

In the invention according to claim 7, the command transmitting means is configured to transmit a special game state designation command for designating whether or not it is in the special game state to the display control means in the recovery processing. Therefore, the subroutine for transmitting the special game state designation command can be performed. Further, when the game is restarted, it can be surely notified to the player whether or not it is in the special game state.

[0539] In the invention of claim 8, the command transmitting means issues an identification information designating command for designating the display result of the identification information to be displayed on the variable display device at the time related to the stop of the power supply in the restoration process. Since it is configured to be transmitted to the display control means, it becomes possible to perform the processing for transmitting the identification information designation command for restoring the information regarding the display result of the identification information by the subroutine. Further, it becomes possible for the player to recognize the display result of the identification information when the game is restarted.

According to the ninth aspect of the present invention, the game control means performs predetermined game control according to a timer interrupt that occurs at predetermined time intervals, and in the restoration process, the command transmission means instructs the electric component control means. After sending the command,
Since the setting is made to generate the timer interrupt every predetermined period, it becomes easy to synchronize the game control means and the electric component control means.

According to the tenth aspect of the present invention, the game control means is configured to execute the processing for prohibiting access to the variable data storage means in the power supply stop processing, so that the power supply is stopped. It is possible to prevent the contents of the fluctuation data storage means from being destroyed after the processing.

In the eleventh aspect of the present invention, the game control means is configured to perform processing for clearing the output signal by outputting a clear signal to the output port in the power supply stop processing. Therefore, the output port is cleared before the power supply is stopped, and the output signal is reliably cleared.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is a front view showing the front surface of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine viewed from the back side.

FIG. 4 is a rear view of a mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a front view showing an exposed portion of a power supply board installed on the mechanism plate.

FIG. 7 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 8 is a block diagram showing a circuit configuration example of a payout control board.

FIG. 9 is a block diagram showing a circuit configuration example of a symbol control board.

FIG. 10 is a block diagram showing a circuit configuration example of a lamp control board.

FIG. 11 is a block diagram showing a circuit configuration example of a power supply board.

FIG. 12 is an explanatory diagram showing another configuration example of the clear switch.

FIG. 13 is a block diagram showing a configuration example of a reset management circuit.

FIG. 14 is a block diagram showing an example of the configuration around a CPU.

FIG. 15 is a timing chart for explaining the operation of a counter which is an example of timer means.

FIG. 16 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 17 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 18 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 19 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 20 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state recovery process.

FIG. 21 is a flowchart showing a game state recovery process.

FIG. 22 is a flowchart showing a 2 ms timer interrupt process.

FIG. 23 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 24 is a flowchart showing non-maskable interrupt processing (processing when power supply is stopped).

FIG. 25 is a flowchart showing non-maskable interrupt processing (processing when power supply is stopped).

FIG. 26: Power supply drop and N when power supply to a game machine is stopped
It is a timing diagram which shows a mode of MI signal.

FIG. 27 is a timing chart showing an example of how a detection signal input process is executed.

FIG. 28 is an explanatory diagram showing a formation example of a switch timer in a RAM.

FIG. 29 is a flowchart showing an example of a switch process.

FIG. 30 is a flowchart showing an example of a switch check process.

FIG. 31 is a flowchart showing an example of prize ball processing.

FIG. 32 is a flowchart showing an example of prize ball processing.

FIG. 33 is a flowchart showing an example of prize ball processing.

FIG. 34 is a flowchart showing a switch-on check process.

FIG. 35 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 36 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 37 is an explanatory diagram showing an example of a command form of a control command.

FIG. 38 is a timing diagram showing a relationship between an 8-bit control signal forming a control command and an INT signal.

FIG. 39 is an explanatory diagram showing an example of contents of a payout control command.

FIG. 40 is an explanatory diagram showing an example of the contents of a display control command.

FIG. 41 is an explanatory diagram showing an example of contents of a lamp control command.

FIG. 42 is a flowchart showing a processing example of command setting processing.

FIG. 43 is a flowchart showing a command transmission processing routine.

FIG. 44 is a flowchart showing an example of a prize sphere number subtracting process.

FIG. 45 is a block diagram showing a configuration example around a payout control CPU.

FIG. 46 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 47 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 48 is a flowchart showing a main process executed by a CPU in the payout control board.

FIG. 49 is a flowchart showing a 2 ms timer interrupt process.

FIG. 50 is a flowchart showing a payout state recovery process.

FIG. 51 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 52 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 53 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 54 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 55 is an explanatory diagram showing a configuration example of a reception command buffer.

FIG. 56 is a flowchart showing an example of command reception processing of the payout control CPU.

FIG. 57 is a flowchart showing an example of switch processing.

FIG. 58 is a flowchart showing an example of payout prohibition state setting processing.

FIG. 59 is a flowchart showing an example of command analysis execution processing.

FIG. 60 is a flowchart showing an example of ball lending control processing.

FIG. 61 is a flowchart showing an example of ball lending control processing.

FIG. 62 is a flowchart showing an example of prize ball control processing.

FIG. 63 is a flowchart showing an example of prize ball control processing.

FIG. 64 is a timing chart showing an example of the timing at which the payout process is executed after the power supply is started.

FIG. 65 is a block diagram showing a configuration of a gaming machine.

FIG. 66 is a flowchart showing another example of non-maskable interrupt processing (power supply stop processing).

FIG. 67 is a flowchart showing another example of the non-maskable interrupt process (power supply stop process).

FIG. 68 is a flowchart showing another example of the non-maskable interrupt process (power supply stop process).

69 is a flow chart showing another example of the power supply stop time process in the game control means. FIG.

FIG. 70 is a flowchart showing another example of the power supply stoppage process in the payout control means.

71 is a block diagram showing a part of another configuration example of the game control means. FIG.

72 is a flowchart showing another example of the 2 ms timer interrupt process executed by the CPU on the main board. FIG.

FIG. 73 is a timing chart for explaining the operation of the software timer and watchdog timer circuit.

FIG. 74 is a block diagram showing a part of another configuration example of the payout control means.

FIG. 75 is a flowchart showing another example of main processing executed by the CPU of the payout control board.

[Explanation of symbols]

1 Pachinko machine 31 Game control board (main board) 37 Discharge control board 56 CPU 371 CPU for payout control 910 Power board 902 Power supply monitoring IC (power supply monitoring means) 971 counter

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuo Kambayashi             Gunma Prefecture Kiryu City Sakaino-cho 6-460 Stock             Company Sankyo F-term (reference) 2C088 BA02 BA13 BA21 BA28 BA32                       BA37 BC58 BC70 EB56 EB58

Claims (11)

[Claims] 1. A gaming machine in which a player can play a predetermined game, wherein the electronic component control means for controlling electrical components provided in the gaming machine, and the game control for controlling the progress of the game. Means, a variable data storage means capable of retaining the stored contents for a predetermined period even if the power supply to the gaming machine is stopped, and a state of a predetermined power source used in the gaming machine are monitored to the gaming machine. And a power supply monitoring means for outputting a detection signal when a detection condition relating to the stop of the supply of electric power is satisfied, and the game control means executes a command transmission program for transmitting a command to the electric component control means. Has command transmission means for transmitting a command according to the progress of the game, and saves the data necessary for restoring the control state in accordance with the detection signal from the power supply monitoring means in the fluctuation data storage means And a restoration process for restoring the control state to the state before the power supply is stopped based on the stored contents stored in the fluctuation data storage means, and the command transmission means By executing the command transmission program called by a subroutine call in the restoration process, a process for transmitting a command for restoring the control state before the power supply is stopped to the electric component control means is executed, The variable data storage means includes a stack area for saving program address data related to the address of the control program being executed in response to a subroutine call, and the game control means is indicated by a stack pointer. Of the data saved in the stack area by address, the next read An address in which data to be stored is specified, and in the power supply stop process, a stack address data related to the address indicated by the stack pointer is saved in the variable data storage means, and the restoration process is performed. In the above, before the command transmitting means first transmits a command, the stack pointer is set by the stack address data saved in the fluctuation data storage means in the power supply stop processing. Machine. 2. The game control means executes a restoration process when the power supply is restored and a predetermined restoration condition is satisfied, and when the predetermined restoration condition is not satisfied, the game control means holds it in the fluctuation data storage means. The gaming machine according to claim 1, which executes an initialization process for initializing the stored contents. 3. The electric component control means includes a payout control means for controlling a payout means for paying out the game medium, and the payout control means prohibits the payout of the game medium when power supply is started. 3. The gaming machine according to claim 1, wherein the payout prohibited state is controlled, and the payout prohibited state is released in response to reception of a predetermined command from the game control means. 4. The command transmitting means transmits a payout state designation command for designating whether to prohibit or permit payout of the game medium in the recovery processing, to the payout control means, and the payout control means The gaming machine according to claim 3, wherein the payout state designation command releases the payout prohibition state when the payout of the game medium is permitted. 5. In connection with the start of power supply to the gaming machine,
The game control means is provided with a starting sequence regulation means for regulating the time when the control relating to the game becomes possible to be later than the time when the electric component control means becomes the state where the electric parts can be controlled. The gaming machine according to any one of claims 1 to 4. 6. The electric component control means displays a display control means for controlling a variable display device that variably displays identification information, and a start winning award storage number that indicates the number of times that the variable display of identification information is held on the variable display device. The starting prize winning memory number display control means for controlling the starting winning prize memory number display means, and the command transmitting means, in the restoration process, issues a starting winning prize memory number designating command for designating the starting winning prize memory number. The gaming machine according to any one of claims 1 to 5, which is transmitted to the number display control means. 7. The electric component control means includes display control means for controlling a variable display device that variably displays identification information, and the gaming machine has a specific display result of the identification information displayed on the variable display device. It is possible to control to a specific game state that is advantageous to the player on the condition that the display mode is set,
The identification information can be controlled to a special game state that is likely to be the specific display mode, and the command transmission means, in the restoration process, a special game state designation command for designating whether or not the special game state is,
The gaming machine according to any one of claims 1 to 5, which transmits to the display control means. 8. The electrical component control means includes a display control means for controlling a variable display device that variably displays identification information, and the command transmission means is a restoration process at a time related to stop of power supply. The gaming machine according to any one of claims 1 to 5, wherein an identification information designating command that designates a display result of the identification information to be displayed on the variable display device is transmitted to the display control means. 9. The game control means performs predetermined game control according to a timer interrupt generated every predetermined period, and after the command transmission means transmits a command to the electric component control means in the recovery processing. The gaming machine according to any one of claims 1 to 8, wherein settings are made to generate the timer interrupt every predetermined period. 10. The game machine according to claim 1, wherein the game control means executes processing for prohibiting access to the fluctuation data storage means in the power supply stop processing. 11. The game control means includes an output port for outputting an output signal, and the game control means outputs a clear signal to the output port in a power supply stop process. The gaming machine according to claim 1, which performs processing for clearing a signal.