JP2005143649A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which enables the accurate determination of the putting out of the prize game media while reducing the number of parts pertaining to the putting out of the game media. <P>SOLUTION: A put-out ball counting switch is provided to be used in common for the detection of the putting out of the prize balls and for the sensing of the putting out of the dispensing balls and the sense signal is applied to the put-out control microcomputer. The prize ball counting signal indicating the sensing of putting out the prize balls is transmitted to the game control microcomputer (S 609d) from the put-out control microcomputer responding to the sensing of putting out the prize balls (S601)(S601-S609d). Moreover, even under the error condition, the put-out control microcomputer subtracts the number of game media put out as stored each time the prize ball counting signal is determined to match the sensing of putting out the prize balls (checking of the error bits is not executed at S601-S612). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gaming machine represented by a pachinko gaming machine or a coin gaming machine. Specifically, it is possible for a player to play a predetermined game using a game medium, and the payout condition is satisfied by the payout of the prize game medium as a prize based on the fact that the payout condition is satisfied by the game and the loan request. The present invention relates to a gaming machine that pays out rental game media based on the above.

  What is conventionally known as this kind of gaming machine, for example, it is possible for a player to play a predetermined game using a game medium such as a game ball, the game to the winning a prize in the game Payouts of premium game media as prizes based on fulfillment of payout conditions due to winning of media, etc., and payout of rental game media based on fulfillment of payout conditions based on a loan request based on a player's lending operation, etc. There is something.

  In such a conventional gaming machine, the progress of the game is controlled by a game control microcomputer consisting of a game control microcomputer, and the prize game medium and the rental game medium are controlled by a payout control microcomputer consisting of a payout control microcomputer. A configuration was adopted in which the payout was controlled. In the gaming machine having such a configuration, when the payout control microcomputer receives a payout control signal for instructing payout control of the prize game medium from the game control microcomputer, the control for paying out the prize game medium is performed. Executed by a computer.

  Specific examples of such conventional gaming machines include the following. First, there was a gaming machine in which detection means comprising count switches for detecting payout of prize game media were separately provided for detection output to the game control microcomputer and for detection output to the payout control microcomputer ( Patent Document 1).

Further, a detection means comprising a count switch for detecting the payout of the prize game medium is provided in common for the detection output to the game control microcomputer and the detection output to the payout control microcomputer, and the detection means Apart from this, there has been a gaming machine provided with detection means comprising a count switch for detecting payout of rental game media for detection output to a payout control microcomputer (Patent Document 2 and Patent Document 3).
Japanese Patent Laid-Open No. 11-244491 (FIG. 6) JP 2000-33171 A (FIG. 15) Japanese Patent Laying-Open No. 2003-190539 (FIG. 7)

  As described above, in the conventional gaming machine, a plurality of detection means for detecting the payout of game media are provided for each control means, for example, for each detection target game medium. For this reason, in the conventional gaming machine, the number of parts increased, resulting in an increase in manufacturing cost. Further, in the conventional gaming machine, regarding the payout of game media, it is required to accurately grasp the payout of premium game media.

  The present invention has been conceived in view of such circumstances, and an object of the present invention is to provide a gaming machine capable of reducing the number of parts related to payout of game media and accurately grasping payout of premium game media. It is to be.

Specific examples of means for solving the problems and their effects

(1) A prize game medium as a prize based on the fact that a player can play a predetermined game using a game medium (game ball) and a payout condition is satisfied by the game (for example, a prize is generated) A game machine (pachinko machine 1) that pays out a prize ball and pays out a rental game medium (rental ball) based on a payment condition established by a loan request (for example, generation of a loan request from a player) Because
A game control microcomputer (CPU 56 etc.) for executing a game control process for controlling the progress of the game;
A payout means (ball payout device 97) for paying out the premium game medium and the rental game medium;
A means for controlling the payout means for paying out the prize game medium when a payout control signal (payout control signal) for instructing payout control of the prize game medium is received from the game control microcomputer; A payout control microcomputer (such as a payout control CPU 371) for controlling the payout means;
A means commonly used for detecting the payout of the premium game medium and the payout of the rental game medium, and outputs a payout detection signal to the payout control microcomputer in response to the detection of the payout of the game medium. A payout detection means (payout number count switch 301) to give,
The game control microcomputer includes payout control signal transmission means (a portion for executing a prize ball transmission process of S232 executed by the CPU 56) for transmitting the payout control signal based on the fact that the payout condition is satisfied,
The payout control microcomputer includes:
A payout type determination means (S602, S603) for determining whether the payout detection signal from the payout detection means corresponds to the detection of the payout of the premium game medium or the rental game medium; ,
A prize game medium payout detection indicating that the payout of the prize game medium is detected when the payout type determination means determines that the payout detection signal is in response to the detection of the payout of the prize game medium. A payout detection signal transmitting means (S609c) for transmitting a signal (prize ball count signal) to the game control microcomputer;
Error determination means (S801, S821, S822, S654, S658, S562, S564, S828a) for determining whether a predetermined error (payout case error, full tank error, etc.) has occurred;
Storage means (RAM provided in the payout control microcomputer) for storing the payout number of prize game media to be paid out in accordance with the payout control signal;
Each time the payout type determination means determines that the payout detection signal is in response to the detection of payout of the prize game medium, a payout number storage subtracting means for subtracting the payout number stored in the storage means ( S604)
The payout number storage subtracting means detects the payout of the prize game medium by the payout type determining means even when the error determining means determines that the predetermined error has occurred. Each time it is determined that it is in accordance with the number of payouts stored in the storage means, the error bit check is not executed in the prize ball lending control processing of FIG. 50 including S604.
According to such a configuration, the payout detecting means used in common for detecting the payout of the premium game medium and the payout of the rental game medium is provided, and the payout detection signal is provided to the payout control microcomputer. It is determined whether the payout detection signal corresponds to the detection of the payout of the premium game medium or the rental game medium according to the detection of the payout of the premium game medium. Sometimes, a prize game medium payout detection signal indicating that a prize game medium payout has been detected is transmitted to the game control microcomputer. Therefore, the detecting means for detecting the payout of the game medium is commonly used for grasping the number of payouts of the prize game medium and the rented game medium in the payout control microcomputer, and the payout control microcomputer and the game control It is commonly used to grasp the payout of premium game media on a microcomputer. Thereby, the number of parts relating to the payout of game media can be reduced, and as a result, the manufacturing cost of the gaming machine can be reduced. Further, even when it is determined that a predetermined error has occurred, every time it is determined that the payout detection signal is in response to the detection of the payout of the premium game medium, it is stored in the storage means. Since the number of payouts is subtracted, the payout control microcomputer can grasp the payout of premium game media in all states including the error state. Thereby, in the gaming machine, the payout of the prize game medium can be accurately grasped.

(2) It further includes payout notifying means (prize ball lamp 51) for notifying payout of the prize game medium,
The game control microcomputer, when receiving the prize game medium payout detection signal, performs control for notifying the payout notification means of the payout of the prize game medium (FIG. 23, a prize ball payout confirmation designation command). Send).

  According to such a configuration, when the game control microcomputer receives the prize game medium payout detection signal, the payout notifying means performs control to notify the payout of the prize game medium. Can be easily confirmed from the outside.

(3) A plurality of control devices that are controlled in response to receiving control signals for controlling the effect devices (variable display device 9, light emitters such as lamps and LEDs, speakers 27) for performing game effects transmitted from the game control microcomputer. A display control microcomputer (display control CPU 101, etc., lamp control CPU 351, sound control CPU 701, etc.),
The rendering device includes a variable display device (variable display device 9) that displays a plurality of types of identification information (symbols) that can be identified.
The display control microcomputer that controls the display of the variable display device among the plurality of effect control microcomputers receives a first control signal (display control command) transmitted from the game control microcomputer as the control signal. Accordingly, a process of executing display control by rewriting the display image to be displayed on the variable display device at every predetermined rewriting timing (rewriting timing of special symbol, every 33 ms), and other processing synchronized with the rewriting timing. A process of transmitting a second control signal (lamp control command, sound control command) to the effect control microcomputer is executed (S327 to S329).

  According to such a configuration, the display control microcomputer of the plurality of effect control microcomputers has received the second control signal transmitted in response to the reception of the first control signal from the game control microcomputer. Accordingly, in the configuration in which another effect control microcomputer controls the effect device, the second control signal is transmitted in synchronization with the display rewrite timing on the change display device, whereby the display on the change display device is performed. For example, the control timing of the other effect devices can be synchronized with the rewriting timing, so that the timing between the control of the variable display device and the control of the other effect devices is unlikely to occur.

(4) The display control microcomputer
Image selection means (S901, S914) for selecting an image (background preview image) to be displayed on the variable display device in response to reception of the first control signal;
Control signal storage means (control ROM provided on the display control board 80) for storing a plurality of types of the second control signals;
Based on which image is selected by the image selection means, one of the second control signals is selected from the control signal storage means (a kind of lamp control command, sound control command according to the type of background notice) Control signal selection means (S917),
Further, the display control microcomputer performs a variable display control based on the image selected by the image selection means (S326) and transmits the second control signal selected by the control signal selection means. Are executed (S406, S496).

  According to such a configuration, the display control microcomputer independently selects an image to be displayed on the variable display device in response to reception of the first control signal, and a plurality of types are selected based on which image is selected. Since any second control signal is selected from the second control signals, the selection of the control contents can be shared between the game control microcomputer and the display control microcomputer. The control burden on the microcomputer can be reduced.

(5) The display control microcomputer is mounted on a display control board (display control board 80),
The other effect control microcomputer is mounted on another effect control board (lamp control board 35, sound control board 70),
When the first detection condition relating to the stop of power supply to the gaming machine is satisfied, the first signal (power-off signal from the power supply board 910) is turned on, and the first detection condition (+ 24V is + 5V) The second detection condition (the power-off signal is output (set to low level)) is set to be satisfied after the following period has been satisfied for a predetermined time) Power supply monitoring means (power supply monitoring circuit 920) for turning on the second signal (reset signal from the power supply board 910) when the period has passed and VCC has exceeded, for example, + 4.5V Further including
The first signal is a backup signal (power-off signal) that causes the microcomputer to which the first signal is input to recognize a decrease in power supply to the gaming machine,
The second signal is a reset signal (reset signal) that causes a microcomputer to which the second signal is input to perform a system reset,
At least one of the display control board and the other effect control board monitors a specific signal (clear pulse) periodically turned on from the microcomputer, and the specific signal is turned on. Microcomputer monitoring means (watchdog timer circuit 357) for turning on a third signal (Q output signal of the watchdog timer circuit 357) for causing the microcomputer to execute a system reset when it has run out,
At least one of the display control board and the other effect control board is either one of the second signal from the power supply monitoring means and the third signal from the microcomputer monitoring means. An input circuit (NAND circuit 360) that turns on a special signal (an output signal of the NAND circuit 360) when the signal is turned on is provided.

  According to such a configuration, the input circuit provided in at least one of the display control board and the effect control board has the second signal that is a signal for executing a system reset from the power supply monitoring unit, A special signal is turned on when any one of the third signal, which is a signal for executing a system reset from the microcomputer monitoring means, is turned on. It is possible to reset the system of the production control microcomputer based on the special signal at the time and during the runaway control microcomputer.

  (6) The power supply monitoring means is input from the power supply monitoring means to the effect control board without passing through the display control board (FIGS. 6 and 82). The second signal is turned on. .

  According to such a configuration, the power supply monitoring unit turns on the second signal input from the power supply monitoring unit to the effect control board without going through the display control board. It can be simplified.

  Embodiments of the present invention will be described below in detail with reference to the drawings. In the following embodiments, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to this, and may be, for example, a coin gaming machine, a slot machine, etc. A payout of a prize game medium as a prize based on the fact that a payout condition is satisfied by the game, and a payout of a rental game medium based on the fact that the payout condition is satisfied by a loan request. It can be applied to all gaming machines that perform the above.

  First, an overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 is a gaming machine in which a player can perform a predetermined game using a game ball (pachinko ball) as a game medium, and an outer frame (not shown) formed in a vertically long rectangular shape. ) And a game frame attached inside the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the game balls. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display units each displaying a symbol as identification information in a variable manner. The fluctuation display device 9 includes, for example, three fluctuation display portions (symbol display areas) of “left”, “middle”, and “right”. Further, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, the symbol display area and the start memory display area are provided separately, so that the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during the variable display. In this example, the start memory display area is provided in the variable display device 9, but a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V winning switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the display variation of the normal symbol display 10 is started. In this embodiment, the left and right lamps (the symbols can be visually recognized when lit) are alternately lit to perform variable display. For example, if the right lamp is lit at the end of the variable display, it is a win. When the stop symbol in the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times for a predetermined time. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increments the LED to be turned on by one. Then, each time the variable display of the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the pachinko gaming machine 1.

  In this example, a prize ball LED 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the supply ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter referred to as a card unit) that enables lending of a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and the card unit When checking the card insertion indicator lamp that indicates that a card has been inserted, the card insertion slot into which a card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special display of the special display on the variable display device 9 starts changing (variation) if the variable display of the symbol can be started. If it is not in a state where the symbol variation display can be started, the starting memory number is increased by one.

  The special symbol variation display in the variation display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When the game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the fluctuation display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol on the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol, or when the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state. Note that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the pachinko gaming machine 1 as seen from the back side.

  As shown in FIG. 2, on the back side of the pachinko gaming machine 1, a variable display control unit 49 including a display control board 80 on which display control means for controlling the variable display device 9 is mounted, a game control micro that controls the progress of the game A game control board (main board) 31 on which a computer or the like is mounted is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed.

  The display control means is realized by a display control microcomputer, VDP or the like mounted on the display control board 80. Although not shown, the pachinko gaming machine 1 includes various decoration LEDs provided on the game board 6, a normal symbol start memory display 41, a decoration lamp 25, a ceiling frame lamp 28a provided on the frame side, A lamp control board 35 on which lamp control means for controlling the left frame lamp 28b, right frame lamp 28c, and the like are mounted, and a voice control board 70 on which sound control means for controlling the speaker 27 are mounted. . The lamp control means is realized by a light emitter control microcomputer mounted on the lamp control board 35 or other circuits. The sound control means is realized by a sound control microcomputer mounted on the sound control board 70 or other circuits. A plurality of microcomputers including a display control microcomputer, a light emitter control microcomputer, and a sound control microcomputer include a presentation device (a variable display device 9, a light emitter such as a lamp / LED, a speaker, etc.). 27) is collectively referred to as an effect control microcomputer for controlling. Each control board on which these effect control microcomputers are mounted is generically referred to as an effect control board.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Most of the power supply substrate 910 overlaps with the main substrate 31, but there is an exposed portion that is exposed so as not to overlap with the main substrate 31. The exposed portion is provided on the main board 31 and each electrical component control board (display control board 80, lamp control board 35, voice control board 70 and payout control board 37) and the pachinko gaming machine 1 in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to each electrical component, and a memory content holding means included in the main board 31 and the payout control board 37 (for example, the contents when the power supply is stopped) And a clear switch as operation means for clearing the backup data stored in the backup RAM). Furthermore, a replaceable fuse is provided inside the power switch at the exposed portion (inside the substrate).

  Each electric component control board (display control board 80, lamp control board 35, voice control board 70 and payout control board 37) includes an electric part control means (display control means, lamp control means) including an electric part control microcomputer. Voice control means and payout control means). The electrical component control means is an electrical component provided in the pachinko gaming machine 1 in accordance with a command signal (control signal) from the game control means (game device: ball payout device 97, variable display device 9, light emission of lamp, LED, etc. Body etc.). Hereinafter, description may be made by including the main board 31 in the electric component control board. In that case, the electrical component control means mounted on the electrical component control board includes a game control means, a means for controlling the electrical components provided in the pachinko gaming machine 1 in accordance with a command signal from the game control means, and a game Each means means for controlling an electrical component provided in the pachinko gaming machine 1 in accordance with a command signal from a control means other than the control means. Further, a board on which a microcomputer that directly receives a command signal from the main board 31 is sometimes referred to as a sub board, and a microcomputer that indirectly receives a command signal from the main board 31 via the sub board. A substrate on which is mounted may be referred to as a sub-sub substrate.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Near the center, an information terminal board (information output board) 34 having terminals for outputting various information from the main board 31 to the outside of the pachinko gaming machine 1 is installed.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A through the curve rod. Above the ball payout device, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device stops. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning prizes or game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. Further, when the game ball is paid out, a sensing lever (not shown) presses a full tank switch (not shown) as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the driving of the hitting ball launching device also stops.

  FIG. 3 is a front view (FIG. 3 (A)) and a cross-sectional view (FIG. 3 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball payout device 97 is fixed to the lower part of the passage body installed between the ball break switch 187 and the ball payout device 97. The passage body has a ball passage for flowing down two rows of game balls whose flow-down direction is converted into the left-right direction by a curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage. In practice, a ball break switch is installed in each ball passage. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 stops detecting a game ball, the ball discharge device 97 has a payout motor (not shown in FIG. 3). Rotation is stopped and game ball payout is immobilized.

  The ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path.

  In the ball payout device 97, a payout motor (not shown) by a stepping motor rotates a cam, for example, and pays out one game ball or one game ball based on a ball lending request. Further, below the ball payout device 97, for example, a payout number count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout number count switch 301 is turned on. That is, the payout number count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control means can count the number of game balls actually paid out by the detection signal of the payout number count switch 301. In this example, the payout number count switch 301 detects both the payout winning balls and the lending balls. In other words, the payout number count switch 301 is an example of a payout detection unit that commonly detects a payout game ball without distinguishing between a winning ball and a rental ball.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. However, a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is constituted by a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Further, for example, it may be configured to separate the winning ball payout and the ball lending by changing the rotation direction of the cam or sprocket, or the ball paying device 97 exemplified in the present embodiment (the cam is rotated by the motor). The present invention can be applied to any structure other than the structure). In this example, even if the prize balls and the rental balls are paid out separately, both the paid-out prize balls and the rental balls are in the area detected by the payout number count switch 301. It is guided and detected in common by the payout number count switch 301.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 29a, 30a, 33a, 39a, and Basically, an input circuit 68 for supplying a signal from the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball apparatus 15, a solenoid 21 for opening and closing the opening and closing plate 20, and a solenoid 21A for switching a path in the special winning opening. A solenoid circuit 59 that is driven in accordance with a command from the circuit 53 is mounted.

  The switches such as the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, and 39a may be referred to as sensors. That is, the name of the game medium detection means (game ball detection means in this example) that can detect a game ball is not limited. Each of the start port switch 14a, the V winning switch 22, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a for detecting a winning is also a winning detecting means. Note that the winning detection means may be configured to collectively detect the respective game balls that have been won separately at the plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball enters the passing gate and a winning is achieved, and a switch ( For example, the gate switch 32a) serves as a winning detection means. Further, in this embodiment, since the game balls won in the V prize area are detected only by the V prize switch 22, the number of game balls won in the big prize opening is the number detected by the V prize switch 22 and the count switch 23. It becomes the sum with the detection number by. However, the game ball that has won the V winning area may be detected by the V winning switch 22 and also by the count switch 23. In this case, the number of game balls won in the big winning opening corresponds to the number detected by the count switch 23.

  Further, on the main board 31, in accordance with the data given from the basic circuit 53, jackpot information indicating the occurrence of jackpot, effective start information indicating the number of start winning balls used for starting the display of the symbols on the variation display device 9, An information output circuit 64 that outputs an information output signal such as probability variation information indicating that a probability variation has occurred to an external device such as a hall computer is mounted.

  A basic circuit 53 realized by a game control microcomputer includes a ROM 54 that stores a program for game control (game progress control), and storage means used as a work memory (variation data storage means that stores fluctuation data). A RAM 55, a CPU 56 that performs control operations according to a program, and an I / O port unit 57 are included. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since CPU 56 executes control according to a program stored in ROM 54, what CPU 56 executes (or performs processing) hereinafter means that CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31. The game control means is realized by a circuit that implements various functions including a basic circuit 53 that is mounted on a main board (game control board) 31 and corresponds to a game control microcomputer. That is, the game control microcomputer is realized by the basic circuit 53 including not only the CPU 56 but also the ROM 54 and RAM 55, and the game control means is realized by various circuits including the basic circuit 53 mounted on the main board 31. The processing in the game control means is realized mainly by the CPU 56 in the game control microcomputer executing according to the program.

  The RAM 55 is an example of a storage unit used in the game control unit, and is a backup RAM as a non-volatile storage unit, part or all of which is backed up by a backup power source created on the power supply board 910. That is, even if the power supply to the pachinko gaming machine 1 is stopped, a part or all of the contents of the RAM 55 are stored for a predetermined period (until the power supply of the backup power supply is disabled). In particular, at least data (special symbol process flag or the like) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power supply is restored after a power failure or the like. . In this embodiment, it is assumed that the entire RAM 55 is backed up. That is, in this example, the RAM 55 and the backup RAM match.

  A reset signal from the power supply board 910 is input to the reset terminal of the CPU 56. The reset signal from the power supply board 910 is delayed by the delay circuit 69 in the main board 31. Further, a power-off signal output from the power supply substrate 910 is input to the basic circuit 53 (specifically, an input port) via the input driver circuit 68. The power-off signal may be an NMI signal that cannot be masked.

  The hitting ball launching device that hits and launches the game ball includes a launch motor 94 that is controlled by a circuit on the payout control board 37, and launches the game ball toward the game area 7 as the launch motor 94 rotates. A drive signal for driving the firing motor 94 is transmitted to the firing motor 94 via the touch sensor substrate 91. The touch sensor detects that the player is touching the operation knob (hitting ball handle) 5 and a signal from the touch sensor is mounted on the touch sensor substrate 91 (the player touches the operation knob 5). Is transmitted to the payout control board 37 via a circuit including a detection circuit for detecting whether or not it is touched. The circuit on the payout control board 37 stops the driving of the firing motor 94 when the signal from the touch sensor circuit indicates an off state. Note that the operation knob 5 is provided with a touch ring that adjusts the resilience and is a part that the player contacts. In the pachinko gaming machine 1, the touch sensor substrate 91 is disposed between the touch ring and the payout control substrate 37, and is disposed in the vicinity of the touch ring. Specifically, the wiring length between the touch ring and the touch sensor substrate 91 is shorter than the wiring length between the touch sensor substrate 91 and the payout control substrate 37.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board, and is provided on the frame side. The display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51 and the ball-out lamp 52 is performed. Each lamp may be an LED or other types of light emitters. That is, a lamp or LED is an example of a light emitter. Further, display control of the fluctuation display device 9 for variably displaying the special symbol and the normal symbol display 10 for variably displaying the normal symbol is performed by display control means mounted on the display control board 80.

  As shown in FIG. 4, in this embodiment, a display control command as a control signal (command signal) is transmitted from the main board 31 to the display control board 80 according to the control state. Then, a lamp control command as a control signal is transmitted from the display control board 80 to the lamp control board 35, and a sound control command as a control signal is transmitted to the sound control board 70. That is, in this example, the display control board 80 is a sub board, and the lamp control board 35 and the sound control board 70 are sub sub boards. The payout control board 37 is a sub board.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer is a one-chip microcomputer and includes at least a RAM. The RAM is an example of a storage unit used by the payout control unit, and is backed up by a power source, like the RAM 55 in the main board 31. The payout control CPU 371, the RAM, the ROM (not shown) storing the payout control program, the I / O port, and the like implement a payout control microcomputer. The payout control means is realized by a circuit that is mounted on the payout control board 37 and implements various functions including a payout control microcomputer. The processing in the payout control means is realized mainly by the payout control CPU 371 in the payout control microcomputer executing according to the program.

  Detection signals from the full tank switch 48 and the payout number count switch 301 are input to the I / O port 372 f of the payout control board 37. Detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control CPU 371 of the payout control board 37 performs a ball payout process when the detection signal from the ball shortage switch 187 indicates a ball full state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop. Furthermore, when the detection signal from the full tank switch 48 indicates a full tank state, the ball launching from the ball striking device is stopped.

  When there is a win, the output circuit 67 of the main board 31 receives a prize ball REQ signal (prize ball request signal) for making a prize ball payout request and a prize ball control indicating the number of prize balls to be paid out as a payout command signal. A signal is output (turns on). The prize ball control signal is composed of 4-bit data (binary 4-digit data) and is output through four signal lines. Note that the ON state of the signal, that is, the output state is a state in which the signal is significant, and turning on means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, when the prize ball control signal indicating the number of prize balls and the prize ball REQ signal are turned on, this means that the dispense control means is instructed to recognize the number of prizes indicated by the prize ball control signal. To do. The prize ball control signal is input to the I / O port 372e via the input circuit 373A. When a prize ball REQ signal and a prize ball control signal are input via the I / O port 372e, the payout control CPU 371 drives the ball dispenser 97 to pay out the number of game balls indicated by the prize ball control signal. To do. A power supply confirmation signal (connection confirmation signal) indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31. The prize ball REQ signal and the prize ball control signal correspond to a payout command signal for designating the number of payouts.

  In this example, the payout control means transmits a prize ball count signal to the main board 31 when the payout of one prize ball is confirmed based on the detection signal from the payout number count switch 301. Further, the payout control means means an error related to game ball payout (an error indicating that the game ball payout process cannot be performed. When this occurs, a payout error signal is transmitted to the main board 31. The prize ball count signal and the payout error signal are transmitted to the main board 31 via the output port 372b and the output circuit 373B of the payout control board 37. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid out and a ball lending number signal indicating the number of balls to be rented via the output port 372b as a terminal board (the frame external terminal board and the board external terminal board). Output) 160. A driver circuit is provided outside the output port 372b, but is not shown in FIG. Further, door opening information switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Further, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing lighting / extinguishing is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel a specific error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG. A drive signal from the payout control board 37 to the firing motor 94 is transmitted to the firing motor 94 via the output port 372 a and the touch sensor board 91.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the pachinko gaming machine 1. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155. The interface board (relay board) 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 based on the input state of the VL signal. When the card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, when a BRDY signal from the card unit 50 is not in an ON state, a prize ball payout control is executed when a payout command signal is received from the game control means. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the card unit 50 is installed adjacent to the pachinko gaming machine 1 as an example separate from the pachinko gaming machine 1. However, the card unit 50 is integrated with the pachinko gaming machine 1. It may be made. Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is a block diagram illustrating a circuit configuration example of the display control board 80, the lamp control board 35, and the sound control board 70. In the display control board 80, the display control CPU 101 in the display control microcomputer operates in accordance with a program stored in a ROM (not shown), and inputs according to a strobe signal (display control INT signal) from the main board 31. A display control command is received via the driver 102 and the input port 103. Further, the display control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD based on the display control command. The VDP 109 is sometimes called a GCL (graphic controller LSI).

  Further, the display control CPU 101 outputs a sound control command to the sound control board 70 via the output port 104 and the output driver 110. Further, the display control CPU 101 outputs a lamp control command to the lamp control board 35 via the output port 105 and the output driver 106.

  In this embodiment, the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c provided on the outside of the game area 7 and the decoration lamp 25 provided on the game board are turned on / off, and a prize ball lamp. 51 and a lamp control command as a second command (second control signal) indicating turning on / off of the ball-out lamp 52 is output from the display control board 80 to the lamp control board 35. Further, a lamp control command as another second command such as a lamp control command indicating the number of lighting of the normal symbol start memory display 41 is also output from the display control board 80 to the lamp control board 35.

  A lamp control command related to the lamp control is output from the output port 104 of the I / O port unit in the display control CPU 101 via the output driver 110. The output port 104 outputs 8-bit data and a 1-bit INT signal. In the lamp control board 35, a lamp control command from the display control board 80 is input to a lamp control CPU (light emitter control microcomputer) 351 through an input port of an I / O port portion in the lamp control board 35.

  In the lamp control board 35, the lamp control CPU 351 outputs an ACK signal (a command indicating reception completion) to the display control CPU 101. The ACK signal is output from the output port of the I / O port unit in the lamp control CPU 351.

  In the lamp control board 35, the lamp control CPU 351 performs the ceiling frame lamp according to the lighting / extinguishing pattern of the ceiling frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25 defined according to each control command. 28a, left frame lamp 28b, right frame lamp 28c, and decorative lamp 25 are turned on / off. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  A signal for driving each lamp output by the lamp control CPU 351 is amplified by a lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED drive circuit 355 and supplied to each LED. A signal for driving the effect driving means 61 is amplified by the drive circuit 356 and supplied to each lamp.

  In this embodiment, a sound control command for instructing the sound output of the speaker 27 provided outside the game area 7 is output from the display control board 80 to the sound control board 70 as the game progresses. .

  In the sound control board 70, a sound control CPU (sound control microcomputer) 701 outputs an ACK signal to the display control CPU 101. The ACK signal is output from the output port of the I / O port unit in the sound control CPU 701.

  The sound control command is output from the output port 105 of the I / O port unit in the display control CPU 101 via the output driver 106. The output port outputs 8-bit data and a 1-bit INT signal. In the sound control board 70, the sound control command from the display control board 80 is input to the sound control CPU 701 through the input port of the I / O port unit in the sound control board 70. The sound control CPU 701 reads data corresponding to the received sound control command from the voice data ROM 704 mounted on the voice data board 70A, and outputs the data to the voice synthesis IC 703 by a digital signal processor, for example.

  Then, the voice synthesis IC 703 generates voice and sound effects according to the instructions of the sound control CPU 701 and outputs them to the amplification circuit 705. The amplification circuit 705 sets the output level of the audio control CPU 701 to a level corresponding to the volume set in the volume 706 (for example, the volume according to the operation state of the volume switch provided in the pachinko gaming machine 1). The amplified audio signal is output to the speaker 27. In this embodiment, the voice data ROM 704 is mounted on the voice data board 70A, which is a board different from the voice control board 70, but the voice data ROM 704 may be mounted on the voice control board 70. Good. In that case, the audio data board 70A is unnecessary.

  The data corresponding to the sound control command stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a special symbol fluctuation period). When receiving the sound control command, the sound control CPU 701 performs sound output control according to the corresponding data in the sound data ROM 704. The sound output control according to the corresponding data is continued until the next sound control command is received. When the sound control CPU 701 receives the next sound control command, the sound control CPU 701 performs sound output control in accordance with the data in the sound data ROM 704 corresponding to the newly input sound control command.

  FIG. 7 is a timing chart showing a transmission form of the second command (lamp control command, sound control command) transmitted from the display control board 80 to the lamp control board 35 or the voice control board 70.

  When transmitting the second command, the effect control means (display control CPU 101) in the display control board 80 sets the command data (MODE data or EXT data) to the I / O port as shown in FIG. The STB signal is turned on (low level). The effect control means (lamp control CPU 351, sound control CPU 701) on the receiving side board (lamp control board 35, voice control board 70) that receives the second command detects that the STB signal is turned on. Then, command data is input via the I / O port, and the ACK signal is turned on (low level) to notify completion of reception.

  After confirming that the ACK signal is turned on, the display control CPU 101 turns off the STB signal. When the reception side effect control means (lamp control CPU 351, sound control CPU 701) confirms that the STB signal has been turned off, it turns off the ACK signal. As described above, transmission / reception of 1-byte command data is realized. Note that the second byte of the second command having a 2-byte configuration is also transmitted and received in the same manner as the first byte.

  In this embodiment, the second command is transmitted and received in the form as shown in FIG. 7, but the form shown in FIG. 7 is an example, and the command data from the display control CPU 101 is sent to the lamp control CPU 351 or the like. If information is transmitted to the sound control CPU 701 and information indicating that the lamp control CPU 351 or the sound control CPU 701 has received command data is transmitted to the display control CPU 101, that is, bidirectional communication. The second command may be transmitted / received in any form as long as the command data is transmitted / received by. For example, instead of the ACK signal, a command indicating reception completion may be transmitted to the display control CPU 101. In this embodiment, the command data has a 2-byte configuration as described later. However, the command data may have a 1-byte configuration or a 3-byte or more configuration, and is not limited to parallel transmission / reception (8-bit parallel in this example). It may be sent and received.

  Further, not limited to bidirectional communication, data or a signal may be transmitted only in the direction from the display control board 80 to the lamp control board 35 or the voice control board 70. Further, data and signals are exchanged between the display control board 80, the lamp control board 35, and the voice control board 70 by the same method as the communication method performed between the main board 31 and the display control board 80 described above. You may make it do. With this configuration, the basic part of the control program related to data and signal communication can be made common, and the control program related to data and signal communication can be diverted to each board without significant changes. it can.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off the power supply to each electrical component control board and mechanism parts in the pachinko gaming machine 1. The power switch 914 may be provided outside the power supply board 910 in the pachinko gaming machine 1. When the power switch 914 is in a closed state (on state), an AC power supply (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply board 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, the display control board 80, the lamp control board 35, and the voice control board 70), and each board in the pachinko gaming machine 1 Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 8), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Therefore, when the power supply to the pachinko gaming machine 1 from the outside is stopped, the direct current voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 8, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. The cable connected to the connector 922C is connected to the lamp control board 36. Each voltage is supplied to the display control board 80 via the lamp control board 36.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the payout control board 37 via the connectors 922A and 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided in addition to the power supply board 910 in the pachinko gaming machine 1.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. And an output driver circuit 925 that amplifies the power-off signal and outputs it to the connectors 922A and 922B. A reset signal for the display control microcomputer and the sound control microcomputer is transmitted to the display control board 80 and the sound control board 70 via the lamp control board 35. In other words, the reset signal from the power supply board 910 is directly transmitted to the lamp control board 35 as the sub-sub board without passing through the display control board 80 as the sub board. That is, a signal transmission path for transmitting a reset signal without using the display control board 80 is provided between the power supply board 910 and the lamp control board 35. Note that the reset signal from the power supply board 910 is directly transmitted to the audio control board 70 which is a sub-sub board, and the reset signal for the display control microcomputer and the light emitter control microcomputer passes through the audio control board 70 and the display control board 80. Further, a signal transmission path for transmitting a reset signal that is configured to be transmitted to the lamp control board 35 may be provided.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC should be used. Can do. The power supply monitoring circuit 920 outputs a power-off signal when a predetermined voltage (for example, + 24V) used in the pachinko gaming machine 1 has become equal to or lower than a predetermined value (for example, + 5V) for a predetermined time (for example, 56 ms). Output. Specifically, the power-off signal is turned on (low level). Further, the power supply monitoring circuit 920 enters a state where the reset signal can be turned on (low level) when, for example, VCC becomes +4.5 V or less.

  When the power supply to the pachinko gaming machine 1 is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level on condition that a predetermined period has elapsed since the power-off signal was output (set to a low level). . The predetermined period is a time sufficient for the microcomputer mounted on the main board 31 and the payout control board 37 to execute power-off processing described later. In addition, when the power supply to the pachinko gaming machine 1 is started and VCC exceeds, for example, +4.5 V, the reset signal is set to the high level. The reset signal is set to high level on the condition that a predetermined period has elapsed. Therefore, when the microcomputer mounted on each electrical component control board (including the main board 31) starts the control operation according to the program in response to the reset signal becoming high level, the power-off signal is always turned off. It is in a state.

  A power-off signal from the power monitoring circuit 920, that is, a detection signal from the power monitoring means is input to the CPU 56 via the input port 572 in the main board 31. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the pachinko gaming machine 1 by monitoring the input signal of the input port 572. Further, the power-off signal from the power supply monitoring circuit 920 is input to the payout control CPU 371 via the input port 372g on the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can confirm the occurrence of the stop of the power supply to the pachinko gaming machine 1 by monitoring the input signal of the input port 372g.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the detection condition relating to the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is a detection condition from the outside of the pachinko gaming machine 1 Although it was used that the predetermined DC voltage created from the voltage (AC24V in this embodiment) was less than the predetermined value, the detection condition is not limited to this, and it can be detected that power from the outside is interrupted. If so, other conditions may be used. For example, the AC wave itself may be monitored to detect that the AC wave has been interrupted, or the AC wave may have been detected by monitoring the digitized AC signal and the digital signal has become flat. May be used as a detection condition.

  9 and 10 are explanatory diagrams showing an example of output port assignment in the game control means. As shown in FIG. 9, the output port 0 is an output port for a payout control signal transmitted to the payout control board 37. Further, 8-bit data of the display control command transmitted to the display control board 80 is output from the output port 1.

Further, from the output port 2, a solenoid (large winning port door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning port, a solenoid (large winning port guide plate solenoid) 21A for switching a path in the large winning port and a variable A drive signal for a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15 is output. Further, a display control INT signal (strobe signal) for a display control command transmitted to the display control board 80 is also output. The display control INT signal is a signal for instructing the display control means to capture 8-bit data of the display control command.


Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 11 is an explanatory diagram showing an example of bit allocation of input ports in the game control means. As shown in FIG. 11, the bits 0 to 7 of the input port 0 are detected by the V winning switch 22, the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a, 30a, and the start port switch 14a, respectively. A signal is input. In addition, bits 0 to 3 of the input port 1 respectively include a power-off signal from the power monitoring board 910, a detection signal from the clear switch 921 from the power board 910, a prize ball count signal from the payout control board 37, and a payout error. A signal is input. The detection signal from each switch, the winning ball count signal, and the payout error signal are logically inverted in the input circuit 68.

  Next, the operation of the pachinko gaming machine 1 will be described. 12 and 13 are flowcharts showing main processing executed by the game control means on the main board 31. FIG. When the power to the pachinko gaming machine 1 is turned on and the input level of the reset terminal to which the reset signal is input becomes high level, the CPU 56 is a security check that is a process for confirming whether the contents of the program are valid or not. After executing the processing, the main processing after step S (hereinafter simply referred to as S) 1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 performs the following process. First, interrupt prohibition is set (S1). Next, the interrupt mode is set to interrupt mode 2 (S2), and a stack pointer designation address is set to the stack pointer (S3). Then, the built-in device register is initialized (S4).

  Next, a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software is executed. Specifically, first, the initialization wait number specification value 1 is set in the wait counter 1 (S41). Further, the initialization wait number designation value 2 is set in the wait counter 2 (S42). As the wait counters 1 and 2, general-purpose registers built in the CPU 56 are used. Then, the value of the wait counter 2 is decremented by 1 until the value of the wait counter 2 becomes 0 (S43, S44). When the value of the wait counter 2 becomes 0, the value of the wait counter 1 is decremented by 1 (S45). When the value of the wait counter 1 is not 0 (S46), the process returns to S42. If the value of the wait counter 1 is 0, the software delay process is terminated.

  When the software delay processing is not executed by the software delay processing as described above, almost only [(initialization wait number specification value 1) × (initialization wait number specification value 2) × (processing time of S43, S44)]. Compared to, the start timing of the game control process can be delayed. In other words, the initialization weight count designation values 1 and 2 are determined so that the start timing of the game control process can be delayed by a desired time. Note that the values of the initialization wait times designation values 1 and 2 are set in the ROM 54. Further, the software delay processing described here is an example, and the software delay processing may be realized by other methods.

  The predetermined period to be delayed by the software delay process ensures at least a period from when the power supply to the pachinko gaming machine 1 is started and becoming operable to at least after the payout control process is started. That is, a predetermined period to be delayed by the software delay process is determined so that the game control process by the game control means is started after the payout control process by the payout control means is started. With this configuration, when the power supply of the pachinko gaming machine 1 is started, the payout control unit can reliably receive the control signal from the game control unit. Note that when the power supply of the pachinko gaming machine 1 is started, the payout control means only needs to be able to reliably receive the control signal from the game control means, so the predetermined period delayed by the software delay processing is at least After a control state in which a control signal can be received by the sub board (dispensing control board 37, display control board 80) or sub sub board (lamp control board 35, voice control board 70) is started (for example, after execution of S715). It suffices that the control signal transmission operation (for example, S14 and S94) on the main board 31 is adjusted. The same applies to the case where delay processing is performed using a hardware circuit.

  When the software delay processing is completed, the CPU 56 initializes the built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (S5), and then makes the RAM 55 accessible. Set (S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  In the CPU 56 used in this embodiment, the following three types of modes are prepared as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input through the input port 1 (hereinafter referred to as a clear switch signal) only once (S7). When the ON state is detected in the confirmation, the CPU 56 executes normal initialization processing (S10 to S15). When the clear switch 921 is in the on state (when pressed), a low level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level. Further, for example, the game store clerk can easily execute the initialization process by starting the power supply to the pachinko gaming machine 1 (for example, turning on the power switch 914) while the clear switch 921 is turned on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, was the data protection process for the backup RAM area (for example, when the power supply stopped such as adding parity data) performed when the power supply to the pachinko machine 1 was stopped? Confirm whether or not (S8). In this embodiment, when power supply is stopped, processing for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in S8. If it is confirmed, it may be determined that there is a backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. Then, the calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the calculated checksum is stored in the backup RAM area. In S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of S10 to S15) that is executed when the power is turned on but not when the power supply is stopped is executed. To do.

  If the check result is normal, the CPU 56 performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (S81), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (S82). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. By the processing of S81 and S82, the saved contents remain as they are in the portion of the work area that should not be initialized. The portion that should not be initialized is, for example, a portion in which data (such as a special symbol process flag) indicating a gaming state before stopping power supply or data indicating the number of unpaid winning balls is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (S83), and the power supply is restored to the sub-boards (the payout control board 37 and the display control board 80) according to the contents. Control is performed so that a control command indicating that it has been sent is transmitted (S84). Then, the process proceeds to S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by an unauthorized means. Therefore, it is difficult to aim at a timing at which the count value of the counter for matching the jackpot determination value. The initial address of the initialization setting table stored in the ROM 54 is set as a pointer (S11), and the contents of the initialization setting table are sequentially set in the work area (S12). By the processing of S11 and S12, for example, initial values are set in various counters and buffers such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, and a total winning ball number storage buffer. In addition, initial values are set for flags for selectively performing processing according to control states such as a special symbol process flag, a winning ball flag, a ball-out flag, and a payout stop flag.

  Further, the CPU 56 sets the head address of the initialization command transmission table stored in the ROM 54 as a pointer (S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Is executed (S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (S17) and the initial value random number update process (S18). The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (S16). When the display random number update process and the initial value random number update process are finished, the interrupt is permitted. The state is set (S19). Note that the display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a counter value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determining random number generation counter). . Game control processing described later (a process in which the game control microcomputer controls the game devices such as the variable display device 9, the variable winning ball device 15 and the ball payout device 97 provided in the pachinko gaming machine 1, Alternatively, when the count value of the jackpot determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a game device control process), an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt occurs during the processing of S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, the count value Continuity may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of S17 and S18.

  FIG. 14 is a timing chart showing the behavior of the microcomputer when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. When power supply to the pachinko gaming machine 1 is started and the voltage of the DC + 24V power supply exceeds a predetermined value, the power-off signal becomes high level (off state). When the value of VCC exceeds a predetermined value, the reset signal becomes high level. As described above, the power supply monitoring circuit 920 sets the power-off signal to the high level and then sets the reset signal to the high level. The reset signal is input to the main board 31, the payout control board 37 and the lamp control board 35. The reset signal is input to the display control board 80 and the sound control board 70 via the lamp control board 35. The reset signal includes a payout control CPU 371 mounted on the payout control board 37, a display control CPU 101 mounted on the display control board 80, a lamp control CPU 351 mounted on the lamp control board 35, and a sound. The sound is input to the reset terminal of the sound control CPU 701 mounted on the control board 70. The payout control CPU 371, the display control CPU 101, the lamp control CPU 351, and the sound control CPU 701 are operable when the reset signal is at a high level. When these CPUs become operable, they first perform initialization processing, and then start payout control processing, display control processing, lamp control processing, and sound control processing, respectively.

  The reset signal input to the main board 31 is delayed by the delay circuit 69 and then input to the reset terminal of the CPU 56. Therefore, the time when the CPU 56 becomes operable is later than the time when the CPU of the sub board or the sub sub board becomes operable. Further, when the CPU 56 becomes operable, the CPU 56 executes security check processing based on the security check program. Then, after completing the security check process, the CPU 56 executes a software delay process and then starts an initialization process and a game control process.

  As described above, the CPU 56 performs a process of transmitting a command (command signal) as a control signal to the CPU of the sub-board in the initialization process. Due to the delay by the delay circuit 69 (delay by the hardware circuit) and the execution of the security check process, the time when the CPU 56 starts the initialization process is later than the time when the CPU of the sub board or the sub sub board completes the initialization process. ing. That is, since the execution time of the security check process is determined according to the frequency of the clock signal supplied to the CPU 56, the time when the CPU 56 starts the initialization process is the time when the CPU of the sub board or the sub sub board completes the initialization process. The delay amount of the delay circuit 69 is set so as to be later than the time point.

  In this embodiment, software delay processing is also executed before the CPU 56 starts initialization processing. Therefore, it is more certain that the time when the CPU 56 starts the initialization process is later than the time when the CPU of the sub-board completes the initialization process. Further, for example, when the CPU of the sub board or the sub sub board is changed to an inexpensive CPU having a slow operation (that is, when the CPU of the sub board or the sub sub board completes the initialization process is delayed), If the delay amount of the delay circuit 69 is not increased, the time when the CPU 56 starts the initialization process may be earlier than the time when the CPU of the sub-board completes the initialization process. However, if it is configured to execute software delay processing as in this embodiment, the time when the CPU 56 starts initialization processing is relative to the execution time of the security check processing and the delay time by the delay circuit 69. Further, since the delay by the time due to the software delay processing is added, the CPU 56 does not change the configuration of the delay circuit 69 even if the time when the CPU of the sub board or the sub sub board completes the initialization process is delayed. It is possible to prevent the time when the initialization process starts from being earlier than the time when the sub-board or the CPU of the sub-sub-board completes the initialization process.

  The delay time (specific period) by the delay circuit 69 is, for example, until the sub-board or the sub-sub-board using the slowest CPU among the sub-boards and sub-sub-boards that may be adopted rises when the power is turned on. Is set to a time (for example, 700 ms) that is slightly shorter than the time obtained by subtracting the execution time of the security check process. Then, the delay time by the software delay processing is adjusted according to the actually used sub board and the operation speed of the sub sub board, and the time when the CPU 56 starts the initialization process is the initialization process of the sub board and the CPU of the sub sub board. It is sufficient to make it later than the point of completing. In this way, if the configuration is delayed not only by software but also by a hardware circuit, the versatility of delay processing by software can be left in preparation for when a specification change such as a change of a sub board or a sub sub board is made. At the same time, delay processing by software can be simplified, and the data capacity of software for delay processing can be reduced.

  When the power supply to the pachinko gaming machine 1 is stopped, the voltage of the DC + 24V power supply gradually decreases. However, when the voltage of the DC + 24V power supply falls below a predetermined value, the power supply monitoring circuit 920 outputs a power-off signal (low level). ). The power-off signal is input to the main board 31 and the payout control board 37. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37, according to the power-off signal being output, the power supply stop process (both power-off control process) Say). The power supply monitoring circuit 920 sets the reset signal to a low level when VCC falls below a predetermined value. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 are system reset in response to the reset signal becoming low level. That is, the CPU 56 and the payout control CPU 371 are not operated. The power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined time elapses from the time when the power-off signal is output when the power supply voltage decreases. In addition, when the CPU 56 and the payout control CPU 371 are not in operation, that is, in the system reset state, the CPU 56 and the payout control CPU 371 each start from the initial state (from the beginning of the control program in accordance with the reset signal). Control is started (from the state when the supply was started).

  Next, the game control process will be described. FIG. 15 is a flowchart showing the timer interrupt process. If a timer interrupt occurs during the execution of the main process, specifically, during the execution of the loop process of S16 to S19, the CPU 56 plays a game in the timer interrupt process activated in response to the occurrence of the timer interrupt. Execute control processing. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) that detects whether or not a power-off signal has been output (whether or not an on-state has been turned on) (S20). Next, detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a, etc. are input via the input circuit 68, and their state is determined (switch) Process: S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Further, in response to receiving the prize ball count signal from the payout control board 37, a process for notifying the player that the prize ball has been paid out is executed (S22a). Specifically, a process (see FIG. 23) of transmitting a prize ball payout confirmation designation command to the display control board 80 for designating that the prize ball has been paid out is executed. In addition, in accordance with the on / off state of the payout error signal from the payout control board 37, the player is informed that an error of out of ball and full of the lower pan (or either full of the ball or full of the lower pan) has occurred. The process for notifying to (S22b) is performed. Specifically, when a payout error signal from the payout control board 37 is turned on, a process of transmitting an error occurrence notification command for notifying occurrence of an error relating to payout of a game ball such as a ball breakage to the display control board 80 ( When the payout error signal from the payout control board 37 is turned off, an error release notification command for notifying that an error relating to the payout of the game ball such as a broken ball has been released is displayed on the display control board. The process of transmitting to 80 (see FIG. 24) is executed.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (S24, S25).

  Further, the CPU 56 performs a special symbol process (S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, the normal symbol process is performed (S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting a display control command related to the special symbol in a predetermined area of the RAM 55 and sending the display control command (special symbol command control process: S28). In addition, a display control command related to the normal symbol is set in a predetermined area of the RAM 55 and a process for sending the display control command is performed (normal symbol command control process: S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (S30).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on the detection signals from the prize opening switches 29a, 30a, 33a, 39a, etc. (S31). Specifically, a payout control signal such as a prize ball control signal indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on turning on the prize opening switches 29a, 30a, 33a, 39a, etc. . The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in accordance with a payout control signal such as a prize ball control signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (S32). Further, a test terminal process, which is a process for generating and outputting a test signal for enabling the control state of the pachinko gaming machine 1 to be confirmed outside the pachinko gaming machine 1, is executed (S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 relates to the solenoid in the RAM area of the output port 2 (see FIG. 9). Is output to the output port (S34: solenoid output processing). Thereafter, the interrupt permission state is set (S35), and the process ends.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 4 ms). In this embodiment, the game control process is executed in the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed in the main process. May be executed. Further, the processes of S21 to S34 (except S30 and S33) correspond to the game control process for controlling the progress of the game.

  16 and 17 are flowcharts illustrating an example of the power-off process in S20. In the power-off process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (S450). If not in the on state, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (S451). If it is on, the value of the backup monitoring timer formed in the RAM 55 is increased by 1 (S452). If the value of the backup monitoring timer coincides with a determination value (for example, 2) (S453), the power supply stop processing after S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from a state in which the progress of the game is controlled to a state in which a power supply stop process (a power-off control process) for saving the game state is executed.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even if the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM 55 is stored by the backup power source for a predetermined period even when the power supply to the pachinko gaming machine 1 is stopped. Therefore, in S8 in the main process, it can be confirmed that the process result of the power supply stop process is stored because the value of the backup monitoring timer is the same as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (S454 to S463). That is, first, the clear data (00) is set in the checksum data area (S454), and the checksum calculation start address corresponding to the start address of the RAM area where the contents should be saved even when the power supply is stopped is set in the pointer. (S455). Also, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (S457). The calculation result is stored in the checksum data area (S458), the pointer value is incremented by 1 (S459), and the value of the checksum calculation count is decremented by 1 (S460). Then, the processes of S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (S462). Then, the inverted data is stored in the checksum data area (S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the number of output ports corresponding to the number of processes is sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (S473). Further, the pointer value is incremented by 1 (S474), and the data at the address pointed to by the pointer (that is, the output port address) is loaded (S475). Further, the value of the pointer is incremented by 1 (S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (S477). Then, the output value data is output to the output port (S478). Thereafter, the number of processes is reduced by 1 (S479), and it is determined whether or not the number of processes is 0 (S480). If the number of processes is not 0, the process returns to S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (S482). When the power-off signal is turned off, a return address is set as the return address and the return address is executed (S483). That is, the process returns to the main process. Specifically, the gaming device provided in the pachinko gaming machine 1 is controlled (concept including both control by itself and transmission of a command signal to cause another microcomputer to control). Return to state.

  When the power supply is stopped by the above processing, the power supply stop processing of S454 to S481 is executed, and data (specified value with backup and checksum) indicating that the power supply stop processing has been executed is stored. Stored in the backup RAM, the RAM access is prohibited, the output port is cleared, and the timer interrupt for executing the game control process is set to the prohibited state.

  In this embodiment, the entire area of the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when the power supply to the pachinko gaming machine 1 is stopped). Accordingly, the checksum based on the contents of the RAM 55 when the power-off signal is output is stored in the RAM 55 together with the value of the backup monitoring timer by the processing of S452 to S479. After the power supply to the pachinko gaming machine 1 is stopped, when the power supply is restored within a predetermined period, the game control means stores the data stored in the RAM 55 (the power supply has been stopped) by the processes of S91 to S94 described above. According to the data indicating the game state that is the control state by the immediately preceding game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the power supply is stopped. If the power supply stop period exceeds the predetermined period, the backup monitoring timer value and the checksum should be different from the regular values. In this case, the initialization process of S10 to S14 is executed. .

  As described above, the power supply stop processing (preparation processing for power supply stop) ensures that the data for returning the gaming state to the state immediately before the power supply is stopped is the fluctuation data storage means (in this example) All areas of the RAM 55). Therefore, even if a power failure occurs due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped. Note that the entire area of the RAM 55 may not be backed up by power, but only the area for storing data for returning the gaming state to the state immediately before the power supply is stopped may be backed up.

  When the power-off signal is turned off, the process returns to S1. In this case, since data indicating that the power supply stop process has been executed is set, the game state recovery process of S91 to S94 is executed. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps 82 and S12, the content of the output port buffer corresponding to the connection confirmation signal is set to a value corresponding to the ON state of the connection confirmation signal. When the prize ball process of S31 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal to the payout control board 37 is turned on. Accordingly, the connection confirmation signal is output (turned on) when the main board 31 rises. Note that a connection confirmation signal is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, the switch process (S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. FIG. 18 is an explanatory diagram showing each 1-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 19 is a flowchart illustrating a processing example of the switch process of S21 in the game control process. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 11) (S101), and sets the input data in the port buffer (S102). Next, the initial value of the wait counter formed in the RAM 55 is set (S103), and the value of the wait counter is decremented by 1 until the value of the wait counter becomes 0 (S104, S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (S107). . Then, the operation result of the logical product is set in the port buffer (S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of wait counter × (processing time of S14, S105)] by the processing of S103 to S108, both are “1”. Only those bits that are marked "1" in the port buffer. That is, if the switch detection signal is kept on for the predetermined period [initial value of wait counter × (processing time of S14, S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (S109). In the exclusive OR operation result, the bit corresponding to the switch for which the previous switch on / off determination result (for example, 4 ms before) differs from the switch on / off determination result determined to be on this time is “ 1 ”. Further, the CPU 56 performs a logical product for each bit between the result of the exclusive OR operation and the data set in the port buffer (S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined as (by the logical product operation) remains as “1”.

  Then, the CPU 56 sets the logical product operation result in S110 in the switch-on buffer (S111), and sets the contents of the port buffer in which the operation result in S108 is set in the previous port buffer (S112).

  Through the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from off to on. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, payout control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 20 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a payout control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 20, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), and the main board 31 rises with respect to the payout control board 37. Is a signal (connection confirmation signal for the main board 31). That is, the connection confirmation signal is a signal indicating whether or not the main board 31 is standing up.

  The prize ball REQ signal is a signal that is in an output state (= ON state) when a prize ball payout request is made (that is, a trigger signal for a prize ball payout request). In addition, the prize ball REQ signal is in a stopped state (off state) after a predetermined period after it is in the output state. The award ball control signal is a signal (award ball number command) output for designating the number (1 to 15) of game balls for which a payout request is made.

  The prize ball count signal is a signal that is turned on when the payout control means confirms the payout of one prize ball, and is turned off after a predetermined period. The payout error signal is a signal that is turned on when an error state related to payout occurs, and is turned off when the error state is canceled.

  FIG. 21 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 21, the connection confirmation signal, the prize ball REQ signal, and the prize ball control signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. The prize ball count signal and the payout error signal are output by the payout control CPU 371 via the output circuit 373B and input to the CPU 56 via the input circuit 68. Each of the connection confirmation signal, the prize ball REQ signal, the prize ball count signal, and the payout error signal is 1-bit data, and is transmitted through one signal line. Since 1 to 15 prize ball control signals are designated, it is composed of 4-bit data and transmitted through four signal lines.

  FIG. 22 is a timing chart showing an example of how to output the payout control signal. As shown in FIG. 22, when the winning opening detection switch such as the start opening switch 14a, the winning opening switches 33a, 39a, 29a, 30a, the V winning switch 22, and the count switch 23 detects the winning of the game ball, the game control is performed. The means turns on the prize ball REQ signal and sets the output state of the prize ball control signal according to the number of prize balls to be paid out according to the winning. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V winning switch 22 or the count switch 23, 15 prize balls are paid out. Further, as described above, the prize ball control signal is composed of 4 bits, and therefore, the lower 4 bits of the prize ball number commands of 00 (H) to 0F (H) represented by 8 bits are The prize ball control signal is transmitted from the main board 31 to the payout control board 37. Hereinafter, the prize ball control signal may be expressed as “00 (H) to 0F (H) prize ball control signal”, but in reality, the prize ball control signal is represented by 8 bits. This corresponds to the lower 4 bits of 0F (H).

  The game control means turns the prize ball REQ signal off after a predetermined period (prize ball REQ signal off waiting time: 60 ms, for example) has elapsed since the prize ball REQ signal was turned on. At that time, the output state of the prize ball control signal is cleared and turned off. That is, the prize ball control signal is set to a state indicating 0 (a state in which an invalid command is output). Accordingly, since the prize ball control signal is in the invalid command output state when the prize ball REQ signal is in the off state, when the on state of the prize ball REQ signal is detected by the payout control means due to noise or the like. However, there is no such thing as accidentally paying out a prize ball. The award ball REQ signal off waiting time is a time for providing an interval between the on periods of a plurality of award ball REQ signals when the award ball payout is continuously executed. The award ball REQ signal off waiting time has a different value when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 changes. That is, when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 changes, the value becomes different.

  As shown in FIG. 21, when a new winning is detected when the prize ball REQ signal is on, the prize ball REQ signal is turned on and the prize ball control signal is output based on the prize. Specifically, when a new winning is detected when the winning ball REQ signal is on, the number of winning balls to be paid out based on the winning is stored in the total winning ball number buffer formed in the RAM 55. Is added to the content. Then, when the game control means turns off the prize ball REQ signal, if the content of the total prize ball number buffer is not 0, the number of prize balls indicated by the contents of the total prize ball number buffer is set to 15 as the upper limit. In order to instruct a prize ball payout, the prize ball REQ signal is turned on and a prize ball control signal is output.

  FIG. 23 is a timing chart showing an example of how to output a prize ball count signal. As shown in FIG. 23, the payout control CPU 371, when the payout number count switch 301 detects the payout of the game ball, checks whether or not the detection is the detection of the payout of the prize ball. If there is, the prize ball count signal is turned on for a predetermined period (for example, 0.5 seconds). That is, each time a payout of one prize ball is confirmed, the prize ball count signal is turned on for a predetermined period. Therefore, for example, the payout number count switch 301 detects the payout of seven game balls. If the detected game ball is a prize ball, the on / off of the prize ball count signal is repeated seven times.

  In each of the above-described prize ball notification processing (S22), the CPU 56 receives a prize ball payout confirmation designation control command (award ball payout confirmation) every time a prize ball count signal is received. (Designation command) is transmitted to the display control board 80. The display control board 80 transmits the received prize ball payout confirmation designation command to the lamp control board 35 (see S343 and S344). The lamp control CPU 351 of the lamp control board 35 executes control for turning on the prize ball lamp 51 for a predetermined period (for example, 0.5 seconds) every time a prize ball payout confirmation designation command is received. As described above, since the prize ball lamp 51 is turned on in response to the confirmation of the payout of one prize ball, prize ball count signals corresponding to the number of prize balls delivered to the CPU 56 are normally input. Can be recognized from the outside of the pachinko gaming machine 1.

  Each time the CPU 56 receives a prize ball count signal, the CPU 56 has sent a prize ball payout confirmation designation command indicating that the payout of one prize ball has been confirmed to the display control board 80. When a predetermined number (for example, 7 times) of winning ball counting signals indicating the amount of winning balls (for example, 7) is received, it indicates that the predetermined number (for example, 7) of winning balls has been confirmed. A prize ball payout confirmation designation command may be transmitted to the display control board 80, and the payout of the first prize ball out of a predetermined number (for example, 7) of prize balls to be paid out is detected. In response to receiving a prize ball count signal based on the fact, a prize ball payout confirmation designation command indicating that a predetermined number (for example, 7) of prize balls has been confirmed is transmitted to the display control board 80. You may do it. In this case, when the lamp control CPU 351 receives a prize ball payout confirmation designation command indicating that a predetermined number of prize balls have been paid out, the lamp control CPU 351 has confirmed the payout of one prize ball as described above. It is preferable to execute control for turning on the prize ball lamp 51 for a longer period of time (for example, 3 seconds) than when the prize ball payout confirmation designation command is received.

  FIG. 24 is a timing chart showing an example of how to output a payout error signal. As shown in FIG. 24, the payout control CPU 371 turns on the payout error signal when it shifts to the error state, and turns off the payout error signal when the error state is canceled. In this example, a payout error signal is output when an error state occurs due to the occurrence of a special error relating to payout of game balls. Specifically, a payout error signal is output, for example, when a special error occurs when the lower pan is full or the ball is full.

  As shown in FIG. 24, when the CPU 56 mounted on the main board 31 receives the payout error signal from the payout control CPU 371 (when the payout error signal is turned on), the display control is performed toward the display control board 80. An error occurrence notification command as a command is transmitted. The error occurrence notification command is a command indicating that an error has occurred. When the payout error signal from the payout control CPU 371 is stopped (when the payout error signal is turned off), the CPU 56 transmits an error release notification command as a display control command to the display control board 80. The error release notification command is a command indicating that the error state has been released.

  When the display control CPU 101 mounted on the display control board 80 receives the error occurrence notification command from the CPU 56, the display control CPU 101 displays the error display on the variable display device 9 and performs a process of notifying the error state. To do. The notification of the error state is performed, for example, by displaying characters or figures such as “An error has occurred!” In the display area of the variable display device 9. When the display control CPU 101 receives the error release notification command from the CPU 56, the display control CPU 101 deletes the error display displayed on the variable display device 9 in order to notify the error state, and is in the error state. Is terminated.

  As described above, since the error is notified when an error state occurs, it is possible to easily notify the player or game clerk that an error has occurred. The notification of the error state may be performed by a display other than the variable display device 9, a voice message, blinking of a light emitter such as a lamp or LED, or a combination of two or more of these. Good.

  FIG. 25 is a flowchart showing an example of the prize ball process in S31. In the prize ball process, the CPU 56 executes a prize ball number addition process (S201) and a prize ball control process (S202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (S203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the prize ball number adding process, a prize ball number table shown in FIG. 26 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “7”) is set in the head address of the winning ball number table, and thereafter, the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to the bit to which the detection signal of each switch at the input port 0 is input (see FIG. 11). The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the seven switch-on buffers.

  FIG. 27 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (S211). Then, the data at the address indicated by the pointer (in this case, the number of processes) is loaded (S212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (S213).

  Then, the pointer value is incremented by 1 (S214), the winning ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (S215), The value is increased by 1 (S216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (S217), and the loaded contents and the data of the winning ball number table pointed to by the pointer (in this case, the switch input bit judgment value) (S218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the value of the pointer is increased by 1 (S219).

  If the calculation result in S218 is 0, that is, if the detection signal of the switch to be inspected is in the on state, the prize ball number table data pointed to by the pointer (in this case, the prize ball number) is used as the prize ball addition value. It is set (S220, S221), and the prize ball addition value is added to the contents of the 16-bit total prize ball number storage buffer formed in the RAM 55 (S222). The total winning ball number storage buffer is formed in the backup RAM. If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (S223, 224). Further, “formed in RAM” means an area in the RAM.

  In S225, the number of processes is reduced by 1. If the number of processes is 0, the process is terminated, and if the number of processes is not 0, the process returns to S214 (S226). In S220, if it is confirmed that the calculation result in S218 is 0, that is, the detection signal of the switch to be inspected is in the OFF state, the process proceeds to S225.

  FIG. 28 is a flowchart showing the prize ball control process of S201. In the prize ball control process, the CPU 56 executes any one of S231 to S234 according to the value of the prize ball process code.

  FIG. 29 is a flowchart showing a prize waiting process 1 (S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 sets the award ball waiting output value (30 (H)) in the port 0 buffer (S243). When the prize ball waiting output value is set in the port 0 buffer, the contents of the port 0 buffer are output to port 0 in S203, whereby the prize ball REQ signal is turned off and the connection confirmation signal is turned on. The state is maintained (see FIG. 9). In addition, the prize ball control signal enters an invalid command (00 (H)). Next, it is confirmed whether or not the prize ball timer is 0 (S244). If the prize ball timer is not 0, the prize ball timer is decremented by 1 (S245), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (time for providing an interval between ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, 00 (H ) Means that the prize ball control signal is being output). The prize ball timer is set in S275 of the prize ball waiting process 3 described later. Further, the processing of S243 to S245 is performed after the execution of the prize ball process 3 of S234 is completed and the previous payout process is completed, and the prize ball REQ signal is turned off and the invalid command (00 (H)) is output.

  If the value of the prize ball timer is 0, the CPU 56 confirms the state of bit 3 (see FIG. 11) of the input port 1 and determines whether or not the payout error signal from the payout control board 37 is on. (S246). If the payout error signal is on, the process is terminated. That is, if the payout error signal is being received, the CPU 56 does not shift to the prize ball transmission process and does not perform the prize ball control signal and prize ball REQ signal transmission process. According to such a configuration, the CPU 56 outputs a prize ball control signal and a prize ball REQ signal to the payout control board 37 when the control state is an error state and the prize ball payout process is not executed (see S621). No need to send. Therefore, in the payout control board 37, a prize ball control signal or a prize ball REQ signal is sent during transmission of a payout error signal, thereby reducing the possibility that the prize ball control signal or the prize ball REQ signal is missed. Can be made.

  Even if the payout error signal is being received, if the value of the total prize ball number storage buffer is not 0 and there is a prize ball to be paid out, the CPU 56 shifts to a prize ball transmission process to give a prize ball. You may make it perform the transmission process of a control signal and a prize ball REQ signal. As will be described later, the payout control means does not execute the award ball payout process when the out of ball or full tank error has occurred (the process after S621 in FIG. 51 is not executed). However, even if an error relating to payout has occurred, the payout control means turns on the prize ball REQ signal as long as no main control unconnected error or prize ball REQ signal error has occurred. When the prize ball control signal is received from the board 31, the number indicated by the prize ball control signal is added to and stored in the prize ball unpaid number counter (see S541, S544, and S545 in FIG. 47). Accordingly, the payout control means can immediately execute the payout process of the winning ball when the error is canceled. Therefore, it is possible to prevent the execution of the payout process for the prize ball to be paid out in the payout control means from being delayed. In addition, because the error of ball breakage or full tank is canceled by turning off the ball break switch or full tank switch, the error can be cleared relatively easily compared to other causes (main control unconnected error, etc.). (See FIG. 56).

  Further, the CPU 56 confirms the state of the bit 2 (see FIG. 11) of the input port 1 and determines whether or not the prize ball count signal from the payout control board 37 is on (S247). If the prize ball count signal is on, the process is terminated. That is, even when the prize ball count signal is being received, the CPU 56 does not shift to the prize ball transmission process and does not perform the prize ball control signal and prize ball REQ signal transmission process. Therefore, when the prize ball count signal is transmitted from the payout control board 37, it is possible to avoid the prize ball control signal and the prize ball REQ signal being transmitted from the main board 31 toward the payout control board 37. Therefore, the payout control board 37 prevents the prize ball control signal and the prize ball REQ signal from being lost due to the prize ball control signal and the prize ball REQ signal being transmitted during the transmission of the prize ball count signal. can do.

  In this example, when the prize ball count signal is in the on state, the determination process of S246 and S247 is repeatedly executed, and when the payout error signal and the prize ball count signal are in the off state, the prize ball transmission process is performed. Will be migrated.

  If the prize ball count signal is not on, the CPU 56 confirms the contents of the total prize ball number storage buffer (S248). If the value is 0, the process ends. If not, the prize ball process code value is set to 1 (S249), and the process ends.

  FIG. 30 is a flowchart showing a prize ball transmission process (S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (S252). If the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value, the content of the total prize ball number storage buffer is set in the prize ball number buffer (S253).

  Thereafter, the output value (10 (H)) during the prize ball REQ is set in the output port 0 buffer (S254). When the output value in the prize ball REQ is set in the output port 0 buffer, the contents of the output port 0 buffer are output to port 0 in S203, so that the prize ball REQ signal is turned on, and the connection confirmation signal Is kept on (see FIG. 9). Further, the content of the winning ball number buffer is set in the lower 4 bits of the output port 0 buffer (S255). Further, a prize ball processing waiting time is set in the prize ball timer (S256). The award ball processing waiting time is, for example, a time predetermined as a period sufficient for completing the award ball payout control on the payout control board 37. Thereafter, the value of the prize ball process code is set to 2 (S257), and the process is terminated.

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball control signal designating the maximum number of payouts of “15” is transmitted to the payout control board 37.

  FIG. 31 is a flowchart showing a prize waiting process 2 (S233) executed when the value of the prize ball process code is 2. In the award ball waiting process 2, the CPU 56 checks whether or not the award ball timer is 0 (S263). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (S264), and the process is terminated. If the value of the prize ball timer is not 0 at this stage, it means that the payout process of the number of prize balls instructed to the payout control means is not completed.

  If the value of the prize ball timer is 0, the CPU 56 determines that the prize ball payout for the number instructed to the payout control means has been completed, and from the contents of the total prize ball number storage buffer, the contents of the prize ball number buffer. The prize ball payout number commanded to the payout control means is subtracted (S265). Then, the value of the prize ball process code is set to 3 (S266), and the process is terminated. It is to be noted that whether or not the number of prize balls paid out for the number instructed to the payout control means is completed is output for the number of prize balls paid out to the payout control means after outputting the prize ball REQ signal without using the prize ball timer. It may be determined based on whether or not a prize ball count signal is received.

  In the prize ball transmission process shown in FIG. 30 and the prize ball waiting process 2 shown in FIG. 31, the game control means transmits the prize ball control signal and then receives a prize ball from the payout control means within a predetermined period. When the count signal has not been received the number of times corresponding to the number specified by the prize ball control signal, it is assumed that an abnormality has occurred in communication with the payout control means, and control for stopping the progress of the game and payout error are performed. It may be configured to output a signal.

  The game control means clears the output state of the output port after saving the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game. Then, the progress of the game is stopped until the abnormality of communication with the payout control means is resolved. In other words, even if a new event (game ball winning etc.) occurs, the corresponding process is not performed, and for example, a newly generated event is stored. The game control means transmits a communication error display command to the display control means of the display control board 80 in order to notify the occurrence of communication abnormality using the variable display device 9 or the like before stopping the progress of the game. It may be configured. When the communication abnormality is resolved, the game control means can restore the output port based on the control state stored in the RAM 55.

  FIG. 32 is a flowchart showing the prize waiting process 3 (S234) executed when the value of the prize ball process code is 3. In the prize ball waiting process 3, the CPU 56 sets the prize ball REQ waiting time in the prize ball timer (S275). Then, the value of the prize ball process code is set to 0 (S276), and the process is terminated.

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The total award ball number storage buffer corresponds to a prize game medium number storage means for storing stored contents for at least a predetermined period by a backup power source as a variable data storage means when power supply to the pachinko gaming machine 1 is stopped. Further, the game control means transmits a payout command signal designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. When the game control means transmits a payout command signal, it determines that the number of prize balls paid out for the number instructed to the payout control means has been completed, and then pays out the number of prize balls stored in the total prize ball number storage buffer. A subtraction process for subtracting the number of payouts specified by the command signal is performed. In addition, without confirming whether or not the number of prize balls paid out to the number designated by the payout control means has been completed, the payout number is immediately calculated from the number of prize balls stored in the total prize ball number storage buffer after sending the payout command signal. A subtraction process for subtracting the number of payouts specified by the command signal may be performed. Further, before the payout command signal is transmitted, a subtracting process for subtracting the payout number specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer may be performed.

  In this embodiment, as the prize game medium number storage means for storing the total number of premium game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of the prize game media in an identifiable manner stores the number of prizes received in each prize area, or the number of prizes for each prize area (for example, the same number of prize balls) (for example, The number of winning holes 14 corresponding to the number of 6 winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 10 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls. And the number of winnings that have not yet been paid out).

  FIG. 33 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 33 is also a specific process of S26 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs the fluctuation shortening timer subtraction process (S310) and the start port switch passage confirmation process (S311), and then according to the internal state (in this example, the special symbol process flag) Any one of S300 to S309 shown below is performed.

  The variation shortening timer subtraction process is a process of subtracting the number of variation shortening timers provided corresponding to the maximum number that can be stored in the start memory (the memory that the start port switch 14a is turned on). In the special symbol jackpot determination process (S301), which will be described later, for example, when the value of the fluctuation shortening timer is 0 and the low probability state (normal state), the starting memory number is the maximum value of the starting memory, the probability variation state Then, if the number of starting memories is “2” or more, it is determined to use a pattern with a shortened variation time as a symbol variation pattern.

  In the starting port switch passage confirmation process, when the CPU 56 determines that the starting ball switch 14a is turned on after the hit ball has won the starting winning port 14 provided in the game board 6, the start memory number is the upper limit value ( In this example, if 4) has not been reached, the number of starting memories is increased by 1, and the value of each random number such as a big hit determination random number is extracted. And the process which stores them in the random value storage area (special symbol determination buffer) corresponding to the value of the starting memory number is executed.

  Special symbol normal processing (S300): The starting memory number is confirmed. If the starting memory number is not 0, the value of the special symbol process flag is changed so as to proceed to S301.

Special symbol jackpot determination processing (S301): The contents of a buffer or the like for storing various random numbers stored when a winning prize is received are shifted. As a result of the shift, it is determined whether or not to win the jackpot based on the contents of the extruded buffer. Note that the maximum number of buffers that can be stored for start winnings is prepared. Further, the content of the buffer pushed out by the shift is the content corresponding to the start winning that occurred most recently. If it is decided to win, the big hit flag is set. Thereafter, the value of the special symbol process flag is changed so as to proceed to S302.

Stop symbol setting processing (S302): The stop symbol of the left / right middle symbol which is the display result of the special symbol variation display is determined. Then, the value of the special symbol process flag is changed so as to proceed to S303.

  Fluctuation pattern setting process (S303): A variation display pattern of a special symbol, that is, a variation display pattern (variation pattern) is determined. Then, a process for outputting a display control command for notifying the determined variation pattern, stop symbol, and the like to the display control board 80 is performed. Thereafter, the value of the special symbol process flag is changed so as to proceed to S304.

  Special symbol variation processing (S304): It is confirmed whether or not the variation time determined according to the variation pattern has elapsed. If it has elapsed, the value of the special symbol process flag is changed so as to proceed to S305.

  Special symbol stop process (S305): If a big hit is determined after a certain period of time (for example, 1.000 seconds), the special symbol process flag value is changed to shift to S306. To do. Otherwise, the value of the special symbol process flag is changed to shift to S300.

  Preliminary winning opening opening process (S306): Control for opening the large winning opening is started. Specifically, the counter and flag are initialized, and the solenoid 54 is driven to open the special winning opening. Then, the value of the special symbol process flag is changed so as to proceed to S307.

  Processing for opening a special prize opening (S307): A process for confirming the closing condition of the special prize opening is performed. If the closing condition for the big prize opening is satisfied, the value of the special symbol process flag is changed so as to proceed to S308.

  Specific area valid time processing (S308): Monitors whether or not the V winning switch 22 has passed, and performs processing for confirming that the big hit gaming state continuation condition is satisfied. If the big hit gaming state continuation condition is satisfied and there are still remaining rounds, the value of the special symbol process flag is changed so as to proceed to S307. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the value of the special symbol process flag is changed so as to proceed to S309.

  Big-hit ending process (S309): Control for causing the effect control means to display to notify the player that the big-hit gaming state has ended. Then, the value of the special symbol process flag is changed so as to proceed to S300.

  FIGS. 34 and 35 are explanatory diagrams showing examples of the contents of display control commands sent from the main board 31 to the display control board 80. FIG. In the example shown in FIG. 34, commands 8000 (H) to 8026 (H) are special content variation patterns in the variation display device 9 that variably displays the special symbols, that is, effect contents related to the display result derivation operation in the variation display device 9. Is a display control command indicating. Note that a command for specifying a variation pattern (variation pattern command) also serves as a variation start instruction. In addition, commands 8000 (H) to 8012 (H) are used in a low probability, and commands 8013 (H) to 8025 (H) are used in a high probability. A command 8026 (H) is a command for designating a shortened display pattern.

  Commands 86XX (H), 87XX (H), and 88XX (H) are display control commands for designating the left middle right stop symbols of the special symbols. The command 8F00 (H) is a display control command (confirmation command) for instructing to stop the special symbol variation display.

  The command 9XXX (H) is a display control command related to the display state of the change display device 9 that is not related to the change of the special symbol and the big hit game. Command 9000 (H) is a special symbol power-on designation command that is sent when power is turned on. When receiving the special symbol power-on designation command, the display control means starts control for initial display. The command AXXX (H) is a display control command that is sent from the start of the jackpot game to the end of the jackpot game. The command BXXX (H) is a display control command related to a normal symbol variation pattern or the like. Command B300 (H) is a normal symbol power-on designation command sent when power is turned on. When the display control means receives the normal symbol power-on designation command, it starts control for initial display.

  The command C0XX (H) is a display control command indicating the number of start memory display areas 18 for changing the display color in the display area for displaying the start winning memory number in the variable display device 9. For example, when receiving the command C0XX (H), the display control means changes the display color of the number of start memory display areas 18 designated by “XX (H)” in each start memory display area 18. That is, the command C0XX (H) is a command for instructing control of a display area provided for informing information on the number of reserved items. Note that the command related to the number of start memory display areas 18 for changing the display color may be configured to indicate increase / decrease in the number of areas for changing the display color.

  The command C100 (H) is a display control command that designates an error display that is displayed on the variable display device 9 and that indicates that an error condition such as a broken ball or full tank has occurred. Since the command C100 (H) is a command for notifying the display control means that an error state has occurred, it is referred to as an error occurrence notification command. The command C101 (H) is a display control command for designating deletion of the error display displayed on the variable display device 9. Since the command C101 (H) is a command for notifying the display control means that the error state has been released, it is referred to as an error release notification command. When receiving the error occurrence notification command, the display control means displays a predetermined error display on the variable display device 9 to notify the player of the occurrence of the error state. When receiving the error release notification command, the display control means deletes the predetermined error display displayed on the variable display device 9 and notifies the player of the release of the error state.

  When the display control means receives the above-described display control command from the game control means of the main board 31, the display control means changes the display state of the variable display device 9 and the normal symbol display 10 according to the contents shown in FIG. Although details will be described later, when the display control means receives a predetermined display control command, the display control means outputs a lamp control command and a sound control command at a predetermined timing.

  As shown in FIG. 35, in this embodiment, information related only to lamp control is also transmitted to the display control board 80 as a display control command. The command C2XX (H) is a display control command indicating the number of lighting of the normal symbol start memory display 41. When the display control means receives a display control command indicating information related to lamp control only, the display control means transmits a lamp control command having the same contents as the display control command to the light emitter control means. When the illuminant control means receives the command C2XX (H) output from the display control means as the lamp control command, the number of indicators designated by “XX (H)” in the normal symbol start memory display 41 are turned on. And That is, the command C2XX (H) is a command for instructing the control of the light emitter that is provided in order to notify the information of the number of reserved symbols of normal symbols. In addition, the command regarding the number of lighting of the normal symbol start memory | storage display 41 may be comprised so that increase / decrease in the number of lighting may be shown.

  The command C300 (H) is a display control command for instructing lighting of the prize ball lamp 51. Command C300 (H) is a command transmitted to the display control means in response to reception of a prize ball count signal from the payout control means, and is referred to as a prize ball payout confirmation designation command. Upon receiving the display control command “C300 (H)”, the display control means outputs the command C300 (H) as the lamp control command. When receiving the lamp control command “C300 (H)”, the light emitter control means turns on the display state of the prize ball lamp 51 and turns it off after a predetermined period. In other words, the lighting state is set for a predetermined period. Command C300 (H) is a command indicating control of a light emitter provided to notify a player or the like that a prize ball has been paid out.

  Commands C400 (H) and C401 (H) are display control commands related to the display state of the bulb-out lamp 52. When receiving the display control command “C40X (H)”, the display control means outputs the command C40X (H) as the lamp control command. When the lamp control command “C400 (H)” is received, the luminous body control means sets the display state of the ball break lamp 52 to the display state with a ball, and when the lamp control command “C401 (H)” is received, The display state of the lamp 52 is set to the display state when the ball is out of sphere. That is, commands C400 (H) and C401 (H) are commands indicating control of a light emitter provided to notify a player or game store clerk that a supply ball has run out.

  Even when a command indicating information related only to sound control is used, the command is transmitted to the display control board 80 as a display control command, and a sound control command indicating the same content as the display control command is displayed. To the audio control board 70. Based on the sound control command, sound output control is executed in the sound control board 70.

  Next, the operation of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 36 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 36, the output port 0 is an output port for outputting each phase signal supplied to the firing motor 94 by the stepping motor and each phase signal supplied to the dispensing motor 289 by the stepping motor. It is. In addition, the output port 1 includes a ball break LED 52, a prize ball LED 51, a prize ball count signal and a payout error signal, a prize ball in-game signal output to the outside of the pachinko gaming machine 1, prize ball information, ball rental information and a gaming machine error. An output port for outputting a status signal.

  The output port 2 is an output port of each segment output of the error display LED 374 by 7 segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 37 is an explanatory diagram showing an example of bit assignment of the input port in the payout control means. As shown in FIG. 37, a 4-bit prize ball control signal is input to bits 0 to 3 of the input port 0. Bits 4 to 7 are supplied with a connection confirmation signal from the main board 31, a prize ball REQ signal from the main board 31, a detection signal from the ball break switch 187, and a detection signal from the payout motor position sensor 295, respectively. In addition, bits 0 to 3 of the input port 1 respectively include a touch sensor signal (launch control signal) from the touch sensor, a detection signal from the payout count switch 301, and an operation signal as an error release signal from the error release switch 375. The detection signal of the full tank switch 48 is input. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 4 to 6 of the input port 1, respectively. An output signal and a power-off signal from the clear switch 921 from the power supply board 910 are input to the input port 2.

  FIG. 38 is a timing chart for explaining the communication between the payout control means of the pachinko gaming machine 1 and the card unit 50. The payout control means turns on the PRDY signal when power supply to the pachinko gaming machine 1 is started and a payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control means. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control means. That is, the BRQ signal is turned on.

  Then, when the payout control means turns on the EXS signal for the card unit 50 and detects the fall (off) of the BRQ signal from the card unit 50, the payout control means 289 drives the payout motor 289 to set a predetermined number (for example, 25). Pay out the rental balls to the player. Then, when the payout is completed, the payout control means lowers the EXS signal for the card unit 50. That is, the EXS signal is turned off.

  Next, the operation of the payout control means will be described. 39 to 42 are flowcharts showing the main process executed by the payout control means. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (S701). Next, the interrupt mode is set to interrupt mode 2 (S702), and a stack pointer designation address is set to the stack pointer (S703). The payout control CPU 371 initializes the built-in device register (S704), initializes the CTC and PIO (S705), and then sets the RAM in an accessible state (S706). Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (S707).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the setting processing of the built-in device register in S704 and the processing in S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register for setting an interrupt vector Settings are made. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 0.7 ms, a value corresponding to 0.7 ms is set in a predetermined register (time constant register) as an initial value.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interruption process includes a payout control process for controlling the payout means (including a process for driving the ball payout device 97 at least in response to a command signal related to paying out a prize ball from the main board 31, and a ball payout device in response to a ball lending request. The process which drives 97 may be included.) Is performed.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  An interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt generated when the internal clock (system clock) of CPU 371 is counted down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the state of the output signal of the clear switch 921 input via the input port 2 is confirmed only once (S708). In the confirmation, when the on-state is detected, the payout control CPU 371 executes an initialization process (S712 to S715). If the clear switch 921 is not in the on state, was the data protection process in the backup RAM area (for example, when the power supply stopped such as adding parity data) performed when the power supply to the pachinko machine 1 was stopped? It is confirmed whether or not (S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 10). Note that such a confirmation method is merely an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in S709. If it is confirmed, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of power supply stop, the payout control state recovery process is not executed, and the initialization process (the process of S712 to S715) is executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the initial value of the award ball unpaid number counter (S711). And then. The process after S712 is executed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (S712). In addition, initial values are set in the flags and counters of the RAM area (S713). The process of S713 includes a process of setting the initial value of the award ball unpaid number counter in the award ball unpaid number counter. Accordingly, when the payout control state restoration process (S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is.

  Then, a CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated (S714). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since the interruption is prohibited in S701 of the initial setting process, the interruption is permitted before the initialization process is completed (S715). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag in the timer interrupt process. In the loop process in the main process, when it is detected that the timer interrupt flag is set, the processes after S750 are executed.

  In S750, the payout control CPU 371 executes a power-off process for monitoring whether or not a power-off signal is output. Then, the payout control process after S751 is executed. In the payout control process, the payout control CPU 371 first performs an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) (S751). In the firing motor control process of S763, the excitation pattern is stored in the excitation pattern buffer that is a RAM area. In S751, the payout control CPU 371 outputs the contents of the excitation pattern buffer to the lower 4 bits of the output port 0. To do.

  The power-off process is a process similar to the power-off process executed by the game control means (see FIGS. 16 and 17). That is, if the power-off signal from the power supply board 910 is on for a predetermined time counted by the backup monitoring timer, the power supply stop process is executed. In the power supply stop process, a check code (specifically a checksum) is calculated for the RAM area that you want to save even when the power supply is stopped, the check code is saved in the backup RAM area, RAM access is prohibited, and output After clearing the port, the loop processing is started. When it is detected in the loop processing that the power-off signal is turned off, the state of the payout control means is the same as when the game control means returns to the state in which the game control process is executed (at least from the main board 31). Including a process of driving the ball payout device 97 in response to the command signal relating to the prize ball payout, and a process of driving the ball payout device 97 in response to the ball lending request may be included. . Specifically, for example, the process returns to S701 of the main process shown in FIG.

  Next, the payout control CPU 371 executes one of tasks 1 to 6 according to the value of the switch counter formed in the RAM. In task 1, 3 is set as the number of inputs to be detected in the number of switch checks (S781), and the address of the firing control signal timer is set in the pointer (S782). Then, a switch check process is executed (S761).

  The switch check process is a process for checking the states of the bits 0, 1, and 2 of the input port 1, that is, checking the states of the detection signals of the firing control signal, the payout number count switch, and the error release switch. Specifically, switch timers (launch control signal timer, payout number count switch timer, error release switch timer) corresponding to each of them are formed in the RAM, and it is detected in the switch check process that they are in the ON state. Then, the value of the corresponding switch timer is incremented by 1, and when it is detected that the switch is off, the value of the corresponding switch timer is cleared. In Task 1, since the number of switch checks is set to 3, the status of the detection signals of the firing control signal, the payout number count switch, and the error release switch is checked. In other tasks, one of them is checked. There may be only one or two status checks. Further, the value of the switch timer is controlled based on the state of the detection signal of the firing control signal, the number-of-payout count switch, and the error release switch (for example, launch motor control processing, prize ball lending control processing, error processing described later, error When the switch timer value has reached a predetermined value, it is determined that the switch timer has been turned on.

  Also, the payout control CPU 371 performs input determination processing (S762). In the input determination process, the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1 (see FIG. 37) are detected, and the detection result is a predetermined 1 byte of RAM (referred to as an input state flag). It is a process to be reflected in. In the payout control process, when control is performed based on the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1, the state of the input port is not directly checked, but the input state is checked. Check the status of the flag.

  Next, the payout control CPU 371 executes a firing motor control process (S763). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Then, the process proceeds to S790.

  In task 2, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (S764). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (S765). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and performing a control for paying out the number of award balls indicated by a prize ball control signal from the main board. Is executed (S766). Then, the process proceeds to S790.

  In task 3, the payout control CPU 371 sets 1 as the number of inputs to be detected in the switch check number (S783), and sets the address of the firing control signal timer in the pointer (S784). Then, a switch check process is executed (S761). Therefore, in task 3, only the state check of the firing control signal is executed. Next, a firing motor control process is executed (S763). Also, a payout motor control process is executed (S768). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed. Then, the payout control CPU 371 executes error processing for detecting various errors (S769). Further, an information output process for outputting a prize ball information signal and a ball lending information signal output to the outside of the pachinko gaming machine 1 is executed (S770). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (S771). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (S772: output processing). However, since the lower 4 bits (fire motors φ1 to φ4) of output port 0 are executed in S751, the output of the lower 4 bits of output port 0 is not performed in the output process. The output port 0 buffer, output port 1 buffer, and output port 2 buffer are a payout motor control process (S768), a prepaid card control process (S764), a main control communication process (S765), an information output process (S770), and a display control process. Updated in (S771). Then, the process proceeds to S790.

  In task 4, the payout control CPU 371 sets 2 as the number of inputs to be detected as the number of switch checks (S785), and sets the address of the payout count switch timer in the pointer (S786). Then, a switch check process is executed (S761). Therefore, in task 4, only the status check of the detection signals of the payout number count switch 301 and the error release switch 375 is executed. Next, input determination processing is executed (S762), and the process proceeds to S790.

  In task 5, the payout control CPU 371 sets 1 as the number of inputs to be detected in the switch check number (S787), and sets the address of the firing control signal timer in the pointer (S788). Then, a switch check process is executed (S761). Therefore, in task 3, only the state check of the firing control signal is executed. Next, a firing motor control process is executed (S763). Further, a prepaid card unit control process is executed (S764). Next, the payout control CPU 371 executes main control communication processing (S765). Further, a prize ball lending control process is executed (S766). Then, the process proceeds to S790.

  In task 6, the payout control CPU 371 executes a payout motor control process (S768). Further, error processing is executed (S769). Further, an information output process is executed (S770). Further, display control processing is executed (S771). Further, an output process is executed (S772), and the process proceeds to S790.

  In S790, the task counter value is incremented by 1, and the process returns to S716. When the value of the task counter reaches 6, it is reset to 0.

  As described above, in this embodiment, when a timer interrupt occurs, all processes in the payout control process (switch check process, input determination process, firing motor control process, payout motor control process, prepaid card unit control) Process, main control communication process, prize ball lending control process, error process, display control process, output process), depending on the value of the task counter when the timer interrupt occurs Only the part is executed. Therefore, by making the timer interrupt generation period relatively short (for example, 0.7 ms), the process to be executed in a short period (for example, the process of S751) can be repeatedly executed in a short period. . In addition, there is a possibility that processing that cannot be executed if all processing in the payout control processing is executed within the timer interruption period, but processing that cannot be executed occurs by executing only a part. Can be prevented.

  FIG. 43 is a flowchart showing the firing motor control process of S763. In the firing motor control process, the payout control CPU 371 performs when the VL signal from the card unit 50 is in an off state (no prepaid card is connected) or when the full tank switch 48 is in an on state (bottom plate full). Shifts to S518 (S511, S513). If the prepaid card is not connected and the lower pan is not full, the process proceeds to S514. In S514, the payout control CPU 371 checks whether or not the touch sensor signal (launch control signal) is on. If it is in the on state, the process proceeds to S515, and if it is not in the on state, the process proceeds to S518.

  In S515, the payout control CPU 371 increments the firing motor excitation pattern counter by one. Then, data corresponding to the value of the excitation pattern counter is read from the firing motor excitation pattern table stored in the ROM (S516). Further, the read data is set in the firing motor excitation pattern buffer (S517). As described above, the contents of the firing motor excitation pattern buffer are output to the output port in S750. In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  In S518, non-rotation data (excitation pattern for preventing rotation of the firing motor 94) is set in the firing motor excitation pattern buffer.

  As described above, the firing motor 94 is disabled when the prepaid card is not connected or when the lower tray is full, so that the game does not proceed even though they are generated. . It should be noted that the firing motor 94 can also be used when a communication error (connection confirmation signal is off) or a prize ball REQ signal error occurs when the prize ball REQ signal is turned on or off at an incorrect timing. May be disabled so that the game ball cannot be launched into the game area 7.

  FIG. 44 is a flowchart showing the payout motor control process in S768. In the payout motor control process, the payout control CPU 371 executes one of S521 to S526 in accordance with the value of the payout motor control code.

  In the payout motor normal process (S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout are sequentially set. Yes.

  In the payout motor start preparation process (S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 excites the bits 4 to 7 of the output port 0 buffer corresponding to the output state of the output port 0. Processing such as setting the initial value of the pattern is performed.

  In the payout motor slow-up process (S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 is longer than the constant speed process in order to smoothly start the payout motor 289. The output port 0 buffer bits 4 to 4 corresponding to the output state of the output port 0 are read out at intervals and at time intervals that gradually approach the time interval for constant speed processing. Set to 7. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the pointer value is incremented by one.

  In the payout motor constant speed process (S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the content of the payout motor excitation pattern table and sets the output state of the output port 0. Set to bits 4-7 of the corresponding output port 0 buffer.

  In the payout motor brake process (S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to smoothly stop the payout motor 289. In addition, the content of the payout motor excitation pattern table is read at a time interval that gradually moves away from the time interval in the case of constant speed processing, and is stored in bits 4 to 7 of the output port 0 buffer corresponding to the output state of the output port 0. Set.

  In the ball biting payout motor brake process (S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 289 in the case of rotation for releasing the ball biting. In order to stop, the payout motor excitation pattern table has a longer interval than that of the rotation of the payout motor 289 for releasing the ball biting and at a time interval gradually moving away from the time interval in the case of the constant speed process. Are read out and set in bits 4 to 7 of the output port 0 buffer corresponding to the output state of output port 0.

  FIG. 45 is a flowchart showing the main control communication process of S765. In the main control communication process, the payout control CPU 371 executes one of S531 to S533 according to the value of the main control communication control code.

  FIG. 46 is an explanatory diagram showing conditions for inputting a prize ball control signal through the input port in the main control communication normal process. As shown in FIG. 46, the main control unconnected error in the 1-byte error flag formed in the RAM (connection confirmation signal is turned off), the prize ball REQ signal error (the prize ball REQ signal is turned on or off at an incorrect timing) ) Is not in the set state and the BRDY signal from the card unit 50 is not in the on state, the payout is made when the connection confirmation signal is in the on state and the prize ball REQ signal is in the on state. The control means inputs a prize ball control signal via the input port. The error bit is a bit in an error flag that is set when it is detected that various errors have occurred.

  FIG. 47 is a flowchart showing a main control communication normal process (S531) executed when the value of the main control communication control code is zero. In the main control communication normal processing, when the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 ends the processing without executing the subsequent processing. (S541). In S541, if any one of the two bits in the error flag is set, it is determined that the error bit is set.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50. That is, when a ball lending request is generated, communication with the game control means of the main board 31 (communication relating to prize ball payout) does not proceed.

  When the conditions of S541 and S542 are not satisfied and the connection confirmation signal is in the on state, the payout control CPU 371 confirms whether or not the prize ball REQ signal is in the on state (S543, S544). If it is in the ON state, the number of prize balls indicated by the prize ball control signal is added to the contents of the prize ball unpaid number counter (S545). Then, the value of the main control communication control code is set to 1 (S548), and the process ends. The prize ball unpaid-out number counter is formed in a non-volatile (power-backed up in this example) RAM area.

  FIG. 48 is a flowchart showing the main control communication in-process (S532) executed when the value of the main control communication control code is 1. In the main control communication process, the payout control CPU 371 confirms the state of the prize ball REQ signal if the connection confirmation signal is in the on state (S551) (S552). If the prize ball REQ signal is off, the prize ball REQ signal error bit is set in the error flag (S553). This is because it is strange that the prize ball REQ signal immediately turns off at this stage.

  Next, the payout control CPU 371 sets the prize ball REQ signal off monitoring time in the main control communication control timer (S557). Then, the value of the main control communication control code is set to 2 (S558), and the process ends.

  FIG. 49 is a flowchart showing main control communication end processing (S533) executed when the value of the main control communication control code is 2. In the main control communication process, if the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 proceeds to S567 (S561). Also, when the connection confirmation signal is in the off state, the process proceeds to S567 (S562). If both error bits are off and the connection confirmation signal is on, it is checked whether or not the prize ball REQ signal is off (S563). When it is turned off, the process proceeds to S567.

  If the prize ball REQ signal is not turned off, the value of the main control communication control timer is confirmed (S564). If the value of the main control communication control timer is not 0, the value of the main control communication control timer is decremented by 1 (S565). If the value of the main control communication control timer is 0, the prize ball REQ signal is not turned off within the monitoring time, the prize ball REQ signal error bit is set in the error flag (S566), and the process proceeds to S567. .

  In S567, the value of the main control communication control code is set to 0, and the process ends.

  FIG. 50 is a flowchart showing the prize ball lending control processing in S766. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (S601), whether the paid out game ball is a winning ball or a lending ball. It is confirmed whether it exists (S602, S603). In this example, whether or not the game ball is a prize ball is confirmed by whether or not the current payout control state is a prize ball. Specifically, whether or not a prize ball is in progress is confirmed, for example, by whether or not a prize ball operating flag in the payout control state flag formed in the RAM is set (S602). Further, whether or not the game ball is a lending ball is confirmed by whether or not the current payout control state is lending the ball. Specifically, whether or not the ball is being lent is confirmed, for example, by whether or not the ball renting operation bit in the payout control state flag formed in the RAM is set (S603).

  If it is during the winning ball, the value of the winning ball unpaid number counter is decremented by 1 (S604). If it is not in the winning ball but in the ball lending, the value of the ball lending unpaid-out number counter is decremented by 1 (S605). Also, if the winning ball is not being lent or not being lent, the value of the award ball unpaid-out counter is decremented by 1 assuming that the paid gaming ball is a winning ball (S604).

  When the value of the award ball unpaid-out counter is decremented by 1, the payout control CPU 371 confirms the state of bits 0 to 3 and bit 5 of the input port 0 and receives a prize ball control signal from the main board 31 or a prize ball. It is determined whether a REQ signal is being received (S606a). When a prize ball control signal or prize ball REQ signal is being received, in this example, the payout control CPU 371 adds 1 to the count value of the unreported number storage counter without transmitting a prize ball count signal ( S606b). The unreported number storage counter is stored in, for example, a RAM provided in the payout control board 37, and is a counter that counts the number of waiting for award ball count signal transmission.

  That is, the payout control CPU 371 does not perform the process of transmitting a prize ball count signal if a prize ball control signal or a prize ball REQ signal is being received. Accordingly, it is possible to avoid a prize ball count signal from being transmitted from the payout control board 37 when a prize ball control signal or a prize ball REQ signal is being transmitted from the main board 31, so It is possible to prevent the prize ball count signal from being lost due to the prize ball count signal being sent during the transmission of the prize ball control signal or the prize ball REQ signal.

  When neither the prize ball control signal nor the prize ball REQ signal is being received, the payout control CPU 371 turns on the prize ball count signal for a predetermined period (S607). The prize ball count signal is turned on only for a predetermined period between a prize ball count signal indicating one prize ball payout detection and a prize ball count signal indicating another prize ball payout detection. This is to put a period of off-state. Therefore, the predetermined period during which the prize ball count signal is turned on is the off period between the on periods of the prize ball count signals indicating the prize balls when the prize balls are paid out continuously. As long as it can be secured, any period may be used.

  Next, the payout control CPU 371 sets the payout ball detection bit of the payout control state flag formed in the RAM (S608). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven during one award ball payout process (maximum 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301.

  After executing S608 or when it is determined as N in S601, the payout control CPU 371 checks the count value of the unreported number storage counter (S609a). If the count value is not 0, the same processing as S606a for determining whether or not a prize ball control signal or prize ball REQ signal is being received from the main board 31 is performed (S609b). When neither the prize ball control signal nor the prize ball REQ signal is being received, the payout control CPU 371 turns on the prize ball count signal for a predetermined period (S609c), and the count value of the unreported number storage counter 1 is subtracted (S609d).

  Thereafter, the payout control CPU 371 executes any one of S610 to S612 according to the value of the payout control code.

  As described above, in this example, when the prize ball control signal or prize ball REQ signal is being received, execution of the prize ball count signal transmission process is delayed, and the prize ball control signal and the prize ball REQ signal are delayed. After receiving is no longer being received, a prize ball count signal is transmitted. When a prize ball control signal or a prize ball REQ signal is being received, the prize ball count signal transmission process may be canceled without delay.

  In the prize ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending) as shown in FIG. Only in the payout start waiting process. That is, the confirmation process of the payout number count switch 301, the subtraction process of the unpaid number counter, the output process of the prize ball count signal, etc. shown in FIG. 50 are executed without checking the error bit. . Therefore, even if an error occurs, the ball lending unpaid-out counter or the winning ball unpaid-out counter is subtracted in accordance with the detection output from the paid-out count switch 301, and the value of the award ball unpaid-out counter When is subtracted, a prize ball count signal is output. Therefore, the number of game balls that have not been paid out can be reliably managed even in an error state. Even if an error state is detected, a prize ball count signal can be output in response to the detection of a payout of a prize ball. Therefore, even in an error state, it is detected on the payout control board 37 side. Information indicating that the winning ball has been paid out can be transmitted to the main board 31 side.

  Also, in the prize ball lending control processing, when there is a detection output from the number-of-payout count switch 301 when neither a prize ball nor a ball is lent, it is determined that the game ball that has been paid out is a prize ball, and no prize ball has been paid out. The value of the number counter is subtracted and a prize ball count signal is output to the main board 31. Therefore, even when an illegal game ball is paid out, a prize ball count signal is transmitted to the game control means (specifically, the CPU 56) mounted on the main board 31. Since the game control means manages the number of prize balls to be paid out, if a prize ball count signal indicating the number of prize balls more than the number of prize balls to be originally paid out is received, illegal payout is performed. Can be determined. When it is determined that an illegal game ball has been paid out, the game control means performs the following appropriate processing.

  For example, the game control means performs a process for notifying a player, a game clerk, or the like of the occurrence of an error using the variable display device 9 or the like. Specifically, the game control means transmits a display control command for notifying the occurrence of an error to the display control means, thereby controlling the display control means to display on the variable display device 9 that the error has occurred. Let it run. The game control means transmits a lamp control command and a sound control command for informing the error to the lamp control means and the sound control means via the display control means. You may make it perform lighting of the lamp and LED for alerting | reporting generation | occurrence | production, and audio | voice output. The game control means performs a process for stopping the progress of the game. Specifically, the game control means saves the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game, then clears the output state of the output port, and the abnormal state is Stop playing until it is resolved. Further, the game control means performs a process (S30) of outputting information indicating that an illegal game ball has been paid out to a hall computer or the like outside the pachinko gaming machine 1. The game control means uses information output processing to send information indicating the number of prize balls to be paid out and a signal indicating the number of prize balls actually paid based on the prize ball count signal to a hall computer outside the pachinko gaming machine 1 or the like. Can be made to cause the hall computer or the like to determine whether or not an illegal game ball has been paid out. Incidentally, all of the above processes may be executed, but at least one or more of the above processes are executed.

  FIG. 51 is a flowchart showing the payout start waiting process (S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (S621). The error bit in the error flag includes a main board non-connection error bit. The main board non-connection error is set when the connection confirmation signal from the main board 31 is in an off state. Accordingly, the payout control means starts substantial control on condition that the connection confirmation signal is turned on after the power supply to the pachinko gaming machine 1 is started.

  On the other hand, if the BRDY signal is not in the on state, the processing for paying out a prize ball after S631 is executed. If the BRDY signal is on and the BRQ signal, which is a ball lending request signal, is on, a ball lending operation flag is set (S623, S624). Then, “25” is set in the unpaid ball lending counter (S625), and “25” is set in the payout motor rotation frequency buffer (S626).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor start preparation process (S522) to the payout motor control code for selecting the process executed in the payout motor control process. Then, the value of the payout control code is set to 1 (S628), and the process is terminated.

  In S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (S631). If 0, the process ends. The prize ball unpaid-out number counter is a value other than 0 (the number indicated by the prize ball control signal) when the prize ball REQ signal is received from the game control means of the main board 31 in S546 in the main control communication normal process. Is added. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball operating flag is set (S635), and the process proceeds to S627.

  FIG. 52 is a flowchart showing payout motor stop waiting processing (S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (S525) in the payout motor control process ends, and confirms the flag in S641 to determine whether or not the payout operation has ended. Can be confirmed.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (S643), and the process ends.

  FIG. 53 is a flowchart showing the payout passing waiting process (S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid number counter is not 0 even after the predetermined period has elapsed, the state shifts to an error state.

  In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and when a prize ball control signal is received during the prize ball payout, Since the value increases, even if the payout is completed normally, the value of the award ball non-payout number counter may not be 0. Therefore, when the payout of the number of prize balls set in S633 or S634 is confirmed (the value of the prize ball unpaid number counter is the total number of unpaid prize balls known by the payout control board 37 (the current payout number). It may be determined that the payout has been completed normally when the number set in S633 or S634 is subtracted from the number including the number of prize balls to be issued). .

  Further, when the ball lending / dispensing is being performed, it is determined that the payout has been completed normally if the value of the lending / unpaid number counter is 0. If the value of the unpaid ball lending counter is not 0, the state shifts to an error state. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, if the value of the unpaid ball lending number counter is not 0, the payout has not been completed normally.

  In the payout passing waiting process, the payout control CPU 371 first decrements the value of the payout control timer by 1 (S651). Then, the value of the payout control timer is confirmed. If the value is not 0 (S652), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out (S652), it is checked whether or not the ball lending payout process (ball lending operation) has been executed (S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in-progress flag set in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (S654). . If the value of the award ball unpaid number counter is 0, it is determined that the award ball payout process has been completed normally, and a payout ball detection bit, a prize ball operating flag, and a ball lending operation bit in the payout control status flag Is reset (S655), the payout control code is set to 0 (S656), and the process is terminated.

  If the value of the award ball unpaid number counter is not 0 and the payout ball detection bit is not set (S658), the payout control CPU 371 does not play the game ball even if a payout operation is performed. Since no payout has occurred and the payout is insufficient, a payout count switch non-passing error bit (payout case error bit) is set as a game ball payout operation failure (S659).

  As described above, in this embodiment, even when the payout is normally completed, the value of the award ball non-payout number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. , The process proceeds to S655. For example, if 15 game balls should be paid out in one prize ball payout process, but only 14 game balls are actually paid out (the payout count switch 301 has only 14 game balls). (If not detected), since the payout ball detection bit is set, it is considered that the winning ball payout processing has been completed normally. In this case, the value of the award ball unpaid-out counter is decremented by only 14. Since the shortage will be paid out in the next prize ball payout process, there will be no disadvantage to the player.

  As described above, if no game balls are paid out even if a payout operation is performed in the payout process, a payout count count switch non-passing error bit (payout case error bit) is set as a game ball payout operation failure. Is done.

  In the prize ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 48 and the payout passing wait process shown in FIG. 53, the error bit is not checked. Therefore, after the process of S626, S633, or S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bit in the error flag checked in S621 includes an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off.

  If it is confirmed in S653 that the ball lending / dispensing process (ball lending operation) has been executed, the payout control CPU 371 confirms whether or not the value of the lending / unpaid number counter is 0 (S657). If it is 0, it is determined that the ball lending / dispensing process has been completed normally, and the process proceeds to S655.

  If the value of the ball lending unpaid number counter is not 0 and the payout ball detection bit is not set (S658), the game ball is not paid out even if the payout process is executed (payout number count). Assuming that the switch 301 has not detected a game ball), the payout case error bit of the error flag is set (S659), and the process ends.

  As described above, even when a payout operation is performed in the payout process related to the ball lending process, if no game balls are paid out, a payout count switch non-passing error bit (payout case) is assumed as a game ball payout operation failure. Error bit) is set.

  FIG. 54 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (S768). In the payout motor constant speed process (S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the dispensing motor position sensor 295 is turned on twice, for example, every time the cam that rotates in conjunction with the dispensing motor 289 rotates once. In order for the detection signal to be output twice each time the cam rotates once, the cam has two locations in the portion that receives light from the light emitting portion in the payout motor position sensor 295 (positions symmetrical with respect to the axis). Is provided with a reflector. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Therefore, even if the payout control CPU 371 gives an excitation pattern having a step number of 1/2 rotation or more to the payout motor 289, the detection signal of the payout motor position sensor 295 does not turn on. Actually, the payout motor 289 does not rotate due to a foreign matter such as dust adhering to the cam portion and the like, and the game ball is clogged (ball engagement has occurred). As a result, the cam rotates. It can be judged that it is not.

  In this embodiment, when the payout motor 289 receives an excitation pattern for 16 steps (2.087 ms per step), the payout motor 289 makes one rotation and pays out one game ball. Then, for example, as shown in FIG. 52, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time an excitation pattern for 8 steps is given to the payout motor 289. It is determined whether or not it is rotating. Then, if the same state is detected five times continuously (the detection signal of the dispensing motor position sensor 295 is turned off five times continuously or turned on five times continuously), it is determined that ball engagement has occurred. A ball biting release process is executed.

  As shown in FIG. 55, the payout control CPU 371 repeats the process of rotating the payout motor 289 at a high speed and the process of rotating at a low speed a predetermined number of times (for example, 9 times) as shown in FIG. Each time an excitation pattern for 8 steps is given to the payout motor 289, the detection signal of the payout motor position sensor 295 is checked to determine whether or not the payout motor 289 is rotating. If it is determined by the detection signal that the rotation of the payout motor 289 has been restored, the ball biting release process is terminated and the normal ball payout process is returned to.

  If there is no change in the detection signal of the payout motor position sensor 295 even if the high speed rotation process and the low speed rotation process are executed a predetermined number of times, a ball biting error bit (payout case error bit) in the error flag Set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 289. When the payout case error bit is reset (see S807 in FIG. 57), the payout control CPU 371 returns to a state where the payout motor 289 can be driven.

  Thus, the payout control means includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the driving of the payout means when the drive state monitoring means detects a malfunction of the payout means. Including.

  Next, error processing will be described. FIG. 56 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 56, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 displays “1” on the error display LED 374 as a main board non-connection error. To do. When the disconnection of the payout number count switch 301 or a ball clogging occurs in the payout number count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Take control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above. When the prize ball REQ signal is turned on at an improper timing or when the prize ball REQ signal is turned off at an improper timing, “5” is displayed in the error display LED 374 as a prize ball REQ signal error. Control to display. A specific method for detecting that the prize ball REQ signal is turned on or off at an incorrect timing is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error. A full error and a ball-out error are managed as special errors.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (S764).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error or a prize ball REQ signal error occurs, the error release switch 375 is operated and an operation signal (error release signal) is output from the error release switch 375. When it is turned on, the payout control means returns the control state to the state before the error occurred.

  FIG. 57 is a flowchart showing the error processing in S769. In the error processing, the payout control CPU 371 checks the error flag, and the set bits thereof are only payout switch abnormality detection error 2, payout case error and prize ball REQ signal error as specific errors (three It is confirmed whether or not only one of these bits, or only two of the three bits, or only these three bits (S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (S803). The error recovery time is the time from when the error release switch 375 is operated until when the error is actually returned to the normal state.

  If the operation signal from the error release switch 375 is not in the ON state, the value of the timer before error recovery is confirmed (S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (S805). If the pre-error recovery timer value becomes 0 (S806), the payout switch abnormality detection in the error flag is detected. Bits of error 2, payout case error and prize ball REQ signal error are reset (S807), and the process proceeds to S808.

  When the processing of S807 is executed, there may be an error bit that is not in the set state among the bits of the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error. There is no problem even if an error bit that is not present is reset. As described above, in this embodiment, when an error state (see FIG. 56) that causes the setting of the payout switch abnormality detection error 2, the payout case error, or the winning ball REQ signal error bit occurs, the payout occurs. The control unit monitors an operation signal as an error release signal output when the error release switch 375 is pressed, and releases the error state on condition that the operation signal is received.

  In this example, the processing of S601 to S605 shown in FIG. 50 is executed even in the error state. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error relating to payout occurs, the number of game balls actually paid out can be accurately managed.

  Even when it is confirmed that the game ball has passed through the payout count switch 301 during the error state, the payout case error bit is not reset. The bit of the payout case error is reset only when the error cancel switch 375 is operated (specifically, when the error return time after operation elapses) (S802, S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed through the payout number count switch 301, etc. The error is not cleared. In other words, even if an insufficient number of game balls are detected by the payout number count switch 301 in the state in which an error due to a shortage of payouts such as a payout case error has occurred, an error release signal is generated according to the operation of the error release switch 375. If it is not received, the error state is not released. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (S810).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control process of S771.

  Further, as shown in FIG. 58, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (S815), and if the connection confirmation signal is not output (if it is in the off state), The board non-connection error bit is set (S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (S817).

  The payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers for which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (S819). If the value of the switch timer corresponding to the payout count switch 301 is equal to or shorter than the switch-on maximum time, the payout switch abnormality detection error 1 bit is reset (S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the switch check process of S761, and is cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “2”) (S821), the payout control CPU 371 performs the ball lending operation flag and the winning ball operation. If both flags are in the reset state, the game ball passes through the payout number count switch 301 even when the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 is set in the error flag (S822, S823). If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (S824).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (S825). If the VL signal is not input (if it is off), the prepaid card unit is not connected in the error flag. An error bit is set (S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (S827).

  In addition, the payout control CPU 371 checks the state of a predetermined error bit (a full error bit indicating the occurrence of a special error, a ball breakage error bit in this example) in the error flag (S828a), and the predetermined error bit. If any of the error bits is set, the payout error signal is turned on (S828b). When the payout error signal is turned on, an error notification process (S22b) is executed in the game control means as described above. If all the predetermined error bits are in the reset state, the payout error signal is turned off (S828c).

  In the display control process of S771, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. In this embodiment, the game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 perform two-way communication with respect to prize ball payout, but a communication error is indicated by an error display LED 374. Can be notified.

  Further, since the communication error is detected on the payout control means side, even if the game control means and the payout control means perform bi-directional communication with respect to the prize ball payout, the communication without increasing the burden on the game control means. Can detect errors.

  In this embodiment, the main board unconnected error is automatically eliminated when the connection confirmation signal is turned on (see S815 and S817), but additionally, a condition that the error release switch 375 is operated is added. The error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 56). ). Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  In this embodiment, the occurrence of an error related to payout is notified by the error display LED 374 mounted on the payout control board 37 installed on the back surface of the pachinko gaming machine 1, but the pachinko game You may mount an alerting | reporting means in the other location (For example, the payout unit in which the ball payout device 97 grade | etc., Was concentratedly arranged). Furthermore, you may make it alert | report by the indicator (for example, prize ball LED51) installed in the front side of the pachinko gaming machine 1. In the display control process, the payout control CPU 371 performs control for turning on the prize ball LED 51 when the prize ball REQ signal is on. When the prize ball REQ signal is off, the prize ball LED 51 is displayed. Control for turning off the light is performed. When an error relating to payout occurs, for example, the prize ball LED 51 is blinked to notify that an error related to payout has occurred. If an error is notified by a display installed on the front side of the pachinko gaming machine 1, a game clerk or the like can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by error display LED374, and the alerting | reporting by the indicator installed in the front side of the pachinko gaming machine 1.

  FIG. 59 (A) is a timing chart showing a state of occurrence of a payout case error (payout shortage error), and FIG. 59 (B) is a timing chart showing a state when the error cancel switch 375 is operated.

  As shown in FIG. 59 (A), the payout motor 289 is rotated in order to pay out a predetermined number of game balls, and after the game ball that should have been paid out last passes the payout number count switch 301 after stopping the rotation. (After 402.087 ms in this example), it is confirmed whether or not there is an unpaid game ball (corresponding to the determination in S654), and if there is an unpaid game ball, a re-payout operation is executed. FIG. 59 (A) shows an example in which two re-payout operations are executed. When two re-payout operations are executed, it is determined as a payout case error (corresponding to the determination in S672), and “4” is displayed on the error display LED 374 by the display control process in S771 (see FIG. 56). ).

  As shown in FIG. 59B, when the error release switch 375 is operated, the re-payout operation is started again after the error release time has elapsed. As shown in FIG. 59B, when the re-payout operation is started again, the display of “4” on the error display LED 374 is erased. That is, when the corrected payout control is performed after the error release switch 375 is operated, the notification indicating the payout insufficient error is not performed.

  FIG. 60 is a flowchart showing a part related to output of the prize ball information signal in the information output process (S770). The prize ball information signal is output from the payout control board 37 to the outside of the pachinko gaming machine 1 through the terminal board 160.

  In the information output process, the payout control CPU 371 checks whether or not the value of the signal output timer is 0 (S831). The signal output timer is a timer for setting an ON period of the one-pulse prize ball information signal. That is, that the value of the signal output timer is not 0 indicates that the prize ball information signal is being output. When the value of the signal output timer is not 0, the value of the signal output timer is subtracted (S841), and when the value of the signal output timer becomes 0 (S842), the prize ball information signal is turned off (S843). ).

  If the value of the signal output timer is 0, it is confirmed whether or not the ball lending operation flag is set (S832). When the ball lending operation flag is not set, if the payout number count switch 301 is turned on (if the game ball passes), the value of the award ball payout number counter is incremented by 1 (S833, S834). The prize ball payout number counter is a counter formed in the RAM.

  When the value of the prize ball payout number counter reaches 10 (S835), the value of the prize ball payout quantity counter is cleared, the prize ball information signal is turned on (S837), and the signal output timer receives the prize ball. The on period value of the information signal is set (S838). With the above processing, every 10 game balls as prize balls are paid out, and one prize ball information signal is output. In this way, when the payout control means detects that a predetermined number (10 in this example) of game balls have been paid out based on the detection signal of the payout number count switch 301, the award indicating the number is shown. A ball information signal is output to the outside of the pachinko gaming machine 1. Such a prize ball information signal is a signal that can specify the number of prize balls detected by the number-of-payout counting switch 301 in response to the prize ball being paid out. In this embodiment, the predetermined number is 10. However, other numbers may be used as the predetermined number. Further, there may be a plurality of predetermined numbers. For example, when 10 game balls are instructed to be paid out by the game control means and 10 game balls have been paid out, the first prize ball information signal is output, and 15 game balls are instructed from the game control means. The predetermined numbers are 10 and 15 when the second prize ball information signal is output when the payout of the game balls is completed.

  In such information output processing, error bit checking is not executed. Accordingly, even in an error state related to payout of game balls, a payout ball information signal is output every time 10 game balls as a prize ball are detected by the payout number count switch 301. Therefore, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed outside the pachinko gaming machine 1. In addition, when the error cancel switch 375 is operated and the hardware is reset (reset to the payout control CPU 371), the payout of the winning ball is performed by operating the error cancel switch 375. The value of the number counter is also cleared. However, in this embodiment, the payout control means is configured such that the error can be released by operating the error release switch 375, and the winning ball payout number counter is not cleared when the error is released. Therefore, the game ball actually paid out is accurately reflected in the prize ball information signal. Furthermore, since the number of game balls actually paid out can be grasped outside the pachinko gaming machine 1 even in an error state related to payout, an illegal act such as causing an error related to payout and illegally paying out game balls is performed. This is easily detected.

  Also, the prize ball payout number counter is incremented by 1 when the payout number count switch 301 detects a game ball in a state where the ball lending operation flag is not set. Therefore, not only when the winning ball operating flag is set (pick ball is being paid out), but also when the winning ball operating flag and the ball lending operation flag are not set (the winning ball is being paid out or lent out). When the payout number count switch 301 detects a game ball, the value is incremented by one. In other words, when the payout number count switch 301 detects a game ball when neither the winning ball is being paid out nor lending the ball, it is considered that the gaming ball has been paid out by paying out the winning ball, and the outside of the pachinko gaming machine 1 (eg, hall computer). Is reflected in the award ball information signal output to. As described above, the game balls actually paid out are always reflected in the signal output to the outside of the pachinko gaming machine 1, and are therefore always reflected in the total result of the number of payouts at the game store, for example. When the payout number count switch 301 detects a game ball when neither a winning ball is being paid out nor a ball is being rented, it may be considered that a game ball has been paid out based on a lending ball request.

  Next, the operation of the display control means mounted on the display control board 80 will be described. FIG. 61 is a flowchart showing main processing executed by the display control CPU 101. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, initializing a 2 ms timer for determining the start interval of display control, and the like (S321). Thereafter, the display control CPU 101 shifts to a loop process for checking the timer interrupt flag (S322). When a timer interrupt occurs, the display control CPU 101 sets a timer interrupt flag in the interrupt processing. If the timer interrupt flag is set in the main process, the display control CPU 101 clears the flag (S323), and executes the following display control process.

  In this embodiment, the timer interrupt takes every 2 ms. That is, the display control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific display control process is executed in the main process. However, the display control process may be executed in the timer interrupt process.

  In the display control process, the display control CPU 101 first executes a command analysis process (S324) for analyzing the received display control command, and a counter update process for updating the count value of the counter for generating a random number (S325). . Then, the display control CPU 101 executes display control process processing (S326). In the display control process process, a process corresponding to the current control state is selected and executed from among the processes corresponding to the control state.

  Next, the display control CPU 101 checks whether or not a V blank interrupt, which is a display rewrite timing on the variable display device 9, has occurred (S327). The presence or absence of the occurrence of the V blank interrupt is confirmed based on an interrupt signal (INT signal) output from the VDP 109 at the start of the V blank. The V blank is the display of the image developed in the display area (not shown) of the VRAM on the display screen of the variable display device 9, and then the image developed next in the display area of the VRAM is displayed on the variable display device 9. This is the period until display starts on the display screen. The VDP 109 outputs an interrupt signal to the display control CPU 101 at the start of the V blank and issues a V blank interrupt. For example, when an image of 30 frames is displayed per second, a V blank interrupt is applied approximately every 33 ms.

  The display control CPU 101 includes an interrupt terminal (INT terminal) for receiving an interrupt signal from the VDP 109. When the input level of the interrupt terminal falls to a low level, the display control CPU 101 detects the occurrence of a V blank interrupt as an external interrupt. For example, as shown in FIG. 62, when the display control CPU 101 detects the occurrence of the V blank interrupt, it sets a flag indicating the presence of the V blank interrupt in the register (S331).

  When there is a V blank interrupt, the display control CPU 101 executes an image development instruction control process as an interrupt process (S328). In the image expansion instruction control process, the display control CPU 101 executes control for instructing the VDP 109 to expand the image data to be displayed on the display screen of the variable display device 9 to the display area of the VRAM. Note that the VDP 109 expands image data in the display area of the VRAM in accordance with an instruction from the display control CPU 101. Then, the VDP 109 creates an image signal based on the image data in the display area, outputs the image signal to the variable display device 9, and displays an image frame on the display screen of the variable display device 9. As described above, since a V blank interrupt is generated every 33 ms, the image frame is updated once every 33 ms. After the image development instruction control process is executed, the display control CPU 101 performs a command transmission process for transmitting the lamp control command and the sound control command stored in the command transmission buffer to the lamp control board 35 and the sound control board 70, respectively. Execute (S329). The command transmission process is also executed every 33 ms as a process corresponding to the V blank interrupt.

  When there is no V blank interrupt, or after executing the command transmission process, the process returns to the process of checking the timer interrupt flag in S702.

  In this embodiment, in the V blank interrupt processing, only flag setting (setting with V blank interrupt) is performed, and specific image development instruction control processing and command transmission processing are executed in the main processing. The image development instruction control process and the command transmission process may be executed by an interrupt process.

  FIG. 63 is a flowchart showing command analysis processing (S324) in the main processing shown in FIG. In the command analysis process, the display control CPU 101 first checks whether or not a reception command (display control command from the game control means) is stored in a command reception buffer provided in the RAM (S341). If no received command is stored, the process ends. When the reception command is stored in the command reception buffer, the display control CPU 101 reads the reception command from the command reception buffer (S342).

  Next, the display control CPU 101 determines whether or not the read reception command is an error occurrence notification command (S343). If the received command is an error occurrence notification command, the following error occurrence notification process is executed (S344).

  For example, as the error occurrence notification process, the display control CPU 101 first sets an error notification execution flag indicating that the error occurrence notification process is being executed. When the error notification execution flag is set, the flag is first checked in the display control process (S326), the image development instruction control process (S328), and the like, and the execution of these processes is stopped. Further, when the display control CPU 101 is currently controlling image display such as variable display on the VDP 109, the display control CPU 101 saves (backs up) the current control state in a predetermined area of the RAM. Then, the display control CPU 101 uses the VDP 109 to display error data in the display area of the VRAM in order to display an error display on the display screen of the variable display device 9 based on the received error occurrence notification command. Executes the control for instructing the deployment of

  Further, when the display control CPU 101 blinks a lamp / LED or sounds a sound effect from the speaker 27 in order to notify the player of the occurrence of an error state, a lamp control command for designating an error occurrence notification. (See FIG. 67) and a sound control command (see FIG. 68) are transmitted to the lamp control board 35 and the sound control board 70, respectively. When the lamp control CPU 351 or the sound control CPU 701 receives a lamp control command or a sound control command for specifying an error occurrence notification, the lamp / LED on / off control and the sound output control from the speaker 27 are executed. In such a case, the control is stopped and the current control state is stored in a predetermined area of the RAM. Then, the lamp control CPU 351 and the sound control CPU 701 execute lamp / LED on / off control and sound output control from the speaker 27 for notifying the occurrence of an error state based on the received control command.

  Next, if the received reception command is not an error occurrence notification command, the display control CPU 101 determines whether the reception command is an error release notification command (S345). If the received command is an error release notification command, the following error occurrence notification release processing is executed (S346).

  For example, as the error occurrence notification cancellation processing, the display control CPU 101 erases the error display displayed on the display screen of the variable display device 9 and changes based on the control state stored in a predetermined area of the RAM. In order to restart the image display from the display state before the error display is performed on the display device 9, control is performed to instruct the VDP 109 to expand the image data in the display area of the VRAM. Further, the display control CPU 101 blinks a lamp / LED or sounds a sound effect from the speaker 27 in order to notify the player of the occurrence of an error state. (See FIG. 67) and a sound control command (see FIG. 68) are transmitted to the lamp control board 35 and the sound control board 70, respectively. When the lamp control CPU 351 receives the lamp control command for specifying the error cancellation notification, the lamp control LED is turned off and the error occurrence notification process is executed based on the control state stored in a predetermined area of the RAM. The lamp / LED lighting / extinguishing control is executed from the previous control state. In addition, when the sound control CPU 701 receives the sound control command for designating the error cancellation notification, the sound control CPU 701 stops the sound output from the speaker 27 and performs error occurrence notification processing based on the control state stored in a predetermined area of the RAM. The sound output control of the speaker 27 is executed from the control state before execution. Further, the display control CPU 101 resets the error notification execution flag. When the error notification execution flag is reset, the display control process (S326), the image expansion instruction control (S328), and the like are resumed.

  If the received command is neither an error occurrence notification command nor an error release notification command, the display control CPU 101 sends the lamp control command and the sound control command corresponding to the read reception command to the lamp control board 35 and the voice control board 70 (frame side), respectively. It is confirmed whether or not it is necessary to transmit to the production control board) (S347). Here, a gate passing memory number lamp designation command (C2XX (H)), a prize ball payout confirmation designation command (C300 (H)), a ball-with-lamp designation command (C400 (H)), and a piece of a ball shown in FIG. The middle lamp designation command (C401 (H)) is a command used only for lamp control, and it is determined that it is necessary to transmit it to the lamp control board 35 as it is. In addition, the variation pattern designation commands (8000 (H) to 8026 (H)) shown in FIG. 35 are commands used for display control and also for lamp control and sound control. When a corresponding lamp control command or sound control command (in this embodiment, a display control command such as a change pattern designation is directly used as a lamp control command or sound control command) needs to be transmitted to the lamp control board 35 or the voice control board 70. To be judged. If it is determined that it is necessary to transmit the lamp control board 35 or the voice control board 70, the display control CPU 101 stores the control command read from the command reception buffer in the command transmission buffer (S348). Then, the write pointer is incremented by 1 (S349). Thereafter, processing corresponding to the received command is performed (S350), and the process returns to S341.

  The process according to the received command is, for example, a process of storing the specified symbol in the stop symbol storage area (RAM) if the received command is a symbol-designated display control command. If it is a display control command, this is a process of setting a variation pattern in a predetermined area (RAM: internal RAM or external RAM of the display control CPU 101) and setting a flag indicating that the variation pattern designation has been received. Is the normal symbol variation pattern designation display control command, the normal symbol variation pattern is set in a predetermined area (RAM: internal RAM or external RAM of the display control CPU 101) and the normal symbol variation pattern designation is received. The received command is the start winning memory number designation command. Lever, a process of storing start winning storage number indicated by the EXT data, a process of setting the command reception flag corresponding for other received command. The display control CPU 101 increments the start memory display area 18 for changing the display color by one when the start winning memory number is incremented by one.

  The lamp control command and the sound control command set in the command transmission buffer are transmitted to the lamp control board 35 and the voice control board 70 in the command transmission process (S329).

  FIG. 64 is a flowchart showing the display control process (S326) in the main process shown in FIG. In the display control process, any one of S900 to S906 is performed according to the value of the display control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (S900): It is confirmed whether or not an effect control command (variation pattern command) capable of specifying the fluctuation time is received by the command reception interrupt process. Specifically, it is confirmed whether or not a flag (variation pattern reception flag) indicating that a variation pattern command has been received is set. The variation pattern reception flag is set when it is confirmed by command analysis processing that a variation pattern designation display control command has been received (S326).

  Preliminary selection processing (S901): Using a random number for determination of the determination, whether or not to perform the notification effect (background notification) and the type of the notification effect when it is performed are determined.

  All symbol variation start processing (S902): Control is performed so that variation of the left and right middle symbols is started.

  Symbol variation processing (S903): Controls the switching timing of each variation state (variation speed) constituting the variation pattern, and monitors the end of the variation time. Further, stop control of the left and right symbols is performed.

  All symbol stop waiting setting processing (S904): When an effect control command for instructing all symbols to stop (effect control command for special symbol stop) is received at the end of the variation time, the symbol variation is stopped and the stop symbol (determined) Control to display symbols.

  Big hit display processing (S905): After the end of the fluctuation time, the control of the probability change big hit display or the normal big hit display is performed.

  Big hit game processing (S906): Control during the big hit game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds is performed.

  In this embodiment, the variable display device 9 can perform a notice effect by displaying characters or the like appearing in the background (parts other than the symbol display area). In the variable display device 9, for example, a notice effect by vibrating the background or changing the background image is also used. In this embodiment, such a notice effect is called an accessory notice. Also, a notice effect by displaying characters appearing in the background is called a background notice. The accessory announcement is determined in accordance with the symbol variation display pattern (variation pattern) in the variation display device 9. That is, when a change display according to a specific change pattern is executed, a specific accessory notice is performed. Since the variation pattern is determined by the game control means, it is determined by the game control means whether or not to perform the accessory announcement and which type of the accessory announcement. Then, whether or not to perform background notice and the type of background notice are determined by the display control means.

  FIG. 65 is an explanatory diagram illustrating an example of background notice executed in the variable display device 9. In this embodiment, the variable display device 9 can perform four types of notice effects (background notices 1 to 4) by displaying characters and the like appearing in the background. Hereinafter, when simply expressing “notice”, it means a background notice.

  FIG. 66 is a flowchart showing the advance notice selection process (S901) in the display control process shown in FIG. In the notice selection process, the display control CPU 101 first confirms whether or not a change pattern that does not perform the notice effect (background notice) is designated by the change pattern command received from the main board 31 (S911). If a variation pattern that does not perform the notice effect is designated, the process proceeds to S921.

  If it is determined in S911 that a change pattern that may cause a notice effect is designated, the display control CPU 101 reads the count value of the notice random number counter, and uses the read value as the notice determination random number value. (S912). Further, the notice selection table corresponding to the received display control command for specifying the variation pattern is selected (S913). The notice selection table is provided for each variation pattern, and is a table in which the presence / absence of the notice effect and the content of the notice effect are associated with the random number for determining the notice.

  Then, a notice designation value (a value that designates whether or not to execute the notice effect and the type of the notice effect) corresponding to the notice determination random number is acquired from the selected notice selection table (S914). Thereby, the presence / absence of execution of the notice effect and the type (type of image) of the notice effect are selected and determined. If it is decided to make a notice according to the obtained notice designation value (S915), a notice start time determination timer is started (S916). Further, a lamp control command and a sound control command corresponding to the type of notice to be executed are set in the command transmission buffer (S917). In this example, the write pointer is incremented by 1 after the command is set in the command transmission buffer. Thereafter, the value of the process flag is updated to a value corresponding to all symbol variation start processing (S921). The set lamp control command and sound control command are any one of E000 (H) to E003 (H) (see FIG. 67).

  In this embodiment, when the display control means receives the display control command designating the variation pattern from the main board 31, whether or not to perform the notice effect (background notice) independently, the kind of notice (type of image), and Is selected, and a lamp control command or a sound control command indicating the type of the selected notice effect is transmitted to the lamp control board 35 or the sound control board 70. The light emitter control means on the lamp control board 35 performs an effect by the lamp / LED corresponding to the selected notice effect in response to the reception of the lamp control command indicating the type of the notice effect. Further, the sound control means in the sound control board 70 performs an effect by sound output in response to reception of a sound control command indicating the type of the notice effect. Therefore, even when the display control means uniquely determines the notice type, the light emitter control means and the sound control means produce an effect synchronized with the notice effect by the image display executed by the display control means using the variable display device 9. It can be done easily.

  In addition, a lamp control command and a sound control command indicating the type of the notice effect are transmitted to the lamp control board 35 and the sound control board 70 by a command transmission process described later. Therefore, when the unique effect determining means included in the display control means mounted on the display control board 80 uniquely determines the effect contents, the lamp control command and the sound control command that can specify the determined effect contents are It is transmitted to the control board 35 and the voice control board 70.

  FIG. 67 is an explanatory diagram showing an example of the contents of a lamp control command sent from the display control board 80 to the lamp control board 35. The lamp control command also has a 2-byte configuration of MODE and EXT. A plurality of types of lamp control commands as shown below are stored in the lamp control command storage area set in the storage area of the ROM storing the control data provided on the display control board 80. In the example shown in FIG. 67, the command 80XX (H) (X = any value of 4 bits) corresponds to the effect content related to the variation pattern of the special symbol in the variation display device 9, that is, the display result derivation operation in the variation display device 9. This is a lamp control command that is designated during change, and designates a lamp / LED (light emitting means such as an effect lamp or LED) display control pattern.

  The command 9XXX (H) is a lamp control command for instructing a lamp / LED display control pattern which is not related to the change of the special symbol or the big hit game. Command 9400 (H) is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration. The command AXXX (H) is a lamp control command for instructing a lamp / LED display control pattern from the start of the jackpot game to the end of the jackpot game. When the light emitter control means receives the lamp control command described above from the display control board 80, it changes the lamp / LED display state in accordance with the contents shown in FIG.

  Command C100 (H) is a lamp control command for designating a lamp lighting pattern for notifying that an out-of-ball condition or a full tank error state has occurred. Since the command C100 (H) is a command for notifying the light emitter control means of occurrence of an error state, it is called an error occurrence notification command. The command C101 (H) is a lamp control command for designating stop of notification of occurrence of an error state by a lamp / LED. Since the command C101 (H) is a command for notifying the light emitter control means that the error state has been released, it is referred to as an error release notification command. Upon receiving the error occurrence notification command, the light emitter control means causes the lamp / LED to be turned on / off according to a predetermined lamp lighting pattern for notifying the occurrence of the error. When the light emitter control means receives the error release notification command, the light emitter control means stops lighting / extinguishing of the lamps / LEDs according to a predetermined lamp lighting pattern, and notifies the player of the cancellation of the error state.

  The command C2XX (H) is a lamp control command for instructing the number of lighting of the normal symbol start memory display 41. When the illuminant control means receives the command C2XX (H) from the display control means, the light emitter control means turns on the number of indicators designated by “XX (H)” in the normal symbol start memory display 41.

  The command C300 (H) is a lamp control command related to the display state of the prize ball lamp 51. When the light emitter control means receives the lamp control command of “C300 (H)”, the display state of the prize ball lamp 51 is set in advance as a display state when one prize ball is paid out (for example, 0). .. light up for a predetermined period such as 5 seconds). That is, the command C300 (H) is a command indicating that the light emitter (prize ball lamp 51) provided for notifying the player or the like that the prize ball has been paid out is controlled.

  Commands C400 (H) and C401 (H) are lamp control commands relating to the display state of the bulb-out lamp 52. When the lamp control command “C400 (H)” is received, the luminous body control means sets the display state of the ball break lamp 52 to the display state with a ball, and when the lamp control command “C401 (H)” is received, The display state of the lamp 52 is set to the display state when the ball is out of sphere. That is, commands C400 (H) and C401 (H) are commands indicating control of a light emitter provided to notify a player or game store clerk that a supply ball has run out.

  The command “DXXX (H)” is a lamp control command created based on the sensor input to the display control board 80. Further, the command “EXXXX (H)” and the command “FXXX (H)” are lamp control commands that are independently generated by the display control unit in connection with the reception of the display control command from the game control unit.

  The command “E000 (H)” is a lamp control command transmitted when the background notice 1 is executed in the variable display device 9. The command “E001 (H)” is a lamp control command transmitted when the background notice 2 is executed in the variable display device 9. The command “E002 (H)” is a lamp control command transmitted when the background notice 3 is executed in the variable display device 9. The command “E003 (H)” is a lamp control command transmitted when the background notice 4 is executed in the variable display device 9. When the lamp control means receives the command “E0XX (H)”, the lamp control means performs lamp / LED lighting control according to the type of background notice designated by “XX (H)”. In “XX (H)”, various types of information such as the type of the character that appears, the appearance timing of the character, and the designation of the background are indicated for each bit (including a plurality of bits). Each bit data may indicate one information, or one information may be indicated by a combination of two or more bit data. Various types of information may also be indicated by each bit data constituting the MODE data.

  The display control means in the display control board 80 receives the display control command having the MODE data and the EXT data from the main board 31 except for the command “DXXX (H)” and the command “EXXX (H)”. The MODE data and the EXT data are transmitted as they are to the lamp control board 35 as a lamp control command. However, among the display control commands from the game control means, those not related to the light emitters controlled by the light emitter control means are not transmitted as lamp control commands. That is, the display control means may be used for control by the light emitter when it receives a display control command from the game control means (actually used for control by the light emitter, flag setting, etc.) The lamp control command corresponding to the display control command received from the game control means is transmitted only when it is not.

  FIG. 68 is an explanatory diagram showing an example of the contents of a sound control command sent from the display control board 80 to the voice control board 70. A plurality of types of sound control commands as shown below are stored in the sound control command storage area set in the storage area of the ROM storing control data provided on the display control board 80. The sound control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 68, the command 80XX (H) (X = any value of 4 bits) corresponds to the effect pattern related to the variation pattern of the special symbol in the variation display device 9, that is, the display result derivation operation in the variation display device 9. This is a sound control command that is designated during variation for designating a sound generation pattern from the speaker 27 that has been selected.

  Command AXXX (H) is a sound control command for instructing a sound generation pattern from the start of the big hit game to the end of the big hit game. When the sound control means receives the above-described sound control command from the display control board 80, the sound control means changes the sound output state of the speaker 27 according to the contents shown in FIG.

  Command C100 (H) is a sound control command for designating a sound generation pattern for notifying that an error condition such as a ball break or full tank has occurred. Since the command C100 (H) is a command for notifying the sound control means of occurrence of an error state, it is referred to as an error occurrence notification command. Command C101 (H) is a sound control command for designating stop of notification of occurrence of an error state by the speaker 27. Since the command C101 (H) is a command for notifying the sound control means that the error state has been released, it is referred to as an error release notification command. When receiving the error occurrence notification command, the sound control means causes the speaker 27 to output sound according to a predetermined sound generation pattern for notifying the occurrence of the error. Then, when receiving the error release notification command, the sound control means stops the sound output from the speaker 27 according to a predetermined sound generation pattern, and notifies the player of the release of the error state.

  The command “DXXX (H)” is a sound control command created based on the sensor input to the display control board 80. The command “EXXXX (H)” is a sound control command generated independently by the display control means in connection with the reception of the display control command from the game control means.

  The command “E000 (H)” is a sound control command transmitted when the background notice 1 is executed in the variable display device 9. The command “E001 (H)” is a sound control command transmitted when the background notice 2 is executed in the variable display device 9. The command “E002 (H)” is a sound control command transmitted when the background notice 3 is executed in the variable display device 9. The command “E003 (H)” is a sound control command transmitted when the background notice 4 is executed in the variable display device 9. When the sound control means receives the command “E0XX (H)”, the sound control means performs sound generation control corresponding to the type of background notice specified by “XX (H)”.

  The display control means in the display control board 80 receives the display control command having the MODE data and the EXT data from the main board 31 except for the command “DXXX (H)” and the command “EXXX (H)”. The MODE data and the EXT data are transmitted to the sound control board 70 as sound control commands as they are. However, among the display control commands from the game control means, those not related to the speaker 27 controlled by the sound control means are not transmitted as sound control commands. In other words, when the display control means receives a display control command from the game control means, the display control means may be used for control by the sound output means (speaker 27) (for control by the sound output means, flag setting, etc.) The sound control command corresponding to the display control command received from the game control means is transmitted only when it is actually used.

  In this embodiment, the command “DXXX (H)” and the command “EXXXX (H)” are always transmitted to both the light emitter control means and the sound control means. Some may be transmitted only to either the control means or the sound control means.

  Hereinafter, transmission of the lamp control command and the sound control command will be described. Note that a command transmission buffer is provided in a predetermined area of the RAM provided in the display control board 80. The command transmission buffer temporarily stores lamp control commands and sound control commands (specifically, 2-byte command data) transmitted to the light emitter control means and the sound control means. In the command transmission buffer, the storage destination of the lamp control command and the sound control command is specified by the write pointer, and the read destination is specified by the read pointer.

  FIG. 69 is a flowchart showing command transmission processing (S329) in the main processing shown in FIG. In the command transmission process, the display control CPU 101 first checks whether or not an untransmitted lamp control command or sound control command (specifically, 2-byte command data) is stored in the command transmission buffer (S351). . Whether the untransmitted lamp control command and sound control command are stored can be confirmed by the writing pointer and the reading pointer. If the two match, an untransmitted control command is not stored. If an unsent control command is not stored, the process ends.

  If an untransmitted control command is stored, the control command is read from the area indicated by the read pointer in the command transmission buffer (S352), and the first byte of the read control command is set as output data ( S353). Also, an output port address for outputting the command data of the control command is set as an output destination (S354).

  FIG. 70 is a flowchart illustrating a configuration example of a command transmission routine. In the command transmission routine, the display control CPU 101 sets output data to an output port designated as an output destination (S371). Then, the STB signal is turned on (S372).

  Next, M is set to a monitoring number counter for monitoring whether the ACK signal is turned on (S373). The value of M corresponds to a value that has a margin in processing time until the light emitter control means and the sound control means turn on the ACK signal in response to the STB signal. Then, the state of the ACK signal is confirmed while decrementing the value of the monitoring number counter (S374, S375).

  If the value of the monitoring number counter becomes 0 before the ACK signal is turned on (S376), a value indicating "abnormal" is set as a return code (S377), and the process is terminated. The return code is set in a predetermined register.

  If the ACK signal is turned on before the value of the monitoring number counter becomes 0, the STB signal is turned off (S378). Then, M (which may be different from the value used in S373) is set in the monitoring number counter for monitoring the ACK signal being turned off (S379). Next, the state of the ACK signal is confirmed while decrementing the value of the monitoring number counter (S380, S381). If the value of the monitoring number counter becomes 0 before the ACK signal is turned off (S382), a value indicating "abnormal" is set as a return code (S383), and the process is terminated. If the ACK signal is turned off before the value of the monitoring number counter becomes 0, a value indicating “normal” is set as a return code (S384), and the process ends.

  Through the command transmission routine as described above, transmission of one byte of the command data of the lamp control command or the sound control command is completed.

  When the command transmission routine is completed, the display control CPU 101 performs the processing from S356 onward in order to transmit the second byte of the received command to the lamp control board 35 and the voice control board 70. If the command transmission routine is not normally completed (if the return code is “abnormal”), for example, the display indicating “abnormal” is performed on the variable display device 9 to interrupt the operation.

  In S356, the display control CPU 101 sets the second byte of the control command as output data. Also, an output port address for outputting the command data of the control command is set as an output destination (S357). Then, the command transmission routine is called (S358). When the command transmission routine ends, the read pointer is incremented by 1 (S359), and the process returns to S351. If the command transmission routine is not normally completed (if the return code is “abnormal”), for example, the display indicating “abnormal” is performed on the variable display device 9 to interrupt the operation.

  The command transmission routine as described above completes the transmission of the command data for the lamp control command and the sound control command.

  Next, operations of the control boards 35 and 70 that perform control based on commands from the display control board 80 will be described. FIG. 71 is a flowchart showing a main process executed by the lamp control CPU 351 constituting the light emitter control means mounted on the lamp control board 35. In the main process, the lamp control CPU 351 first executes an initialization process for initializing a register, a RAM including a work area, an output port, and the like (S401). Next, a command reception process (S402), which is a process for receiving a lamp control command from the display control board 80, and a process for analyzing the received lamp control command (S403: command analysis process).

  Thereafter, the lamp control CPU 351 proceeds to a loop process for monitoring the timer interrupt flag (S404). As shown in FIG. 72, when a timer interrupt occurs, the lamp control CPU 351 sets a timer interrupt flag (S411). If the timer interrupt flag is set in the main process, the lamp control CPU 351 clears the flag (S405) and performs a lamp process update process (S406).

  In this embodiment, the lighting pattern of the lamp / LED that is controlled to blink according to the progress of the game is controlled according to the lamp data as shown in FIG. The lamp data is stored in the ROM, and is prepared for each type of control pattern (display control means corresponding to the lamp control command and the production status for designating the lamp lighting pattern when the special symbol is changed as shown in FIG. 67. (It is prepared for each lamp control command related to other game effects sent out from the player. Therefore, it is prepared for each notice type when performing the notice effect).

  For example, when the lamp control command received from the display control board 80 is 8000 (variation pattern designation # 1), data (4 bytes) corresponding to 80 (H) in the command upper byte table is referred to. The upper 2 bytes of the data is an address storing a process when a lamp control command whose upper byte is 80 (H) is received. Then, as shown in FIG. 74, in the processing, the data of the lamp data selection table indicated by the sum of the contents of the lower 2 bytes in the data of the command upper byte table and the EXT data of the received lamp control command is specified. Is done. Therefore, the lower 2 bytes in the command upper byte table referred to when the upper byte of the received lamp control command is 80 (H) corresponds to the head address of the lamp data selection table related to the variation pattern designation.

  In the lamp data, data indicating that the lamp / LED is turned on or off and data indicating a lighting or extinguishing period (process timer value) are set. That is, data indicating the lighting pattern of the light emitter is stored in the lamp control data area.

  In the ramp process update process (S406), a timer value initially set to a value corresponding to the process timer value is subtracted, and when the timer times out, the data set at the next address in the ramp data is set. Accordingly, the lamp / LED is determined to be turned off or turned on, and a process timer value corresponding to the determination result is set in the timer. Further, since the process timer value is set to the timer, it is the time of switching on / off, so that a signal for turning on / off the lamp / LED is output to the corresponding output port.

  FIG. 75 is a flowchart showing command reception interrupt processing. The STB signal indicating that the lamp control command is output from the display control board 80 is input to the interrupt terminal of the lamp control CPU 351. When the STB signal changes to, for example, a low level, the lamp control CPU 351 is interrupted, and a command reception interrupt process is executed. In the command reception interrupt process, the lamp control CPU 351 sets a command reception interrupt flag (S422).

  FIG. 76 is a flowchart showing command reception processing in the main processing shown in FIG. In the command reception process, the lamp control CPU 351 checks whether or not a command reception flag is set (S431). If not set, the process is terminated. When the command reception flag is set, the command reception flag is reset (S432), and it is confirmed whether or not the STB signal is surely turned on via the input port (S433). If the STB signal is not on, the process is terminated.

  If the STB signal is on, a lamp control command (specifically, 1 byte of 2-byte command data) is input via the input port and stored in a command reception buffer formed in the RAM ( S434). Then, the ACK signal is turned on (S435). Next, when the STB signal is turned off (S436), the ACK signal is turned off (S437). In addition, when performing the process of S436, if the STB signal is not turned off even after a predetermined time has elapsed, a notification may be made using a predetermined lamp or LED.

  Through the processing as described above, the lamp control command is received, and the received lamp control command is stored in the command reception buffer. In this embodiment, since the ramp control command has a 2-byte structure, when an interrupt based on the STB signal is generated twice and the processes of S432 to S437 are executed twice, One lamp control command is stored in the command reception buffer. The command reception buffer is configured in the same manner as the command reception buffer included in the display control unit mounted on the display control board 80, for example. In this embodiment, only the command reception flag is set in the command reception interrupt process, and the reception process is performed in the command reception process outside the interrupt process, but the command reception process is also performed in the command reception interrupt. You may comprise so that it may carry out.

  The lamp control command stored in the command reception buffer is analyzed in the command analysis process (S403) in the main process, and the lamp process update process (S406) is executed according to the analysis result. In the command analysis process (S403), the same processes as those in S341, S342, and S346 are executed among the processes shown in FIG. 63 described above.

  When the lamp control means receives the prize ball payout confirmation designation command transmitted from the display control means, the lamp control means performs a control for lighting the prize ball lamp 51 for a predetermined period as a process according to the received command. Accordingly, it is possible to notify the player that the prize ball has been paid out. When the lamp control means receives the error occurrence notification command transmitted from the display control means, the lamp control means performs a control to turn on / off a predetermined lamp / LED according to a specified lamp lighting pattern as a process according to the received command. When the error cancellation notification command transmitted from the display control means is received, the control for turning on / off the predetermined lamp / LED is stopped. Thereby, it is possible to notify the player that an error such as a ball break has occurred in the payout control means.

  FIG. 77 is a flowchart showing a main process executed by the sound control CPU 701 constituting the sound control means mounted on the sound control board 70. In the main process, the sound control CPU 701 first executes an initialization process for initializing a register, a RAM including a work area, an output port, and the like (S491). Next, a command reception process (S492), which is a process for receiving a sound control command from the display control board 80, and a process for analyzing the received sound control command are performed (S493: command analysis process). In the command reception process and the command analysis process, the same process as the process in the light emitter control means described above is executed, and thus detailed description thereof is omitted here.

  Thereafter, the sound control CPU 701 proceeds to a loop process for monitoring a timer interrupt flag (S494). As shown in FIG. 78, when a timer interrupt occurs, the sound control CPU 351 sets a timer interrupt flag (S497). If the timer interrupt flag is set in the main process, the sound control CPU 701 clears the flag (S495) and performs a sound process update process (S496).

  The sound output pattern from the speaker 27 controlled according to the progress of the game is controlled according to sound data as shown in FIG. The sound data is stored in the ROM, and is prepared for each type of control pattern (display control means according to the sound control command and the production status for designating the sound generation pattern when the special symbol shown in FIG. 68 changes) Are prepared for each sound control command related to other effects sent out from (ie, prepared for each notice type in the case of performing a notice effect).

  In the sound process update process (S496), a process for subtracting a timer value, which is initialized to a value corresponding to the process timer value, is performed. When the timer times out, the data set at the next address in the audio data is added. Accordingly, it is determined to change to the output voice, and a process timer value corresponding to the determination result is set in the timer. Also, since the output voice is switched when the process timer value is set in the timer, a new output is sent to the voice synthesis circuit 703 via the output port for outputting data to the voice synthesis circuit 703. Data corresponding to audio is output.

  When the sound control means receives the error occurrence notification command transmitted from the display control means, the sound control means performs sound output control of the speaker 27 according to the designated sound generation pattern as a process corresponding to the received command, and the display control means. When the error release notification command transmitted from is received, the audio output control of the speaker 27 is stopped. Thereby, it is possible to notify the player that an error such as a ball break has occurred in the payout control means.

  FIG. 80 is a timing diagram showing transmission timings of display control commands related to symbol variation display. The game control means transmits a display control command designating a variation pattern when the variation display is started. When the display control command for specifying the variation pattern is received, the display control means starts a variation display effect based on the received command, and transmits a ramp control command for specifying the variation pattern and a sound control command for specifying the variation pattern. When the display control means decides to perform the notice effect (Y in S915), the lamp control command and sound control command for specifying the content of the notice effect (command E000 (H shown in FIGS. 67 and 68) ) To any of commands E002 (H)).

  When the lamp control command designating the variation pattern is received, the light emitter control means starts a light emitter effect based on the received command. In addition, when the light emitter control means receives a lamp control command designating the content of the notice effect, the light emitter effect is executed with a lighting pattern corresponding to the received command.

  When the sound control command designating the variation pattern is received, the sound control means starts a sound output effect based on the received command. In addition, when the sound control means receives the sound control command that specifies the content of the notice effect, the sound control effect is executed with a sound generation pattern corresponding to the received command.

  When the game control means transmits the display control command for designating the variation pattern, the game control means subsequently transmits display control commands for designating the left symbol, the middle symbol, and the right symbol. When the variation time (variation display period) ends, the game control means displays a special symbol stop (8F00 (H)) display control command for instructing the stop of all symbols in order to finally stop (determine) the left and right middle symbols. Send. Note that a command to stop all symbols is not transmitted to the light emitter control means or the sound control means, but the production control period is determined based on the command for designating the variation pattern. The light emitter effect and the sound output effect are also finished within the variable display effect period.

  As described above, the payout number count switch 301 for detecting the payout of the game ball without distinguishing the winning ball and the lending ball is provided, and the detection output of the payout number count switch 301 is input only to the payout control means, and the payout control means. However, when a detection signal from the payout number count switch 301 is input, it is determined whether a payout of a prize ball or a payout of a lending ball is detected. Since the count signal is transmitted to the game control means, the game control means can recognize the unpaid number of prize balls, and lend out a prize ball with one payout number count switch 301. Since the ball payout is also detected, the number of parts is reduced, and the cost of the pachinko gaming machine 1 can be reduced.

  Further, in the above-described embodiment, the payout control means detects the winning ball payout when the detection signal from the payout number count switch 301 is input even in the error state where the payout of the game ball is stopped. When it is determined that there is a prize ball, the prize ball count signal is transmitted to the game control means, so that a prize ball count signal indicating that the payout of the prize ball has been detected can be reliably transmitted to the game control means. .

  In the above-described embodiment, the payout control means transmits a payout error signal to the game control means when the bottom pan full or an out of ball error occurs (turns on). It is possible to make the game control means recognize that an error relating to the payout of the ball has occurred.

  In the embodiment described above, the game control means transmits an error occurrence notification command for notifying the occurrence of an error to the display control means in response to receiving the payout error signal from the payout control means. Thus, it is possible to cause the display control means to perform a process for notifying the occurrence of an error, and to allow the player to easily recognize the occurrence of the error. The game control means also transmits an error occurrence notification command to the lamp control means and the sound control means via the display control means, so that a process for notifying the lamp control means and the sound control means of the occurrence of the error is performed. The occurrence of an error can be recognized more easily by the player. Note that the notification of the occurrence of an error may be performed by at least one of the display control unit, the lamp control unit, and the sound control unit, and it is not necessary for all the control units to perform the notification.

  Further, in the above-described embodiment, when the game control means receives a payout error signal from the payout control means, it is configured not to send a payout command signal to the payout control means. It is possible to reduce the possibility that the payout command signal is missed in the payout control means. Even when the game control means receives a payout error signal from the payout control means, and there is an unpaid prize ball, it is configured to send a payout command signal to the payout control means. Can prevent the execution of the prize ball payout process from being delayed when the error is canceled in the payout control means.

  In the embodiment described above, the payout control means receives the detection signal from the payout number count switch 301 when the payout ball is not paid out or the lending ball is not paid out, and the game ball that has been paid out is awarded. Since the award ball count signal is transmitted to the game control means as being a ball, the award ball count signal can be transmitted to the game control means even when a non-regular game ball is paid out to the game control means. Appropriate processing can be performed.

  In the above-described embodiment, when the game control means transmits a payout command signal, a subtraction process is performed to subtract the payout number specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer. Since it is configured to perform, it is possible to prevent the designation of payout from being executed again for a prize ball for which payout has already been designated. Further, since the number of payouts specified by the payout command signal is subtracted regardless of whether or not the prize ball count signal is received, the prize ball number subtraction process stored in the total prize ball number storage buffer is executed. Therefore, it is possible to reduce the control burden of the skill control means.

  In the above-described embodiment, after the payout command signal is transmitted as described above, the total winning ball number storage buffer is used regardless of whether or not a signal indicating completion of the payout process from the payout control board 37 is received. Although the configuration example for executing the subtraction processing of the stored number of prize balls has been described above, the present invention is not limited to this, and after the game control means transmits a payout command signal, in response to receiving the prize ball count signal, A configuration example may be adopted in which a subtraction process for subtracting the number of payouts confirmed to have been actually paid out from the number of prize balls stored in the total number of winning balls storage buffer may be adopted. Each of these configuration examples is an example of an embodiment in which a prize ball count signal is transmitted from the payout control microcomputer to the game control microcomputer, and is treated as a representative embodiment regardless of whether the explanation is made earlier or later. Is called.

  When subtracting the number of prize balls stored in the total prize ball number storage buffer in response to reception of the prize ball count signal, the game control means performs the prize ball control signal in the prize ball control process (see FIG. 28). Is transmitted (S255), instead of performing the process (S256, S263, 264) of counting the execution time of the payout process, a process of counting the number of times the prize ball count signal is received is performed. Then, when the number of received prize ball count signals becomes the number of prize balls to be paid specified by the payout command signal, the number of payouts specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer. Is subtracted (S265). If comprised as mentioned above, it will become possible to manage reliably the number of unpaid prize balls in the game control means.

  FIG. 81 is a flowchart showing the award ball waiting process 2 in the above example. In this example, the CPU 56 checks whether or not a prize ball count signal is received in the prize ball waiting process 2 (S267). When the prize ball count signal is received, the payout confirmation number is incremented by 1 (S268). The number of payout confirmations is the number of prize balls whose payout has been confirmed after the payout command signal transmitted in the prize ball transmission process (see FIG. 30) is output. For example, the number of payout confirmations stored in the RAM 55 is stored. Stored in the area. Next, the CPU 56 compares the number of payout confirmations with the number of payouts specified by the payout command signal (the content of the prize ball number buffer, that is, the number of prize ball payouts commanded to the payout control means). When it is confirmed that the number of payouts designated by the player is reached (Y in S269), it is determined that the number of prize balls paid out for the number instructed to the payout control means has been completed. The contents of the sphere number buffer are subtracted (S265). Then, the value of the prize ball process code is set to 3 (S266), and the process is terminated.

  After confirming that the number of prize balls paid out for the number instructed to the payout control means is completed and finishing the process of subtracting the contents of the prize ball number buffer, the CPU 56 indicates that the contents of the total prize ball number storage buffer is 0. If not, a new payout command signal designating the number of payouts for the next prize ball is transmitted.

  In the above example, after confirming the payout of the designated number of prize balls, the number of prize balls stored in the total prize ball number storage buffer is subtracted together. In the process of counting the number of receptions, each time a prize ball count signal is received, the number of receptions is incremented by 1 and the number of prize balls stored in the total prize ball number storage buffer is decremented by 1. Also good. If the configuration is such that the number of unpaid prize balls is managed by bi-directional communication between the game control means and the payout control means as described above, the game control means based on the prize ball count signal from the payout control means. It is possible to accurately manage the number of unpaid prize balls. That is, if the unpaid number of prize balls is not managed using the prize ball count signal, the management of the number of unpaid prize balls is performed by unidirectional communication. There is a problem that the number of unpaid prize balls ascertained in the means is not always accurate. As described above, if it is configured to manage the number of unpaid prize balls in the game control means by two-way communication, it is possible to subtract the unpaid number when the prize balls are actually paid out. It becomes possible to accurately manage the number of unpaid prize balls.

  Further, in the above-described embodiment, based on the fact that the low-level reset signal from the power supply board 910 is input to the reset terminal of each effect control board 80, 35, 70, each effect control board 80, 35, The 70 microcomputers are configured to be system reset, respectively. However, based on the fact that a high level NAND output signal is input to the reset terminal of each production control board 80, 35, 70, each production control board 80, 35. , 70 are configured such that the system is reset, respectively, the output of the watchdog timer circuit and the reset signal from the power supply board 910 are partially or entirely on each of the effect control boards 80, 35, 70. The NAND output may be input to the reset terminal.

  FIG. 82 shows that in the lamp control board 35 and the display control board 80, the NAND output of the output of the watchdog timer circuit and the reset signal is input to the reset terminal, and the high-level NAND output signal is input to the reset terminal. It is a block diagram which shows the example at the time of setting it as the structure by which the microcomputer of each production | presentation control board 80 and 35 is each system-reset based on.

  In this example, as shown in FIG. 82, the lamp control board 35 is provided with a counter (watchdog timer circuit) 357 that functions as a watchdog timer. The watchdog timer circuit 357 counts the output pulse of the oscillation circuit 359, and when it counts up, generates a high-level pulse as a Q output. The pulse signal is logically inverted by an inverting circuit 358 and input to the NAND circuit 360. The reset signal from the power supply substrate 910 and the Q output from the watchdog timer circuit 357 are input to the input terminal of the NAND circuit 360. An output signal (NAND output signal) of the NAND circuit 360 is supplied to a reset terminal of the lamp control CPU 351. The lamp control CPU 351 may be set to output a system clock or a divided clock thereof, and the clock may be used as an input clock signal of the watchdog timer circuit 357.

  In addition, when the lamp control CPU 351 performs the light emitter control, a clear pulse (a pulse that is periodically turned on) is periodically supplied to the watchdog timer circuit 357. The output period of the clear pulse is shorter than the time until the watchdog timer circuit 357 counts up. Accordingly, no pulse appears in the Q output of the watchdog timer circuit 357 when the lamp control CPU 351 is performing normal light emitter control.

  In this example, as shown in FIG. 82, the display control board 80 is provided with a counter (watchdog timer circuit) 111 that functions as a watchdog timer. The watchdog timer circuit 111 counts the output pulse of the oscillation circuit 113, and when it counts up, generates a high-level pulse as a Q output. The pulse signal is logically inverted by the inversion circuit 112 and input to the NAND circuit 114. A reset signal supplied from the power supply substrate 910 via the lamp control substrate 35 and a Q output from the watchdog timer circuit 111 are input to the input terminal of the NAND circuit 114. The output signal (NAND output signal) of the NAND circuit 114 is supplied to the reset terminal of the display control CPU 101. The display control CPU 101 may be set to output a system clock or a divided clock thereof, and the clock may be used as an input clock signal of the watchdog timer circuit 111.

  Note that when the display control CPU 101 is performing display control, a clear pulse (a pulse that is periodically turned on) is periodically supplied to the watchdog timer circuit 111. The output period of the clear pulse is shorter than the time until the watchdog timer circuit 111 counts up. Accordingly, no pulse appears in the Q output of the watchdog timer circuit 111 when the display control CPU 101 performs normal display control.

  In this example, NAND circuits 360 and 114 output high level NAND output signals in response to the reset signal becoming low level (on state). Further, in response to the Q output of the high level (ON state) signal from the watchdog timer circuits 357 and 111, the NAND circuits 360 and 114 output high level NAND output signals. When the high-level NAND output signal is input to the effect control CPUs 351, 101, the effect control CPUs 351, 101 are system reset. The voice control board 70 may be configured similarly.

  If comprised as mentioned above, it can prevent with a simple structure that a microcomputer (CPU 351,101,701 for presentation control) runs away. In addition, since the board configuration is simple, fraud such as mounting an illegal circuit on the boards 35, 70, 80 can be easily detected.

  In the above example, each production control board 80, 35, 70 equipped with a microcomputer that is reset based on the input of a high level signal to the reset terminal has been described as an example. In the above example, If an inverting circuit is provided on the output side of the NAND circuits 360 and 114, the effect control boards 80, 35, each having a microcomputer that is reset based on the low level signal input to the reset terminal. 70 can be applied.

  Further, in the above example, in order to reset the two systems of the low level reset signal from the power supply board 910 and the low level signal obtained by inverting the high level signal output from the watchdog timer circuits 357 and 111. These signals can be input to the microcomputer with a simple configuration.

  In the above example, the output signals of the NAND circuits 360 and 114 are input to the reset terminal of the microcomputer. However, the microcomputer to be reset based on the input of the low level signal to the reset terminal is used. Each mounted production control board 80, 35, 70 is provided with an OR circuit instead of the NAND circuits 360, 114, and a low level reset signal from the power supply board 910 and Q output from the watchdog timer circuits 357, 111 are output. The configuration may be such that when either the low level signal obtained by inverting the high level signal is input, the low level signal is output as the OR circuit output. Even in such a configuration, signals for resetting the two systems can be input to the microcomputer with a simple configuration.

The configuration in which the output signal of the NAND circuit is input to the reset terminal of the microcomputer based on the reset signal and the Q output of the watchdog timer circuit as described above includes the display control board 80, the audio control board 70, and the lamp. It may be provided on at least one of the control board 35 and the control board 35.
Next, main effects obtained by this embodiment will be described together.

  As shown in FIG. 5, a payout number count switch 301 is provided as a payout detection means commonly used for detection of award ball payout and lending ball payout, and payout control is performed using a detection signal of the payout number count switch 301. Further, as shown in S602 and S603 in FIG. 50, it is determined whether the detection signal corresponds to the detection of the payout of the game ball of the prize ball or the lending ball. When it is determined that the winning ball payout is detected, a winning ball count signal indicating that the winning ball has been detected is transmitted to the game control microcomputer as shown in S609c. Is done. Therefore, the detecting means for detecting the payout of the game ball is commonly used for grasping the number of payouts of the winning ball and the lending ball in the payout control microcomputer, and the payout control microcomputer and the game control microcomputer are used. Commonly used for grasping the payout of prize balls. Thereby, the number of parts related to the game ball payout such as the game ball payout detecting means can be reduced, and as a result, the manufacturing cost of the pachinko gaming machine 1 can be reduced. Further, as shown in S828a and S828b of FIG. 58, when it is determined that a special error such as a full tank error or a ball shortage error has occurred, a payout error signal indicating that the special error has occurred is displayed. Since it is transmitted from the payout control microcomputer to the game control microcomputer, the game control microcomputer can reliably grasp and manage the occurrence of the special error.

  As shown in S802 to S807 of FIG. 57, specific errors such as payout switch abnormality detection error 2, payout case error, and prize ball REQ signal error are paid out according to the operation of the error release switch 375. Since the error state is canceled on the condition that the control microcomputer has received the error cancellation signal, the attendant at the game hall can surely grasp and manage the occurrence of the specific error. In this way, the occurrence of a special error and a specific error is grasped and managed by the game control microcomputer and the game hall staff, so that the occurrence of the special error and the specific error can be reliably managed. This reliable management can prevent the player from being disadvantaged based on the occurrence of an error.

  Also, as the reset condition of the payout case error bit reset in S807 of FIG. 57, it is not set that the unpaid number counter has become 0, and the error cancel switch 375 has been turned on in S802 (error When the release switch 375 is turned on, an error recovery time is set, and an error due to a shortage of payouts such as a payout case error has occurred. In this case, even if an insufficient number of game balls are detected by the payout number counting switch 301, the error state is not released unless an error release signal is received in response to the operation of the error release switch 375. Will not be released automatically, and the staff at the amusement hall will generate and resolve errors due to insufficient payouts. Ri can be reliably ascertained.

  In addition, the error bit check is not executed in the information output process of FIG. 60 including the step of S837 for outputting the prize ball information signal, so that a predetermined error (various errors such as a payout case error and a full tank error) occurs. Even when it is determined that there is an error state, the prize ball information signal is output to the outside of the pachinko gaming machine 1 every time the number-of-payout counting switch 301 detects the payout of a predetermined number (for example, ten) of prize balls. Since it is transmitted, the number of prize balls paid out in all states including the error state can be grasped outside the pachinko gaming machine 1. Thereby, the number of award balls that have been paid out can be accurately grasped outside the pachinko gaming machine 1.

  In addition, since the error bit check is not executed in the prize ball lending control process of FIG. 50 including the step of row S604 for subtracting the number of prize balls not paid out, various errors such as predetermined error (payout case error, full tank error, etc.) are performed. Even when it is determined that an error) has occurred, every time it is determined that the payout detection signal corresponds to the detection of a prize ball, the number of prize balls not paid out is subtracted in S604. The payout control microcomputer can grasp the payout of prize balls in all states including the error state. Thereby, in the pachinko gaming machine 1, the payout of the prize ball can be accurately grasped. In addition, it is determined that the predetermined error as described above has occurred because the error bit check is not executed in the prize ball lending control process of FIG. 50 including the step of S609c for outputting the prize ball count signal. Sometimes, every time it is determined that the payout detection signal is in response to the detection of a prize ball, a prize ball count signal is transmitted, so that the payout of prize balls in all states including an error state is controlled by a game. It can be grasped in a microcomputer. Thereby, in the pachinko gaming machine 1, the payout of the prize ball can be accurately grasped.

  Further, as shown in S22b of FIG. 15 and the timing chart of FIG. 24, when the game control microcomputer receives the payout error signal, it is notified that a special error has occurred, so that the occurrence of the error is surely ensured. Can be confirmed.

  Also, in S246 of FIG. 29, when the payout error signal is in the ON state, control is performed so that the prize ball process code is not set to 1, so that the shift to the prize ball transmission process for transmitting the prize ball command is prevented. As a result, when the payout error signal is received, transmission of the prize ball command from the game control microcomputer to the payout control microcomputer is stopped, so that the prize ball command is transmitted despite an error relating to payout. It is possible to prevent such unnecessary processing from being performed.

  61. As shown in S327 to S329 in FIG. 61, the lamp control command and the sound control command are respectively sent to the light emitter control microcomputer and the flash control command in synchronization with the V blank interrupt timing which is the display rewrite timing on the variable display device 9. It is transmitted to the sound control microcomputer. For this reason, the control of the variable display device 9 and the control of the lamp and the voice control, respectively, such as the control timing of the other effect devices such as the lamp control and the voice control can be synchronized with the rewriting timing of the display on the variable display device 9. It is possible to prevent deviation from occurring in the timing.

  In addition, as shown in S911 to S917, the display control microcomputer performs an image display such as the presence / absence of the notice effect and the content of the notice effect in response to the reception of the display control command from the game control microcomputer. Choose your own. The display control microcomputer selects a lamp control command or a sound control command corresponding to the selected effect from a plurality of types of commands based on which effect is selected, and the lamp control board 35. Or to the voice control board 70. For this reason, since the selection of control content related to the game can be shared between the game control microcomputer and the display control microcomputer, the control burden on the game control microcomputer can be reduced.

  As shown in FIG. 82, a NAND circuit 360 provided on the lamp control board 35 includes a reset signal from the power supply monitoring circuit 920 on the power supply board 910 and a watchdog timer circuit 357 provided on the lamp control board 35. When any one of the Q output signals from is turned on, a system reset signal is input (on state) to the light emitter control microcomputer, so that the pachinko gaming machine 1 is turned on and emits light. When the body control microcomputer runs away, the light emitter control microcomputer can be system-reset based on the output signal of the NAND circuit 360. Even when such a configuration is adopted for the sound control board as described above, the same effect can be obtained for the sound control microcomputer.

  Further, as shown in FIGS. 6 and 82 and the like, the reset signal is not provided between the power supply board 910 and the lamp control board 35 and between the power supply board 910 and the sound control board 70 without using the display control board 80. Since the reset signal transmission path for transmitting the signal is provided, the power supply monitoring circuit 920 turns on the reset signal input to the other effect control board without going through the display control board 80. The configuration can be simplified.

  Further, as shown in FIG. 23, when the game control microcomputer receives the prize ball count signal, a prize ball payout confirmation designation command is transmitted to the display control board 80, whereby the prize ball lamp 51 causes the prize ball. Therefore, the payout of the prize ball can be easily confirmed from the outside of the pachinko gaming machine 1.

  In addition to the effects described above, the following effects can also be obtained.

  In the above-described embodiment, the game control means controls not to send a payout command signal while receiving the prize ball count signal from the payout control means, and the payout control means pays out from the game control means. Since the control is made so that the prize ball count signal is not transmitted during reception of the command signal, the payout command signal transmitted from the game control means to the payout control means and the payout control means are transmitted to the game control means. It is possible to prevent competition with the prize ball count signal. Therefore, in the payout control means and the game control means, it is possible to prevent the control signal (payout command signal, prize ball count signal) from being lost.

  The payout control means transmits a command acceptance signal indicating that the payout command signal transmitted from the game control means has been received to the game control means, and the game control means accepts the command received from the payout control means. When the signal is received, the winning ball number stored in the total winning ball number storage buffer may be subtracted. Here, the command acceptance signal corresponds to an acceptance confirmation signal for the payout command signal, and is also referred to as a prize ball BUSY signal. Even in such a configuration, the number of unpaid prize balls can be centrally managed by the game control means.

  In the embodiment described above, the game control means is configured to execute processing for turning on the prize ball lamp 51 in response to reception of the prize ball count signal. Even if it is not controlled by the control means (that is, the control means for receiving the detection signal from the payout number count switch 301), it is determined that the player has been awarded a prize ball or that the game ball that has been paid out is a prize ball. It becomes possible to notify the store clerk. In the above example, as a process for turning on the prize ball lamp 51, a process of transmitting a prize ball payout confirmation designation command to the display control board 80 is executed. Then, the display control board 80 transmits the received prize ball payout confirmation designation command to the lamp control board 35. When the prize ball payout confirmation designation command is received, the lamp control CPU 351 of the lamp control board 35 executes control for lighting the prize ball lamp 51 for a predetermined period. However, the game control means may control the prize ball lamp 51, and the game control means may execute a driving process for turning on the prize ball lamp 51 in response to reception of the prize ball count signal. . Further, it may be notified that a prize ball has been paid out by a light emitting body other than the prize ball lamp 51 or a display device.

  In the above-described embodiment, when the error bit is set due to the occurrence of a ball-out condition or a full-bottom-plate condition (S621), the process after S622 of the payout start waiting process (see FIG. 51) Is not executed, and the game ball payout process is not executed, so that it is possible to prevent the game ball payout process from being executed in an abnormal state. Therefore, it is possible to prevent a situation where the payout is not performed effectively.

  In the above-described embodiment, the display control means performs the process of receiving the first control signal from the game control means and the process of transmitting the second control signal to the other effect control means. It is supposed to be configured. In other words, since the sub-sub-board and the sub-sub-board are configured so that the control signal is transmitted from the sub-board to the sub-sub-board, the display control board 80 that is the sub-board is another effect control board ( The control contents can be instructed to the lamp control board 35 and the voice control board 70), and the control burden on the game control means can be reduced. An effect control board (lamp control board 35, audio control board 70) other than the display control board 80 may be a sub board.

  In the above-described embodiment, the game control unit and the payout control unit execute the power-off process (FIGS. 16 and 17) for saving the control state in response to the input of the power-off signal from the power supply board 910. The power supply is reduced because the system is reset in response to the input of the reset signal from the power supply board 910 when the power cut-off process is completed and the standby loop state is entered. When this is done, the control state can be stored in each of the game control means and the payout control means.

  In the above-described embodiment, the power supply board 910 is configured to transmit a reset signal to the sub-sub board (for example, the lamp control board 35) without passing through the sub-board (display control board 80). Therefore, the system reset timing in the sub-board and the sub-sub-board can be set to the same timing.

  In the above-described embodiment, the display control unit controls the image display device by rewriting the display image at predetermined timings based on the first control signal from the game control unit, and performs a plurality of effect controls. The means executes an effect corresponding to the variable display of the identification information based on the input control signal, and the display control means synchronizes the other effect control means with the rewrite timing of the display image in the image display device. Since the second control signal is transmitted, the synchronization of effects performed by the display control means and the other effect control means is prevented as much as possible.

  That is, a command transmission process (S329) based on a V blank interrupt executed every predetermined period (every 33 ms) is executed, and the display control means in the variable display device 9 with respect to the light emitter control means and the sound control means. Synchronously with the rewrite timing of the display image (this synchronized timing means the execution timing of the command transmission process (S329) executed at the special symbol rewrite timing that occurs every 33 ms. That is, it is executed every 33 ms. The execution timing of the command transmission process (S329) is called “synchronized timing.”) Since the lamp control command and the sound control command are output, the display control board 80, the lamp control board 35, and the voice control are configured. It is possible to prevent as much as possible a synchronization shift of effects performed with the substrate 70. For example, the operation timing of the moving image displayed on the variation display device 9, the audio output timing from the speaker 27, and the blinking timing of a light emitter such as a lamp are synchronized.

  Further, as described above, the lamp control command and the sound control command are rendered using the light emitter and the speaker 27 related to the varying display pattern executed based on the display control command (the effect corresponding to the variation display of the identification information). ) Since it is configured to include a command (effect pattern command (command 80XX (H)) indicating the contents, it is possible to prevent a synchronization shift of the effect related to the variable display.

  Further, as described above, when the display control unit instructs the lamp control board 35 and the voice control board 70 to produce the effect pattern, the command having the same configuration as the received variation pattern command (the command having the same MODE data and EXT data). ) (When the command transmitted to the lamp control board 35 or the voice control board 70 is received in the command analysis processing shown in FIG. 63 (Y in S343), the received command is set in the transmission buffer as it is. (S344), the command transmission process shown in FIG. 69 is transmitted to the lamp control board 35 and the voice control board 70), so that it is not necessary to execute a process for creating a new command. Control burden is reduced.

  In the above-described embodiment, the game control unit transmits a variation pattern command indicating the content of variation display of identification information to the display control unit, and the display control unit receives the variation pattern command. The second control signal (command indicating the content of the notice effect) indicating the content of the effect according to the received variation pattern command and the variation display of the identification information is transmitted to the other effect control means. The content of the effect indicated by the control signal is a content that is uniquely determined by the display control means based on the input variation pattern command, thereby reducing the control burden on the game control means. An effect in which the contents of the effects are synchronized can be executed by the display control means and the other effect control means.

  That is, since the display control means makes a decision regarding the notice effect by the notice selection process (see FIG. 66), and the lamp control command and the sound control command are uniquely set and transmitted by the process shown in S917. The control burden on the game control means is reduced.

  Further, as described above, since the STB signal, the command data, and the ACK signal are exchanged between the display control board 80 and the lamp control board 35 or the voice control board 70, the bidirectional communication is performed. Further, it is possible to prevent a recognition shift from occurring between the display control board 80 and the lamp control board 35 or the voice control board 70, and it is possible to eliminate the missing of the lamp control command and the sound control command.

  Further, as described above, the display control means, the lamp control means, and the sound control means start the effects related to the variable display based on the reception of the command (80XX (H)) indicating the effect pattern. Since it is comprised, the game control means which outputs an effect pattern command can manage the start timing of an effect.

  Further, as described above, the display control means immediately outputs (executes after receiving and analyzing) the lamp control command and the sound control command having the same configuration as the received display control command to the lamp control means and the sound control means. Since the command transmission process (output in S329) is configured, it is possible to prevent the synchronization of effects related to the variable display executed by the display control means, the lamp control means, and the sound control means, respectively. Can do.

  In addition, as described above, a command (for example, EXXXX (H)) uniquely created by the display control means is a plurality of types (for example, notice 1 to notice 4) prepared in advance as effects related to the variable display effect. Among them, since it is configured to include information indicating which of the effects to execute, it is possible to reduce the control burden of the game control means regarding the determination of the contents of the effects and to execute a wealth of effects. So you can improve the fun of the game.

  Moreover, although the command (for example, EXXXX (H)) used for the notice effect is used as a command that the display control unit independently creates, a command other than those may be created. For example, a sound control command for causing the speaker 27 to output a sound output pattern for notifying that a prize ball has been paid out may be created in response to receiving a prize ball payout confirmation designation command. . Such command creation processing is executed, for example, when it is confirmed in the command analysis processing (FIG. 63) that the received command is a prize ball payout confirmation designation command.

  Further, as described above, the display control command transmitted from the main board 31 to the display control board 80 is not used for the effect control in the display control board 80, and is directly applied to the lamp control board 35 and the voice control board 70. Since a command that can only be transmitted as a control command or a sound control command (that is, a command that is passed through in the display control board 80) is included, processing related to command transmission can be shared. Further, useless control is not performed on the display control board 80 by a command that only gives a control instruction from the light emitter or the speaker 27.

  Next, modifications and feature points of the embodiment described above are listed below.

  (1) In the above-described embodiment, the lamp control board 35 and the voice control board 70 are provided separately. However, a single board having the functions of the lamp control board 35 and the voice control board 70 may be provided. . In this case, the light emitter and the speaker 27 may be controlled by one microcomputer.

  (2) In the above-described embodiment, the lamp control board 35 is mounted with the lamp control CPU 351, and the sound control board 70 is mounted with the sound control CPU 701, and the lamp control CPU 351 and the sound control CPU 701 are The lamp control and the sound control were independently executed based on the lamp control command and the sound control command transmitted from the display control CPU 101, respectively. However, the present invention is not limited to such a configuration, and the lamp control board 351 and the sound control CPU 701 are not mounted on the lamp control board 35 and the sound control board 70, and the display control CPU 101 is based on the display control command. Lamp / LED lighting / extinguishing control is executed by outputting a command signal to the lamp driver 354 and the LED driving circuit 355 mounted on the lamp control board 35, and sound control is performed based on the display control command. Voice output control from the speaker 27 may be executed by outputting a command signal to the voice synthesis IC 703 mounted on the substrate 70. That is, the display control means mounted on the display control board 80 not only controls the image display of the variable display device 9 by controlling the VDP 109, but also on the lighting / extinguishing of the lamp / LED and the sound output from the speaker 27. Further, it may be an effect control means that also controls. In such a configuration, for example, when receiving a prize ball payout confirmation designation command, the display control CPU 101 outputs a command signal to the lamp control board 35 based on the command, and turns on the prize ball lamp 51. .

  (3) In the above-described embodiment, the processing based on the V blank interrupt is executed every 33 ms. However, “33 ms” is an example, for example, 16.7 ms (in the case of 60 frames per second), etc. Processing based on the V blank interrupt may be executed every other period.

  (4) In the embodiment described above, the game control means outputs a control signal (connection confirmation signal) indicating that power supply to the pachinko gaming machine 1 has started to the payout control means at the start of power supply. Thus, the payout control means can recognize that the power supply has started and the control operation of the game control means has started.

  (5) In the above-described embodiment, the payout request is made by the prize ball REQ signal, and the number of payouts is specified by the prize ball control signal, but the payout request and the number of payouts are designated by the prize ball control signal. May be. In this case, the payout control means may determine that the payout request is made at the same time when the prize ball control signal is output. According to such a configuration, it is not necessary to use the prize ball REQ signal.

  (6) In the above-described embodiment, the payout control means determines that the prize ball payout has ended when it detects that the payout motor 289 has rotated by the planned payout number. However, the number of times the payout motor position sensor detects is the expected payout number. If it reaches, the end of the prize ball payout may be determined. That is, the payout control means is configured to determine whether or not the payout is completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 289 or the number of detections by the payout motor position sensor). May be.

  (7) In the above-described embodiment, the payout control means confirms that the game ball has been paid out based on the detection signal of the payout number count switch 301, but the game ball is based on the output signal of the payout motor position sensor. You may make it confirm that was paid out.

  (8) The payout control means detects the amount of operation of the drive means (for example, payout motor 289, cam, etc.) of the payout means, and whether or not an abnormality related to payout (payout unit error) has occurred based on the detection. It may be configured to determine. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  (9) In the above-described embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent. The present invention can be applied.

  (10) In the above-described embodiment, the payout is prohibited when the ball is out of play or the lower pan is full. However, when other payouts are not desirable or when payout cannot be performed, May be set in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from a door opening switch for detecting this.

  (11) In the above-described embodiment, different expressions such as transmission / reception and output / input are used for the exchange of various signals, but transmission and output or reception and input are used in substantially the same meaning. Needless to say, these expressions are interchangeable. In addition, the transmission / reception of signals having many meanings such as control commands is made transmission / reception, and the transmission / reception and output / input are made of transmission / reception of signals for transmitting information by switching on / off. There are also cases where they are used properly. Even in this case, these expressions are interchangeable.

  (12) In the above-described embodiment, the on / off state of the signal may be a high level state / low level state, and conversely, may be a low level state / high level state.

  (13) In the above-described embodiment, the following pachinko gaming machine 1 is disclosed.

  When the game control microcomputer starts supplying power to the pachinko gaming machine 1 and the game control process is ready to be executed, the game control process is started (specifically, for example, a control command in S14, S94, etc.) When the game control process is ready to be executed, at least the payout control process (or display control process, lamp control process, voice control process) is started. (Specifically, it may be after the process of receiving the control command from the main board 31 is made executable, for example, delaying until after the interrupt is permitted in S715). A pachinko gaming machine 1 that executes a delay process (for example, S41 to S46) for delaying the predetermined period of time. In the delay process, for example, the control signal transmission process (for example, S14 and S94) after the game control process is started is started at least when the game control process becomes executable. The process (or display control process, lamp control process, voice control process) is started to be executed and delayed for a predetermined period until the control signal can be received (for example, after the interrupt is permitted in S715). You may do it. If comprised as mentioned above, when the power supply of the pachinko gaming machine 1 is started, the control means mounted on the sub-board or the sub-sub-board can reliably receive the control signal from the game control means. .

  (14) In the above-described embodiment, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can at least read the information such as the identification code that can identify the recording information. It may be something that can be recorded on. Further, the recording medium may be one in which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to the card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  (15) The pachinko gaming machine of the above-described embodiment mainly has a predetermined game value when the stop symbol of the special symbol that is variably displayed on the variation display unit 9 based on the start winning is a combination of the predetermined symbols. The first type of pachinko gaming machine that can be granted to the player, but the second type that allows the player to be given a predetermined game value when there is a prize in the predetermined area of the electric game that is released based on the start prize. A third type in which a predetermined right is generated or continued when there is a prize for a predetermined electric game that is released when a stop symbol of a symbol that is variably displayed based on a start winning prize becomes a combination of a predetermined pattern The present invention can be applied even to a pachinko gaming machine. Furthermore, the present invention can be applied to a slot machine or the like in which the game medium is a coin (medal) without being limited to a pachinko game machine in which the game medium is a game ball.

  (16) In the above-described embodiment, there are three error states such as the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error as error states that can be canceled by the error release switch 375. Was described as an example. However, the present invention is not limited to this, and the error states that can be canceled by the error release switch 375 are not limited to the above-described three types of error states. There may be.

  (17) In the above-described embodiment, as an example of an error due to insufficient payout of game balls, an error in which no game balls are paid out even if a payout operation is performed in the payout process has been described. However, the present invention is not limited to this, and an error due to insufficient payout of game balls may include an error in which game balls are paid out, including the case where no game balls are paid out, but less than the planned payout number. .

  (18) In the above-described embodiment, it has been explained that the error relating to the payout control includes a specific error and a special error, and the specific error and the special error are different types of errors. . However, the present invention is not limited to this, and depending on the type of error, it may be set to correspond to both a specific error and a special error. For example, as an example, the payout case error may be set as a special error in addition to being set as a specific error.

  (19) It should be understood that the embodiment disclosed herein is illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is the front view which looked at the pachinko game machine from the front. It is the rear view which looked at the pachinko game machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the structural example of a display control board, a lamp control board, and an audio | voice control board. It is a timing diagram which shows the transmission form of a 2nd command. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the bit allocation example of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a timing diagram which shows the mode of operation | movement of a microcomputer when power supply is started with respect to the pachinko gaming machine and when power supply is stopped. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is explanatory drawing which shows the buffer used by switch processing. It is a flowchart which shows an example of a switch process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a timing diagram which shows an example of how to output a payout control signal. It is a timing chart showing an example of how to output a prize ball count signal. It is a timing chart showing an example of how to output a payout error signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows prize ball waiting processing 3. It is a flowchart which shows the example of a special symbol process process. It is explanatory drawing which shows the example of the content of a display control command. It is explanatory drawing which shows the example of the content of a display control command. It is explanatory drawing which shows the example of bit allocation of the output port in a payout control means. It is explanatory drawing which shows the bit allocation example of the input port in a payout control means. It is a timing diagram for demonstrating communication between a prepaid card unit and a pachinko gaming machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows a discharge motor control process. It is a flowchart which shows a payout motor control process. It is a flowchart which shows main control communication processing. It is explanatory drawing which shows the conditions for inputting a prize ball control signal via an input port in main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a timing diagram which shows the mode of occurrence of the payout case error. It is a flowchart which shows the part in connection with the output of the prize ball information signal of an information output process. It is a flowchart which shows the main process which CPU for display control performs. It is a flowchart which shows the timer interruption process which CPU for display control performs. It is a flowchart which shows a command analysis process. It is a flowchart which shows a display control process process. It is explanatory drawing which shows the example of a notice effect. It is a flowchart which shows the prior notice selection process of a display control process process. It is explanatory drawing which shows the example of the content of a lamp control command. It is explanatory drawing which shows the example of the content of a sound control command. It is a flowchart which shows a command transmission process. It is a flowchart which shows a command transmission routine. It is a flowchart which shows the main process which CPU for lamp control performs. It is a flowchart which shows the timer interruption process which CPU for lamp control performs. It is explanatory drawing which shows lamp data. It is explanatory drawing which shows a lamp data selection table. It is a flowchart which shows the command reception interruption process which CPU for lamp control performs. It is a flowchart which shows the command reception process which CPU for lamp control performs. It is a flowchart which shows the main process which CPU for sound control performs. It is a flowchart which shows the timer interruption process which CPU for sound control performs. It is explanatory drawing which shows sound data. It is explanatory drawing which shows how to distribute a fluctuation pattern. It is a flowchart which shows the other example of the prize ball waiting process 2. FIG. It is a block diagram which shows the example at the time of setting it as the structure provided with the watchdog timer circuit in the production control board.

Explanation of symbols

  1 Pachinko machine, 56 CPU, 97 ball payout device, 371 payout control CPU, 301 payout number count switch, 375 error release switch, 9 variable display device, 27 speaker, 101 display control CPU, 351 lamp control CPU, 701 Sound control CPU, 31 game control board (main board), 80 display control board, 37 payout control board, 35 lamp control board, 70 voice control board, 910 power supply board, 357 watchdog timer circuit, 360 NAND circuit.

Claims (6)

Based on the fact that a player can play a predetermined game using a game medium, payout of a prize game medium as a prize based on the fact that the payout condition is satisfied by the game, and the payout condition is satisfied by a loan request A gaming machine for paying out rental game media,
A game control microcomputer for executing a game control process for controlling the progress of the game;
A payout means for paying out the premium game medium and the rental game medium;
Means for controlling the payout means, and controls the payout means to pay out the prize game medium when receiving a payout control signal for instructing payout control of the prize game medium from the game control microcomputer. A payout control microcomputer,
A means commonly used for detecting the payout of the premium game medium and the payout of the rental game medium, and outputs a payout detection signal to the payout control microcomputer in response to the detection of the payout of the game medium. A payout detection means for giving,
The game control microcomputer includes payout control signal transmission means for transmitting the payout control signal based on the fact that the payout condition is satisfied,
The payout control microcomputer includes:
A payout type determination means for determining whether the payout detection signal from the payout detection means corresponds to the detection of the payout of the premium game medium or the rental game medium;
A prize game medium payout detection indicating that the payout of the prize game medium is detected when the payout type determination means determines that the payout detection signal is in response to the detection of the payout of the prize game medium. A payout detection signal transmitting means for transmitting a signal to the game control microcomputer;
Error determination means for determining whether or not a predetermined error has occurred;
Storage means for storing the number of prize game media to be paid out in accordance with the payout control signal;
A payout number storage subtracting means for subtracting the payout number stored in the storage means each time the payout type determination means determines that the payout detection signal is in response to detection of payout of the prize game medium; Including
The payout number storage subtracting means detects the payout of the prize game medium by the payout type determining means even when the error determining means determines that the predetermined error has occurred. A gaming machine characterized by subtracting the number of payouts stored in the storage means each time it is determined that the response is in accordance with the above. A payout notification means for notifying the payout of the prize game medium;
2. The game control microcomputer according to claim 1, wherein when the prize game medium payout detection signal is received, the game control microcomputer performs control for notifying the payout notification means of the payout of the prize game medium. 3. Game machines. A plurality of effect control microcomputers for controlling in response to reception of a control signal for controlling the effect device for performing the game effect transmitted from the game control microcomputer;
The effect device includes a variable display device that displays a plurality of types of identification information that can be identified, respectively.
The display control microcomputer that controls the display of the variable display device among the plurality of effect control microcomputers is configured to receive the first control signal transmitted from the game control microcomputer as the control signal. A process of executing display control by rewriting a display image to be displayed on the display device at every predetermined rewriting timing, and a second control signal is transmitted to another effect control microcomputer in synchronization with the rewriting timing. The gaming machine according to claim 1, wherein processing is executed. The display control microcomputer is
Image selecting means for selecting an image to be displayed on the variable display device in response to reception of the first control signal;
Control signal storage means for storing a plurality of types of the second control signals;
Control signal selection means for selecting any second control signal from the control signal storage means based on which image is selected by the image selection means,
Further, the display control microcomputer performs a variable display control based on the image selected by the image selection means, and executes a process of transmitting the second control signal selected by the control signal selection means. The gaming machine according to any one of claims 1 to 3, wherein the gaming machine is characterized by that. The display control microcomputer is mounted on a display control board,
The other effect control microcomputer is mounted on another effect control board,
The second signal is set so that the first signal is turned on when the first detection condition relating to the stop of the power supply to the gaming machine is satisfied, and is satisfied after the first detection condition is satisfied. Power supply monitoring means for turning on the second signal when the detection condition is satisfied,
The first signal is a backup signal that causes the microcomputer to which the first signal is input to recognize a decrease in the supply of power to the gaming machine,
The second signal is a reset signal that causes a microcomputer to which the second signal is input to perform a system reset,
When at least one of the display control board and the other effect control board monitors a specific signal periodically turned on from the microcomputer, and the specific signal is no longer turned on A microcomputer monitoring means for turning on a third signal for causing the microcomputer to execute a system reset;
At least one of the display control board and the other effect control board is either one of the second signal from the power supply monitoring means and the third signal from the microcomputer monitoring means. 5. The gaming machine according to claim 1, further comprising an input circuit that turns on the special signal when the signal is turned on.   The power supply monitoring means turns on the second signal input from the power supply monitoring means to the effect control board without going through the display control board. The gaming machine described.

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