JP2003033535A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome problems due to the incompletion of a series of control regarding a game during a period until a next interruption is generated. SOLUTION: In a timer interruption process, a CPU inputs a detection signal of a switch, and performs the state judgement for them, and performs a process to store the input state of the detecting signal of the switch in a switch timer. Then, in a game control process, the stored content of the switch timer is copied in a switch state storage region. Then, a game control is executed using the stored information of the switch state storage region. Therefore, even when an interruption is generated before a series of processes for the game control process are not completed, problems due to the generation of the interruption can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine that allows a player to play a predetermined game.

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Furthermore, a variable display unit whose display state can be changed is provided,
There is one configured to give a predetermined game value to the player when the display result of the variable display section becomes a predetermined specific display mode.

The gaming value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who easily wins a hit ball, or is advantageous for the player. To generate the right to pay for the prize, and to make it easier for the conditions for paying out prize balls to be met.

In the pachinko gaming machine, it is usually called a "big hit" that the display result of the variable display section for displaying the special symbol is a combination of predetermined specific display modes.
When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which a hit ball is easy to win is entered. Then, in each opening period, when a predetermined number (for example, 10) of winning holes are won, the winning holes are closed. The number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied when the special winning opening is closed, the jackpot gaming state ends.

Further, in the variable display device, the symbols other than the symbol which is the final stop symbol (for example, the middle symbol of the left and right middle symbols) continue for a predetermined time, and stop and swing in a state in which it matches the specific display mode. , Scaled or deformed state, or multiple symbols fluctuate synchronously in the same symbol, or the position of the displayed symbol is swapped, the possibility of a big hit before the final result is displayed The effect that is performed in a state in which the above is continued (hereinafter, these states are referred to as the reach state) is referred to as the reach effect. A variable display including a reach effect is called a reach variable display. By changing the variation pattern in the reach state from the variation pattern in the normal state, the interest of the game is enhanced. When the display result of the symbols variably displayed on the variably display device does not satisfy the condition for reaching the reach state, the result is “out”, and the variably display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game on the gaming machine is controlled by the game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display unit are controlled by a video display processor (VDP) that generates image data according to an instruction from the microcomputer and transfers the image data to the variable display unit side. The program capacity of a microcomputer is large.

Therefore, the identification information and the like displayed on the variable display section cannot be controlled by the microcomputer of the game control means having a limited program capacity, and the display control is different from that of the microcomputer of the game control means. A symbol control board having a display control means such as a microcomputer is installed. The game control means for controlling the progress of the game needs to send a command for display control to the display control means.

When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game proceeds to the game mounted on the main board. Since it is controlled by the control means, the number of prize balls based on the winning is determined by the game control means and transmitted to the payout control board. On the other hand, rental of game media is
Since it has nothing to do with the progress of the game, it is generally controlled by the payout control means without passing through the game control means.

As described above, the game machine is equipped with various control means in addition to the game control means. Then, the game control means for controlling the progress of the game sends each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the game control means and other control means may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

[0010]

Generally, each electric component control means is constructed to include a microcomputer, and a series of control relating to the game is executed by an interrupt process which is carried out every predetermined time. However, since the control related to the game has become diversified and complicated, it may take a long time before the series of control related to the game is completed. Therefore, there is a possibility that the series of controls executed in the interrupt process may not be completed before the next interrupt occurs. In this way, if the next interrupt process is started without completing a series of control related to the game, depending on the contents of the control that has not been executed, it may cause a disadvantage to the player or the game store. Will result in.

Therefore, it is an object of the present invention to provide a gaming machine capable of eliminating the inconvenience caused by the fact that a series of control related to the game is not completed by the time the next interrupt occurs.

[0012]

A gaming machine according to the present invention comprises:
An electronic component control means for controlling an electric component (for example, a variable winning ball device, a ball payout device 97) which is a gaming machine that allows a player to play a predetermined game ( For example, the CPU 56 and the payout control CPU 37
1) and an input signal detecting means capable of detecting an input signal from the outside of the electric component control means (for example, an input port and a means having a processing function relating to an input signal to the input port in the CPU 56). The same applies to other boards), and the electric component control means repeatedly executes an interrupt process (for example, a timer interrupt process) that is executed every time an interrupt signal is generated at predetermined intervals. The main processing is executed continuously, and the interruption processing monitors the input state of the input signal from the outside and stores the input information indicating the result of the input state (for example, switch input processing). Process), and in the main process, an input information setting process (for example, a switch state setting process) of reading and duplicating the input information stored by the input information storing process, Duplicate information replicated by force information setting processing (e.g., switches the timer value stored in the switch state save area) control of the electrical component based on (e.g., by winning balls processing shown in FIG. 25, step S1
53, step S159, step S225, step S234, and a control process (for example, a game control process, a payout control process) for performing each control executed according to the determination result in step S224, To do.

The electric component control means, in the interrupt processing,
Numerical data update processing for updating at least one numerical data (for example, step S22 to step S25) is executed, and in the main processing, numerical data setting processing for reading and setting the value stored by the numerical data update processing (for example, , Step S16c, step S16d)
And the control of the electric component based on the duplicated value duplicated by the numerical data setting process in the control process.

The numerical data may include random number value data (for example, display random number, determination random number) used by the electric component control means to determine the game contents executed by the electric component. .

The numerical data may include an operation timer (for example, a general-purpose timer, a production timer, a process timer, a variation timer) for managing the operation period of the electric component.

In the input information storing process (eg, switch input process), determination information (eg, switch timer value) based on the input state of the input signal is stored, and in the input information setting process (eg, switch state setting process). The determination information is duplicated as duplication information, and in the control processing (eg, game control processing), it is shown that the duplication information (eg, the value of the switch timer) has been detected by the input signal detection means continuously for a predetermined number of times. If it is a normal input signal, it is determined that there is a normal input signal, and if it does not indicate that the input signal detecting means has continuously detected a predetermined number of times, it is not a normal input signal. It may be configured to make a determination.

The electric component control means may be a game control means (for example, CPU 56) for controlling the progress of the game.

In the gaming machine, a game is played using a predetermined game medium, and a passage detection switch (for example, a winning opening switch 29a, 30a, 33a) for detecting passage of the game medium in an area where the game medium can pass. , 39a, gate switch 32a, starting opening switch 14a, count switch 2
3, V winning switch 22), the input signal detection means may be configured to detect the input signal from the passage detection switch.

The game machine is played by launching a predetermined game medium into the game area, and a variable display device (for example, a variable display device 9) that can derive a display result after variably displaying identification information. The game area includes a starting area for variably displaying the identification information as the game medium passes, and the passage detection switch is provided in the starting area.
A display including a start detection switch (for example, a start opening switch 14a) for detecting a game medium passing through the start area, and the control process is executed when it is determined that there is a regular input signal from the start detection switch. It may be configured to include a process of determining a result (for example, step S35, step S37 to step S39).

According to the establishment of a predetermined condition, it can be controlled to a specific game state that is advantageous to the player, and a variable winning device (for example, a variable winning ball device) that can be opened in the specific game state is provided in the game area, and passage detection The switch includes a winning detection switch (for example, a count switch 23) provided in the variable winning device and detecting a game medium that has won the variable winning device. The control process is performed by a regular input signal from the winning detection switch. It may be configured to include a winning number counting process (for example, steps S245 to S251) that is performed when it is determined that the winning number of the game medium to the variable winning device is counted.

The variable winning device has a plurality of winning regions,
At least one of the plurality of winning areas is set as a specific area, and when the game medium passes through the specific area during the specific game state, the specific game state can be continued.
The passage detection switch is provided in the specific area and includes a specific area passage switch (for example, a V winning switch 22) that detects a game medium that has passed through the specific area.
It may be configured to include a process (for example, step S308) of performing control for continuing the specific game state, which is executed when it is determined that there is a regular input signal from the specific region passing switch.

The gaming machine is provided with at least one winning opening in the game area, and the passage detection switch is a winning opening switch (for example, winning opening switches 29a, 30a, 33a,) for detecting the game medium winning in the winning opening. 39a), the control process is executed when it is determined that there is a regular input signal from the winning opening switch, and processing for executing payout of the prize game medium according to the winning of the winning opening (for example, It may be configured to include steps S226 to S227 and steps S247 to S251).

The gaming machine is capable of paying out a prize game medium which is paid out in accordance with the fact that the game medium has passed at least a predetermined prize area provided on the game area, and the electric parts are at least a prize game. A payout device (for example, a ball payout device 97) capable of paying out a medium,
The electric component control means may be a payout control means (for example, payout control CPU 371) that controls the payout device.

The gaming machine has a payout game medium detection switch (for example, a prize ball count switch 301) for detecting the passage of at least the prize game medium paid out by the payout device.
A. When a switch for detecting the passage of the rental game medium is provided, the switch is composed of, for example, a ball lending count switch 301B. ), The input signal detection means detects an input signal from the payout game medium detection switch, and is executed when the control processing determines that there is an input by the payout game medium detection switch, A process of counting the number and performing drive control of the payout device according to the number of payouts (for example, steps S538 and S53).
9, step S542) may be included.

The gaming machine is constructed so that it can be connected to a recording medium processing device (for example, a prepaid card unit 50) that receives a game medium lending request from a player, and the input signal detecting means is at least from the recording medium processing device. It is possible to detect an input of a lending request signal (for example, a BRQ signal), and the control process is executed when it is determined that there is an input from the lending request signal. Drive control processing (eg, step S518,
It may be configured to include step S522).

The power supply to the gaming machine is provided with the fluctuation data storing means for storing the fluctuation data which fluctuates according to the progress of the game and holding the stored contents for a predetermined period even if the power supply to the gaming machine is stopped. In the power supply stop process executed when the power supply is stopped, a saving process is executed to save the copy information copied by the input information setting process in the variable data storage means, and the variable data storage is performed when the power supply is restored. It may be configured to be able to perform a state restoration process for restoring the control state based on the stored contents stored in the means.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of a pachinko gaming machine as seen from the front, and FIG. 2 is a front view showing the front surface of the gaming board. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine and can be applied to, for example, an image-type gaming machine or a slot machine.

The pachinko gaming machine 1 is composed of an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame mounted inside the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a frame-shaped glass door frame 2 that is provided in the game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanical parts and the like are attached, and various parts attached to them (excluding a game board described later). It is a structure including and.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply plate (upper plate) 3. Below the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball feed tray 3 and a hitting ball operation handle (operation knob) 5 for firing the hit ball. Glass door frame 2
A game board 6 is detachably attached to the back surface of the. The game board 6 is a structure including a plate-shaped body that constitutes the game board 6 and various parts attached to the plate-shaped body. A game area 7 is formed on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display device (special symbol display device) 9 including a plurality of variable display portions for variably displaying symbols as identification information is provided. The variable display device 9 includes, for example, “left”, “middle”,
There are three "right" variable display parts (symbol display areas).
Below the variable display device 9, an opening / closing wing piece device 15 as a starting winning opening 14 is provided. The winning ball that has entered the starting winning opening 14 is guided to the rear surface of the game board 6 and detected by the starting opening switch 14a. The opening / closing wing piece device 15 has opening / closing wing pieces provided in a pair on the left and right, and opens / closes by opening / closing the opening / closing wing pieces. By the opening / closing wing piece device 15 performing the opening / closing operation, it is brought into an advantageous state for the player who easily wins the game ball in the starting winning opening 14. In addition,
The open / close wing piece device 15 is opened by a solenoid 16.

At the lower part of the opening / closing wing piece device 15, an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided. The opening / closing plate 20 is a means for opening and closing the special winning opening. Among the prize balls guided from the opening / closing plate 20 to the rear surface of the game board 6, the prize winning ball that enters one (V prize area) is detected by the V prize switch 22, and the prize ball from the opening / closing plate 20 is detected by the count switch 23. To be done. On the back surface of the game board 6, a solenoid 21A for switching the route inside the special winning opening is also provided. In this example, each part (for example, the opening / closing plate 20, the solenoid 21) arranged around the special winning opening constitutes a variable winning ball device. Therefore, the game ball that has won the variable winning ball device is detected by the V winning switch 22 and the count switch 23. In addition, in the lower part of the variable display device 9, a special symbol starting memory display (hereinafter, referred to as starting memory display) 18 by four LEDs for displaying the number of effective winning balls that have entered the starting winning opening 14, that is, the number of starting memories. Is provided.
Each time there is an effective start prize, the start memory indicator 18 increases the number of LEDs to be turned on by one. Then, each time the variable display of the variable display device 9 is started, the number of LEDs to be turned on is reduced by 1.

When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the display on the normal symbol display 10 is started. In this embodiment, the left and right lamps (the pattern can be visually recognized when turned on) are alternately turned on to perform variable display. For example, when the variable display ends, the right lamp is turned on. Then, when a predetermined symbol (hit symbol) is displayed as a stop symbol on the normal symbol display device 10, the opening / closing winglet device 15 is opened for a predetermined number of times and for a predetermined time. Ordinary symbol display 1
In the vicinity of 0, there is provided a normal symbol starting memory display device 41 having a display section of four LEDs for displaying the number of winning balls that have entered the gate 32. Each time there is a prize in the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Then, each time the variable display of the normal symbol display device 10 is started, the number of LEDs to be turned on is reduced by 1.

The game board 6 has a plurality of winning openings 29, 30,
33, 39 are provided, and the winning openings 29, 30, 3 for gaming balls
The prizes for the prizes 3, 39 are the prize opening switches 29a, respectively.
It is detected by 30a, 33a and 39a. Each winning opening 29, 30, 33, 39 constitutes a winning area provided on the game board 6 as an area for accepting a game medium and allowing winning. It should be noted that the starting winning opening 14 that accepts the game medium and allows the winning, and the special winning opening also constitute the winning area. Decorative lamps 25 that are displayed blinking during the game are provided around the left and right sides of the game area 7, and there is an outlet 26 at the bottom for absorbing hit balls that have not been won. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b and a right frame lamp 28
c is provided. Further, a decorative LED is installed around each structure (a special winning opening, etc.) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of the decorative light-emitting body provided in the game machine.

In this example, the prize ball lamp 51 that lights up when the remaining number of prize balls is present near the left frame lamp 28b.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the top frame lamp 28a.
As described above, the pachinko gaming machine 1 of this example is provided with lamps and LEDs as light-emitting bodies at various places. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming machine 1,
Also shown is a card unit 50 that allows for ball lending by inserting a prepaid card.

In the card unit 50, a usable indicator lamp 151 indicating whether or not the card unit 50 is usable, and a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. A fraction display switch 1 for displaying on a frequency display LED provided in the vicinity of the hit ball supply tray 3
52, the connection stand direction indicator 15 showing which side the pachinko gaming machine 1 the card unit 50 corresponds to
3, a card insertion display lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The game ball shot from the hitting ball launching device enters the game area 7 through the hit ball rail, and then comes down from the game area 7. When the ball hits the starting winning opening 14 and is detected by the starting opening switch 14a, if the variable display of the symbol can be started, the variable display device 9 starts the variable display (variation) of the special symbol. If it is not in a state where variable display of symbols can be started, the number of starting memories is increased by 1.

The variable display of the special symbol on the variable display device 9 is stopped when a certain time has elapsed. If the special symbol combination at the time of stop is a big hit symbol (specific display result), the big hit game state is entered. That is, the opening / closing plate 2
0 is released until a fixed time elapses or a predetermined number (for example, 10) of hit balls are won. Then, when the hit ball enters the V winning area while the opening / closing plate 20 is open and is detected by the V winning switch 22, the continuation right is generated and the opening / closing plate 20
Is released again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

The combination of special symbols in the variable display device 9 at the time of stop is a big hit symbol with probability variation (probability variation symbol)
In the case of the combination of, the probability of the next big hit is high. That is, the state of probability change is more advantageous for the player.

When the hit ball wins the gate 32, the normal symbol is displayed in a variable manner on the normal symbol display 10. Further, when the stop symbol in the normal symbol display 10 is a predetermined symbol (hit symbol), the opening / closing winglet device 15 is opened for a predetermined time. Furthermore, in the probability variation state, the probability that the stop symbol on the normal symbol display 10 becomes a hit symbol is increased, and the opening time and the number of times of opening and closing the winglet device 15 are increased. That is, the opening / closing winglet device 15
The opening time and the number of times of release are increased when the stop symbol of the normal symbol is a hit symbol or the stop symbol of the special symbol is a probability variation symbol, and the state is changed from the disadvantageous state to the advantageous state for the player. In addition, increasing the number of releases
It is a concept that includes changing from a closed state to an open state.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a rear view of the gaming machine viewed from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

As shown in FIG. 3, on the back side of the game machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board on which a game control microcomputer and the like are mounted (mainly Substrate) 31 is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decorations L provided on the game board 6
ED, starting memory indicator 18 and normal symbol starting memory indicator 41, decoration lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 28c, prize ball lamp 51 and ball out lamp provided on the frame side. There is also provided a lamp control board 35 on which a lamp control means for controlling lighting of 52 is mounted, and a sound control board 70 on which a sound control means for controlling sound generation from the speaker 27 is mounted. In addition, DC3
A power supply board 910 and a firing control board 91 on which a power supply circuit for creating 0V, DC21V, DC12V and DC5V is mounted are provided.

On the back side of the game machine, a terminal board 160 having terminals for outputting various information to the outside of the game machine is installed above. Terminal board 160
At least, the terminal for ball breakage for introducing the output of the ball breakage detection switch and outputting it externally, the terminal for prize balls for externally outputting the prize ball number signal and the external output for the ball lending number signal A ball lending terminal is provided. Further, in the vicinity of the center, an information terminal board (information output board) 34 provided with each terminal for outputting various information from the main board 31 to the outside of the gaming machine is installed.

Further, a memory content holding means (for example, a backup RA capable of holding the content even when power supply is stopped) included in each board (main board 31, payout control board 37, etc.).
There is provided a switch board 190 on which a clear switch 921 as an operation means for clearing the backup data stored in M) is mounted. Switch board 1
The 90 is provided with a clear switch 921 and a connector 922 connected to another substrate such as the main substrate 31.

The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. 4, the curve gutter 1
After 86, the ball payout device covered with the prize ball case 40A is reached. At the upper part of the ball payout device, a ball break switch 187 is provided as a game medium cut detection means. When the out-of-ball switch 187 detects out-of-ball, the payout operation of the ball payout device is stopped. The out-of-ball switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage, but the out-of-ball detection switch 167 that detects a shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail 39 (the storage tank 38). (Provided near). When the out-of-ball detection switch 167 detects a shortage of game balls, the supply mechanism provided on the game machine installation island supplies game balls to the game machine.

A large number of game balls as prizes based on prizes and game balls based on ball lending requests are paid out, and the hit ball supply plate 3 becomes full, and finally the game balls reach the contact port 45 and further game balls are provided. When paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In that state, the rotation of the payout motor in the ball payout device is stopped, and the operation of the ball payout device is stopped.

As shown in FIG. 4, a ball passage 191 extending from the curve gutter 186 to the discharge port 192 at the bottom of the game machine is formed on the side of the ball payout device. Ball passage 19
1 is provided with a ball removing lever 193, and when the ball removing lever 193 is operated by a game store clerk or the like, a game ball passage from the guide rail 39 to the ball removing passage 191 is formed and stored in the storage tank 38. The played game ball is discharged from the discharge port 192 to the outside of the game machine.

FIG. 5 is an exploded perspective view showing a structural example of the ball payout device 97. In this example, a ball payout device 97 is formed inside the three cases 140, 141, 142 as the prize ball case 40A. Holes 170, 171 communicating with the ball passage at the bottom of the ball break switch 187 are provided in the upper part of the cases 140, 141, and the game ball has holes 170, 171.
It flows into the ball payout device 97 from 171.

The ball payout device 97 includes a payout motor (eg, stepping motor) 289 serving as a drive source. The rotational force of the dispensing motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the dispensing motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

The ball passage 293 is provided with a distribution member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when paying out a prize ball, the game ball falls down along one of the flow paths in the ball passage 293, and when lending the ball, the game ball flows down through the other flow path in the ball passage 293. To fall down. The payout motor 289 and the solenoid 310 are controlled by the payout control CPU mounted on the payout control board 37. The payout control CPU is the main board 31.
The payout motor 289 and the solenoid 310 are controlled in accordance with a command from the game control CPU mounted on the.

A prize ball sensor (prize ball count switch) 301A for detecting the game balls paid out by the ball payout device is provided below the downflow path selected at the time of paying out prize balls.
A ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by a ball payout device is provided below the flow-down path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals.

Incidentally, on the peripheral portion of the gear 291, there is formed a protrusion forming a payout motor position sensor. The protrusion allows the light from the light emitting body (not shown) to pass through or shield the light receiving unit (not shown) of the payout motor position sensor in accordance with the rotation of the gear 291 or the rotation of the payout motor 289. To do. The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

The ball payout device may be configured to perform both prize ball payout and ball lending, but a ball payout device for paying a prize ball and a ball payout device for lending a ball are separately provided. It may be. Further, for example, the rotation direction of the sprocket may be changed to divide the prize ball payout and the ball lending, and the ball payout device having any structure other than the ball payout device 97 exemplified in the present embodiment. The present invention can also be applied by using.

FIG. 6 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 6 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a symbol control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
Control circuit 53, a gate switch 32a, a starting opening switch 14a, a V winning switch 22, a count switch 23, winning opening switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for giving the signal from 21 to the basic circuit 53
8, a solenoid 16 for opening / closing the open / close winglet device 15, a solenoid 21 for opening / closing the open / close plate 20 and a solenoid 21A for switching the path within the special winning opening are included in the basic circuit 5
A solenoid circuit 59 that is driven in accordance with a command from No. 3 is mounted.

Although not shown in FIG. 6, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Switches such as the prize ball count switch 301A may be called a sensor. That is, a game medium detecting means capable of detecting a game ball (a game ball detecting means in this example)
If so, the name does not matter. Each of the starting port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a for performing the winning detection is an example of the winning detection means (passage detection switch).
Also, the full tank switch 48 and the out-of-ball switch 187 are
It is an example of a route abnormality detecting means for detecting abnormality of a payout route. But also. The winning detection means may be one that collectively detects each of the gaming balls that have been won separately in a plurality of winning openings. Further, even if a passing gate such as the gate switch 32a is used for paying out prize balls, entering a game ball into the passing gate is a prize, and a switch provided in the passing gate (for example, The gate switch 32a) serves as a winning detection means.

Further, according to the data given from the basic circuit 53, the big hit information indicating the occurrence of the big hit, the effective starting information indicating the number of the starting winning balls used to start the variable display of the symbols on the variable display device 9, and the probability variation. An information output circuit 64 that outputs an information output signal such as probability variation information indicating that it has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 is a ROM 54 for storing a game control program and the like, and R as a storage means (means for storing variation data) used as a work memory.
AM55, CPU5 which controls according to the program
6 and I / O port section 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. Note that the 1-chip microcomputer only needs to have at least the RAM 55 built therein, and
The OM 54 and the I / O port unit 57 may be external or built-in.

Further, a part or all of the RAM (which may be a RAM with a built-in CPU) 55 is a backup RAM backed up by a backup power supply created in the power supply board 910. In other words, even if the power supply to the gaming machine is stopped,
The contents of part or all of M55 are saved.

The hit ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 controls the ball to be fired at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 includes the starting memory indicator 18, the normal symbol starting memory indicator 41 and the decorative lamp 25 provided on the game board. In addition to performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the out-of-ball lamp 52 provided on the frame side is performed. Further, the display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the ordinary symbol is the symbol control board 80.
The display control means mounted on the.

FIG. 7 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full tank switch 48 is transmitted via the relay board 71 to the main board 3.
1 is input to the I / O port unit 57. The detection signal from the ball break switch 187 is also input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates the full state, a payout control command instructing that the payout should be stopped is sent. When receiving the payout control command instructing that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid award ball.

When there is a winning, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is an I / O port 372a.
The payout control command is input via the, and the ball payout device 97 is driven according to the payout control command to perform the prize ball payout. In this embodiment, the payout control CPU 371 is
1-chip microcomputer, at least RA
M is built in.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A lent ball number signal indicating the number of lent balls is output to the terminal board 160 via 72c. Furthermore, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signals from the ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually loaned ball. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the distribution solenoid 3 is used.
The drive signal to 10 is transmitted to the distribution solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

A card unit control microcomputer is mounted on the card unit 50. Also,
The card unit 50 is provided with a fraction display switch 152, a connecting board direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). To the balance display board 74, a frequency display LED, a ball lending switch and a return switch, which are provided in the vicinity of the hitting ball supply tray 3, are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

Then, the payout control board 37 has a payout control C.
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. After that, if the BRDY signal from the card unit 50 is not on,
The prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, the payout control board 3
At least a part of the RAM (may be a RAM with a built-in CPU) existing in 7 is backed up by a backup power supply created in the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is saved for a predetermined period.

In this embodiment, the case where the card unit 50 is installed as a separate body from the gaming machine and adjacent to the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. May be. Further, the present invention can be applied even when a game ball corresponding to the amount of coins is lent out in response to the coin insertion.

FIG. 8 shows the circuit configuration in the symbol control board 80, LCD (liquid crystal display device) 82 which is an example of realizing the variable display device 9, an ordinary symbol display device 10, an output port of the main substrate 31 (port 0). , 2) 570 and 572 and output buffer circuits 620 and 62A.
8-bit data is output from the output port (output port 2) 572, and a 1-bit strobe signal (INT signal) is output from the output port 570.

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and when the INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, the display control command is received via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. If the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls the display of the screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP (video display processor) 103. The VDP 103 is the character RO
Read the required data from M86. VDP103 is
Image data to be displayed on the LCD 82 is generated according to the input data, and the R, G, B signals and the synchronization signal are set to L.
Output to CD82.

FIG. 8 also shows a reset circuit 83 for resetting the VDP 103, an oscillating circuit 85 for supplying an operating clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image including characters, figures, symbols, or the like displayed on the LCD 82.

The input buffer circuits 105A and 105B are
The signal can be passed only in the direction from the main board 31 to the symbol control board 80. Therefore, the pattern control board 8
There is no room for signals to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute an irreversible information input means together with the input ports. Even if the circuit in the symbol control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

Noise filter 10 for cutting off high frequency signals
For example, a 3-terminal capacitor or a ferrite bead is used as 7, but the presence of the noise filter 107 eliminates the influence of noise on the display control command between the substrates. A noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 9 is a block diagram showing signal transmitting / receiving portions of the main board 31 and the lamp control board 35.
In this embodiment, a point frame lamp 28a, a left frame lamp 28b, and a right frame lamp 2 provided outside the game area 7.
8c and lighting of the decorative lamp 25 provided on the game board /
A lamp control command indicating turning off and turning on / off of the prize ball lamp 51 and the out-of-ball lamp 52 is output from the main board 31 to the lamp control board 35. Further, a lamp control command indicating the number of lighting of the starting memory display 18 and the normal symbol starting memory display 41 is also output from the main board 31 to the lamp control board 35.

As shown in FIG. 9, the lamp control commands relating to the lamp control are output ports (output ports 0, 3) 570, 5 of the I / O port section 57 in the basic circuit 53.
It is output from 73. Output port (output port 3) 57
3 outputs 8-bit data, and output port 570 outputs 1
The bit INT signal is output. In the lamp control board 35, the control command from the main board 31 is sent to the lamp control CPU via the input buffer circuits 355A and 355B.
351 is input. If the lamp control CPU 351 does not have an internal I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

In the lamp control board 35, the lamp control CPU 351 follows the lighting / extinguishing patterns of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25 defined according to each control command. A lighting / extinguishing signal is output to the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25. The lighting / extinguishing signal is output to the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25. In addition, the lighting / extinguishing pattern is the CP for lamp control
It is stored in the built-in ROM of U351 or the external ROM.

On the main board 31, the CPU 56 controls the RA
When there is an unpaid remaining number of award balls in the stored contents of M55, a control command for instructing lighting of the award ball lamp 51 is output, and the out-of-ball switch 187 (which is installed upstream of the award ball passage on the back surface of the game board). When the game ball is not detected (see FIG. 3), a control command for instructing lighting of the out-of-ball lamp 52 is output. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. Lamp control CPU
351 turns on / off the prize ball lamp 51 and the out-of-ball lamp 52 according to these control commands. In addition,
The lighting / extinguishing pattern is stored in the built-in ROM or the external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a lighting / extinguishing signal to the starting memory indicator 18 and the normal symbol starting memory indicator 41 in response to the control command.

The input buffer circuits 355A and 355B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 35
5A and 355B are the main board 31 and the lamp control board 35.
The signal can only be passed in the direction towards. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if the circuit in the lamp control board 35 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

In the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside the 70 and 573. The buffer circuits 620 and 63A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. With such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the lamp control board 35 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 10 is a block diagram showing a configuration example of the signal transmission portion of the voice control command on the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 is output from the main board 31 to the voice control board 70 according to the progress of the game.

As shown in FIG. 10, the voice control command is output from the output ports (output ports 0 and 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53. The output port (output port 4) 574 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the voice control board 70, each signal from the main board 31 is input to the input buffer circuit 70.
Input to the voice control CPU 701 via 5A and 705B. If the voice control CPU 701 does not include an I / O port, the input buffer circuit 705A,
An I / O port is provided between the 705B and the voice control CPU 701.

Then, for example, the voice synthesizing circuit 702 by a digital signal processor is used for the voice control CPU 7
A sound or sound effect according to the instruction 01 is generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level according to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

The input buffer circuits 705A and 705B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the voice control board 70. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574, respectively. The buffer circuits 620 and 67A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the voice control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 11 is a block diagram showing a configuration example of the power supply board 910. The power supply board 910 includes a main board 31,
Design control board 80, sound control board 70, lamp control board 3
5 and the payout control board 37 and other electric part control boards are installed independently of each other, and each electric part control board in the gaming machine and the voltage used by the mechanical parts are generated. In this example, AC2
4V, VSL (DC + 30V), DC + 21V, DC + 1
Generates 2V and DC + 5V. Further, the backup power source, that is, the capacitor 916 serving as a memory holding unit,
It is charged from DC + 5V, that is, from the line of the power supply that drives the ICs on each substrate. Note that VSL is a rectifier circuit 912.
At, the rectifying element rectifies and boosts AC 24V. VSL serves as a solenoid drive power source.

The transformer 911 converts the AC voltage from the AC power supply into 24V. 24V AC voltage is applied to connector 9
It is output to 15. In addition, the rectifier circuit 912 is an AC 24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 may include one or more converters I
C922 (only one is shown in FIG. 11) and VSL
Based on the above, + 21V, + 12V and + 5V are generated and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the game machine from the outside is stopped, the DC voltage of + 30V, + 12V, + 5V, etc., decreases relatively gently. The connector 915 is connected to, for example, a relay board, and the relay board supplies electric power of a required voltage to each electric component control board and mechanical components.

However, the power supply board 910 may be provided with each connector reaching each electric component control board, and each voltage may be supplied from the power supply board 910 to each board without the relay board. Further, although one connector 915 is representatively shown in FIG. 11, the connector is provided for each electric component control board.

+ 5V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the game machine is stopped (RAM whose power is backed up, that is, backup storage means that can be in a storage content holding state even when the power supply is stopped).
It becomes a backup power supply that supplies electric power so that the memory state can be maintained. In addition, a diode 9 for preventing backflow is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, the backup + 5V is applied to the main board 31 and the payout control board 3
7 is supplied.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, it is determined that the power supply is stopped, and a power-off signal is output. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC, is used. Power supply monitoring IC
The power-off signal from 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of the power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V
Therefore, it can be expected to prevent erroneous detection of switch-on at the moment of power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in + 12V generated after + 30V is generated, before the voltage starts to drop.

When the voltage of the + 12V power supply drops, the switch output comes to be in the ON state, but if the + 30V power supply voltage that drops earlier than + 12V is monitored and the stop of the power supply is recognized, the switch output will show the ON state. It is possible to enter the state of waiting for the restoration of the power supply before entering the state where the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric part control board, the power supply cutoff circuit can supply a power-off signal to the plurality of electric part control boards. Even if there are any number of electrical component control boards that require a power-off signal, one power source monitoring means may be provided, so that even if each electrical component control means in each electrical component control board performs recovery control described below. , The cost of gaming machines does not rise so much.

Note that in the configuration shown in FIG. 11, the detection signal (power-off signal) of the power supply monitoring IC 902 is transmitted via the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control circuit). Although it is transmitted to the substrate 37), for example, one detection signal may be transmitted to the relay substrate and the same signal may be distributed from the relay substrate to each electric component control substrate. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, the main substrate 31
Regarding the power-off signal output to the payout control board 37, the monitoring voltage of the power-source monitoring circuit that outputs the power-off signal may be different.

FIG. 12 shows the CPU 56 in the main board 31.
It is a block diagram showing an example of the circumference. As shown in FIG. 12, the power-off signal from the power-source monitoring circuit (power-source monitoring means; first power-source monitoring means) of the power-supply board 910 is the CPU.
It is connected to 56 non-maskable interrupt terminals (XNMI terminals). Therefore, the CPU 56 causes the non-maskable interrupt (NM
I) It is possible to confirm the occurrence of the stop of the power supply to the gaming machine by the process.

A system reset circuit 65 is also shown in FIG. The reset IC 651 is
The output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level when the predetermined time elapses. That is, the reset signal is raised to the high level to bring the CPU 56 into the operable state. The reset IC 651 monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, and has a predetermined voltage value (lower than the power supply voltage value at which the power supply monitoring circuit outputs a power cutoff signal). When the value is less than or equal to (value), the output goes low. Therefore, the CPU 56 is reset in the system (that is, returned to the initial state of the system) after performing a predetermined power supply stoppage process in response to the power off signal from the power monitoring circuit.

As shown in FIG. 12, the reset IC 651 is used.
The reset signal from is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level.
Then, the Q5 output of the counter IC 941 is the NOT circuit 9
It is input to the NAND circuit 947 via 45 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The NAND circuit 9 is connected to the other input of the OR circuit 949.
The output of 47 is introduced via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. With such a configuration, when the power is turned on, the reset terminal of the CPU 56 is supplied with the reset signal (low level signal) twice.
Reliably starts operation.

Then, for example, the detection voltage of the power supply monitoring circuit (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to the low level is set to + 9V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 have the same power supply VSL.
Since the voltage is monitored, the difference between the timing when the voltage monitoring circuit outputs the power-off signal and the timing when the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop time process to the reliable completion of the power supply stop time process in response to the power off signal from the power supply monitoring circuit.

The voltages of the power supplies monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.
The system reset circuit 65 corresponds to the second power supply monitoring means.

At least part of the RAM is backed up by the backup power supply supplied from the power supply board while the power is not supplied from the + 5V power supply which is the driving power supply for the CPU 56 and the like, and even if the power supply to the gaming machine is stopped. Content is saved. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operating state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the game state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

In the configuration shown in FIG. 12, the reset terminal of the CPU 56 is supplied with the reset signal (low level signal) twice when the power is turned on, but the reset signal is surely reset even if the rising timing of the reset signal is only once. When using the released CPU, reference numerals 941 to 949
The circuit element indicated by is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has 4 bits of 3 and a 1-byte port of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output.

FIG. 13 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 13, bits 0 to 7 of the input port 0 have respective winning opening switches 33a, 39a, 29a, 30a, and
Detection signals of the gate switch 32a, the starting opening switch 14a, the count switch 23, and the V winning switch 22 are input. In addition, the detection signals of the prize ball count switch 301A, the full tank switch 48, the ball cut switch 187, the count switch short circuit signal, and the detection signal of the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. In this way, the detection signal of the clear switch 921, that is, the operation input of the operating means, is the input port (the input unit of 8-bit configuration) to which the detection signal of the switch for detecting the game ball is input.
Bit in the same input port as (input port circuit)
Has been entered in.

Next, the operation of the gaming machine will be described. Figure 1
4 is a flowchart showing main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main processing, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the stack pointer designated address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). After initializing the built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to the accessible state (step S6).

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, the CTC has two external clock / timer trigger inputs CLK / TRG2,3.
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode to always fly to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the internal device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, the interrupt request from each built-in device can be easily processed, and the interrupt process can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 confirms the state of the output signal of the clear switch 921 inputted through the input port only once (step S7). If ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15).
When the clear switch 921 is on (when pressed), a low level clear switch signal is output. Note that, for example, the game store staff can easily execute the initialization process by starting the power supply to the gaming machine while turning on the clear switch 921. That is, the RAM clear or the like can be performed.

If the clear switch 921 is not in the ON state, the data protection processing of the backup RAM area (for example, processing when power supply is stopped such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. When such a protection process is performed, backup is made. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area during the power supply stop process. In this example, as shown in FIG. 15, if “55H” is set in the backup flag area, it means that there is backup (on state), and if a value other than “55H” is set, there is no backup (off). State).

After confirming that there is a backup, the CPU 5
6 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Further, the number of checksum calculations corresponding to the number of checksum target data is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The data after inversion is used as the checksum.

In the power supply stop process, the checksum is calculated by the same process as the above process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If the power is restored after an unexpected power outage such as a power outage, backup RA
Since the data in the M area should have been saved, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply was stopped. In such a case, since the internal state cannot be returned to the state when the power supply was stopped, the initialization process that is executed when the power is turned on, not when the power supply is restored from the stop, is executed.

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply was stopped (step S10). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored.

As described above, the backup RA is backed up by using the backup flag and the check data such as the checksum.
By checking whether or not the data in the M area is saved, it is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

If "backup is present" is not confirmed by the state of the backup flag, the initialization process described below is performed without performing the game state recovery process described below, so backup data exists. It is possible to prevent the game state restoration process from being executed despite not doing so, and it is possible to return the control state to the initial state by the initialization process.

Furthermore, when the check result using the check data is not normal, the initialization process described below is performed without performing the game state recovery process described below, so that the power supply is stopped. It is possible to prevent the game state recovery process from being executed based on the backup data that has become different contents,
By the initialization processing, the control state can be returned to the initial state.

In the initialization processing, the CPU 56 first executes R
AM clear processing is performed (step S11). Further, a predetermined work area (for example, a random number counter for normal symbol determination, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
Work area setting processing for setting an initial value to a prize ball flag, out-of-ball flag, payout stop flag, or other flag for selectively performing processing according to the control state is performed (step S1).
2). Further, a process of transmitting a payout permission state designation command (hereinafter, referred to as a payable state designation command) for instructing that the ball can be paid out from the ball payout device 97 to the payout control board 37 (step S13). . Also,
Other sub-boards (lamp control board 35, sound control board 70,
A process of transmitting an initialization command for initializing the pattern control board 80) to each sub-board is executed (step S1).
4). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing to turn off the prize ball lamp 51 and the ball out lamp 52 (for the lamp control board 35) Etc.)

Then, the register of the CTC provided in the CPU 56 is set so that the timer interrupt is periodically applied every 2 ms (step S15). That is,
A value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, in the main process, the game control process (step S16) is repeatedly executed. FIG. 16 is a flowchart showing an example of the game control process which the CPU 56 repeatedly executes in the main process. In the game control process, the CPU 56 first sets an interrupt prohibited state (step S16a) and then performs a switch state setting process (step S16b). In the switch state setting process, a process of copying stored contents (an example of input information) of a switch timer (see FIG. 22) described later to a switch state saving area provided in the RAM 55 is performed. In the counter state setting process (step S16c), a process of copying the count value of each counter (an example of numerical data) to the counter state saving area provided in the RAM is performed. Then, the timer state setting process (step S16d)
At, a process of copying the value of each timer (an example of numerical data) such as a general-purpose timer to a timer state saving area provided in the RAM 55 is performed. That is, in each state setting process (step S16b to step S16d), the RAM is
The current switch timer value, the count value of each counter, and the value of each timer, which are respectively stored in the predetermined areas of 55, are stored in separate areas (switch state storage in this example) provided in the RAM 55. Area, counter state saving area, and timer state saving area). Therefore, the states of the switch timer, the counter, and the timer at the time when each state setting process (step S16b to step S16d) are executed are the switch state saving area, the counter state saving area,
And copied to the timer state save area. When each state setting process (step S16b to step S16d) is completed, the interrupt enabled state is set (step S16e). As described above, in this example, each state setting process (step S1
When 6b to step S16d) are executed, the interrupt disabled state is set. The switch state saving area, the counter state saving area, and the timer state saving area are RA
It is provided in the backup RAM area of M55.

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S16f).

Next, the CPU 56 updates the count value of the counter for generating the display random number and the initial value random number (steps S16g and S16h). It should be noted that what is updated is the counter for generating each random number, and the value stored in the counter state storage area is not updated. Also, when we say "numerical data", each random number, a counter for generating each random number,
Alternatively, it means any of the count values. That is, each random number, the counter for generating each random number, and the count value thereof are examples of numerical data. The display random number is a random number for determining the symbol displayed on the variable display device 9, and the display random number updating process is a process of updating the count value of the counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random numbers. The initial value random number is a random number for determining an initial value of a count value of a counter (big hit determination random number generation counter) for generating a random number for determining whether or not to make a big hit. For example, in a timer interrupt process described later, when the count value of the big hit determination random number generation counter makes one round, an initial value is set to the counter. The process of updating the count value of each counter for generating each random number for determination, such as the random number for jackpot determination used for game control, is not executed in the game control process,
It is performed by a timer interrupt process described later.

In this example, the interrupt-prohibited state is not set when the display random number updating process is executed. Therefore, the display random number updating process is also executed in the timer interrupt process described later, which may conflict with the process in the timer interrupt process. In this example, this competition ensures the randomness of the count value of the display random numbers. Note that a configuration may be adopted in which the continuity of the count values of the display random numbers is ensured by setting the interrupt prohibited state when the display random number updating process is executed.

FIG. 17 is an explanatory diagram showing each random number. Each random number is used as follows. (1) Random 1: Determine whether to generate a big hit (for big hit determination = special symbol determination) (2) Random 2-1 to 2-3: For left and right middle out-of-range symbol determination (3) Random 3: Determine the combination of symbols at the time of big hit (for big hit symbol determination = for special symbol judgment) (4) Random 4: Determine fluctuation pattern at reach (for fluctuation pattern determination)

In order to enhance the game effect, a random number other than the random numbers (1) to (4) described above (for example, a random number for initial value determination) is also used. Further, for example, by setting an initial value for each random number (for example, an initial value set for each random number) at regular intervals, the random numbers of the above (1) to (4) are configured not to be synchronized with each other. Is desirable. The random number for determining the variation pattern may be a random number used not only for determining the variation pattern at the time of reach, but also for determining the variation pattern at the time of out of reach. In step S16g, the CPU 56
The counter for counting (2) the random number for deviating symbol determination and the variation pattern determining (4) is counted up (1 is added). That is, those are display random numbers, and the other random numbers are determination random numbers.

Further, the CPU 56 performs special symbol process processing (step S16i). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S16j). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the game state.

Next, the CPU 56 performs a process of setting a display control command relating to a special symbol in a predetermined area of the RAM 55 and transmitting a display control command (special symbol command control process: step S16k). Further, the display control command relating to the normal symbol is set in a predetermined area of the RAM 55, and the process of transmitting the display control command is performed (normal symbol command control process: step S16l).

Further, the CPU 56 carries out an information output process for outputting data such as big hit information, start information and probability variation information supplied to the hall management computer (step S16m).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S16n). The solenoid circuit 59 drives the solenoids 16, 21, 21A in response to a drive command in order to open or close the open / close wing piece device 15 or the open / close plate 20 or switch the game ball passage in the special winning opening. To do.

Also, the CPU 56 causes the winning opening switch 29
The prize ball processing for setting the number of prize balls based on the detection signals of a, 30a, 33a and 39a is executed (step S).
16o). Specifically, the winning opening switches 29a, 30
In response to the winning detection based on that any one of a, 33a, and 39a is turned on, a payout control command indicating the number of prize balls is output to the payout control board 37. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in response to a payout control command indicating the number of prize balls.
Then, the CPU 56 confirms the number of stored winning awards, and turns on / off the corresponding holding lamp of the starting memory indicator 18 when the current number of stored winning awards has changed compared to the time of the previous confirmation. A storage process of setting the lamp control command designating the number in the command transmission table is executed (step S16p). In addition, even when designating the lighting / lighting-out of the holding lamp of the normal pattern starting memory display 41, a module common to the module used when designating the lighting / lighting-out of the holding lamp of the starting memory display 18 is used. It

When such a timer interruption occurs periodically every 2 ms set in step S15,
As shown in FIG. 18, the CPU 56 performs the register saving process (step S20) and then, via the switch circuit 58, the gate switch 32a and the starting opening switch 14
a, a count switch 23 and a winning opening switch 24a
A switch detection signal such as the above is input to determine their states, and a process of storing the input state of the switch detection signal in a switch timer described later is performed (switch input process: step S21).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used for game control is performed (step S22).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S23 and S24).

Further, the value of each timer such as a general-purpose timer (operation timer) for managing the operation time of the gaming machine is incremented by 1 (step S25). After that, the contents of the register are restored (step S26) and the interrupt enabled state is set (step S27).

According to the above control, in this embodiment, the processes of steps S21 to S25 are activated every 2 ms. In addition, in this embodiment,
Although the processes of steps S21 to S25 are executed in the timer interrupt process, only the flag indicating that an interrupt has occurred is set in the timer interrupt process, and the processes of steps S21 to S25 are the main processes. May be executed in.

As described above, the input information indicating the input state of the input state sensing means is stored in the timer interrupt processing (step S21), and the input information is read out and stored in the switch state storage area in the main processing ( After setting (step S16b), the game-related control (steps S16f to S16p) is performed by using the save information in the switch state save area, so the interrupt process is performed before the series of game control processes is completed. Even if the input information is updated by starting, it is possible to prevent an unprocessed part from remaining in the game control process, and eliminate the inconvenience caused by not completing the series of game control processes.

The counter (random number data) is updated and stored in the timer interrupt process (step S22).
(Step S24), in the main process, after reading the stored count value (numerical data) of the counter and storing (setting) it in the counter state saving area (Step S24).
16c), control related to the game using the stored information in the counter state storage area (steps S16f to S16)
Since p) is configured to be performed, the random number value data can be surely updated at every predetermined period, and the possibility that the update interval becomes large can be eliminated, so that the random number value data becomes a specific value. It is possible to prevent inconvenience caused by the fact that the operating state continues for a long time.

Furthermore, the operation timer (for example, a general-purpose timer) is updated and stored in the timer interrupt processing (step S25), and the stored value (numerical data) of the operation timer is read in the main processing. After saving (setting) in the state save area (step S16d), the control related to the game (step S16f to step S16p) is performed using the save information in the timer state save area, so the operation timer is updated for a predetermined period. It can be done reliably every time, and the operation timer will function correctly,
It is possible to prevent an operational deviation from occurring in various operations executed in the gaming machine.

FIG. 19 is a game state recovery process (step S
10 is a flowchart showing an example of 10). In the game state restoration process, the CPU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (a stack pointer save buffer in a work area where power is backed up) in a power supply stop process which will be described later in detail. Therefore, in step S81, the RAM
Return by setting the area value in the stack pointer. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the CPU 56 confirms whether or not the payout is stopped (step S82). Whether or not the payout has been stopped is determined by the RAM whose power is backed up.
Predetermined work area stored in the area (for example, random symbol for normal symbol determination, normal symbol determination buffer, special symbol left middle right symbol buffer, special symbol process flag,
The payout stop flag as the payout state data in the payout command storage pointer, the award ball flag, the out-of-ball flag, the payout stop flag, etc.) is confirmed. When it is in the payout stop state, a payout control command (payout stop state designation command) for instructing the stop of payout is transmitted to the payout control means mounted on the payout control board 37 (step S83). If the payout is not stopped, the payout control unit sends a payout control command (payable state designation command) to the payout control means (step S84).

Next, the CPU 56 sends a display control command for restoring the display state of the special symbol on the variable display device 9 when the power supply is stopped (step S85).

After that, the CPU 56 clears the backup flag (step S91), that is, resets the flag indicating that the predetermined storage protection process has been executed at the previous power supply stop. Therefore, it is possible to prevent unnecessary information from remaining after the control state is restored.
Also, the saved values of various registers are read from the stack area, and various registers (IX register, HL register, D
Set to E register, BC register) (step S9)
2). That is, register restoration processing is performed. The value of the stack pointer is decremented each time each register is restored. That is, the value of the stack pointer is updated to point to the address immediately before the stack area. Then, when the parity flag is not turned on, the interrupt permission state is set (steps S93 and S94). Finally, AF
The registers (accumulator and flag registers) are restored from the stack area (step S95).

Then, the RET instruction is executed. RET
When the instruction is executed, the CPU 56 realizes the return operation of the program by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state recovery processing. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S92, the stack pointer pointing to the stack area is NM.
It indicates the area where the address of the program being executed when the power supply stop processing by I was started is saved. That is, the return address stored in the stack area pointed to by the restored stack pointer is
This is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, the next RET instruction in step S95 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address data (program address data) saved in the stack area.

By the above processing, the backup RAM
Based on various information stored in the area, the game state is restored to the state before the power was cut off. In this example, the switch state saving area, the counter state saving area, and the timer state saving area are provided in the backup RAM area, so even if the power supply is stopped, they are saved in each state saving area. The value of the existing switch timer, the counter value, and the timer value are not lost, and the game control using these information is restored.

FIG. 20 is a flow chart showing an example of a non-maskable interrupt process (power supply stoppage process) executed in response to a power-off signal from the power supply board 910. When a non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 uses the stack pointer as the address of the program being executed at the time of the non-maskable interrupt (specifically, the next address after completion of execution). It is saved in the stack area pointed to by and the value of the stack pointer is increased.
That is, the value of the stack pointer is updated to point to the next address in the stack area.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) to the stack area pointed to by the stack pointer (step S51). At this time, the value of the stack pointer is updated to point to the next address of the stack area. Also, the interrupt flag is copied to the parity flag (step S52). Parity flag is backup R
It is formed in the AM region. The interrupt flag is a flag indicating whether the interrupt is enabled or disabled, and is in the control register built in the CPU 56. The ON state of the interrupt flag indicates that the interrupt is disabled.
As described above, the parity flag is referred to in the game state recovery process. Then, in the game state recovery process, if the parity flag is in the on state, it is not set to the interrupt permission state.

In addition, BC register, DE register, HL
The register and the IX register are saved in the stack area pointed to by the stack pointer (steps S54 to 57). At this stage, in the stack area, the address of the program being executed when the non-maskable interrupt occurs, the BC register,
The values of the DE register, the HL register and the IX register are stored in order. The value of the stack pointer is updated to point to the next address of the stack area each time each register is saved. The value of the stack pointer is saved in a predetermined area (stack pointer save buffer) in the work area (step S5).
8).

Next, the designated value with backup ("55H" in this example) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, the parity data is created (steps S60 to S67). That is, first, clear data (0
0) is set in the checksum data area (step S60), and the checksum calculation start address is set in the pointer (step S61). Further, the number of checksum calculations is set (step S62).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated (step S63). The calculation result is stored in the checksum data area (step S6).
4), the pointer value is incremented by 1 (step S65), and the checksum calculation count value is decremented by 1 (step S6).
6). The processes of steps S63 to S66 are repeated until the value of the checksum calculation count becomes 0 (step S
67).

When the value of the checksum calculation frequency becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). And
The inverted data is stored in the checksum data area (step S69). This data becomes the parity data that is checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S70). After that, the built-in RAM 55 cannot be accessed. Therefore, even if the program goes out of control due to the voltage drop, the contents stored in the RAM will not be destroyed.

Then, when the access prohibition value is set in the RAM access register, the CPU 56 enters the standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the power supply stoppage process is executed according to the NMI, but the power-off signal is changed to C
You may connect to the maskable terminal of PU56 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

FIG. 21 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power cutoff signal: power supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to + 22V, the power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (becomes a low level).

The power-off signal is introduced to the electric component control board (in this embodiment, the main board 31 and the payout control board 37), and the CPU 56 and the payout control CPU 371 receive N signals.
It is input to the MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the system reset circuit mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 And the payout control CPU 371 enters the system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stoppage process before being brought into the system reset state.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, at least on the main board 31 and the payout control board 37, the processing at the time of power supply stop is executed, and
56 and the payout control CPU 371 are in the system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Generates a voltage drop signal (power cut detection signal). As shown in FIG. 21, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stoppage process.

Here, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, but the timing of generating the power supply cutoff signal is I
The voltage to be monitored is the highest power supply V at the timing such that the operation time for the electric component control means operating at the C drive voltage to perform the predetermined power supply stop processing is secured.
It does not have to be the voltage of SL. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off signal can be generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stoppage process is secured. .

In this case, as described above, it is preferable that the monitored voltage is a voltage that can be expected to prevent erroneous switch-on detection when the power supply is stopped. That is, the voltage (switch voltage) supplied to the various switches of the gaming machine is +1
Since it is 2V, it is preferable that the voltage drop can be detected at a stage before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

Next, a specific example of the switch input process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch is certainly turned on, and the process corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 22,
The switch timer indicates the number N of detection signals (clear switch 92
(Except for the detection signal of 1). In this embodiment, N = 13. In the RAM 55,
The addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (from the top to the bottom shown in FIG. 13).

FIG. 23 is a flow chart showing a processing example of the switch input processing of step S21 in the timer interrupt processing. Since it is executed in the timer interrupt process,
In this example, the switch input process is executed every 2 ms. In the switch input process, the CPU 56 first inputs the data input to the input port 0 (step S).
101). Next, "8" is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, the switch check processing subroutine is called (step S104).

FIG. 24 is a flow chart showing the switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0 as the "comparison value" (step S121). In addition, clear data (00) is set (step S1
22). Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S).
124). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after addition becomes 0, the added value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in the off state, clear data is set in the switch timer (step S126). That is, if the switch is in the off state, the value of the switch timer returns to 0.

Thereafter, the CPU 56 adds 1 to the pointer (address of the switch timer) (step S130) and subtracts 1 from the number of processes (step S13).
1). If the number of processes is not 0, step S122
Return to. Then, the processing of steps S122 to S132 is repeated.

The processing of steps S122 to S132 is repeated for the number of processings, that is, eight times, and during that time, the switch detection signal input to the 8 bits of the input port 0 is sequentially turned on or off. If the check process is performed and the switch is on, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes step S of the switch processing.
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S107). Then, the switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is executed, steps S122 to S122
The processing of 132 is repeated for the number of processings, that is, four times, and during that time, with respect to the detection signal of the switch input to the 4 bits of the input port 1, the check processing of whether it is in the on state or the off state is performed sequentially. If it is on, the value of the corresponding switch timer is incremented by one.

In this embodiment, since the timer interrupt is taken every 2 ms, the switch input processing is also performed every 2 ms.
Will be executed once. Therefore, if the corresponding switch is on, the switch timer is incremented by 1 every 2 ms.

25 to 27 are flowcharts showing an example of the prize ball process of step S16o in the game control process. In the present embodiment, in the prize ball processing, the winning opening switches 33a, 39a, 29 to which prize balls are paid out.
a, 30a, the count switch 23, and the starting opening switch 14a are determined to be surely turned on, and
When it is turned on, the payout control command indicating the number of prize balls is controlled to be sent to the payout control board 37, and it is determined whether the full tank switch 48 and the out-of-ball switch 187 are surely turned on. Processing such as control so that a predetermined payout control command is sent to the payout control board 37 is performed. The determination as to whether or not each switch is turned on is made based on the stored contents of the switch state saving area. In the switch state storage area, the stored contents of the switch timer are copied in the switch state setting process of step S16b executed before the prize ball process in the game control process.

In the prize ball process, the CPU 56 sets "1" as the offset of the input determination value table (step S150) and "9" as the offset of the switch timer address (step S151). The offset “1” in the input determination value table (see FIG. 29) is
This means that the second data “50” in the input determination value table is used. In addition, each switch timer is shown in FIG.
Since they are arranged in the same order as the bit order of the input ports shown in FIG. 3, the offset "9" of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input judgment value table is set with a judgment value for each switch, which is used to judge that the switch is surely turned on when the number of times the switch is continuously turned on is set.
It is the M region. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 29, in the input determination value table, “2”, “50”, “250”, “30”, in order from the top, that is, from the area having the smallest address value.
The determination values of "250" and "1" are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value, and the switch timer value determined by the start address of the switch timer and the offset value (in the switch state save area (A stored value) is compared, and if they match, a switch-on flag is set, for example.

An example of the switch-on check routine is shown in FIG. In the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the full-tank switch 48 stored in the switch state saving area matches the full-tank switch-on determination value “50”. So (step S153),
The full tank flag is set (step S154). Although not shown in FIG. 25, when the value of the switch timer corresponding to the full tank switch 48 stored in the switch state storage area is 0, the full tank flag is reset.

Further, the CPU 56 sets "2" as the offset of the input judgment value table (step S15).
6), "0A (H)" is set as the offset of the switch timer address (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the offset “0A (H)” of the address of the switch timer corresponds to the switch timer (switch (Which is a switch timer stored in the state storage area) is specified. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 stored in the switch state storage area matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S159). The out-of-ball flag is set (step S160). In addition, although not clearly shown in FIG.
A switch-off timer corresponding to 87 is prepared, and when the value of the switch-off timer stored in the switch state storage area is 30, the out-of-ball flag is reset.

Then, the CPU 56 confirms whether or not the dispensing is stopped (step S201). The payout stop state is a state after a payout stop state designating command, which is a payout control command for instructing the payout control board 37 to be in a state where the payout should be stopped, specifically, the work area. The payout stop flag in is set. If it is not in the payout stop state, it is confirmed whether the out-of-ball state flag or the full tank flag is turned on (step S202).

When any of them changes to the ON state,
The payout stop state flag is set (step S
203), the command transmission table relating to the payout stop state designation command is set (step S204), and the command setting process is called (step S205). In step S204, a command transmission table (R
The start address of OM) is set as the address of the command transmission table. In the command transmission table relating to the payout stop state designation command, the INT data, the first byte of the payout control command, and the second byte of the payout control command, which will be described later, are set. In addition, in step S202, when one of the flags is already in the on state and the other flag is in the on state, the processes of steps S203 to S205 are not performed.

If the payout is stopped, it is confirmed whether the out-of-ball flag and the full tank flag are both turned off (step S206). When both are in the off state (when the release condition described later is satisfied), the payout stop flag is reset (step S207), and the command transmission table regarding the payable state designation command is set (step S208). The set process is called (step S209). In step S208, the start address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payable state designation command, INT data, which will be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

The cancellation condition is a condition for canceling the dispensing stop state, and is a condition that is satisfied when it is no longer necessary to maintain the dispensing stop state. In this example, the cancellation condition is that the surplus ball receiving tray 4 is used when the dispensing stop state is set.
Is said to have become neither full nor full of balls.

Further, the CPU 56 sets "0" as the offset of the input judgment value table (step S22).
1), "0" is set as the offset of the switch timer address (step S222). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the switch timer address offset “0” specifies the switch timer corresponding to the winning opening switch 33a. Means Also, "4" is set as the number of repetitions (step S223).
Then, the switch-on check routine is called (step S224).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 29) (step S281). And
An offset is added to the address (step S28
2) The switch-on determination value is loaded from the added address (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284) and adds an offset to the address (step S285). When the offset is added, the value of the switch timer stored in the switch state storage area is loaded from the address after the addition (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the value of the switch timer corresponding to the switch among the switch timer values stored in the switch state saving area is loaded. To be done.

Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, the switch-on flag is set (step 128).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning port switch 33a stored in the switch state storage area matches the switch-on determination value "2", the switch is switched. The on flag is set (step S225). Then, the switch check-on routine updates the address offset of the switch timer (step S
230), since it is executed by the number of repetitions initially set (steps S228, S229), eventually, the corresponding switch timers stored in the switch state storage area for the winning opening switches 33a, 39a, 29a, 30a. Is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" as the number of prize balls to be paid out is set in the ring buffer (step S226). Then, 10 is added to the value stored in the total prize ball number storage buffer (step S22).
7). When data is written in the ring buffer, the write pointer is incremented, and when data is written in the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball numbers instructed to the payout control means (however, the value is subtracted when payout is made).
It is formed in the backup RAM. In this embodiment, when the data is written in the ring buffer, addition processing is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, addition processing of the number of prize balls corresponding to the payout control command to be output may be performed on the stored value of the total prize ball storage buffer.

Next, the CPU 56 sets "0" as the offset of the input judgment value table (step S23).
1), "5" is set as the offset of the switch timer address (step S232). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the offset "5" of the address of the switch timer specifies the switch timer corresponding to the starting port switch 14a. Means Then, the switch-on check routine is called (step S
233).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a stored in the switch state storage area matches the switch-on determination value "2", the switch-on flag is set (step S234). When the switch-on flag is set, "6" as the number of prize balls to be paid out is set in the ring buffer (step S23).
5). Further, 6 is added to the value stored in the total prize ball storage buffer (step S236).

Next, the CPU 56 sets "0" as the offset of the input determination value table (step S24).
1), "6" is set as the offset of the switch timer address (step S242). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 13, the offset “6” of the switch timer address indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S
243).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 stored in the switch state storage area matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, "15" as the number of prize balls to be paid out is set in the ring buffer (step S24).
5). In addition, 15 is added to the value stored in the total prize ball storage buffer (step S246).

If data exists in the ring buffer (step S247), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (in the ring buffer). It is updated to point to the next area (step S249), the command transmission table regarding the number of prize balls is set (step S250), and the command setting process is called (step S251). The operation of the command set process will be described later in detail.

In step S250, the start address of the command transmission table (ROM) in which the payout control command relating to the number of prize balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of prize balls includes INT data (01
(H)), the first byte of the payout control command (F
0 (H)), and the data of the second byte of the payout control command are set. However, "80 (H)" is set as the second byte of data.

As described above, when the payout control command for instructing the number of prize balls is output from the game control means to the payout control board 37, the address setting of the command transmission table regarding the number of prize balls and the setting of the transmission buffer are performed. Is done. Then, by the command setting process, the payout control command is sent to the payout control board 37 based on the command transmission table regarding the number of prize balls and the setting contents of the transmission buffer. In step S247, it is possible to confirm whether or not there is data by the difference between the write pointer and the read pointer. However, a counter indicating the number of unprocessed data in the ring buffer is provided, and the data is present according to the count value. You may confirm whether or not.

Then, the content of the total prize ball number storage buffer is 0.
If not, that is, if there is still a prize ball left, C
The PU 56 turns on the prize ball payout flag (step S
252, S253).

When the prize ball payout flag is on (step S254), the CPU 56 monitors the number of prize balls actually paid out from the ball payout device 97 and stores the total prize ball number storage buffer. The number of prize balls subtraction processing for subtracting the value is performed (step S255). When the prize-ball paying-out flag changes from on to off, the lamp control board 3
5, a lamp control command for instructing lighting of the prize ball lamp 51 is transmitted.

Upon receipt of the payout stop state designation command, the payout control means stops both the ball payout as a prize ball and the ball payout as a ball lend. When the payable state designation command is received, both the ball payout as a prize ball and the ball payout as a ball lend are made possible. However, from the game control means to the payout control means, a payout control command for stopping or restarting ball payout as a prize ball and a payout control command for stopping or restarting ball payout as a ball lending are different control commands. You may make it transmit as.

In addition, in this embodiment, even when the payout is stopped (steps S201 and S206), the step S
The processing of 221 to S251 is executed. That is, the game control means can send a payout control command for instructing the number of prize balls even in the payout stopped state.
That is, the command for instructing the number of prize balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is released, the prize ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of prize balls based on the winning in the payout stop state.

Further, in this embodiment, the processing of steps S221 to S251 is executed regardless of the payout status of the game medium. That is, the game control means can send a payout control command for instructing a new prize ball number, regardless of whether or not the specified number of prize balls has been paid out up to the previous time. Therefore, it is possible to reduce the processing load related to the payout of the game control means, and to quickly perform the prize ball payout processing.

FIG. 30 is a flow chart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process processing shown in FIG. 30 is shown in FIG.
This is a specific process of step S16i in the flowchart of FIG. CPU56, when performing the special symbol process processing, fluctuation reduction timer subtraction processing (step S310)
After performing step S300-
Any one of S309 is performed. The fluctuation reduction timer is a timer for setting the fluctuation time when the fluctuation time of the special symbol is shortened. In this example, the time is measured based on the value of the general-purpose timer stored in the timer state storage area (for example, by performing the same processing as in FIG. 34 and FIG. 35 described later), and the variation time of the special symbol. Is to be shortened.

Special symbol fluctuation waiting processing (step S30
0): A winning ball is won in the starting winning opening 14 and the starting opening switch 1
Wait for 4a to turn on. When the starting opening switch 14a is turned on, if the number of memory for winning the winning prize is not full, the number of memory for winning the winning prize is incremented by 1 and a random number for jackpot determination and the like are extracted.

Special symbol determination processing (step S301):
When the variable display of the special symbols can be started, the number of memory for winning the winning start is confirmed. If the number of memory for winning a prize is not 0,
Depending on the value of the extracted big hit determination random number, it is decided whether to make a big hit or not.

Stop symbol setting process (step S302):
The stop symbol of the left and right middle symbols is determined.

Reach operation setting process (step S30)
3): It is determined whether or not the reach operation is performed based on the combination of the stop symbols in the left and right, and when the reach is determined, the reach variation period is determined according to the value of the variation pattern determination random number. decide.

All symbol variation start processing (step S30
4): The variable display device 9 is controlled so that all the symbols start changing. At this time, to the symbol control board 80, the left and right middle final stop symbols and the information instructing the variation mode are transmitted. Further, in this example, the variable time timer is set. The fluctuation time timer is a timer for setting the ending time of the fluctuation of the special symbol. When the processing is completed, the internal state (process flag) is updated so as to shift to step S305.

All symbol stop waiting processing (step S30
5): Predetermined time (time indicated by the fluctuation time timer set in step S304. If it is determined in step S310 that the fluctuation time is to be shortened, the time that the decision is reflected is reflected. When) is passed, all the symbols displayed on the variable display device 9 are stopped.
Then, when shifting to the big hit gaming state, the internal state (process flag) is updated so as to shift to step S306. If not, the internal state is updated to shift to step S300.

Special winning opening opening processing (step S30
6): Start the control for opening the special winning opening. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. In addition, the process timer sets the execution time of the process during opening of the special winning opening, and the big hit flag (a flag indicating that the big hit is in progress)
Set. When the processing is completed, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30
7): The control for sending the display control command data of the special winning opening round display to the symbol control board 80, the processing for confirming the establishment of the closing condition of the special winning opening, etc. are performed. When the final closing condition for the special winning opening is satisfied, the internal state is updated so as to shift to step S308.

Specific area effective time processing (step S30
8): The presence or absence of passage of the V winning switch 22 is monitored, and the processing for confirming the establishment of the jackpot gaming state continuation condition is performed. When the conditions for continuation of the jackpot gaming state are satisfied, and there are still remaining rounds, the internal state is updated so as to shift to step S306. If the jackpot gaming state continuation condition is not satisfied within a predetermined effective time, or if all the rounds are finished, the internal state is set to step S.
Update to move to 309.

Big hit end processing (step S309): Display for notifying the player that the big hit game state has ended. When the display ends, the internal state is updated so as to shift to step S300.

FIG. 31 is a flow chart showing the processing for determining that the hit ball has won the starting winning opening 14. When the ball hits the starting winning opening 14 provided on the game board 6, the starting opening switch 14a is turned on. For example, in the special symbol variation waiting process of step S300 of the special symbol process process, as shown in FIG. 31, the CPU 56 determines that the starting opening switch 14a is turned on via the switch circuit 58 (step S41), and starts. It is confirmed whether or not the winning award memory number has reached the maximum value of 4 (step S42). As described in steps S231 to S233, it is determined whether or not the starting opening switch 14a is turned on, the information regarding the state of the starting opening switch 14a stored in the switch state saving area, and the input determination value table ( The determination is made based on the determination value corresponding to the starting port switch 14a set to (see FIG. 29). If the number of memory of winning a prize for winning does not reach 4, the number of memory of starting award winning is increased by 1 (step S43), and the random number for jackpot determination stored in the counter state saving area in the counter state setting process of step S16c described above Extract the value of each random number. Then, they are stored in the random value storage area corresponding to the value of the number of memory for winning the winning prize (step S4).
4). It should be noted that if the number of memory for winning a prize for winning has reached 4, the process for increasing the number of memory for starting a prize is not performed. That is, in this embodiment, it is possible to store the number of hit balls that are won in the maximum of four starting winning openings 14. Furthermore, in this example,
If the variable display of the display symbol can not be started (the state in which the variable display process of the display symbol is not executed) (N of step S45), the number of starting winning prizes stored after the addition in step S43 is stored as a reserved number. The area is stored (step S46), and the transmission setting of the lamp control command for turning on the corresponding holding lamp of the start storage indicator 18 is set (step S47). The reserved number storage area is provided in a predetermined area of the RAM 55, for example.

In the special symbol process processing of step S26, the CPU 56 confirms the value of the number of stored winning awards as shown in FIG. 32 (step S30). If the number of memory of winning prizes for starting is not 0, the value stored in the random number storage area corresponding to the number of memory of winning prizes for starting = 1 is read (step S31), and the value of the number of memory of winning prizes for starting is decreased by 1,
At the same time, the value in each random value storage area is shifted (step S32). That is, the number of memory for winning a prize for start = n (n = 2,
Each value stored in the random number value storage area corresponding to (3, 4) is stored in the random number value storage area corresponding to the number of memory for winning start winnings = n-1. Next, the CPU 56 sets the number of stored winning awards stored in the reserved number storage area and the step S
Comparing with the current number of starting prize winning memory subtracted in 53,
If the values are different (the number of memory for the current starting winning prize is 1
In the case of (small), the transmission setting of the lamp control command for turning off the corresponding holding lamp of the starting storage indicator 18 is performed, and the processing for storing the current starting winning prize storage number in the holding number storage area is performed (step S33). ). In this way, if the variable display of the display symbol can be started, the process of turning on the hold lamp of the start memory indicator 18 is not executed, and the hold value of the start memory indicator 18 is held using the stored value in the hold number storage area. Since it is configured to determine whether or not to turn off the lamp, when the variable display of the display symbol based on the start detection is made immediately after the start detection is made, the start storage indicator 18 is held by the start detection. Since the process of turning on / off the lamp is not executed, it is possible to prevent the holding lamp of the start memory indicator 18 from turning on for a moment. Note that the above-described processing of FIGS. 31 and 32 is performed by one common module (in this case, if it is determined as “Y” in step S45, the process proceeds to step S30). It is desirable to be carried out.

Then, the CPU 56 determines the hit / miss based on the value read in step S31, that is, the value of the extracted random number for big hit determination (step S34). Here, the big hit determination random number is 0 to 299.
The value in the range of is decided. As shown in FIG. 33, when the probability is low, for example, when the value is “3”, it is determined as “big hit”, and when it is any other value, “out”
To decide. When the probability is high, for example, the value is “3”,
If it is any one of "7", "79", "103", and "107", it is determined as "big hit", and if it is any other value, it is determined as "outlier".

When it is determined that the big hit, the big hit symbol determination random number (random 3) is extracted and the big hit symbol is determined according to the value (step S35). In this embodiment, each symbol of the symbol numbers set in the jackpot symbol table according to the value of the extracted random 3 is determined as the jackpot symbol. In the big hit symbol table, symbol numbers in the left and right corresponding to each of a combination of a plurality of kinds of big hit symbols are set. In addition, step S31
The variation pattern of the symbol is determined based on the value read in step 1, that is, the value of the extracted variation pattern random number (random 4) (step S56).

If it is determined that the data is out of alignment, the CPU 56
Decides the stop symbol when it is not a big hit. In this embodiment, the left symbol is determined according to the value read in step S31, that is, the value of the extracted random 2-1 (step S37). Also, random 2-2
The medium symbol is determined according to the value of (step S38). Then, the right symbol is determined according to the value of Random 2-3 (step S39). Here, when the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the value of the random number corresponding to the middle symbol is set as the middle symbol stop symbol so that it does not match the big hit symbol. To do.

Further, when the left and right symbols are the same, that is, when it is determined that the reach is established, the CPU 56 reads the value read in step S31, that is, the extracted fluctuation pattern determining random numbers. A pattern variation pattern is determined based on the value of (random 4) (step S40).

Note that, for example, in the case of a high probability state, it is possible to use a variation pattern having a reduced variation time as the variation pattern at the time of deviation. By doing so, it is possible to increase the number of fluctuations per hour and give the player many opportunities to be a big hit.

As described above, it is determined whether the display mode of the symbol variation based on the starting winning is the big hit, the reach mode, or the off mode, and the combination of the respective stop symbols is determined.

The process shown in FIG. 32 is step S30 in the special symbol process process shown in FIG.
This corresponds to the process when the processes of 1 to S303 are collectively shown.

As described above, in this example, each random number is updated by the timer interrupt process (steps S22 to S23),
In the main process, after copying the random number value to the counter state saving area (step S16c), it is confirmed that the game medium has won the starting winning opening (confirmed based on the stored information in the switch state saving area). Under this condition (step S41), each random number value stored in the counter state saving area is extracted and stored in the random number value storage area (step S44), and then stored in the random number value storage area. Using each random number value, it is determined whether or not to make a big hit. Therefore, it is possible to reliably update the random number data every predetermined period, and it is possible to eliminate the possibility that the update interval becomes large, so that the state in which the random number data has a specific value continues for a long time. It is possible to prevent the inconvenience caused by doing so.

FIG. 34 is a flow chart showing an example of the variable time timer setting process. This variation time timer setting process is included in the all symbol variation start process in step S304. In the variable time timer setting process, the CPU 56
Extracts the value of the general-purpose timer stored in the timer state storage area (step S304a). Next, by adding the variation time (N) to the extracted value (T) of the general-purpose timer, the value (T + N) of the general-purpose timer at the end of the fluctuation
Is calculated (step S304b), and the calculated value (variation end time value: T + N here) is stored in a predetermined area of the RAM 55, for example (step S304c). By storing the variation end time value as described above, the variation time timer is set.

FIG. 35 is a flow chart showing an example of the timeout check process. This timeout check process is included in the all symbol stop waiting process of step S305. CPU in the timeout check process
56 extracts the value of the general-purpose timer stored in the timer state storage area (step S305a). Next, in step S304c described above, the fluctuation end time value stored in the RAM 55 is read, and it is confirmed whether or not the fluctuation end time value and the value of the extracted general-purpose timer match (step S305b). Then, when the fluctuation end time value and the value of the general-purpose timer match, the CPU 56 issues a display control command (decision command) for instructing to stop the variable display of the special symbol as if the fluctuation time timer has timed out. Send out. That is, in this example, the general-purpose timer functions as a variable time timer that measures the variable time.

As described above, the general-purpose timer (operation timer) is updated in the timer interrupt process (step S25),
In the main process, after the value of the general-purpose timer is read out and stored (set) (step S16d), the set value of the general-purpose timer is used to determine whether or not the variable time timer has timed out. ing.
Therefore, the operation timer can be surely updated every predetermined period, and the operation timer can function accurately. Therefore, the fluctuation time timer realized by the operation timer will function accurately, and the fluctuation time of the special symbol can be accurately controlled, which causes a deviation in operation in the gaming machine. Can be prevented.

Next, a method of sending a control command from the game control means to each electric component control means will be described. When the control command is to be output from the game control means to another electric component control board (sub board), the start address of the command transmission table is set. Figure 3
FIG. 6A is an explanatory diagram showing a configuration example of a command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the 1st byte.
The MODE data of the first byte of the control command is set in the command data 1 of the second byte. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

The EXT data itself may be set in the command data 2 area, but the command data 2
May be set with data for designating the address of the table in which the EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, command data 2 is EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
In this embodiment, if the work area reference bit is 1, it indicates that the content of the transmission buffer is used as the EXT data. If the work area reference bit is 1, the other 7 bits can be configured to indicate that the other 7 bits are an offset for designating the address of the table in which the EXT data is stored.

FIG. 36 (B) is an explanatory diagram showing a structural example of INT data. Bit 0 in the INT data indicates whether or not the payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, the CPU 56
For example, in the prize ball process (step S32 of the main process), "01 (H)" is set in the INT data. Also,
Bit 1 in the INT data is the design control board 80.
Indicates whether or not the display control command should be sent. If bit 1 is "1", it indicates that the display control command should be sent. Therefore, the CPU 56 sets "02 (H)" to the INT data in the special symbol command control process (step S28 of the main process), for example.

Bits 2 and 3 of the INT data are bits indicating whether or not to send a lamp control command and a sound control command, respectively, and the CPU 56 outputs a special command at the timing to send these commands. In the symbol process processing or the like, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When sending those commands, the corresponding bit of the INT data is set to "1", and the command data 1 and the command data 2 are MOD.
E data and EXT data are set.

In this embodiment, for the payout control command, a ring buffer and a transmission buffer are prepared as shown in FIG. 36 (C). Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. Also, when sending the payout control command regarding the number of prize balls,
One data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 36C, the ring buffer can store data corresponding to 12 payout control commands. That is, there are 12 buffers. The number of buffers in the ring buffer may be any number corresponding to the number of winning openings for generating prize balls. This is because even if the simultaneous winnings occur, it is possible to store the payout control command data based on the respective winnings.

FIG. 37 is an explanatory diagram showing an example of the command form of the control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always "1", and the first bit (bit 7) of the EXT data is always "0". As described above, the control command, which is a command to the electric component control board, is composed of a plurality of data, and can be distinguished by the leading bit. Note that the command form shown in FIG. 37 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used. Further, although FIG. 37 exemplifies the payout control command sent to the payout control board 37,
The control commands sent to the other electric component control boards have the same configuration.

FIG. 38 is an 8-bit control signal CD0-CD forming a control command for each electric component control means.
7 is a timing diagram showing the relationship between 7 and the INT signal. As shown in FIG. 38, when the period indicated by A elapses after the MODE or EXT data is output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data. INT which is a signal
Set the signal to high level (on data). When the period indicated by B elapses, the INT signal is set to low level (off data). Furthermore, if there is data to be sent next, that is, after sending the MODE data, the data of the second byte is sent to the output port after a period indicated by C. Regarding the data of the second byte, the periods A and B are the same as the case of the first byte.
In this way, the capture signal is output for each of MODE and EXT data.

The period A is a period for the CPU 56 to prepare for sending a command, that is, a period required for setting a sending command in the buffer, and is a period for stabilizing data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal as a capture signal is output after a predetermined period (period of A: part of the off output period) has elapsed. Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the OFF output period) is a period in which the electric component control unit is set so that the data can be reliably fetched. In the period of B and C,
The data on the signal line does not change. That is, the data output is maintained until the B and C periods elapse.

In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal for the first byte to the start of the transmission of the data of the second byte, is longer than the reception processing time in the electric component control means that takes the longest time for the command reception processing. Is also set to be long.

Note that each electric component control means detects that the INT signal has risen, and starts the processing of fetching 1-byte data by, for example, interrupt processing.

Since the periods B and C are longer than the reception processing time in the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing to each electric component control means by the common module. However, any electric component control means can surely receive the control command from the game control means.

The CPU 56 becomes ready to send the next data when a predetermined period of time elapses after executing the INT signal output process, but during the predetermined period (B and C periods),
It is longer than the period (period A) from the transmission of data before the T signal output process to the start of output of the INT signal. As described above, the period A is the stabilization period in the command signal line, and the periods B and C are the periods for ensuring the time required for the receiving side to take in the data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can surely receive the command, and the transmission of one command is completed. There is also an effect that the period required for is shortened.

FIG. 39 is an explanatory diagram showing an example of the contents of the payout control command. In this example, a plurality of types of payout control commands are used to execute the payout control. Figure 3
In the example shown in FIG. 9, MODE = FF (H), EX
The command FF00 (H) of T = 00 (H) is a payout control command (payable state designation command) for instructing that the payout is possible. MODE = FF (H), EX
The command FF01 (H) of T = 01 (H) is a payout control command (payout stop state designation command) for instructing that the payout should be stopped. Also, MODE
The command F0XX (H) of = F0 (H) is a payout control command (payout number designating command) for designating the number of prize balls. “XX”, which is EXT, indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout ball payout and the ball lending are stopped, and FF00.
When the payout control command (H) is received, prize balls can be paid out and balls can be lent. Further, when the payout control command for designating the number of prize balls is received, the prize ball payout control according to the number designated by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the level of the INT signal changes, and “recognitionally being sent only once” means that in this example, the payout control signal is sent to each of the first byte and the second byte. Accordingly, the INT signal is output only once in a pulse shape (rectangular wave shape).

A control command for each electric component control board is
When outputting to the corresponding output port (output ports 1 to 4), one of the bits 0 to 3 of the output port 0 becomes "1" (high level) for a predetermined period. And the bit array in the output port 0 correspond to each other. Therefore, when the control command is sent to each electric component control board, the INT signal can be easily output based on the INT data.

FIG. 40 is an explanatory diagram showing an example of the contents of the display control command sent to the symbol control board 80. In the example shown in FIG. 40, commands 8000 (H) -80
XX (H) (X = any value of 4 bits) is a display control command that specifies a variation pattern of the special symbol in the variable display device 9 that variably displays the special symbol. The command for designating the variation pattern also serves as a variation start instruction.

Commands 8F00 (H) and 8F01
(H) is a special symbol power-on designation command and a normal symbol power-on designation command that are sent out when the power is turned on. The normal symbol power-on time designation command is used when the display control means normally performs the symbol variation control, and when the normal symbol display device 10 is controlled by the lamp control means, it is sent to the symbol control board 80. Not done. When the display control means receives the special symbol power-on time designation command, it starts the control for initial display.

Commands 91XX (H), 92XX (H)
And 93XX (H) is a display control command for designating the left middle right stop symbol of the special symbol. Also, command A
000 (H) is a display control command (decision command) for instructing to stop the variable display of special symbols.

The command BXXX (H) is a display control command sent from the start of the big hit game to the end of the big hit game. The command B300 (H) is a command to be sent a predetermined number of times at a predetermined timing during the big hit game (for example, the number of rounds-1 times at a timing at which a big hit symbol is displayed during each round). It is a display control command (big hit symbol display command) for designating the display of symbols. Also, the command CXXX
(H) is a display control command relating to the display state of the variable display device 9 which is not related to the variation of the special symbol and the big hit game. Then, the commands D000 (H) to D400
(H) is a display control command relating to a variation pattern of a normal symbol.

When the display control means of the symbol control board 80 receives the above-mentioned display control command from the game control means of the main board 31, according to the contents shown in FIG. Change the display status.

FIG. 41 is an explanatory diagram showing an example of the contents of the lamp control command sent from the main board 31 for controlling the game to the lamp control board 35. The lamp control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 41, the command 80XX (X = any value of 4 bits) is a lamp control command for designating a lamp / LED display control pattern corresponding to the variation pattern of the special symbol in the variable display device 9. Although not shown, the command A0XX (H) is a lamp control command for instructing the lamp / LED display control pattern when the variable display of the special symbol is stopped, and the command BXXX (H) is
Ramp from the big hit game start to the big hit game end
It is a lamp control command for instructing an LED display control pattern. The command 9001 (H) is a lamp control command for instructing the lamp / LED display control pattern at the customer waiting demonstration.

The commands 8XXX (H), 9XXX
(H), AXXX (H), BXXX (H) and CXX
X (H) is a lamp control command sent from the game control means according to the game progress status. When the lamp control means receives the above-mentioned lamp control command from the game control means of the main board 31, it changes the display state of the lamp / LED according to the contents shown in FIG. In addition, command 8
XXX (H), 9XXX (H), AXXX (H), BX
XX (H) and CXXX (H) are commonly used with a display control command and a voice control command, for example, in a common control state.

The command E1XX (H) is a lamp control command indicating the number of lighting of the start memory indicator 18. For example, the lamp control means turns on the number of displays designated by “XX (H)” in the start memory display 18. Further, the command E0XX (H) is a lamp control command indicating the number of lights of the normal symbol starting memory display 41. For example, the lamp control means normally turns on the number of display devices designated by "XX (H)" in the symbol starting memory display device 41. That is, those commands are commands for instructing the control of the light-emitting body provided for notifying the information of the number of holdings. The command regarding the number of lighting of the starting memory display 18 and the normal symbol starting memory display 41 may be configured to indicate the increase or decrease of the number of lighting.

Commands E200 (H) and E201
(H) is a lamp control command relating to the display state of the prize ball lamp 51, and includes commands E300 (H) and E3.
01 (H) is a lamp control command related to the display state of the out-of-bulb lamp 52. The lamp control means is the main board 3
When the lamp control command of "E201 (H)" is received from the game control means of No. 1, the display state of the prize ball lamp 51 is changed to a predetermined display state when there is a prize ball remaining, and the lamp of "E200 (H)" is displayed. When the control command is received, the display state of the prize ball lamp 51 is changed to a predetermined display state as when there is no prize ball remaining. When the lamp control command of "E300 (H)" is received from the game control means of the main board 31, the display state of the out-of-ball lamp 52 is changed to the display state with a ball, and the lamp control command of "E301 (H)" is issued. When it is received, the display state of the out-of-ball lamp 52 is changed to the in-bulb display state. That is, the command E2
00 and E201 (H) are commands indicating that a light emitting body provided for notifying a player or the like that there is a non-prize game ball, and a command E300.
(H) and E301 (H) are commands indicating that the light emitter provided to notify the player or the game store staff that the supply ball is out is controlled.

FIG. 42 is an explanatory diagram showing an example of the contents of a voice control command sent from the main board 31 for controlling a game to the voice control board 70. Voice control commands are also MOD
It has a 2-byte structure of E and EXT. In the example shown in FIG. 42, the command 80XX (H) (X = an arbitrary value of 4 bits) is a voice control command for designating the sound generation pattern in the variable period of the special symbol. Command BXXX
(H) is a voice control command that specifies a sound generation pattern from the start of the big hit game to the end of the big hit game. Other commands are voice control commands that are not related to special symbol variations and jackpot games. When the voice control means of the voice control board 70 receives the above-mentioned voice control command from the game control means of the main board 31, it changes the voice output state according to the contents shown in FIG.

FIG. 43 is a flow chart showing a processing example of the command set processing (steps S205, S209, S251). The command set process is a process including a command output process and an INT signal output process. In the command setting process, the CPU 56 first saves the address of the command transmission table (contents of the pointer as the transmission signal instruction means) to the stack or the like (step S3).
31). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore,
The address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sends the command data 1
Is read out and is set to the argument 2 (step S334).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S335).

FIG. 44 is a flow chart showing the command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351).
Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of the output port for outputting the payout control signal. Further, the addresses of the ports 2 to 4 are the addresses of the output ports for outputting the display control signal, the lamp control signal and the voice control signal.

Next, the CPU 56 shifts the comparison value right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S355). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (ie, MODE data) is output to the address set as the IO address (step S3
56). When the first shift processing is performed, the address of port 1 is set as the IO address, so the MODE data of the payout control command is set to port 1 at that time.
Is output to.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the processing number (step S358). When the port 1 is shown before the addition, the address of the port 2 is set to the IO address by the addition process for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0,
It returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not the lamp control command and the sound control command should be sent. In this way, when each shift process is performed, the IO address has the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process. It is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
A control command is sent to. That is, one common module can perform a process of sending a control command to each electric component control means.

Further, in this way, since the control command to which the control command should be output is determined only by the shift processing, it is determined to which electric component control means the control command should be output. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 in which the INT data before the shift processing is started (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is a port for outputting the INT signal for each control signal, and bit 0 of port 0
4 to 4 are the payout control INT signal and the display control IN, respectively.
It is a port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and decrements by 1 until the value becomes 0 (steps S363, S36).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S36).
5) output the data to port 0 (step S3)
66). Therefore, the INT signal becomes low level. Then, a predetermined value is set in the wait counter (step S3
62), and subtracts 1 by 1 until the value becomes 0 (steps S368 and S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time that is generated in steps S367 to S369 and the subsequent processing time (if MODE data is output at this time, the time required for control until the EXT data is output). ) Is the period added. By setting the period of C in this way,
Even when the commands are continuously sent, a predetermined period of time elapses after the output of one command is completed and before the sending of the next command is started, and the electric component control means for receiving the command. On the side of, the command delimiters can be easily identified and each command is reliably received.

Therefore, the value set in the wait counter in step S367 is set so that the period C is a period sufficient for surely performing the command receiving process by all the electric component control means which are the control command receiving targets. Value. The value set in the wait counter is
The value is longer than the time (corresponding to the period A) required for the processes of steps S357 to S359. In addition, A
If it is desired to lengthen the period A, a wait process for creating the period A (for example, a process of setting a predetermined value in the wait counter and performing subtraction until the value of the wait counter becomes 0) is performed.

As described above, the 1st byte MODE data of the control command is transmitted. Therefore, CPU5
In step S336 shown in FIG. 43, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S339). If it is not 0, the contents of the transmission buffer are loaded into the argument 2 (step S341). If the extended data is used when the value of the work area reference bit is "1", the start address of the command extended data address table is set in the pointer and the command data is set in the pointer. The address is calculated by adding the values of bit 6 to bit 0 of 2. Then, the data of the area pointed to by the address is loaded into the argument 2.

Since the data capable of specifying the number of prize balls is set in the transmission buffer, the data is set in the argument 2. If the extended data is used when the value of the work area reference bit is “1”, the command extended data address table contains
EXT data that can be sent to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table according to the content of the command data 2 is loaded into the argument 2.

Next, the CPU 56 calls the command transmission processing routine (step S342). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent out.

As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte structure is transmitted to the corresponding electric component control means. The electric component control means starts the control command fetching process when the rising edge of the INT signal is detected, but for any electric component control means, a new signal from the game control means is signaled before the fetching process is completed. It is never printed on the line. That is, a reliable command reception process is performed in each electric component control means. In addition, each electric component control means is
The control command acquisition process may be started at the falling edge of the T signal. Also, the polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, in the prize ball processing, when the prize ball payout condition is satisfied, the data capable of specifying the number of prize balls is stored in the ring buffer capable of storing a plurality of data at the same time. When the payout control command designating the is sent, the data in the area of the ring buffer pointed by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of prize ball payout conditions are satisfied at the same time, the data capable of specifying the number of prize balls based on the satisfaction of those conditions is stored in the ring buffer, so that the command output process based on the satisfaction of each condition does not pose a problem. To be executed.

Furthermore, in this embodiment, both the payout stop state designating command or the payable state designating command and the command indicating the number of prize balls can be sent in one prize ball process. That is, a series of processes that are regarded as a repeating unit of the game control process (step S1)
A plurality of commands can be sent within the period in which the processing from 6a to step S16p) is executed. Further, in this embodiment, since a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, payout control command) to each control means, for example, When data capable of specifying the control command is set in the ring buffer of the control command, the lamp control command, and the sound control command, a plurality of display control commands, lamp control commands, and sound control commands can be performed by one command control process. Can also be configured to deliver. That is, a plurality of control commands can be sent at the same time (meaning that the game control processing is repeated (not necessarily in a fixed cycle)). Since the transmission timings of those control commands occur at the same time in the progress of the game production, it is convenient to have such a configuration. However, since the payout control command is generated irrespective of the progress of the game effect, it is generally not sent at the same time as the display control command, the lamp control command and the sound control command.

FIG. 45 is a flowchart showing an example of the prize sphere number subtracting process. In the process of subtracting the number of prize balls, C
The PU 56 first loads the value stored in the total prize ball number storage buffer (step S381). Then, it is confirmed whether the stored value is 0 (step S382). If it is 0, the process ends.

If not 0, the above-mentioned step S16b
Load the switch timer for the prize ball count switch stored in the switch state storage area at (step S
383), load value and ON determination value (“2” in this case)
And are compared (step S384). If they match (step S385), it is determined that the prize ball count switch 301A is surely turned on, that is, one game ball is surely paid out from the ball payout device 97, and the stored value of the total prize ball number storage buffer is set. 1 is subtracted (step S386).

Also, the value of the prize ball information counter is incremented by 1 (step S387). When the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information output counter is incremented by 1 (step S38).
9), the value of the prize ball information counter is decremented by 10 (step S
390). The value of the prize ball information output counter is as shown in FIG.
Reference is made in the information output process (step S16m) in the game control process shown in, and if the value is 1 or more, one pulse is output as the prize ball signal. Therefore, in this embodiment, each time 10 game balls are paid out as prize balls, one prize ball signal is output to the outside of the gaming machine.

When the value stored in the total award ball storage buffer becomes 0 (step S391), the award ball payout flag is cleared (step S392) to notify that there is no remaining award ball. After the command data indicating that the prize ball lamp 51 is turned off is set in the command transmission table for the lamp control command (step S393), the lamp control command sending process is executed (step S394).

Next, the payout control means will be described as an example of the electric component control means other than the game control means.

FIG. 46 is a block diagram showing an example of the structure around the payout control CPU 371. As shown in FIG. 46, a power-off signal from a power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to a non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via a buffer circuit 960. There is. Therefore, the payout control CPU 37
1, it is possible to confirm the occurrence of the stop of power supply to the gaming machine by the non-maskable interrupt process.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. Then, when the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt will occur in response to the input of the INT signal.

A system reset circuit 975 is also mounted on the payout control board 37, but in this embodiment,
Reset IC 97 in system reset circuit 975
When the power is turned on, 6 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level after the predetermined time has elapsed. Also, reset IC9
Reference numeral 76 monitors the power supply voltage of VSL and sets the output to a low level when the voltage value becomes a predetermined value (for example, + 9V) or less. Therefore, when the power supply to the gaming machine is stopped, the reset IC 9
When the signal from 76 goes low, the payout control CPU 371 is system reset.

The predetermined value for the reset IC 976 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the payout control CPU 371 can operate for a while. Further, the reset IC 976 is used for the payout control CPU 3
Since it is configured to monitor a voltage higher than the voltage required by 71 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the payout control CPU 371. Therefore, more precise monitoring can be performed. The system reset circuit 975 corresponds to the second power supply monitoring means.

While the power is not being supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, so that a power failure or the like occurs. Contents are saved even when power supply to the gaming machine is stopped. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, at the time of recovery from a power failure or the like, the payout control state at the time of power failure can be restored.

In the structure shown in FIG. 46, system reset circuit 975 outputs a low level for a period determined by the capacitance of the capacitor when the power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
Similarly to the case of 1, the circuit configuration in which the reset release timing occurs a plurality of times may be used.

FIG. 47 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 47, the input port A (address 06H) is an input port for taking in the 8-bit payout control signal of the payout control command sent from the main board 31. Further, the detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Detection signal is input.

FIG. 48 shows payout control means (CP for payout control).
7 is a flowchart showing a main process of U371 and peripheral circuits such as ROM and RAM. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and the stack pointer designated address is set to the stack pointer (step S703). Further, the payout control CPU 37
1 initializes built-in device registers (step S704), and initializes CTC and PIO (step S704).
After performing 705), the RAM is set to the accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the built-in device register setting processing of step S704 and the processing of step S705, register setting for setting the channel to be used in timer mode, register setting for permitting interrupt generation, and register for setting interrupt vector Settings are made. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set in the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, a switch input process and a timer update process are executed.

Further, another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving the payout control command from the game control means, and that channel is used. Is used in counter mode. Therefore, in the built-in device register setting processing of step S704 and the processing of step S705, in order to set the register setting for setting the channel to be used in the counter mode, the register setting for permitting interrupt generation, and the interrupt vector. Register setting is performed.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set the interrupt processing start address according to the interrupt vector sent by the CTC.

An interrupt based on the count-up of channel 2 (CH2) of CTC is an interrupt that occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as the specific register
An initial value "1" is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rising or falling of the signal input to the CLK / TRG2 terminal. You can make a choice. In this embodiment, the timer counter register CLK / TRG is output at the rising edge of the signal input to the CLK / TRG2 terminal.
The count value of 2 is set to -1.

The CTC channel 3 (CH3) count-up interrupt is generated when the internal clock (system clock) of the CPU is counted down and the register value becomes "0". 2m
s Used as a timer interrupt. Specifically, CPU3
A clock obtained by dividing the operation clock of 71 is given to the CTC, the value of the register is subtracted by the input of the clock, and when the value of the register becomes 0, a timer interrupt is generated.
For example, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the CH3 register.

The interrupt based on the count-up of CH2 of CTC has a higher priority than the interrupt based on the count-up of CH3. Therefore, when count-ups occur at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process is prioritized.

Next, the payout control CPU 371 confirms the state of the output signal of the clear switch 921 inputted through the input port only once (step S707).
When ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S713). Clear switch 92
When 1 is ON (when it is pressed), the low level clear switch signal is output. In addition,
At the input port 372, the on state of the clear switch signal is high level. Further, in the payout control means,
The determination in step S707 may not be performed.

Note that, like the CPU 56 of the main board 31, the payout control CPU 371 also determines whether the ON state is at least 2 when it makes the ON determination of the switch detection signal.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms) does not continue, it is not considered to be switch-on, but when the clear switch 921 is detected to be on, ON / OFF is determined by the ON determination. That is, it is determined whether or not the clear switch 921 as the operating means is in a predetermined operating state.
The initialization request detection determination period for U371 to determine is
The period is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detecting means has detected the game medium.

If the clear switch 921 is not turned on, the payout control CPU 371 confirms whether or not backup data exists in the payout control backup RAM area (step S708). For example, similar to the processing of the CPU 56 of the main board 31, whether or not backup data exists is determined by whether or not the backup flag that is set when the power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) of the backup RAM area. When the power is restored after the power supply is stopped due to an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, it is not possible to return the internal state to the state at the time of stopping the power supply, so the initialization process that is executed when the power is turned on is executed instead of when the power is restored from an insufficient power failure.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power supply was stopped (step S710). Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
First performs a RAM clear process (step S71).
1). Then, the CTC provided in the payout control CPU 371 so that a timer interrupt is periodically applied every 2 ms.
The register is set (step S712). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Since the interrupt is prohibited in step S701 of the initialization process, the interrupt is permitted before the initialization process is completed (step S713).

Execution of initialization processing (steps S711 to S)
When 713) is completed, the payout control process is repeatedly executed in the main process as shown in FIG. In the payout control process, the payout control CPU 371 first sets an interrupt prohibited state (step S751) and then performs a switch state setting process (step S752). In the switch state setting process, stored contents (an example of input information) of a switch-on counter (in this example, a prize ball count switch-on counter, a ball lending count switch-on counter, which will be described later) are mounted on the payout control board 37. A process of copying to the switch state saving area provided in the RAM is performed. Also, the timer state setting process (step S75
In 3), the value of each timer such as a general-purpose timer (an example of numerical data) is stored in the payout control board 37 in the RAM.
The process of copying to the timer state saving area provided in. That is, each state setting process (step S75
2. In step S753), the current switch timer value and each timer value stored in predetermined areas of the RAM mounted on the payout control board 37 are mounted on the payout control board 37, respectively. A process of copying to another area (a switch state saving area and a timer state saving area in this example) provided in the existing RAM is executed. Therefore, each state setting process (step S75
2. The switch timer and the state of the timer at the time when step S753) is executed are copied to the switch state saving area and the timer state saving area, respectively. Each state setting process (step S752, step S7
When step 53) ends, the interrupt enabled state is set (step S754). As described above, in the present example, when each state setting process (step S752, step S753) is executed, the interrupt prohibited state is set. The switch state saving area and the timer state saving area are provided in the backup RAM area of the RAM mounted on the payout control board 37.

In the payout control process, the payout control CPU
371 first confirms the stored information in the switch state setting area, and if the prize ball count switch 301A or the ball lending count switch 301B or the like input to the input port 372b is on, the corresponding game ball Subtract the number of payouts (Payout number subtraction process: step S75
5).

Next, the payout control CPU 371 sets the payout stop state when the payout stop state designation command is received from the main board 31, and releases the payout stop state when the payable state designation command is received. (Payment stop state setting process: step S756). Further, the received payout control command is analyzed, and the process according to the analysis result is executed (command analysis execution process: step S757). Further, prepaid card unit control processing is performed (step S758).

Next, the payout control CPU 371 controls the payout of the lent balls in response to the ball lending request (step S759). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls stored in the total number memory (step S760). At this time, the payout control CPU 371 sets the ball distribution member 311 to the prize ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the 72c and the relay board 72 to perform payout motor control processing for rotating the payout motor 289 for a predetermined number of rotations (step S761). .

In this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control process, eight types of excitation pattern data are repeatedly output to the payout motor 289. Further, in this embodiment, each excitation pattern data is output by 4 ms. The output period of the excitation pattern data is measured in the same manner as the motor rotation time timer described later. Further, when the game balls are paid out by using the solenoid instead of the payout motor 289, the measurement of the excitation period of the solenoid (for example, the on / off period for paying out one game ball) will be described later. It may be performed in the same manner as the motor rotation time timer.

Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S762). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S763).

In this embodiment, the payout control CPU 3
71 built-in CTCs are set to repeatedly generate timer interrupts. In this embodiment, the repetition period is 2
Set to ms. And when a timer interrupt occurs,
The timer interrupt process shown in FIG. 49 is executed. In the timer interrupt process, the payout control CPU 371 performs the register saving process (step S720), and then the prize ball count switch 301A and the ball lending count switch 30.
A detection signal of a switch such as 1B (an example of an input state detection unit) is input to determine the states thereof, and a process of storing the input state of the detection signal of the switch in a switch-on counter described later (switch input process: Step S72
1).

Next, the value of each timer such as a general-purpose timer (operation timer) for managing the operation time of the gaming machine is incremented by 1 (step S722). After that, the contents of the register are restored (step S723) and the interrupt enabled state is set (step S724).

According to the above control, in this embodiment, the processing in steps S721 to S722 is 2 m.
It will be activated every s. In this embodiment, steps S721 to S7 are performed in the timer interrupt process.
Although the process of 22 is executed, the timer interrupt process may set only a flag indicating that an interrupt has occurred, and the processes of steps S721 to S722 may be executed in the main process. .

As described above, the input information indicating the input state of the input state sensing means is stored in the timer interrupt processing (step S721), and the input information is read out and stored in the switch state storage area in the main processing ( After the setting (step S752), the control related to the payout (steps S755 to S763) is performed using the storage information in the switch state storage area. Even if the input information is updated after the start of the process, it is possible to prevent an unprocessed part from remaining in the payout control process, and solve the inconvenience caused by not completing the series of payout control processes.

Also, the operation timer (for example, general-purpose timer) is updated and stored in the timer interrupt processing (step S722), and the stored operation timer value (numerical data) is read out in the main processing. After saving (setting) in the state save area (step S753), the control related to payout (step S755 to step S763) is performed using the save information in the timer state save area, so the operation timer is updated for a predetermined period. It can be done reliably every time, and the operation timer will function correctly,
It is possible to prevent an operational deviation from occurring in various operations executed in the gaming machine.

FIG. 50 is a flow chart showing an example of the payout state recovery process of step S710. In the payout state recovery process, the payout control CPU 371 first performs a stack pointer return process (step S73).
1). The value of the stack pointer is saved in a predetermined RAM area (power source is backed up) in the power supply stoppage process described later. Therefore, step S7
At 31, the value in the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the payout control CPU 371 clears the backup flag (step S732), that is, resets the flag indicating that the predetermined storage protection process has been executed at the previous power supply stop. Further, the saved values of various registers are read from the stack area and set in the various registers (step S733). That is,
Performs register restoration processing. Then, when the parity flag is not turned on, the interrupt enable state is set (step S
734, S735). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S736).

Then, the RET instruction is executed, but the return destination here is not the portion that called the payout state recovery processing. This is because the stack pointer restoration process is performed in step S731, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred at the time of the previous power supply stop in the program. Therefore, the next RET instruction in step S736 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

By the above processing, the backup RAM
Based on various information stored in the area, the payout state is restored to the state before the power was cut off. In this example, the switch state save area and the timer state save area are provided in the backup RAM area, so the value of the switch-on counter saved in each state save area is maintained even when the power supply is stopped. , And the timer value is not lost, and the payout control using these pieces of information is restored.

FIG. 51 is a flow chart showing an example of a non-maskable interrupt process (NMI process: power supply stop process) which is executed in response to a power-off signal from the power supply board 910.

In the power supply stop process, the payout control CPU 371 sets the AF register to a predetermined backup R.
It is saved in the AM area (step S801). Also, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether it is in the interrupt permitted state or the interrupt prohibited state, and is in the control register built in the payout control CPU 371. The ON state of the interrupt flag indicates that the interrupt is disabled. As described above, the parity flag is referred to in the game state recovery process. Then, in the payout state recovery process, if the parity flag is in the ON state, the interrupt permission state is not set.

Also, BC register, DE register, HL
The registers, IX register and stack pointer are saved in the backup RAM area (steps S804-8).
08).

Next, the designated value with backup ("55H" in this example) is stored in the backup flag. The backup flag is formed in the backup RAM area. Then, a process similar to the process of the CPU 56 of the main board 31 is performed to create parity data and backup R
It is stored in the AM area (steps S810 to S819).
Then, an access prohibition value is set in the RAM access register (step S820). After that, the built-in RAM cannot be accessed. When the access prohibition value is set in the RAM access register, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

FIG. 52 is an explanatory diagram showing a usage example of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number memory (for example, 2 bytes) and a rental ball number memory are formed.
The total number storage stores the total number of prize ball payout numbers instructed from the main board 31 side. The loaned ball number storage is for storing the number of unpaid lent balls. In addition,
The backup RAM area is not limited to the area for storing the above-mentioned information regarding the number of game balls, and various kinds of flags such as a flag indicating an error state such as a payout stop flag, an award ball path error flag, and a backup flag, which will be described later, for example. An area for storing flags, an area for storing various buffers such as a reception command buffer, and the like are also formed. Further, in this example, the switch state saving area and the timer state saving area are also formed in the backup RAM area. Further, the RAM area in which the data used in the payout control process is stored may be backed up by power supply.

Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in the prize ball control process (step S760), for example, the contents are stored in the total number memory. To increase. In addition, in the ball lending control process (step S759), each time the ball lending request signal is received from the card unit 50, the content is increased to the lending ball number storage by one unit (for example, 25 pieces). Further, the payout control CPU 3
71 indicates that the award ball count switch 301A detects one award ball payout in the switch input process (step S721), and the payout amount subtraction process (step S755).
When the confirmation is made on the basis of the storage information in the switch state storage area, the value of the total number storage is decremented by 1. In addition, when it is confirmed in the switch input process (step S721) that the ball lending count switch 301B has detected one lending ball payout based on the stored information in the switch state saving area in the payout amount subtraction process (step S755), Decrease the value of the number of lent balls stored by 1.

Therefore, the number of unpaid prize balls and the number of lent balls are backup RAs that can retain their contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply interruption such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the stored contents of the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is made based on the number of unpaid prize balls and the number of lent balls when the power supply is stopped, and is given to the player. The disadvantage can be reduced.

FIG. 53 is an explanatory diagram showing a configuration example of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type reception buffer that can store six 2-byte payout control commands is used. Therefore, the reception buffer is composed of 12-byte areas of the reception command buffers 1 to 12. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter takes a value of 0-11.

FIG. 54 is a flow chart showing the payout control command receiving process by the interrupt process. The payout control INT signal from the main board 31 is sent to the payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 54 is started. In addition, CP for payout control
The U371 is a CPU having a structure in which, when an interrupt occurs, no further maskable interrupt occurs unless the interrupt is permitted by software.

Although the command receiving process of the payout control means will be described here, the same command receiving process is executed by the display control means, the lamp control means and the sound control means. In this embodiment, CLK /
Although the initial setting was made such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the TRG2 terminal rises, that is, the initial setting is made such that an interrupt occurs at the rising edge of the INT signal. CLK / TRG
When the input of 2 terminals falls, timer counter register C
Initialization may be performed such that the value of LK / TRG2 is decremented by one. In other words, the initialization may be performed so that an interrupt occurs at the falling edge of the INT signal.

That is, if the interrupt is generated at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the capture signal, the edge may be a rising edge or a falling edge. It may be. In any case, the interrupt is configured to occur at the level change timing (edge) of the pulse-shaped (rectangular wave-shaped) INT signal as the acquisition signal. By doing so, it becomes possible to receive the command promptly at the stage when the command acquisition is instructed. In addition, the period of A (Fig. 3
Since the output of the INT signal is waited until 8), the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output.
Therefore, the payout control command is properly received by the payout control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
Data is read from 72a (see FIG. 7) (step S
851). Then, it is confirmed whether or not it is the first byte of the payout control command having a 2-byte structure (step S8).
52). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is "1". The first bit is "1" in the MODE byte (first byte) of the payout control command having a 2-byte structure (see FIG. 37). Therefore, if the leading bit is "1", the payout control CPU 371 determines that the valid first byte has been received and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step). S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

If the first byte has already been received,
It is confirmed whether the first bit of the received 1 byte is "0". If the first bit is "0",
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The head bit is “0”, which is supposed to be the EXT byte (second byte) of the payout control command having a 2-byte structure (see FIG. 37). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not "0". If it is determined as "N" in step S854, the process of step S856 is not performed, so the command received next is stored in the buffer area where the command received this time should have been stored. It

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether the command reception counter is 12 or more (step S857), and if it is 12 or more, the command reception number counter is cleared (step S858). After that, the saved registers are restored (step S859),
Finally, the interrupt permission is set (step S860).

During the command reception interrupt process, the interrupt is disabled. As described above, since the interrupt is enabled during the 2ms timer interrupt process, if a command reception interrupt occurs during the 2ms timer interrupt process, the command reception interrupt process is executed with priority. It Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since the other interrupt processing is not executed during the command receiving processing, the maximum time required for the command receiving processing is determined. If the other interrupt processing can be executed during the command receiving processing, it is difficult to estimate the maximum time required for the command receiving processing. Since the maximum time required for the command receiving process is determined, the period C in the command sending process of the game control means (see FIG. 38)
Can be accurately determined.

Also, the payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX
It is configured so that it can be immediately distinguished from T) on the receiving side.
That is, the receiving side can immediately detect whether the data as MODE or the data as EXT is received by the first bit. Therefore, as described above, it is possible to easily determine whether or not proper data has been received.

In this embodiment, in the command reception interrupt processing, control for storing the received command in the reception buffer is performed. (See FIG. 58)
May be configured to be executed in the command reception interrupt processing. In this way, when even the command determination processing for determining the command in the reception buffer is executed in the command reception interrupt processing, the command determination is also executed promptly.

FIG. 55 is a flow chart showing an example of the switch input process of step S721 in the timer interrupt process. The switch input process is executed once every 2 ms because it is executed in the timer interrupt process. In the switch input process, the payout control CPU 371 confirms whether or not the prize ball count switch 301A is in the ON state (step S721a). If it is in the ON state, the payout control CPU 371 increments the prize ball count switch ON counter by 1 (step S721b). The prize ball count switch ON counter is a counter for counting the number of times the ON state of the prize ball count switch 301A is detected.

When it is confirmed in step S721a that the prize ball count switch 301A is not in the ON state, the payout control CPU 371 clears the prize ball count switch ON counter (step S721c). Next, it is confirmed whether or not the ball lending count switch 301B is in the ON state (step S721d). If it is in the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by 1 (step S721e). The ball lending count switch ON counter is a counter for counting the number of times the ON state of the ball lending count switch 301B is detected.

When it is confirmed in step S721d that the ball lending count switch 301B is not in the ON state, the payout control CPU 371 clears the ball lending count switch ON counter (step S721f).

FIG. 56 is a flow chart showing an example of the payout amount subtraction processing of step S755. In the payout amount subtraction processing, the payout control CPU 371 reads out the count switch-on counters (in this example, the prize ball count switch-on counter and the ball lending count switch-on counter) from the switch state storage area. The stored contents of the count switch-on counter are copied to the switch state storage area in the switch state setting process (step S752) described above.

Next, the payout control CPU 371 checks the value of the read prize ball count switch on counter (step S755b), and if the value is 2, it is determined that one prize ball has been paid out. to decide. When it is determined that one prize ball has been paid out, the payout control C
The PU 371 decrements the prize ball unpaid counter (the number of prize balls stored in the total number memory) by -1 (step S755).
c).

Further, the payout control CPU 371 checks the value of the read ball lending count switch on counter (step S755d), and if the value is 2, it is determined that one lending ball has been paid out. to decide. When it is determined that one loan ball has been paid out, the payout control CPU 371 decrements the unpaid ball unpaid number counter (the number of loan balls stored in the loan ball number storage) by -1 (step S755e). ).

FIG. 57 is a flow chart showing an example of the payout stop state setting processing in step S756. In the payout stop state setting process, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S756a). If there is a receive command in the receive buffer, it is confirmed whether the received payout control command is a payout stop state designation command (step S).
756b). If it is the payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S756c).

When it is confirmed in step S756b that the received command is not the payout stop state designation command, it is confirmed whether or not the received payout control command is the payout possible state designation command (step S756d). If it is a payable state designation command, the payout stop state is canceled (step S756e).

When setting the payout stop state,
For example, the driving of the payout motor 289 is stopped, and an internal flag (payment stopped flag) indicating that the payout is stopped is set. When the payout stop state is released, the driving of the payout motor 289 is restarted and the payout stop flag is reset. That is, in step S756c, data indicating that payout is prohibited (set payout suspension flag)
Is being executed in the predetermined storage area, and in step S756e, the processing for storing the data indicating that the payout is permitted (the reset payout suspension flag) in the predetermined storage area is executed. It is running.

The discontinuation flag is stored in, for example, the backup RAM area. The payout suspension flag has a 1-byte structure including bits D0 to D7, for example. In this case, for example, if D0 is "1", it indicates the state in which the dispensing stop state is set, and if D1 is "1", it indicates the state in which the dispensing stop state is released. Further, D2 is used, for example, to indicate that it is in a waiting state for returning after the payout stop state is released. Note that D3 to D7 are unused areas.

FIG. 58 is a flow chart showing an example of the command analysis execution processing of step S757. In the command analysis execution processing, the payout control CPU 371
It is confirmed whether or not there is a receive command in the receive buffer (step S757a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for designating the number of prize balls (step S7).
57b). The payout control CPU 371 makes the determination in step S757b for the received command stored in the address in the reception buffer pointed to by the read pointer as the command instruction means. After the determination, the value of the read pointer is incremented by +1. When the address pointed to by the read pointer exceeds the address of the reception command buffer 12 (see FIG. 53), the value of the read pointer is updated to point to the reception command buffer 1.

If the received payout control command is the payout control command for designating the number of prize balls, the number designated by the payout control command is added to the total number storage (step S757c). That is, the payout control CPU 371
Stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

If necessary, the payout control CPU 371 performs the subtraction of the command reception number counter and the reception command shift processing in the reception buffer. Further, the payout stop state setting process and the command analysis execution process may be repeated until the value of the read pointer and the latest command storage position in the reception buffer match. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands, but the repeated processing is executed until they match. , There are no outstanding received commands. That is, all the received commands stored in the reception buffer are read and processed in one process.

FIG. 59 is a flow chart showing an example of the prepaid card unit control processing in step S758. In the prepaid card unit control process, the payout control CPU 371 confirms whether or not the VL signal input from the card unit control microcomputer is detected (step S758a). If the VL signal is not detected, the value of the general-purpose timer is extracted from the timer state saving area (step S758b). If the VL signal non-detection timer has not been set (step S7)
58c N), a value (non-connection state determination value) obtained by adding the non-connection state determination time to the value of the extracted general-purpose timer is calculated (step S758d). The non-connection state determination time is VL
This is the time during which the non-detection state of the signal continues, and the predetermined time during which it is determined that the signal is in the non-connection state. In this example,
The non-connection state determination time is 250 ms. Then, the calculated non-connection state determination value R provided in the payout control board 37
It is saved in a predetermined area of AM (step S758e).
The VL signal non-detection timer is set by storing the non-connection state determination value.

If the VL signal non-detection timer has already been set (Y in step S758c), the payout control CPU 371 determines that the value of the extracted general-purpose timer and the set non-connection state determination value are equal to each other. It is confirmed whether or not they match (step S758f). If they match, it is determined that the VL signal non-detection timer has timed out, and the output of the firing control signal to the firing control board 91 is stopped, and the drive motor 94 is stopped.
Is stopped (step S758g). By the above processing, when the OFF of the VL signal is detected continuously for 250 ms (= 2 ms × 125), the ball firing prohibited state is set. In this example, as described above, the general-purpose timer is
It is also used to determine whether or not the prepaid card unit is in a non-connected state, and plays a role of a VL signal non-detection timer that measures a non-detection period of the VL signal.

When the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection timer (step S758h). Specifically, if the non-connection state determination value is set, processing for clearing the value is performed. And the payout control CPU 3
If the firing control signal output is stopped (step S758i), the 71 starts the firing control signal output to the firing control board 91 to make the drive motor 94 operable (step S758j).

60 and 61, step S759 is executed.
It is a flow chart which shows an example of the ball lending control processing of.
In addition, in this embodiment, the maximum value of the continuous payout number is one unit (for example, 25) of the lending sphere, but the maximum value of the continuous payout number may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is suspended (step S510). If it is stopped, the process ends.
Whether or not the ball lending is being stopped is confirmed by whether or not the payout stopping flag set in the payout stop state setting process shown in FIG. 57 is turned on.

If the ball lending is not stopped, the payout control CP
The U371 confirms whether or not the lending of balls is in progress (step S511), and if the lending of balls is in progress, the process proceeds to the process of lending balls shown in FIG. 61. In addition, whether or not the lent-out of the lent-out sphere is being performed is determined by the state of the lent-out-of-ball-lending flag described later. If the loan balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S512). Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending balls nor the prize balls are being paid out, the payout control CPU 371 confirms whether or not there is a ball lending request from the card unit 50 (step S5).
13). To confirm whether or not there is a ball lending request, in this example,
This is performed by checking the state of the BRQ signal stored in the switch state storage area. Specifically, in the switch input process (step S721) of the timer interrupt process, the state of the BRQ signal is confirmed and stored in a predetermined area of the RAM included in the payout control board 37. Then, in the switch state setting process (step S752) of the main process, the information indicating the state of the BRQ signal stored in the switch input process is copied to the switch state storage area. In step S513, the state of the BRQ signal stored in the switch state storage area as described above is confirmed,
If the BRQ signal is in the ON state, it is determined that there is a ball lending request from the card unit 50. Strictly speaking, when the rising of the BRQ signal is detected from the state of the BRQ signal stored in the switch state storage area, it is determined that there is a ball lending request.

If there is a ball lending request, the ball lending processing flag is turned on (step S514), and 25 (one unit of ball lending: 100 yen in this case) is backed up RA.
The number of lent balls in the M area is set to be stored (step S51)
5). Then, the payout control CPU 371 turns on the EXS signal (step S516). In addition, the ball dispensing device 9
The distribution solenoid 310 is driven to set the ball distribution member 311 below 7 on the ball lending side (step S51).
7). Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized the acceptance. The ball lending processing flag is set in the backup RAM area.

Next, the payout control CPU 371 is set to 25
The motor rotation time timer for measuring the motor rotation time for paying out the individual game balls is set (step S518). Specifically, the value of the general-purpose timer is extracted from the timer state saving area, and a value (rotation end determination value) is calculated by adding the motor rotation time to the extracted value of the general-purpose timer.
Then, the calculated rotation end determination value is stored in a predetermined area of the RAM included in the payout control board 37. By thus storing the rotation end determination value, the motor rotation time timer is set. When the motor rotation time timer is set, the payout motor 289 is turned on (step S51
9), and shifts to the processing during ball lending shown in FIG. 61.

FIG. 61 is a flowchart showing the processing during ball lending in the payout control processing by the payout control CPU 371. In the ball lending process, the payout motor 289 is turned on if it is not turned on. In addition, in this embodiment,
Switch input processing in step S721 and step S
In the payout number subtraction processing of 755, it is confirmed whether or not the game balls have been paid out based on the detection signal of the ball lending count switch 301B. Therefore, in the ball lending control processing, the subtraction of the number of loaned balls is not performed.

CP for payout control in the ball lending control process
U371 confirms whether or not it is during the lending ball passage waiting time (step S520). If it is not during the waiting time for passing the rental ball, the rental ball is paid out (step S521),
It is confirmed whether or not the driving of the payout motor 289 should be ended (whether one unit of payout operation is ended) (step S52).
2). The confirmation as to whether or not the rotation corresponding to the predetermined number of payouts is completed is made by confirming whether or not the motor rotation time timer has timed out. Specifically, the value of the general-purpose timer is extracted from the timer state storage area, and it is confirmed whether or not the extracted value of the general-purpose timer matches the set rotation end determination value. If they match, it is determined that the motor rotation time timer has timed out. When the motor rotation time timer times out, the rotation end determination value is cleared. as mentioned above,
In this example, the general-purpose timer is also used to determine whether or not the driving of the payout motor 289 should be ended, and also serves as a motor rotation time timer for measuring the rotation time of the payout motor 289.

When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 causes the payout motor 28
The driving of No. 9 is stopped (step S523), and the lending ball passage waiting time is set (step S524). Specifically, extract the value of the general-purpose timer from the timer state saving area,
A value (passing waiting end determination value) is calculated by adding the lending sphere passing waiting time to the extracted value of the general-purpose timer. Then, the payout control board 37 includes the calculated passage waiting end determination value R
Save in a predetermined area of AM. By storing the passage waiting end determination value in this way, the lending sphere passing waiting time timer is set, and the lending sphere passing waiting time is set. The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B.

If it is in the lending ball passage waiting time in step S520 (the lending ball passage waiting time timer is set), the payout control CPU 371 confirms whether or not the lending ball passage waiting time has ended. Do (step S52
5). To confirm whether the waiting time for passing the rental ball has ended,
It is performed by confirming whether or not the loan-ball waiting time timer has timed out. Specifically, the value of the general-purpose timer is extracted from the timer state storage area, and it is confirmed whether or not the extracted value of the general-purpose timer matches the set passage waiting end determination value. If they match, it is determined that the lending ball passage waiting time timer has timed out and the lending ball passage waiting time has ended. If the lending sphere passage waiting time timer times out, the passage waiting end determination value is cleared. As described above, in this example, the general-purpose timer is also used to determine whether or not the lending ball passage waiting time has expired. It also plays a role.

When the end of the waiting time for passing the loan ball is confirmed,
Since one unit of lent balls has been paid out, the EXS signal is turned off to indicate that the next lent request can be accepted for the card unit 50 (step S526). The distribution solenoid is turned off (step S527), and the ball lending processing flag is turned off (step S528). If the last payout ball has not passed the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. Further, in this embodiment, both the prize balls and the ball lending are performed by the same payout device.

If the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period after turning off the EXS signal indicating acceptance of the ball lending request, the distribution solenoid and the payout motor The ball lending process may be continued without turning off. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be continuously executed.

The content of the number of rented balls is stored by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the game machine is stopped. Therefore, when the power supply is restored within the predetermined period, the payout control CPU 371 can continue the ball lending process based on the content of the loan ball number storage.

62 and 63, step S760 is executed.
It is a flow chart which shows an example of the prize ball control processing. In addition, in this example, the maximum value of the continuous payout amount is set to the same number as one unit of the lending sphere (for example, 25), but the maximum value of the continuous payout amount may be another number.

In the prize ball control processing, the payout control CPU
The 371 first confirms whether or not the prize ball is stopped (step S530). If it is stopped, the process ends. Whether or not the prize ball is stopped is confirmed by whether or not the payout stop flag set in the payout stop state setting process shown in FIG. 57 is turned on.

If the prize ball is not stopped, the payout control CPU
The 371 confirms whether or not the lending balls are being paid out (step S531), and if the lending balls is being paid out, the process is ended. Whether or not the ball lending is being paid out is determined by the state of the ball lending processing flag. If the payout of the rented balls is not in progress, it is confirmed whether or not the prize ball payout processing has already been started, that is, whether or not the prize balls are being paid out (step S53).
2). If it is in the prize ball, the process moves to the process in the prize ball shown in FIG. Whether or not a prize ball is in play is determined by the state of a prize ball processing flag, which will be described later.

If the prize ball is not being paid out, the payout control CPU
371 confirms whether the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number memory is 2.
It is confirmed whether it is 5 or more (step S536). The prize ball processing flag is set in the backup RAM area.

If the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 measures 25 motor payout time for paying out the 25 game balls. Set the timer (step S
537). Specifically, the value of the general-purpose timer is extracted from the timer state saving area, and a value (rotation end determination value) is calculated by adding the motor rotation time for paying out 25 gaming balls to the extracted value of the general-purpose timer. To do. Then, the calculated rotation end determination value is stored in a predetermined area of the RAM included in the payout control board 37. By storing the rotation end determination value in this way, the 25-piece dispensing operation timer is set.

If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 determines the motor rotation time for paying out the game balls according to the number stored in the total number memory. An all-pieces payout operation timer is set for measurement (step S538). Specifically, extract the value of the general-purpose timer from the timer state saving area,
A value (rotation end determination value) is calculated by adding the motor rotation time for paying out the number of game balls stored in the total number memory to the extracted value of the general-purpose timer. Then, the calculated rotation end determination value is stored in a predetermined area of the RAM included in the payout control board 37. By storing the rotation end determination value in this manner, the all-pieces payout operation timer is set. Next, the payout motor 289 is turned on (step S539). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the prize ball side. Then, the process shifts to the process of paying out prize balls in the prize ball control process shown in FIG.

FIG. 63 is a flow chart showing an example of a prize ball process in the payout control process by the payout control CPU 371. In the prize ball control processing, the payout motor 289
If is not on, turn it on. In this embodiment, in the switch input process of step S721 and the payout amount subtraction process of step S755, it is confirmed whether or not the game balls are paid out by the detection signal of the prize ball count switch 301A. In the control process, the total number storage is not subtracted.

[0372] In processing during prize balls, the payout control CPU
The 371 confirms whether or not it is during the prize ball waiting time (step S540). If it is not during the prize ball passage waiting time, whether or not the prize balls should be paid out (step S541) and the driving of the payout motor 289 should be ended (whether the payout operation of 25 or a predetermined number of less than 25 has ended). Is confirmed (step S542). Whether or not the rotation corresponding to the predetermined number of payouts is completed is set to 25.
This is performed by checking whether the individual dispensing operation timer or the all-piece dispensing operation timer has timed out. Specifically, extract the value of the general-purpose timer from the timer state saving area,
It is confirmed whether or not the extracted value of the general-purpose timer matches the set rotation end determination value. If they match, it is determined that the set 25-piece payout operation timer or the set total-piece payout operation timer has timed out.
When the 25-piece dispensing operation timer or the all-piece dispensing operation timer times out, the set rotation end determination value is cleared. As described above, in this example, the general-purpose timer is also used to determine whether or not the driving of the payout motor 289 should be ended, and the rotation of the payout motor 289 for paying out the 25 game balls. Measure time 2
It also plays the role of a five-piece payout operation timer and the role of an all-pieces payout operation timer that measures the rotation time of the payout motor 289 for paying out a predetermined number of game balls less than 25.

When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 causes the payout motor 28
The driving of No. 9 is stopped (step S543), and the prize ball passing waiting time is set (step S544). In particular,
The value of the general-purpose timer is extracted from the timer state storage area, and a value (passing waiting end determination value) is calculated by adding the prize ball passage waiting time to the extracted value of the general-purpose timer. Then, the RAM provided in the payout control board 37 with the calculated passage waiting end determination value.
In a predetermined area of. By thus saving the passage waiting end determination value, the prize ball passage waiting time timer is set, and the prize ball passage waiting time is set. The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

If it is in the prize ball passage waiting time in step S540 (the state where the prize ball passage waiting time timer is set), the payout control CPU 371 confirms whether or not the prize ball passage waiting time has ended. Perform (step S545). Whether or not the prize ball passage waiting time has ended is confirmed by confirming whether or not the prize ball passage waiting time timer has timed out. Specifically, the value of the general-purpose timer is extracted from the timer state storage area, and it is confirmed whether or not the extracted value of the general-purpose timer matches the set passage waiting end determination value. If they match, it is determined that the prize ball passage waiting time timer has timed out and the prize ball passage waiting time has ended. If the prize ball passage waiting time timer times out, the passage waiting end determination value is cleared. As described above, in this example, the general-purpose timer is also used to determine whether or not the prize-ball passing waiting time has expired, and the prize-ball passing waiting time timer for measuring the prize-ball passing waiting time is used. It also plays a role.

When the prize ball passage waiting time is over, all the prize balls set in step S537 or step S538 have been paid out. Therefore, C for payout control
If the prize ball passage waiting time has ended, the PU 371 turns off the prize ball processing flag (step S546). If the last payout ball has not passed the prize ball count switch 301A before the prize ball passage waiting time has elapsed, a prize ball path error is determined.

In this embodiment, step S5
11, the ball lending is prioritized over the prize ball processing according to the determination in step S531, but the prize ball processing may be prioritized over the ball lending.

The contents of the total number storage and the number of rented balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored within a predetermined period, the payout control C
The PU 371 can continue the payout process based on the content of the total number storage.

Note that the payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number memory, but for each prize ball number (for example, 15, 10, 6, 6).
Individual). For example, in the switch input process (step S721) of the timer interrupt process, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by +1. To do. Then, in the switch state setting process (step S752) of the main process, the contents of the number counter are copied to the switch state saving area,
When the award ball payout corresponding to the number counter stored in the switch state storage area is performed in the payout number subtraction process (step S755), the number counter is decremented by one. Also in that case, each number counter and the switch state saving area are formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored within a predetermined period, the payout control CPU 371 continues the prize ball payout process based on the contents of the number counters and the switch state saving area. be able to.

Next, error processing will be described. Figure 6
4 is an error type and an error display LED 374 (see FIG. 7).
It is an explanatory view showing the relation with the display of (refer). In addition, FIG.
5 and FIG. 66 are flowcharts showing an example of the error processing in step S762.

In this example, in the error processing, the payout control CPU 371 displays the error display LED 37 when the prize ball path error flag is turned on (step S601).
"0" is displayed in 4 (step S602). Further, when the prize ball route error flag is turned off, LE for error display is displayed.
The display "0" of D374 is erased (step S60).
3). The prize ball path error flag indicates that the prize ball payout process is being executed in the prize ball control process.
Within a predetermined period (in this example, a general-purpose timer is used to measure time)
Information that the prize ball count switch 301A has not been turned on, the save information of the timer state save area (the value of the general-purpose timer)
Set when confirmed using. The confirmation as to whether or not the predetermined period has elapsed is performed in the same manner as the confirmation as to whether or not the motor rotation time has elapsed described in the ball lending control process (the same applies hereinafter).

When the ball lending route error flag is turned on (step S604), "1" is displayed on the error display LED 374 (step S605). Also, when the ball lending route error flag is turned off, the error display LED
The display "1" of 374 is erased (step S606).
Note that the ball lending route error flag indicates that the ball lending count is within the predetermined period (in this example, a general-purpose timer is used) even though the ball lending process is executing the lending ball payout process. It is set when it is confirmed that the switch 301B is not turned on by using the save information (the value of the general-purpose timer) in the timer state save area.

When the prize ball clogging flag is turned on (step S607), the error display LED 374 is set to "2".
Is displayed (step S608). Further, when the prize ball clogging flag is turned off, the display "2" of the error display LED 374 is erased (step S609). The award ball clogging flag is set when it is confirmed that the award state of the award ball count switch 301A has continued for a long period of time using the save information (the value of the general-purpose timer) in the timer state save area.

When the loan ball clogging flag is turned on (step S610), "3" is displayed on the error display LED 374 (step S611). Further, when the loan ball clogging flag is turned off, the error display LED 37
The display "3" of 4 is erased (step S612). The ball lending flag is set to the ball lending count switch 3
This is set when it is confirmed that the ON state of 01B has continued for a long period of time using the save information (the value of the general-purpose timer) in the timer state save area.

When the motor sensor output abnormality is detected (step S613), "4" is displayed on the error display LED 374 (step S614). Also, when the motor sensor output error is released, the error display LED
The display "4" of 374 is erased (step S615).
The motor sensor output abnormality is determined in step S522 shown in FIG. 61 or step S542 shown in FIG.
It is detected when it is confirmed using the save information (the value of the general-purpose timer) of the timer state save area that the motor position sensor has been kept on for a predetermined period or longer and has been kept off for a predetermined period or longer.

When the VL off detection flag is set (step S621), "5" is displayed on the error display LED 374 (step S622). When the VL off detection flag is reset, the error display L
The display "5" on the ED 374 is erased (step S62).
3). The VL off detection flag is set in step S758g shown in FIG.

When communication with the card unit 50 is executed at an irregular timing (step S6)
24), assuming that a prepaid card unit communication error has occurred, "6" is displayed on the error display LED 374 (step S625). When such an error is eliminated, the display "6" of the error display LED 374 is erased (step S626).

[0387] When the dispensing stop state is set (step S627), the error display LED 374 is set to "7".
Is displayed (step S628). When the dispensing stop state is released, the display "7" of the error display LED 374 is erased (step S629). The payout stop state is the state set to the payout stop state in step S756c in FIG. That is, it is a state after the payout prohibition is notified by the payout stop state designation command from the game control means.

In the present embodiment, the ball payout device 9
Since 7 pays out both the prize balls and lends the balls, the payout stop state is a state in which both the prize ball payout and the ball lending are stopped. However, when the payout device for paying out the prize balls and the payout device for lending the balls are provided separately, the LE for error display is displayed.
In D374, the prize ball stop state and the ball lending stop state may be notified separately.

FIG. 67 is a timing chart showing an example of signal processing between the payout control CPU 371 of the payout control board 37 and the card unit 50 during a payout operation by ball lending. As shown in FIG. 67, when the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37,
The PRDY signal is turned on. When the card is accepted in the card unit 50 and the ball lending switch is operated to input the ball lending switch signal, the card unit controlling microcomputer turns on the BRDY signal. When a predetermined delay time (period A) has elapsed from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37. Period A
Is, for example, a period within a range of 30 ms to 50 ms.

When the payout control CPU 371 detects that the BRDY signal is turned on, it extracts the value of the general-purpose timer from the timer state saving area and determines whether the period A is added to the extracted value of the general-purpose timer. The value is calculated and stored in a predetermined area of the RAM provided in the payout control board 37. After that, in the payout control process, the value of the general-purpose timer is extracted from the timer state saving area until the BRQ signal is detected, and it is confirmed whether or not the extracted value of the general-purpose timer matches the set determination value. . If they match, it is determined that the period A has elapsed, and it is determined that a prepaid card unit communication error has occurred. BRQ before matching
When the signal is detected, the set judgment value is cleared. In this example, as described above, it is determined whether or not the period A has passed by using the storage information of the timer state saving area in which the value of the general-purpose timer updated in the timer interrupt process is copied. A timer realized by using a general-purpose timer for measuring the period A is called a communication management timer. In addition,
The communication management timer also means a timer that measures the period B to the period F.

When a predetermined delay time (period B) elapses from the time when the BRQ signal is detected, the payout control CPU 371 of the payout control board 37 sends an E to the card unit 50.
Raise the XS signal. The period B is, for example, 14 ms-
The period is within the range of 10 s. The period B is measured in the same manner as the period A described above. If the EXS signal is not turned on even after the period B has elapsed, it is determined that a prepaid card unit communication error has occurred.

From the time the EXS signal rises, until the predetermined delay time (period C) elapses, the card unit 50
It is monitored whether or not the trailing edge of the BRQ signal from is detected. The period C is, for example, a period within the range of 32 ms to 56 ms. The period C is measured in the same manner as the period A described above. Then, before the period C elapses, the BRQ
If the falling edge of the signal is not detected, it is determined that a prepaid card unit communication error has occurred.

When the falling edge of the BRQ signal from the card unit 50 is detected, the payout motor 289 is driven to pay out a predetermined number of lent balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. If the fall of the EXS signal is not performed until the predetermined delay time (period D) has elapsed from the detection of the fall of the BRQ signal, it is determined that a prepaid card unit communication error has occurred. The period D is, for example, 10 ms
The period is within the range of 10 s. The period D is measured in the same manner as the period A described above.

If the BRQ signal is detected by the time the predetermined delay time (period E) elapses after the EXS signal is lowered, the next ball payout operation is started. Period E
Is, for example, a period within 256 ms. Period E
Is measured in the same manner as the period A described above. On the other hand, E
If the OFF of the BRDY signal is detected by the predetermined delay time (period F) after the XS signal is lowered, the ball lending process is terminated. Period F is, for example, 256 m
The period is within s and is the same period as the period E in this example. The period F is measured in the same manner as the period A described above. If the BRQ signal is not detected and the BRDY signal is not turned off before the period E (period F) elapses, it is determined that a prepaid card unit communication error has occurred.

Next, the control processing in the symbol control board 80 will be described. FIG. 68 shows a display control CPU 101.
6 is a flowchart showing a main process executed by the. In the main processing, first, 2 ms for clearing the RAM area, setting various initial values, and determining the display control activation interval.
Initialization processing for initializing the timer and the like is performed (step S770). Then, in this embodiment,
The display control CPU 101 shifts to loop processing for repeatedly performing display control processing. In the display control process, the display control CPU 101 first sets the interrupt prohibited state (step S771), and then the counter state setting process (step S771).
At 772), a process of copying the count value (an example of numerical data) of each counter used in the symbol control board 80 to the counter state saving area provided in the RAM included in the symbol control board 80 is performed. Then, in the timer state setting process (step S773), a process of copying the value (an example of numerical data) of each timer such as a general-purpose timer to the timer state saving area provided in the RAM is performed.
That is, in each state setting process (steps S772 to S773), the current count value of each counter and each timer value stored in a predetermined area of the RAM included in the symbol control board 80 are respectively stored in the RAM.
A process of copying to another area (in this example, the counter state saving area and the timer state saving area) provided in the. Therefore, each state setting process (step S7
The states of the counter and the timer at the time of executing steps 72 to S773) are copied to the counter state saving area and the timer state saving area, respectively. When each state setting process (step S772 to step S773) is completed, the interrupt permission state is set (step S77).
4). As described above, in the present example, when each state setting process (step S772 to step S773) is executed, the interrupt prohibited state is set. The counter state saving area and the timer state saving area are provided in the backup RAM area of the RAM.

Next, the display control CPU 101 analyzes the received display control command (command analysis execution process: step S775). In addition, the display control CPU 10
1 performs display control process processing (step S77).
6). In the display control process process, a process corresponding to the current control state is selected and executed from the processes according to the control state.

In this embodiment, it is assumed that the timer interrupt is taken every 2 ms. That is, the timer interrupt process is activated every 2 ms. FIG. 69 is a flowchart showing the timer interrupt processing. In the timer interrupt process, the display control CPU 101 performs a register save process (step S780), and then updates the count value of the counter for generating a random number for reach advance determination in this example. (Step S781). Further, the display control CPU 101 performs a process of updating the count value of the counter for generating a random number for determining a big hit announcement (step S782).

In addition, the value of each timer such as a general-purpose timer (effect timer) for managing each effect time such as variable display effect on the symbol control board 80 is incremented by 1 (step S783). After that, the contents of the register are restored (step S784), and the interrupt enabled state is set (step S784).
785).

According to the above control, in this embodiment, the processing of steps S781 to S783 is 2 m.
It will be activated every s. In this embodiment, steps S781 to S7 are performed in the timer interrupt process.
Although the processing of 83 is executed, for example, only the flag indicating that an interrupt has occurred is set in the timer interrupt processing, and the processing of steps S781 to S783 may be executed in the main processing. .

As described above, the counter (random number value data) is updated and stored in the timer interrupt process (steps S781 to S782), and the count value of the counter (numerical data) stored in the main process is updated. ) Is read out and stored (set) in the counter state storage area (step S772), and display control is performed using the stored information in the counter state storage area (steps S775 to S7).
Since it is configured to perform 76), it is possible to reliably update the random number value data every predetermined period, and it is possible to eliminate the possibility that the update interval becomes large. Therefore, the random number value data becomes a specific value. It is possible to prevent inconvenience caused by the fact that the operating state continues for a long time.

Further, the effect timer (for example, a general-purpose timer) is updated and stored in the timer interrupt process (step S783), and the stored effect timer value (numerical value data) is read in the main process. After saving (setting) in the state save area (step S773), display control is performed using save information in the timer state save area (step S773).
775 to step S776) is performed, so that the effect timer can be reliably updated every predetermined period,
Since the effect timer comes to function accurately, in various effects executed on the symbol control board 80, it is possible to prevent deviations in effect operation.

The effect timer is, for example, a command non-reception timer, a timer for determining a reach warning start time for measuring the period from when it is determined to give a reach warning until the reach warning is started, and a big hit warning. It is used for a big jackpot announcement start time determination timer that measures the period from when it is determined to when the jackpot announcement is started, and a fluctuation time timer that measures the period from the fluctuation start to the fluctuation end of the special symbol. The specific usage is the same as the case where a general-purpose timer is used as the above-described motor rotation time timer and the like, so detailed description will be omitted here.

FIG. 70 is an explanatory diagram showing display random numbers handled by the display control CPU 101. As shown in FIG. 70,
In this embodiment, as the display random number, there are a reach announcement random number (reach announcement determination random number) and a big hit announcement random number (big hit announcement determination random number). The reach announcement random number is for deciding whether or not the reach announcement is given, and the jackpot announcement random number is for deciding whether or not the jackpot announcement is given. In this example, the reach announcement random number and the big hit announcement random number each have a 1-byte configuration, and take values in the same range of 0 to 255. The reach announcement random number and the big hit announcement random number may be configured to take values in different ranges. Further, in this embodiment, the random number for light emitter handled by the CPU 351 for lamp control and the random number for sound handled by the sound control CPU 701 are set to be in the same range as the display random number shown in FIG. 70. There is. Therefore, in this embodiment, like the display random number, there are the reach announcement random number and the big hit announcement random number as the light emitter random number, and the reach announcement random number and the big hit announcement random number as the sound random number.

FIG. 71 is a flow chart showing the display control process process (step S776) in the main process shown in FIG. In the display control process processing,
Step S830 according to the value of the display control process flag
One of the processes from S835 to S835 is performed. In each process, the following process is executed.

Display control command reception waiting process (step S830): It is confirmed by the command reception interrupt process whether or not a display control command (fluctuation pattern command) capable of specifying the variation time is received. Specifically, it is confirmed whether or not a flag indicating that the variation pattern command has been received is set. Such a flag is set when the received command stored in the received command buffer is a variable pattern command.

Reach notice, big hit notice determination process (step S831): It is determined whether or not to give a reach notice and a big hit notice, and when it is decided to give a notice, the type of notice is decided.

All symbol variation start processing (step S83
2): Control is performed so that the fluctuation of the left and right middle symbols is started.

Processing during symbol fluctuation (step S833): The switching timing of each fluctuation state (fluctuation speed, background, character) forming the fluctuation pattern is controlled, and the end of the fluctuation time is monitored. In addition, stop control of the left and right symbols is performed.

All symbol stop waiting setting process (step S83
4): At the end of the fluctuation time, if the display control command (decision command) for instructing the stop of all symbols is received, the fluctuation of the symbols is stopped and the stop symbol (decision symbol) is displayed.

Big hit display processing (step S835): After the end of the fluctuation time, the probability variation big hit display or the normal big hit display is controlled.

Next, the operation of the lamp control means as the luminous body control means including the lamp control CPU 351 mounted on the lamp control board 35 will be described.

FIG. 72 is a flow chart showing the main processing executed by the lamp control CPU 351. In the main process, the lamp control CPU 351 first executes an initialization process for initializing the registers, the RAM including the work area, the output port and the like (step S44).
1). After that, in this embodiment, the CP for lamp control is used.
The U351 shifts to a loop process for repeatedly performing the lamp control process. In the lamp control process, the CPU for lamp control
351 first sets the interrupt-disabled state (step S
442), counter state setting processing (step S443)
Then, a process of copying the count value (an example of numerical data) of each counter used in the lamp control board 35 to the counter state saving area provided in the RAM included in the lamp control board 35 is performed. Then, in the timer state setting process (step S444), a process of copying the value (an example of numerical data) of each timer such as a general-purpose timer to the timer state saving area provided in the RAM is performed. That is, each state setting process (step S443 to step S443)
444), the current count value of each counter and each timer value stored in a predetermined area of the RAM included in the lamp control board 35 are respectively stored in different areas (in this example,) provided in the RAM. , Counter state saving area, and timer state saving area). Therefore, each state setting process (step S44
The states of the counter and the timer at the time when the steps 3 to S444) are executed are copied to the counter state saving area and the timer state saving area, respectively. When each state setting process (step S443 to step S444) is completed, the interrupt enabled state is set (step S445).
As described above, in this example, each state setting process (step S
When 443 to step S444) are executed, the interrupt disabled state is set. The counter state save area and the timer state save area are backup RAM of RAM.
It is provided in the area.

Next, it is confirmed whether or not the lamp control command is received from the main board 31 (step S446:
Command recognition processing). Also, the lamp control CPU 351
Performs the reach announcement determination process for deciding whether or not to perform the light emitter control regarding the reach announcement based on the value of the reach announcement determination random number stored in the counter state saving area (step S447). Based on the value of the random number for jackpot announcement determination stored in the state storage area, a jackpot announcement determination process for determining whether or not to perform light emitter control regarding the jackpot announcement is performed (step S448).
Then, in accordance with the received lamp control command and the decision result of the reach announcement and the big hit announcement, command execution processing for changing the lamp data to be used is performed (step S449). The lamp control command from the main board 31 is fetched by an interrupt process started in response to the input of the INT signal and stored in the input buffer formed in the RAM.

After that, in this embodiment, the lamp control CPU 351 performs the lamp process update processing and the port output processing (steps S450 and S451).

In this embodiment, the lighting pattern of the lamps / LEDs which are controlled to blink according to the progress of the game is RO
It is controlled according to the lamp data stored in M.
The ramp data is prepared for each type of control pattern (the ramp / LE during the change of the special symbol shown in FIG. 41).
The control command for designating the effect pattern by D and the control command for other game effects sent from the game control means according to the game progress status are prepared for each, and further reach is associated with each of the control commands for specifying the effect pattern. If you give a notice, if you give a big jackpot announcement, if you have a reach announcement and a big jackpot announcement are prepared for each case). For lamp data, lamp / LE
Data indicating that D is turned on or off and data indicating a period of turning on or off (process timer value) are set. That is, data indicating the lighting pattern of the light emitter is stored in the control data area.

In the lamp process update processing, it is determined whether or not the process timer has timed out, based on the value of the effect timer stored in the timer state storage area. Specifically, the production timer value stored in the timer state storage area is set to the process timer value corresponding to the data set to turn off or turn on the lamp / LED, and the production is started based on that data. The process end judgment value is calculated and stored in a predetermined area of the RAM. The effect timer is updated in the timer interrupt process, and the latest effect timer value is copied to the timer state save area in the timer state setting process each time the main process is repeated. Then, it is confirmed whether the value of the effect timer saved in the timer state saving area matches the calculated process end judgment value. If they match, the process timer has timed out. To determine. When it is determined that the process timer has timed out, it is determined to turn off or turn on the lamp / LED according to the data set in the next address in the lamp data, and the process according to the determination result. The timer value is added to the value of the effect timer stored in the timer state storage area to calculate and store a new process end determination value. When the new process end determination value is set, it is when the lighting / lighting is switched. Therefore, in the port output processing, data for lighting or extinguishing the lamp / LED is output to the corresponding output port.

In this embodiment, it is assumed that the timer interrupt is taken every 2 ms. That is, the timer interrupt process is activated every 2 ms. FIG. 73 is a flowchart showing the timer interrupt processing. In the timer interrupt process, the lamp control CPU 351 performs the process of saving the register (step S461) and then, in this example, the process of updating the count value of the counter for generating the random number for the reach advance determination. (Step S462). Further, the lamp control CPU 351 performs a process of updating the count value of the counter for generating the random number for determining the big hit announcement (step S463).

Also, 1 is added to the value of each timer such as a general-purpose timer (effect timer) for managing each effect time of turning on / off the lamp / LED in the lamp control board 35 (step S464). After that, the contents of the register are restored (step S465) and the interrupt enabled state is set (step S466).

According to the above control, in this embodiment, the processing in steps S462 to S464 is 2 m.
It will be activated every s. It should be noted that in this embodiment, the timer interrupt processing is performed in steps S462 to S4.
Although the process of 64 is executed, the timer interrupt process may set only a flag indicating that an interrupt has occurred, and the processes of steps S462 to S464 may be executed in the main process. .

As described above, the counter (random number value data) is updated and stored in the timer interrupt process (steps S462 to S463), and the stored count value of the counter (numerical value data) in the main process. ) Is read out and stored (set) in the counter state storage area (step S443), and then effect control is performed using the stored information in the counter state storage area (steps S446 to S4).
Since the configuration of 51) is performed, the random number value data can be surely updated at every predetermined period, and the possibility that the update interval becomes large can be eliminated, so that the random number value data becomes a specific value. It is possible to prevent inconvenience caused by the fact that the operating state continues for a long time.

Also, the effect timer (for example, a general-purpose timer) is updated and stored in the timer interrupt process (step S464), and the stored effect timer value (numerical value data) is read out in the main process. After saving (setting) in the state save area (step S444), effect control is performed using save information in the timer state save area (step S444).
Since it is configured to perform 446 to step S451), the effect timer can be reliably updated every predetermined period,
Since the effect timer comes to function accurately, it is possible to prevent deviation in the effect from occurring in various effects executed on the lamp control board 35.

The production timer is used, for example, as a process timer. The specific usage is the same as when the general-purpose timer is used as the above-described motor rotation time timer, for example, as described in the lamp process update processing.

Here, the address map of the ROM mounted on the lamp control board 35 will be described. The ROM area includes a control data area and a control program area.
In the control data area, an initialization data table used for initialization of registers, RAM, output ports, etc., a storage display LED display table used for turning on / off control of the start storage indicator 18, etc., and a lamp described later. Data etc. are stored. In the control program area, the main processing program, initialization processing,
Programs for command recognition processing and command execution processing are stored, and programs for specific lamp / LED processing, lamp process update processing, port output processing, command reception interrupt processing, and timer interrupt processing are also stored.

FIG. 74 is an explanatory diagram showing an example of the contents of the lamp data stored in the control data area. In this embodiment, data indicating the lighting pattern of the lamp / LED is stored in the lamp data in the control data area. As the lamp / LED lighting pattern stored in the lamp data, the lamp / LED lighting pattern as shown in FIG. 74 is determined corresponding to the pattern command (80XX (H)). The lighting patterns of the lamps / LEDs when making a reach announcement and the lighting patterns of the lamps / LEDs when making a big hit announcement are determined according to the variation modes. That is, in this example, the lighting patterns of the lamps / LEDs when the reach notice stored in the lamp data is given, and the lamps / LEDs when the big hit notice is given
The lighting pattern of is set so that the lamp / LED is turned on in synchronization with the variation mode of the reach warning display or the big hit warning display executed on the symbol control board 80. Then, in the lamp process update process (step S450) in the main process, turning on / off of the lamp / LED is controlled with reference to the lamp data.

Next, the operation of the sound control means (sound control means) including the sound control CPU 701 mounted on the sound control board 70 will be described.

FIG. 75 is a flow chart showing the main processing executed by the sound control CPU 701. C for sound control
In the main process, the PU 701 first registers,
An initialization process for initializing the RAM including the work area, the output port, etc. is executed (step S471). After that, in this embodiment, the sound control CPU 701 shifts to loop processing for repeatedly performing sound control processing. In the sound control process, the sound control CPU 701 first sets the interrupt prohibition state (step S472), and then, in the counter state setting process (step S473), count values (numerical values of the counters used in the sound control board 70. A process of copying an example of data) to a counter state saving area provided in the RAM included in the sound control board 70 is performed. Then, in the timer state setting process (step S474), the value (an example of numerical data) of each timer such as a general-purpose timer is set to R.
Processing for copying to the timer state saving area provided in the AM is performed. That is, each state setting process (step S4
73 to step S474), the current count value of each counter and each timer value stored in a predetermined area of the RAM provided in the sound control board 70 are respectively stored in different areas (provided in the RAM). In this example, the process of copying to the counter state saving area and the timer state saving area) is executed. Therefore, the states of the counter and the timer at the time when each state setting process (step S473 to step S474) is executed are copied to the counter state saving area and the timer state saving area, respectively. Each state setting process (step S473 to step S4
When step 74) is completed, the interrupt permission state is set (step S475). As described above, in the present example, when each state setting process (step S473 to step S474) is executed, the interrupt prohibited state is set. The counter state saving area and the timer state saving area are provided in the backup RAM area of the RAM.

Next, it is confirmed whether or not a sound control command has been received from the main board 31 (step S476: command recognition processing). Further, the sound control CPU 701 performs the reach advance notice determination processing for determining whether to perform the light emitter control regarding the reach advance notice based on the value of the reach advance announcement determination random number stored in the counter state storage area (step (S477), the jackpot announcement determination process for deciding whether or not to perform the light emitter control regarding the jackpot announcement is performed based on the value of the jackpot announcement random number stored in the counter state storage area (step S478). And
In accordance with the received sound control command and the decision result of the reach announcement and the jackpot announcement, command execution processing is performed, which is processing such as changing the audio data to be used (step S47).
9). The sound control command from the main board 31 is IN
It is fetched by an interrupt process started in response to the input of the T signal and stored in the input buffer formed in the RAM.

Then, in this embodiment, the sound control C
The PU 701 performs voice process update processing and port output processing (steps S480 and S481).

In this embodiment, the voice pattern output from the speaker 27 according to the progress of the game is controlled according to the voice data stored in the ROM. Voice data is prepared for each type of control pattern (see FIG. 4).
It is prepared for each control command for designating the effect pattern by the voice output means during the change of the special symbol shown in 2 and the control command for other game effects sent from the game control means according to the game progress situation, and further. (It is prepared for each case of making a reach announcement corresponding to each control command indicating the type of variation pattern designation, a big hit announcement, a reach announcement and a big hit announcement).

Further, the voice synthesis circuit 702 receives the transfer request signal (SIRQ) and the serial clock signal (SIC).
K), the serial data signal (SI) and the transfer end signal (SRDY). Speech synthesis circuit 702
When SIRQ goes low, SI is taken in bit by bit in synchronization with SICK, and when SRDY goes low, data consisting of each SI received up to that point is set to 1
Interpreted as one audio playback data.

Data corresponding to the serial data signal output to the voice synthesizing circuit 702 and data indicating the duration (process timer value) of the voice generated according to the data are set in each voice data. There is. That is, the control data stores data indicating the output pattern from the sound generating means (the speaker 27 in this example).

In the voice process update process, the value of the timer whose value is initialized according to the process timer value is subtracted, and when the timer times out, the data set in the next address in the voice data is changed. Accordingly, the output voice is determined to be changed, and the process timer value corresponding to the determination result is set in the timer. Since the output voice is switched when the process timer value is set to the timer, in the port output process (step S470), the output voice is output to the voice synthesis circuit 702 via the output port.
The data corresponding to the new output voice is output to the voice synthesis circuit 702.

In the voice process update process, based on the value of the effect timer saved in the timer state save area,
Determine if the process timer has timed out.
Specifically, when starting the production based on the data of the process timer value corresponding to the data set to output the sound from the speaker 27 to the value of the production timer stored in the timer state storage area. To calculate the process end determination value and store it in a predetermined area of the RAM. The effect timer is updated in the timer interrupt process, and the latest effect timer value is copied to the timer state save area in the timer state setting process each time the main process is repeated. Then, it is confirmed whether the value of the effect timer saved in the timer state saving area matches the calculated process end judgment value. If they match, the process timer has timed out. To determine. If it is determined that the process timer has timed out, it is determined to perform voice output according to the data set in the next address in the voice data, and the process timer value according to the determination result is A new process end determination value is calculated by adding it to the value of the effect timer saved in the timer state saving area and saved. When a new process end judgment value is set, it means that the output voice has been switched.
In the port output process (step S481), the data corresponding to the new output voice is output to the voice synthesis circuit 702 via the output port for outputting the data to the voice synthesis circuit 702.

Concretely, the voice control CPU 701 is
In port output processing, SIRQ is turned on (low level), data (voice command) read from ROM (voice command data area) is output as SI in synchronization with SICK, and SRDY is set to low level when output is completed. To do. Upon receiving data by SI, the voice synthesis circuit 702 generates a voice according to the received data.

In this embodiment, it is assumed that the timer interrupt is taken every 2 ms. That is, the timer interrupt process is activated every 2 ms. FIG. 76 is a flowchart showing the timer interrupt process. In the timer interrupt process, the sound control CPU 701 performs a register save process (step S491), and then updates the count value of the counter for generating a random number for reach advance determination in this example. (Step S492). Also, CP for sound control
U701 performs a process of updating the count value of the counter for generating the random number for determining the big hit announcement (step S493).

Further, the value of each timer such as a general-purpose timer (effect timer) for managing each effect time such as sound output in the sound control board 70 is incremented by 1 (step S49).
4). After that, the contents of the register are restored (step S
495), and sets the interrupt-enabled state (step S49).
6).

According to the above control, in this embodiment, the processing in steps S492 to S494 is 2 m.
It will be activated every s. It should be noted that in this embodiment, the timer interrupt processing is performed in steps S492 to S4.
Although the processing of 94 is being executed, in the timer interrupt processing, for example, only the flag indicating that an interrupt has occurred is set, and the processing of steps S492 to S494 may be executed in the main processing. .

As described above, the counter (random number data) is updated and stored in the timer interrupt process (steps S492 to S493), and the count value of the counter (numerical data) stored in the main process is updated. ) Is read out and stored (set) in the counter state storage area (step S473), and then effect control is performed using the stored information in the counter state storage area (steps S476 to S4).
81), since the random number value data can be surely updated every predetermined period and the update interval can be eliminated, the random number value data becomes a specific value. It is possible to prevent inconvenience caused by the fact that the operating state continues for a long time.

Also, the effect timer (for example, a general-purpose timer) is updated and stored in the timer interrupt process (step S494), and the stored effect timer value (numerical data) is read in the main process. After saving (setting) in the state save area (step S474), effect control is performed using save information in the timer state save area (step S474).
Since 476 to step S481) are configured to be performed, the effect timer can be reliably updated every predetermined period,
Since the production timer functions accurately, it is possible to prevent production deviations from occurring in various productions executed on the sound control board 70.

The production timer is used, for example, as a process timer. The specific usage is the same as that when a general-purpose timer is used as the motor rotation time timer described above, for example, as described in the voice process update processing.

Here, the RO mounted on the sound control board 70
The address map of M will be described. The ROM area includes a control data area and a control program area. The control data area stores an initialization data table used when initializing the register, the RAM, the output port, and the like. In the control data area, the address of the program in which the processing corresponding to the upper byte (MODE data) of the voice control command is stored, and the MOD
A command upper byte table in which an address table corresponding to E data is set is stored. In the command execution process (step S479), the contents of the command upper byte table are referred to according to the MODE data of the received voice control command, and the corresponding process (program) is executed. In the processing, the data in the audio data selection table stored next to the command upper byte table in the control data area is specified according to the address table and the lower byte (EXT data) of the received audio control command. . Then, the audio data pointed to by the specified data is selected.

In the control program area, main processing programs, initialization processing, command recognition processing, and command execution processing programs are stored. Also,
A voice address selection processing program is also stored.
Further, the control program area stores voice process update processing, port output processing, command reception interrupt processing, and timer interrupt processing.

In this embodiment, the voice synthesis circuit 702 is used.
Data to be given to the voice command data, that is, data indicating the output voice is stored in the voice command data in the control data area. Then, in the voice process update process (step S480) in the main process, the voice data is referred to, and further the voice command data is referred to, and the output voice is controlled. FIG. 77 is an explanatory diagram showing an example of the content of the audio data stored in the control data area. In this embodiment, data indicating a voice output pattern (voice command data) is stored in the voice data in the control data area. As a voice output pattern stored in the voice data, a voice output pattern as shown in FIG. 77 is determined in correspondence with the pattern command (80XX (H)), and further, a voice when a reach warning is given. An output pattern and a voice output pattern when a big hit announcement is given are defined according to the variation modes. That is, in this example, the pattern of the voice output when giving the reach notice stored in the voice data, and the pattern of the voice output when giving the big hit notice are the reach notice display and the big hit executed on the symbol control board 80. The audio output is set to be synchronized with the variation of the notice display. Then, in the voice process update process (step S480) in the main process, the voice output is controlled with reference to the voice data.

In the above-described embodiment, whether or not the notice effect is performed by the display control board 80, the lamp control board 35, and the sound control board 70 and the kind of the notice effect when the notice effect is performed are determined. Although it is configured, the display control board 80 determines whether to display the background pattern or the character on the variable display device 9, and determines the type of the background pattern or the character when displaying the variable using the predetermined random number. Good. In this case, the random number may be updated in the same manner as the reach announcement determination random number or the big hit announcement determination random number, and may be copied to the counter state saving area and used for the determination.

As described above, in the interrupt process, the input state of the input signal from the outside is monitored, and the input information storing process of storing the input information indicating the result of the input state (for example, the switch input process). In the main process, the input information setting process (for example, switch state setting process) of reading and duplicating the input information stored by the input information storing process and the electrical information based on the duplicate information copied by the input information setting process are executed. Since it is configured to execute a control process (for example, a game control process, a payout control process, etc.) for controlling a component (for example, a variable winning ball device, a ball payout device 97), a series of control processes Even if the interrupt processing is started and the input information is updated before the end of, the duplicate input information is not updated until the series of control processing ends. It is possible to prevent the portion to be the unprocessed control process remains has the effect that the disadvantage that a series of control process is brought about by not completed is eliminated.

As described above, in the control processing (eg, game control processing), the copy information (eg, switch timer value) is continuously input a predetermined number of times by the input signal detecting means (eg, input port and CPU 56). If it indicates that there is a detection by the input signal detection means, it is determined that there is a regular input signal, and it is indicated that the input signal detection means has continuously detected a predetermined number of times. If the input signal is not a normal input signal, it is determined that the input signal is not a proper input signal. Therefore, it is possible to prevent the game machine from running out of control due to malfunction of the input state sensing means due to electrostatic / electromagnetic noise or chattering. Can be prevented.

Further, as described above, a passage detection switch for detecting passage of the game medium (for example, winning opening switches 29a, 30a, 33a, 39a, gate switch 32a, starting opening switch 14a, count switch 2)
3. The V winning switch 22) is provided, and the input signal detecting means is configured to detect the input signal from the passage detecting switch. Therefore, although the game medium is detected, the processing based on this is performed. The inconvenience of not being forgotten can be eliminated.

Further, as described above, it is executed when it is determined that the control processing includes the regular input signal from the start detection switch (for example, the start opening switch 14a).
Since it is configured to include a process (for example, step S35, step S37 to step S39) for determining a display result (identification information as a variable display result derived and displayed on the variable display device 9), it passes through the starting area. It is possible to eliminate the inconvenience that the identification information is not variably displayed on the basis of the detected game medium.

As described above, the control process is executed when it is determined that there is a regular input signal from the winning detection switch (for example, the count switch 23).
The variable winning device (eg, variable winning ball device) is configured to include a winning number counting process (eg, step S245 to step S251) for counting the number of winning winning game media. It is possible to solve the inconvenience that the number of winnings corresponding to the winning is not counted even though the winning is won.

Further, as described above, in order to continue the specific game state, which is executed when it is determined in the control processing that there is a regular input signal from the specific area passing switch (for example, the V winning switch 22). Since the control process (for example, step S308) is included, there is an inconvenience that the specific game state is not continued based on this even though the game medium is detected in the specific region. It can be resolved.

Also, as described above, the winning combination switch (eg, winning combination switches 29a, 30a,
33a, 39a) is executed when it is determined that there is a regular input signal, processing for executing payout of the prize game medium according to the winning in the winning opening (for example, step S226 to step S227, step S247)
Since it is configured to include step S251), it is possible to eliminate the inconvenience that the prize game medium based on the prize is not paid out even though the prize is won.

Further, as described above, the path abnormality detecting means (for example, the out-of-ball switch 187, the full tank switch 48) for detecting the abnormality of the payout path for paying out the game medium is provided, and the input signal detecting means is the path abnormality. Since it is configured to detect the input signal from the sensing means, it is possible to eliminate the inconvenience that proper processing based on this is not performed even if there is an abnormality in the payout path.

As described above, in the control process, a payout game medium detection switch (for example, the prize ball count switch 301A. If a switch for detecting the passage of the rental game medium is provided, the switch is, for example, a ball. A process of counting the number of payouts of the game medium and performing drive control of the payout device according to the number of payouts, which is executed when it is determined that the input is made by the lending count switch 301B. Since it is configured to include S538, S539, and step S542), even though the game medium paid out by the payout means is detected, it is not counted as a paid-out game medium and many It is possible to eliminate the inconvenience that the game medium is paid out.

Further, as described above, the recording medium processing device (for example, the prepaid card unit 50) for accepting the game medium lending request from the player is connectable, and the input signal detecting means is the recording medium processing device. For renting a game medium, which can be detected when at least a lending request signal (for example, a BRQ signal) from the device is detected and the control process determines that there is an input from the lending request signal. Since it is configured to include the drive control process of the payout device (eg, step S518, step S522), a recording medium (eg, prepaid card)
It is possible to eliminate the inconvenience that the game medium is not rented in response to the request for lending using the.

As described above, in the power supply stop process executed when the power supply to the gaming machine is stopped, the copy information copied by the input information setting process is saved in the variable data storage means. When the processing is executed and the power supply is restored, the state restoration processing for restoring the control state based on the stored contents stored in the variable data storage means can be performed. It is possible to prevent the copy information from being lost even when the power supply to the device is stopped.

Also, as described above, in the interrupt processing, the numerical data updating processing for updating at least one numerical data (for example, step S22 to step S25).
And a numerical data setting process for reading and setting the value stored in the numerical data updating process in the main process (for example, step S16c, step S16).
While executing d), control processing (for example, game control processing, payout control processing, display control processing, lamp control processing,
In the sound control process), the electric parts are controlled based on the duplicated values duplicated by the numerical data setting process.Therefore, before the series of control processes is completed, the interrupt process is started and the numerical data is Even if it is updated, the duplicated value is not changed until the series of control processing is completed, so that it is possible to prevent the control processing from leaving an unprocessed portion, which is caused by the series of control processing not being completed. This has the effect of eliminating the inconvenience.

Also, as described above, the numerical data includes random number value data (for example, display random number, determination random number) used by the electric component control means to determine the game contents executed by the electric component. Since it is configured, the random number value data can be surely updated at every predetermined period, and the possibility that the update interval becomes large can be eliminated, so the random number value data has a specific value. It is possible to prevent inconvenience due to the state continuing for a long time.

Further, as described above, since the numerical data is configured to include an operation timer (for example, a general-purpose timer, a production timer, a process timer) for managing the operation period of the electric component, the operation timer Since the update can be surely performed at every predetermined period and the operation timer can function accurately, it is possible to prevent an operation deviation from occurring in various operations executed in the gaming machine. it can.

As described above, the numerical data is the data extracted when the game medium passes through the starting area, and is for determining the specific game state used for determining whether or not to set the specific game state. Since it is configured to include data (random number for jackpot determination), the specific game state determination data can be reliably updated every predetermined period, and it is possible to eliminate the possibility that the update interval will increase. , It is possible to prevent the state in which the specific game state determination data is a value that is the specific game state, from continuing for a long time.

Further, as described above, since the numerical data is configured to include the identification information determination data (design determination random number) used to determine the identification information as the display result, the identification information determination Since it is possible to reliably update the usage data for each predetermined period and eliminate the possibility that the update interval becomes large, it is possible to prevent the determined identification information from being biased.

As described above, variable display mode determination data (fluctuation pattern determination random numbers) for determining in the numerical data which variable display mode the variable display mode of the identification information in the variable display device is to be executed. Since it is configured to include, it is possible to reliably update the variable display mode determination data for each predetermined period, it is possible to eliminate the risk of increasing the update interval, the display mode to be determined It is possible to prevent the deviation.

As described above, in addition to the numerical data, the effect state determination data (for determining the effect control contents executed by using the electric parts for effecting the game in relation to the game status of the gaming machine ( For example, since it is configured to include a random number for reach announcement determination and a random number for jackpot announcement determination, the performance state determination data can be reliably updated every predetermined period, and the update interval may increase. Since it can be eliminated, it is possible to prevent the determined effect state from being biased.

As described above, the numerical value data is used as a performance timer for managing the execution period of the game performance executed by at least one of the variable display device as an electric component, the sound output means, and the light emitter. Since it is configured to include, the production timer can be surely updated every predetermined period, and the production timer will function correctly, so in various productions executed in the gaming machine, the production state It is possible to prevent the occurrence of the deviation.

Further, as described above, in the numerical data, a payout operation timer (for example, a motor rotation time timer, which manages the time associated with the payout operation of the game medium by the payout device,
Since it is configured to include an all-pieces payout operation timer and a 25-pieces payout operation timer, the payout operation timer can be surely updated every predetermined period, and the payout operation timer can function accurately. It is possible to prevent an error from occurring between the number of game media to be paid out and the number of game media actually paid out.

Further, as described above, the numerical data is added to the recording medium processing device (for example, the prepaid card unit 5).
0) A communication management timer that manages the communication time with (for example,
67 is configured to include the general-purpose timer described in FIG. 67, the communication management timer can be reliably updated every predetermined period, and the communication management timer can function accurately. It is possible to prevent an abnormality from occurring in the communication state with the medium processing device.

In the above-described embodiment, the general-purpose timer is used to measure the time, but a variable timer set for each process and used in the process may be used to measure the time. Good. Here, processing such as setting and updating of the variation timer used to determine the transmission of the confirmation command on the main board 31 will be described with reference to FIGS. 78 to 80. FIG. 78
[Fig. 6] is a flowchart showing the processing of S25 in the above-mentioned timer interrupt processing when the variable timer is used. As shown in FIG. 78, in the timer interrupt process, the CPU 5
If the change timer is not 0, the value of 6 (step S25
N of a) and the value of the fluctuation timer are subtracted (-1) (step S25b).

FIG. 79 is a flow chart showing the processing for setting the fluctuation timer for determining the transmission of the confirmation command. The process shown in FIG. 79 is included in the all symbol variation start process in step S304 described above. In the fluctuation time timer setting process, the CPU 56 sets the fluctuation time of the identification information in the fluctuation timer (step S304A), and stores the fluctuation timer in a predetermined area of the RAM 55, for example.

FIG. 80 is a flow chart showing an example of the processing for checking the time-out of the fluctuation timer for determining the transmission of the confirmation command. This timeout check process is included in the all symbol stop waiting process of step S305 described above. In the timeout check process, the CPU 56 extracts the value of the variable timer stored in the timer state storage area (step S305).
A). Then, it is confirmed whether or not the value of the extracted fluctuation timer is 0 (step S305B). Then, if the value of the fluctuation timer is 0, the CPU 56 sends a display control command (decision command) instructing to stop the variable display of the special symbol because the fluctuation timer has timed out (step S305c). That is, the fluctuation timer here serves as a timer for measuring the fluctuation time.

As described above, the variable timer set in the variable time timer setting process is updated (subtracted) by the timer interrupt process (step S25b), and the value of the variable timer is read out and saved (set) in the main process. (Step S16d), it is configured to determine whether the set fluctuation timer has timed out. Therefore, the change timer can be surely updated every predetermined period, and the change timer can function accurately. Therefore, even if the variation timer as described above is used, it is possible to accurately control the variation time of the special symbol, and thus it is possible to prevent the operational deviation in the gaming machine from occurring. .

The fluctuation timer may be used to measure other time. In this case, FIG.
Processing may be performed in the same manner as in 8 to 80. Further, the variation timer may be used in a substrate other than the main substrate 31.

The random numbers described in the above-mentioned embodiments are examples, and other random numbers for determining a normal symbol for determining whether or not the display result of the normal symbol is a winning symbol, for example. A configuration using random numbers may be used.

Further, in the above-described embodiment, a plurality of types of electric parts provided in the game machine (for example, the opening / closing wing piece device 15, the ball payout device 97, the variable display device 9, the lamp
(Electric parts such as LEDs, various electrical parts such as speakers)
Each electric component control board (main board 31, payout control board 3
7, the pattern control board 80, the lamp control board 35, the sound control board 70) was used for control, but a board having a function of two or more boards of each electric component control board is provided, and the above-described embodiment is adopted. In the form, a plurality of types of electric components, which are controlled by two or more substrates, may be controlled by one substrate. For example, a main board having the functions of all the boards (main board 31, payout control board 37, design control board 80, lamp control board 35, and sound control board 70) is provided, or the design control board 80, the lamp control board. It is conceivable that an effect control board having a part or all of the functions of the sound control board 35 and the sound control board 70 is provided. Further, the function of one board may be divided, and a plurality of types of electric components controlled by one board in the above-described embodiment may be controlled by separate boards.

Further, the pachinko gaming machine 1 of each of the above-described embodiments has a predetermined game value when the stop symbol of the special symbol which is variably displayed on the variable display device 9 based on the starting winning is a combination of the predetermined symbols. It was a first-class pachinko game machine that can be given to players, but if there is a prize in a predetermined area of an electric accessory (an example of a variable prize device) that is released based on a start prize, a predetermined game value is given to the game. If a prize is given to the electric player in a predetermined area when a predetermined game value is given, the state where the game value is given continues (for example, the jackpot state continues. , Which means to move to the next round.) Type 2 pachinko game machine or a predetermined electric accessory that is released when the stop pattern of the symbols that are variably displayed based on the winning a prize becomes a combination of the predetermined symbols For example, it may be an accessory that is opened when conditions other than the combination of stop symbols are established, an accessory that is not opened and is a structure that is difficult to win, and may have other configurations.) The present invention can be applied even to a third-class pachinko gaming machine in which a predetermined right is generated or continues on the condition that a game medium has passed through a specific area provided inside the electric accessory. .

In the above-mentioned embodiment, the "specific game state" means a state advantageous to the player to whom a predetermined game value is given. Specifically, the "specific game state" is, for example, a state in which the state of the variable winning ball device is advantageous for a player who is likely to win a hit ball (big hit gaming state), and a right to be a state advantageous for the player. Is a state in which a predetermined game value is given, such as a state in which the game is generated, a state in which the prize game medium payout condition is easily established.

[0475]

As described above, according to the first aspect of the present invention, the electric machine control means executes the interruption process for each occurrence of the interruption signal generated every predetermined period, The main process to be repeatedly executed continuously is performed, and in the interrupt process, the input state of the input signal from the outside is monitored, and the input information storing process of storing the input information indicating the result of the input state is executed, In the main process, an input information setting process for reading and duplicating the input information stored by the input information storing process, and a control process for controlling electric parts based on the duplicated information copied by the input information setting process are executed. Even if the interrupt processing is started before the series of control processing is completed and the input information is updated, it is possible to prevent the unprocessed portion from remaining in the control processing. Can have the effect that the disadvantage that a series of control process is brought about by not completed is eliminated.

According to the second aspect of the present invention, the electric component control means executes the numerical data updating process for updating at least one numerical data in the interrupt process, and the numerical data updating process is performed in the main process. It is configured to read numerical values and perform a numerical data setting process to duplicate them, and to control electrical parts based on the duplicated values duplicated by the numerical data setting process in the control process. Even if the interrupt process is started before the end and the numerical data is updated, it is possible to prevent the unprocessed part from remaining in the control process, and the inconvenience caused by not completing the series of control processes. Has the effect of being eliminated.

According to the third aspect of the invention, in the numerical data,
Since it is configured to include random number value data used by the electrical component control means to determine the game content executed by the electrical component, the random number value data can be surely updated every predetermined period, and updated. Since it is possible to eliminate the possibility that the interval becomes large, it is possible to prevent inconvenience caused by the fact that the state in which the random number data has a specific value continues for a long time.

According to the invention of claim 4, the numerical data includes
Since it is configured to include an operation timer for managing the operation period of the electric parts, the operation timer can be surely updated every predetermined period, and the operation timer will function correctly, so that the game It is possible to prevent an operational deviation from occurring in various operations executed in the machine.

In the invention according to claim 5, when the copy information indicates that the input signal detecting means has continuously detected a predetermined number of times in the control processing, there is a regular input signal. If it is determined that the input signal is not detected by the input signal detecting means for a predetermined number of times in succession, it is determined that the input signal is not a proper input signal. It is possible to prevent the game machine from running away due to malfunction due to electrostatic / electromagnetic noise or chattering of a switch or the like that outputs a signal detected by the signal detection means.

According to the sixth aspect of the invention, since the electric component control means is constituted as the game control means for controlling the progress of the game, the control processing executed by the game control means has a portion that is not yet processed. It is possible to prevent the remaining, and it is possible to eliminate inconvenience such as malfunction caused by the completion of the series of control processes.

According to the seventh aspect of the invention, since the input signal detecting means is configured to detect the input signal from the passage detecting switch, the processing based on the game medium can be performed even though the game medium is detected. The inconvenience of not being performed can be eliminated.

According to the eighth aspect of the invention, the control processing includes processing for determining the display result, which is executed when it is determined that there is a normal input signal from the start detection switch. It is possible to eliminate the inconvenience that the variable display of the identification information based on this is not performed even though the game medium that has passed through the starting area is detected.

According to the ninth aspect of the present invention, when the control processing determines that there is a regular input signal from the winning detection switch, the winning number counting for counting the number of winning game media to the variable winning device is executed. Since the processing is configured to be included, it is possible to eliminate the inconvenience that the number of winnings is not counted in accordance with the winning of the game medium in the variable winning device.

According to the tenth aspect of the invention, in the control processing,
The game medium is detected in the specific area because it is configured to include a process for performing control for continuing the specific game state, which is executed when it is determined that there is a regular input signal from the specific area passing switch. Despite that, it is possible to eliminate the inconvenience that the specific game state is not continued based on this.

In the eleventh aspect of the present invention, the control processing includes
Since it is configured to include processing for executing payout of the prize game medium according to the winning of the winning opening, which is executed when it is determined that there is a regular input signal from the winning opening switch, the winning opening Despite winning the
The inconvenience that the prize game medium based on this is not paid out can be solved.

According to the twelfth aspect of the present invention, the gaming machine is capable of paying out a prize game medium to be paid out when the game medium passes at least a predetermined winning area provided on the game area. Since the electric part is a payout device capable of paying out at least the prize game medium, and the electric part control means is the payout control means for controlling the payout device, the payout process of the game medium is performed. Non-payment due to unprocessing can be prevented.

According to the thirteenth aspect of the invention, the control processing includes
Since it is configured to include the process of counting the number of payouts of the game medium and controlling the driving of the payout device according to the number of payouts, which is executed when it is determined that there is an input by the payout game medium detection switch. , It is possible to eliminate the inconvenience that many game media are paid out without being counted as paid-out game media, even though the game media paid out by the payout means are detected. it can.

According to the fourteenth aspect of the invention, the control processing includes
Since it is configured to include a drive control process of the payout device for lending a game medium, which is executed when it is determined that there is an input from the lending request signal, a recording medium (for example, a prepaid card) It is possible to solve the inconvenience that the game medium is not rented in response to the request for lending using the request.

According to the fifteenth aspect of the invention, in the power supply stop processing executed when the power supply to the gaming machine is stopped, the copy information copied by the input information setting processing is stored in the variable data storage means. When the save process is executed and the power supply is restored, the state restore process for restoring the control state based on the stored contents saved in the variable data storage means can be performed, so that the game is played. Even if the power supply to the machine is stopped, it is possible to prevent the copy information from being lost.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is a front view showing the front surface of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine viewed from the back side.

FIG. 4 is a rear view of a mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 7 is a block diagram showing a circuit configuration example of a payout control board.

FIG. 8 is a block diagram showing a circuit configuration example of a symbol control board.

FIG. 9 is a block diagram showing a circuit configuration in the lamp control board.

FIG. 10 is a block diagram showing a circuit configuration in the voice control board.

FIG. 11 is a block diagram showing a circuit configuration example of a power supply board.

FIG. 12 is a block diagram showing an example of a configuration around a CPU for power supply monitoring and power supply backup.

FIG. 13 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 14 is a flowchart showing main processing executed by a CPU on a main board.

FIG. 15 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state recovery process.

FIG. 16 is a flowchart showing a game control process.

FIG. 17 is an explanatory diagram showing each random number.

FIG. 18 is a flowchart showing a 2 ms timer interrupt process.

FIG. 19 is a flowchart showing a game state recovery process.

FIG. 20 is a flowchart showing a non-maskable interrupt process (power supply stop process).

FIG. 21: Power supply drop and N when power supply to a game machine is stopped
It is a timing diagram which shows a mode of MI signal.

FIG. 22 is an explanatory diagram showing a formation example of a switch timer in a RAM.

FIG. 23 is a flowchart showing an example of a switch input process.

FIG. 24 is a flowchart showing an example of a switch check process.

FIG. 25 is a flowchart showing an example of prize ball processing.

FIG. 26 is a flowchart showing an example of prize ball processing.

FIG. 27 is a flowchart showing an example of prize ball processing.

FIG. 28 is a flowchart showing a switch-on check process.

FIG. 29 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 30 is a flowchart showing special symbol process processing.

FIG. 31 is a flowchart showing a process of determining that a hit ball has won a starting winning opening.

FIG. 32 is a flowchart showing a process for determining a variable display stop symbol and a process for determining a variation pattern.

FIG. 33 is a flowchart showing a big hit determination process.

FIG. 34 is a flowchart showing a variable time timer setting process.

FIG. 35 is a flowchart showing a timeout check process.

FIG. 36 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 37 is an explanatory diagram showing an example of a command form of a control command.

FIG. 38 is a timing diagram showing a relationship between an 8-bit control signal forming a control command and an INT signal.

FIG. 39 is an explanatory diagram showing an example of contents of a payout control command.

FIG. 40 is an explanatory diagram showing an example of the contents of a display control command.

FIG. 41 is an explanatory diagram showing an example of contents of a lamp control command.

FIG. 42 is an explanatory diagram showing an example of the content of a voice control command.

FIG. 43 is a flowchart showing a processing example of command set processing.

FIG. 44 is a flowchart showing a command transmission processing routine.

FIG. 45 is a flowchart showing an example of a prize sphere number subtracting process.

FIG. 46 is a block diagram showing a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 47 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 48 is a flowchart showing a main process executed by a CPU in the payout control board.

FIG. 49 is a flowchart showing a 2 ms timer interrupt process.

FIG. 50 is a flowchart showing a payout state recovery process.

FIG. 51 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

52 is an explanatory diagram showing a configuration example of a RAM in the payout control means. FIG.

FIG. 53 is an explanatory diagram showing a configuration example of a reception command buffer.

FIG. 54 is a flowchart showing an example of command reception processing of the payout control CPU.

FIG. 55 is a flowchart showing an example of switch input processing.

FIG. 56 is a flowchart showing an example of payout amount subtraction processing.

FIG. 57 is a flowchart showing an example of payout stop state setting processing.

FIG. 58 is a flowchart showing an example of command analysis execution processing.

FIG. 59 is a flowchart showing an example of prepaid card unit control processing.

FIG. 60 is a flowchart showing an example of ball lending control processing.

FIG. 61 is a flowchart showing an example of ball lending control processing.

FIG. 62 is a flowchart showing an example of prize ball control processing.

FIG. 63 is a flowchart showing an example of prize ball control processing.

FIG. 64 is an explanatory diagram showing the relationship between the type of error and the display of the error display LED.

FIG. 65 is a flowchart showing an example of error processing.

FIG. 66 is a flowchart showing an example of error processing.

FIG. 67: CP for payout control during payout operation by ball lending
It is a timing diagram which shows the example of signal processing of U and a card unit.

FIG. 68 is a flowchart showing main processing executed by the display control CPU.

FIG. 69 is a flowchart showing a timer interrupt process executed by the display control CPU.

FIG. 70 is an explanatory diagram showing an example of display random numbers.

71 is a flowchart showing display control process processing. FIG.

FIG. 72 is a flowchart showing a main process executed by a lamp control CPU.

FIG. 73 is a flowchart showing a timer interrupt process executed by the lamp control CPU.

FIG. 74 is an explanatory diagram showing lamp data in an address map of a ROM mounted on the lamp control board.

FIG. 75 is a flowchart showing main processing executed by the sound control CPU.

FIG. 76 is a flowchart showing a timer interrupt process executed by the sound control CPU.

77 is an explanatory diagram showing audio data in an address map of a ROM mounted on the sound control board. FIG.

FIG. 78 is a flowchart showing an example of the process of step S25 when the timer is updated by the subtraction process.

FIG. 79 is a flowchart showing a variable time timer setting process when the timer is updated by the subtraction process.

FIG. 80 is a flow chart showing a timeout check process when the timer is updated by the subtraction process.

[Explanation of symbols]

1 Pachinko machine 31 Main board 35 lamp control board 37 Discharge control board 55 RAM 56 CPU 70 sound control board 80 symbol control board 101 Display control CPU 351 CPU for lamp control 371 CPU for payout control 701 CPU for sound control

Continuation of front page (51) Int.Cl. ⁷ identification code FI theme code (reference) A63F 7/02 352 A63F 7/02 352L

Claims (15)

[Claims] 1. A gaming machine that allows a player to play a predetermined game, the electrical component control means for controlling electrical components provided in the gaming machine, and the outside of the electrical component control means. And an input signal detection means capable of detecting an input signal from the electric component control means, wherein the electric component control means executes an interrupt process executed every time an interrupt signal generated every predetermined period and a main process repeatedly executed continuously. Processing, and in the interrupt processing, monitor the input state of the input signal from the outside, execute the input information storage processing that stores the input information indicating the result of the input state, in the main processing, To execute an input information setting process for reading and duplicating the input information stored by the information storing process, and a control process for controlling the electric component based on the duplicate information copied by the input information setting process. Gaming machine and features. 2. The electrical component control means executes a numerical data update process for updating at least one numerical data in the interrupt process, and reads the value stored by the numerical data update process in the main process. The gaming machine according to claim 1, wherein the numerical data setting process to be duplicated is executed, and the electric component is controlled based on the duplicated value duplicated by the numerical data setting process in the control process. 3. The gaming machine according to claim 2, wherein the numerical data includes random number value data used by the electric component control means to determine the game content executed by the electric component. 4. The game machine according to claim 2, wherein the numerical data includes an operation timer for managing an operation period of the electric component. 5. The input information storing process stores determination information based on an input state of an input signal, and the determination information is duplicated as duplicate information in an input information setting process. In the control process, the duplicate information is reproduced a predetermined number of times. If it indicates that the input signal detecting means has continuously detected, it is determined that there is a regular input signal, and the input signal detecting means continuously detects a predetermined number of times. If not, the gaming machine according to any one of claims 1 to 4, wherein it is determined that the input signal is not a regular input signal. 6. The gaming machine according to claim 1, wherein the electric component control means is a game control means for controlling the progress of the game. 7. A game machine is provided with a passage detection switch for detecting passage of a game medium in a region where the game medium can pass, wherein a game is played using a predetermined game medium, and an input signal detecting means is provided. The gaming machine according to claim 6, wherein an input signal from the passage detection switch is detected. 8. A game machine is played by launching a predetermined game medium into a game area, and the game medium passes through a variable display device that can variably display identification information and then derive a display result. By this, the starting area for variably displaying the identification information is provided in the game area, the passage detection switch is provided in the starting area, and the starting detection switch for detecting the game medium passing through the starting area is provided. 8. The gaming machine according to claim 7, wherein the control process includes a process of determining the display result, which is executed when it is determined that there is a regular input signal from the start detection switch. 9. According to the establishment of a predetermined condition, it becomes possible to control to a specific game state advantageous to a player, a variable winning device which can be opened in the specific game state is provided in a game area, and a passage detection switch is variable. It is provided in the winning device,
Including a winning detection switch for detecting the game medium that has won the variable winning device, the control process is executed when it is determined that there is a regular input signal by the winning detection switch, to the variable winning device 9. The gaming machine according to claim 7, further comprising a winning number counting process for counting the number of winning winning game media. 10. The variable winning device has a plurality of winning areas, at least one of the plurality of winning areas is a specific area, and when a game medium passes through the specific area during a specific gaming state. The specific game state can be continued, and the passage detection switch includes a specific area passage switch which is provided in the specific area and detects a game medium that has passed through the specific area. 10. The process including the control for continuing the specific game state, which is executed when it is determined that there is a regular input signal from the passage switch.
The game machine described. 11. The gaming machine is provided with at least one winning opening in the game area, the passage detection switch includes a winning opening switch for detecting a game medium winning in the winning opening, and the control processing is the winning prize. 8. The gaming machine according to claim 7, further comprising processing for executing a payout of a prize game medium according to a winning of the winning opening, which is executed when it is determined that there is a regular input signal from the mouth switch. 12. The game machine is capable of paying out a prize game medium to be paid out in accordance with the fact that the game medium has passed at least a predetermined prize area provided on the game area, and the electric component is at least A payout device capable of paying out a prize game medium, wherein the electric component control means is a payout control means for controlling the payout device, claim 1, claim 4, claim 4, or claim 5. Game machine. 13. The gaming machine has a payout game medium detection switch for detecting the passage of at least the prize game medium paid out by the payout device, and the input signal detection means has an input signal from the payout game medium detection switch. The control process is executed when it is determined that there is an input by the payout game medium detection switch, the number of payouts of the game medium is counted, and drive control of the payout device according to the payout number is performed. The gaming machine according to claim 12, including processing. 14. The game machine is configured to be connectable to a recording medium processing device that receives a game medium lending request from a player, and the input signal detecting means inputs at least the lending request signal from the recording medium processing device. 13. The control process includes a drive control process of a payout device for renting a game medium, which is executed when it is determined that there is an input from the lending request signal. Item 13. A gaming machine according to item 13. 15. A variation data storage means for storing variation data that fluctuates according to the progress of a game, and storing the stored content for a predetermined period even if power supply to the gaming machine is stopped, In the power supply stop process executed when the power supply is stopped, a saving process of saving the copy information copied by the input information setting process in the variable data storage means is executed, and when the power supply is restored, The gaming machine according to any one of claims 1 to 14, which is capable of performing a state restoration process for restoring the control state based on the stored contents stored in the fluctuation data storage means.