JP4166800B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, there is provided a variable display device capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display device is in a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. In other words, or a condition for winning a prize ball is easily established.

  In a pachinko gaming machine, the combination of a predetermined display mode with a display result of a variable display device that displays special symbols is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In a gaming machine, when the payout control means for controlling the prize ball payout according to the winning is mounted on a payout control board different from the game control board on which the game control means for controlling the progress of the game is mounted Since the progress of the game is controlled by the game control means mounted on the game control board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board. On the other hand, the rental of game media is irrelevant to the progress of the game, and is generally controlled by the payout control means without going through the game control means. Hereinafter, the game control means and other control means for controlling various electrical components provided in the gaming machine are referred to as electrical component control means, and the board on which the electrical component control means is mounted is referred to as an electrical component control board. is there.

  In general, each electrical component control means includes a microcomputer. That is, a program is stored in a ROM or the like, and data temporarily generated for control or data that changes as control proceeds is stored in the RAM. Then, when the power supply stop state due to a power failure or the like occurs in the gaming machine, the data in the RAM is lost. For example, if a power supply stop state occurs during a jackpot game and data for control is lost, the player cannot enjoy the profit based on the occurrence of the jackpot.

  In order not to give such a disadvantage to the player, the game control is interrupted according to a predetermined signal generated in accordance with the decrease in the power supply voltage value, and the power supply to the gaming machine is stopped at that time. Among them, there is a gaming machine that stores data in a RAM (backup storage means) that is backed up and waits until the power supply is completely stopped. Such a gaming machine resumes the game based on the stored gaming state when the power supply is resumed while the gaming state is stored in the backup storage means, which gives the player a disadvantage. It is prevented. When the power supply is resumed, the game can be resumed from the state when the power supply is stopped by the stored data. However, in such a gaming machine, if the data in the backup storage means has changed for some reason in the power supply stop state, it cannot be recovered to the state when the power supply was stopped, and erroneous game control is performed. There is a problem that the game may be resumed based on the state.

  In addition, even if the electrical component control means restores the control state based on the held data, it may not be completely restored to the state before the power supply is stopped. In that case, the game may be resumed from a gaming state that is disadvantageous to the player as compared to the gaming state before the power supply is stopped.

  The present invention is an invention for solving the problems as described above, and when an electric power supply to a gaming machine is stopped, an operation state of an electrical component is appropriately set to store an appropriate gaming state. Another object of the present invention is to provide a gaming machine that can reliably recover the control state when the power supply is stopped when the power supply is resumed.

A gaming machine according to the present invention is a gaming machine in which a player can perform a predetermined game, and an operation means for outputting an operation signal in accordance with an operation, a game control microcomputer for controlling the progress of the game, comprising a microcomputer for game control has a RAM in which data is held even stops power supply to the gaming machine from a backup power supply, when the power supply is stopped for a game machine, for storing a control state In the power supply stop process, designated data for indicating the presence of backup data is set in the RAM, and when power supply is started, an operation signal from the operation means is check whether it is input, when it is confirmed that the operation signal from the operating means is not input, designation data of whether or not it is stored in the RAM Run the constant, specified data performs state restoration process to restore the control state based on the stored contents which is stored in the RAM on condition that it is determined to have been stored in the RAM, an operation signal from the operation means When the input is confirmed, the stored contents of the RAM area are initialized without executing the determination, the initial setting process is performed, and then a predetermined routine is repeatedly executed, and the main routine is being executed. In response to a maskable timer interrupt that occurs every predetermined time, an interrupt routine that is started by interrupting the main routine is executed, and in the interrupt routine, it is determined whether or not to enter a specific gaming state A specific gaming state determination numerical value updating process for updating the specific gaming state determination numerical value within a predetermined range, and an initial value for updating the specific gaming state determination numerical value at a predetermined time RA A game control process including an initial value changing process for changing to an initial value value stored at a predetermined address and an initial value updating process for updating an initial value value stored at a predetermined address is executed. At the same time, in the main routine, as a predetermined process, the initial value numerical value update process for updating the initial value numerical value stored in the predetermined address is executed, and before the initial value numerical value update process in the main routine is started. set, prevents interruption by timer interrupt, and sets after the completion of the initial value for the numerical updating the state you allow interruption by the timer interrupt.
Further, the game control microcomputer is shorter than a game medium detection determination period for determining a detection signal from the game medium detection means for detecting a game medium whether or not an operation signal from the operation means is input. You may comprise so that it may confirm in a request | requirement detection determination period.
In addition, the gaming machine includes a payout control microcomputer that performs payout processing of the prize game medium based on a payout control command output from the game control microcomputer in response to winning, and the payout control microcomputer is a backup power source. Has a payout control RAM that retains data even when the power supply to the gaming machine is stopped, and when it is confirmed that an operation signal is input from the operation means when the power supply is started A game medium detection determination period for initializing the storage contents of the payout control RAM and determining a detection signal from the game medium detection means for detecting whether or not an operation signal from the operation means is input It may be configured to confirm in a shorter request detection determination period.

According to the first aspect of the present invention, the game control microcomputer checks whether or not an operation signal from the operation means is input when power supply is started, and operates the operation from the operation means. When it is confirmed that no signal is input, it is determined whether or not designated data for indicating the presence of backup data is stored in the RAM, and it is determined that the designated data is stored in the RAM. has been that performs state restoring processing to restore the control state based on the stored contents which is stored in the RAM on the condition, when it is confirmed that the operation signal from the operation unit is input, executes the determination Since the storage contents of the RAM area are initialized without any problem, it is possible to reliably continue the control from the control state before the power supply is stopped.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board with the glass door frame removed. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be, for example, a slot machine. It can also be applied to image-type gaming machines.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided. Further, a start memory display 18 having four display units for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number, is provided at the bottom of the variable display device 9. In this example, with the upper limit being four, every time there is an effective start winning, the start memory display 18 increases the number of lit display sections one by one. Then, each time the variable display of the variable display device 9 is started, the lit display portion is reduced by one.

  When a game ball wins the gate 32, variable display of the display of the normal symbol display 10 by 7 segment LED is started. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having four display units for displaying the number of winning balls that have entered the gate 32 is provided. In this example, with the upper limit of four, every time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of display units that are lit one by one. Each time the opening control of the variable winning ball apparatus 15 is performed, the number of lit display units is reduced by one.

  The game board 6 is provided with a plurality of winning holes 24, 29, 30, 33, and winning of game balls to the winning holes 24, 29, 30, 33 is performed by winning port switches 24a, 29a, 30a, 33a, respectively. Detected. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7.

  In this example, a prize ball lamp 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on in the vicinity of the top frame lamp 28a when the supply ball is cut. A cut lamp 52 is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the hit ball enters the start winning opening 14 and is detected by the start opening switch 14a, the variable display device 9 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state.

  When the hit ball wins the gate 32, the display number as the normal symbol on the normal symbol display 10 is continuously changed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, a game control board (main board) 31 on which a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control microcomputer, and the like are mounted. Is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Further, various decoration LEDs provided on the game board 6, special symbol start memory display 18 and normal symbol start memory display 41, decoration lamp 25, top frame lamp 28a provided on the frame side, left frame lamp 28b. , A lamp control board 35 on which lamp control means for controlling lighting of the right frame lamp 28c, the winning ball lamp 51 and the off-ball lamp 52 is mounted, and a sound control board on which sound control means for controlling sound generation from the speaker 27 is mounted 70 is also provided. Further, a power supply board 910 and a launch control board 91 on which a power supply circuit for creating DC30V, DC21V, DC12V, and DC5V is mounted are provided.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  Furthermore, for clearing backup data stored in storage content holding means (for example, a backup RAM capable of holding the contents even when power supply is stopped) included in each board (main board 31 and payout control board 37). A switch board 190 on which a clear switch 921 as an operation means is mounted is provided. The switch board 190 is provided with a clear switch 921 and a connector 922 connected to another board such as the main board 31.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG. 4, reach the ball payout device covered with the prize ball case 40A through the curve rod 186. Above the ball payout device, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  The ball break switch 187 is locked at a position where it can be detected that about 27 to 28 game balls are present in the payout ball passage leading to the ball payout device. That is, the ball break switch 187 has a maximum payout amount per unit of prize balls (15 in this embodiment) and a maximum payout amount per unit of ball lending (100 yen: 25 in this embodiment). It is installed in a position where it can be confirmed that it is secured.

  The game ball paid out from the ball payout device is guided to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45.

  When a lot of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out, the hitting ball supply tray 3 becomes full, and finally game balls are paid out after the game balls reach the contact port 45. The game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the drive of the launching device also stops.

  As shown in FIG. 4, a ball removal passage 191 is formed on the side of the ball payout device from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is an exploded perspective view showing a configuration example of the ball dispensing device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, 142 as the prize ball case 40A. The upper portions of the cases 140 and 141 are provided with holes 170 and 171 communicating with the lower ball passage of the ball break switch 187, and the game balls flow into the ball dispensing device 97 through the holes 170 and 171.

  The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a drive source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted to the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

  The ball passage 293 is provided with a sorting member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when the winning ball is paid out, the game ball falls down so that the game ball flows down one flow path in the ball passage 293, and when the ball is lent, the game ball flows down the other flow path in the ball passage 293. To fall down. The payout motor 289 and the solenoid 310 are controlled by a payout control CPU mounted on the payout control board 37. The payout control CPU controls the payout motor 289 and the solenoid 310 in accordance with a command from the game control CPU mounted on the main board 31.

  A prize ball sensor (prize ball count switch) 301A for detecting a game ball paid out by the ball payout device is provided below the flow path selected at the time of paying out the winning ball, and below the flow path selected at the time of lending the ball. Is provided with a ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by the ball paying device. The detection signal of the winning ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on these detection signals.

  FIG. 6 is a front view showing a part of the switch board 190 installed in the game board 6. As shown in FIG. 6, the switch board 190 is mounted with a connector 922 for connecting the output of the clear switch 921 to another board such as the main board 31 via a cable.

  FIG. 7 is a configuration diagram showing an example of the configuration of the clear switch 921 mounted on the switch board 190. FIG. 7A shows a clear switch 921 having a push button structure. When the clear switch 921 is pressed, a clear switch signal at a low level (ON state) is output and transmitted to the main board 31 or the like via the connector 922. If the clear switch 921 is not pressed, a high level (off state) signal is output.

  FIG. 7B is a configuration diagram illustrating another configuration example of the clear switch 921. The clear switch 921 shown in FIG. 7B includes a switching operation unit 921a for performing selection switching between “OFF”, “ON”, and “clear”. No signal is generated when “OFF” is selected by the switching operation unit 921a. When “ON” is selected, a high level signal is output. The clear switch 921 may also serve as a switch for switching on / off the power supply to the gaming machine 1. In that case, when “OFF” is selected, the power supply to the gaming machine 1 is stopped (the gaming machine is turned off). When “ON” or “Clear” is selected, power is supplied to the gaming machine 1 (the gaming machine is powered on). Further, when “Clear” is selected, a low-level clear switch signal is output.

  In this embodiment, the switch board 190 on which the clear switch 921 is mounted is provided separately from other boards, but the clear switch 921 may be mounted on another board. For example, the power supply board 910 may be mounted. When the clear switch 921 is mounted on the power board 910, even if the power board 910 is used as it is for the replaced game board 6 when the game board 6 is replaced, the replaced game board 6 The game state restoration process or the like can be executed as it is. That is, the power supply board 910 can be reused.

  FIG. 8 is a block diagram illustrating an example of a circuit configuration in the main board 31. 8 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a symbol control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 24a, 29a, 30a, 33a, A switch circuit 58 for supplying signals from the tongue switch 48, the ball break switch 187, the prize ball count switch 301A and the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball apparatus 15, and a solenoid for opening and closing the opening and closing plate 20. 21 and a solenoid circuit 59 for driving a solenoid 21A for switching a route in the special winning opening in accordance with a command from the basic circuit 53 is mounted.

  Although not shown in FIG. 8, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 24a, 29a, 30a and 33a, the full switch 48, the ball running switch 187, the winning ball count switch 301A, etc. Also, what is called a sensor may be used. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program, a RAM 55 as a storage means (variation data storage means) used as a work data area (work area) and a stack area (evacuation area), and a control operation according to the program. CPU 56 and I / O port unit 57 are included. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  Further, a part or all of the RAM (may be a CPU built-in RAM) 55 is a backup RAM that is backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 are saved for a predetermined period.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory display 18, the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board. In addition, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the ball-out lamp 52 provided on the frame side is performed. In addition, display control of the variable display device 9 for variably displaying the special symbol and the normal symbol display 10 for variably displaying the normal symbol is performed by display control means mounted on the symbol control board 80.

  FIG. 9 shows the circuit configuration in the symbol control board 80. The LCD (liquid crystal display device) 82, the normal symbol display 10, and the output ports (ports 0 and 2) of the main board 31 are examples of realization of the variable display device 9. It is a block diagram shown with 570,572 and output buffer circuit 620,62A. The output port (output port 2) 572 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal).

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  FIG. 9 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105 </ b> A and 105 </ b> B can pass signals only in the direction from the main board 31 toward the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input ports. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added between the substrates due to the presence of the noise filter 107, the influence is eliminated. . A noise filter may also be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

  FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full switch 48 is input to the I / O port portion 57 of the main board 31 via the relay board 71. The detection signal from the ball break switch 187 is also input to the I / O port portion 57 of the main board 31 through the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 should stop paying out when the detection signal from the ball-off switch 187 indicates a ball-out state, or when the detection signal from the full-tan switch 48 indicates a full-up state. A payout control command is sent to instruct that this is the case. When receiving a payout control command instructing that payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, the detection signal from the prize ball count switch 301A is input to the I / O port portion 57 of the main board 31 via the relay board 72 and the relay board 71, and also from the payout control board 37 via the relay board 72. Input to the input port 372b. The prize ball count switch 301A is provided in a payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

  When there is a winning, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the payout control command to perform prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 via the output port 372c. Further, an error signal is output to the error display LED 374 via the output port 372d.

  Further, a detection signal from the payout motor position sensor for detecting the rotational position of the ball lending count switch 301B and the payout motor 289 is input to the input port 372b of the payout control board 37 via the relay board 72. . The ball lending count switch 301B is provided in a payout mechanism portion of the ball payout device 97, and detects a lending ball actually paid out. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the drive signal to the sorting solenoid 310 is transmitted. Is transmitted to the sorting solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372b and the output port 372e.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to a non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, at least a part of the RAM (may be a CPU built-in RAM) present on the payout control board 37 is backed up by a backup power source created on the power board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 11 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of the electric part control boards such as the main board 31, the symbol control board 80, the sound control board 70, the lamp control board 35, and the payout control board 37, and each electric part control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. Further, a capacitor 916 serving as a backup power source, that is, a memory holding power supply means, is charged from a line of power source for driving DC + 5V, that is, an IC on each substrate. Note that VSL is generated by rectifying and boosting AC24V with a rectifier element in the rectifier circuit 912. VSL is a solenoid driving power source.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 includes one or a plurality of converter ICs 922 (only one is shown in FIG. 11), generates + 21V, + 12V, and + 5V based on VSL and outputs the generated voltages to the connector 915. A relatively large capacitor 923 is connected to the input side of the converter IC 922. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as + 30V, + 12V, + 5V, etc., decreases relatively slowly. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board. Further, in FIG. 11, one connector 915 is representatively shown, but the connector is provided for each electric component control board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 has a storage state with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is stopped (a RAM that is backed up by power, that is, a backup storage unit that can be in a storage content holding state even when the power supply is stopped). It becomes a backup power supply that supplies power so that it can be maintained. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line. In this embodiment, +5 V for backup is supplied to the main board 31 and the payout control board 37.

  The power supply board 910 is equipped with a power supply monitoring IC 902 as a power supply monitoring circuit. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. A power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output becomes on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage, which decreases faster than + 12V, and the power supply is stopped, the switch output is turned on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 that is separate from the electrical component control board, a power-off signal can be supplied from the power monitoring circuit to the plurality of electrical component control boards. Even if there are any number of electrical component control boards that require a power-off signal, it is only necessary to provide one power supply monitoring means. Therefore, even if each electrical component control means in each electrical component control board performs recovery control described later. The cost of the gaming machine does not increase so much.

  In the configuration shown in FIG. 11, the detection signal (power cut-off signal) of the power monitoring IC 902 is sent to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. For example, a configuration may be adopted in which one detection signal is transmitted to the relay board, and the same signal is distributed from the relay board to each electrical component control board. Further, a buffer circuit corresponding to the number of substrates that require a power-off signal may be provided. Further, regarding the power-off signal output to the main board 31 and the payout control board 37, the monitoring voltage of the power-supply monitoring circuit that outputs the power-off signal may be different.

  FIG. 12 is a block diagram illustrating a configuration example around the CPU 56 in the main board 31. As shown in FIG. 12, the power-off signal from the power supply monitoring circuit (power supply monitoring means; first power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. Therefore, the CPU 56 can confirm the occurrence of the stop of power supply to the gaming machine by the non-maskable interrupt (NMI) process.

  FIG. 12 also shows a system reset circuit 65. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same as the power supply voltage monitored by the power supply monitoring circuit, and the voltage value is lower than a predetermined value (the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). When the value is less than or equal to, the output is set to low level. Accordingly, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit, and then the system is reset.

  As shown in FIG. 12, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the power supply monitoring circuit (the voltage that outputs the power-off signal) is + 22V, and the detection voltage for setting the reset signal to low level is + 9V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 monitor the voltage of the same power supply VSL. It is possible to reliably set the difference in timing for outputting the signal within a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop process in response to the power-off signal from the power supply monitoring circuit until the completion of the power supply stop process.

  The power supply voltage monitored by the power supply monitoring circuit and the system reset circuit 65 may be different. The system reset circuit 65 corresponds to second power supply monitoring means.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if power supply to the gaming machine is stopped Is done. When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the gaming state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

  In the configuration shown in FIG. 12, although the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the reset is surely released even if the rising timing of the reset signal is only once. When the CPU is used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The PIO has 4 bits PB0 to PB3 and 1 byte port PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output.

  FIG. 13 and FIG. 14 are explanatory diagrams showing assignment of output ports in this embodiment. As shown in FIG. 13, the output port 0 is an output port for an INT signal of a control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1, and the 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2. The 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. As shown in FIG. 14, 8-bit data of the sound control command sent to the sound control board 70 is output from the output port 4.

  Further, various information output signals from the output port 5 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output. Then, a drive signal from the output port 6 to the solenoid 16 for opening and closing the variable winning ball apparatus 15, the solenoid 21 for opening and closing the opening / closing plate 2 of the big winning opening, and the solenoid 21A for switching the path in the big winning opening. Is output.

  As shown in FIG. 14, each INT signal (payout control signal INT, display control signal INT, lamp control signal INT) output to the payout control board 37, the symbol control board 80, the lamp control board 35, and the sound control board 70. And an output port (output port 0) for outputting the voice control signal INT) and an output port for outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7 and the voice control signals CD0 to CD7. (Output ports 1 to 4) are different ports.

  Therefore, when outputting the INT signal, the possibility that the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, and the audio control signals CD0 to CD7 are erroneously changed is reduced. Further, when outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, or the audio control signals CD0 to CD7, the possibility of erroneously changing the INT signal is reduced. As a result, a command for each electric component control board is more reliably sent from the game control means of the main board 31. Furthermore, since all the INT signals are output from the output port 0, the burden of the INT signal output process of the game control means is reduced.

  FIG. 15 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 15, the bits 0 to 7 of the input port 0 detect the winning port switches 33a, 24a, 29a, 30a, the start port switch 14a, the count switch 23, the V winning switch 22, and the gate switch 32a, respectively. A signal is input. In addition, the award ball count switch 301A, the full switch 48, the ball break switch 187 detection signal, the count switch short-circuit signal, and the clear switch 921 detection signal are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. As described above, the detection signal of the clear switch 921, that is, the operation signal of the operation means is a bit in the same input port as the input port (an input unit having an 8-bit configuration) to which the detection signal of the switch for detecting the game ball is input. (Input port circuit). Note that the detection signal of the clear switch 921 indicating the switch operation state corresponds to the output of the operation signal.

  Next, the operation of the gaming machine will be described. FIG. 16 is a flowchart showing main processing executed by game control means (CPU 56 and peripheral circuits such as ROM and RAM) in the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts main processing after step S1. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is in the high level (see FIG. 15). Further, for example, the game store clerk can easily execute the initialization process by starting the power supply to the gaming machine while the clear switch 921 is turned on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. In this example, as shown in FIG. 17, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, there is no backup (OFF). State).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped (step S10). ). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  In this way, it is possible to accurately return the gaming state to the state when the power supply is stopped by checking whether the data in the backup RAM area is stored using the backup flag and check data such as a checksum. it can. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the state recovery process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol process flag, a payout command storage pointer, a winning ball flag, a ball out flag, a payout A work area setting process for setting an initial value to a flag such as a stop flag for selectively performing processing according to the control state is performed (step S12). Further, a process of transmitting to the payout control board 37 a payout permission state designation command (hereinafter referred to as a payout enable state designation command) instructing that payout from the ball payout device 97 is possible (step S13). . Further, a process of transmitting an initialization command for initializing other sub boards (lamp control board 35, sound control board 70, symbol control board 80) to each sub board is executed (step S14). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the extinction of the prize ball lamp 51 and the ball-out lamp 52 (to the lamp control board 35) Etc).

  In the initialization process, a payout enable state designation command is always transmitted to the payout control board 37. Even if the state of the gaming machine is a state in which a payout from the ball payout device 97 is not possible, the fact is detected in the game control process executed immediately after that and an instruction is given that the payout is not possible. There is no problem because a withdrawal prohibition state designation command to be sent (hereinafter referred to as a withdrawal stop state designation command) is transmitted. In the process of transmitting the payable state designation command and the initialization command to other sub-boards, for example, the address of the table (ROM area) in which each command is set is set to the pointer, and the command setting process (see FIG. 37) may be called.

  Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S15). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

When the execution of the initialization process (steps S11 to S15) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is
This is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process described later, and thus conflicts with the process in the timer interrupt process. This is to avoid that. That is, if the timer interrupt is generated during the process of step S17 and the counter value for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  FIG. 18 is a flowchart illustrating an example of the game state recovery process. In the game state restoration process, the CPU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (stack pointer save buffer in the work area backed up by power) in the power supply stop process described in detail later. Therefore, in step S81, the RAM area value is set in the stack pointer to return. Note that the register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

  Next, the CPU 56 checks whether or not the payout has been stopped (step S82). Whether or not the payout is stopped is determined according to a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol, This is confirmed by a payout stop flag as payout state data in a symbol process flag, a payout command storage pointer, a winning ball flag, a ball runout flag, a payout stop flag, etc. If it is in the payout stop state, a payout control command (payout stop state designation command) for instructing the payout stop is transmitted to the payout control means mounted on the payout control board 37 (step S83). If it is not in the payout stop state, a payout control command (payable state designation command) for instructing that payout is possible is sent to the payout control means (step S84). As will be described later, the payout stop flag is set when a payout stop state designation command is received, and is reset when a payout ready state designation command is received. Therefore, the payout stop flag can be issued with a payout stop state designation command. Among the state designation commands, data corresponding to the command last transmitted by the game control means before the power supply is stopped is set.

  Since the payout control means cannot recognize the shortage of the supply balls or the full tank of the surplus ball receiving tray 4, if there is no notification from the game control means, the shortage of the supply balls or the surplus ball receiving tray 4 is full at the time of recovery from a power failure or the like. Nevertheless, there is a risk of starting the game ball payout process. However, in this embodiment, in the game state recovery process, a payout control command for instructing stoppage of payout or a payout control command for instructing that payout is possible is transmitted. Even though the surplus ball receiving tray 4 is full, the game ball payout process is not started.

  Here, when the payout state determination means (a part of the game control means) for determining whether or not the game medium can be paid out detects that the payout is not possible, one type of the game medium is determined regardless of the cause. The payout stop state designation command is transmitted. However, the command may be transmitted separately for each cause (in this example, a command indicating a shortage of supply balls and a command indicating a lower pan full). Further, when the game ball cannot be paid out, a command instructing to prohibit the release of the game ball may be transmitted to the payout control board 37 in order to prohibit the continuation of the game. When the payout control means mounted on the payout control board 37 receives a command instructing prohibition of the game ball, the drive of the hitting ball launching device is stopped. In addition, when the game ball cannot be paid out, the game control means may give a signal instructing the launch control means to prohibit the launch of the game ball directly. Further, the payout control means may stop driving the ball striking device when a payout stop state designation command is received.

  Next, the CPU 56 checks whether or not the special display is changing in the variable display device 9 when the power supply is stopped (step S85). Whether or not the special symbol is changing when the power supply is stopped can be confirmed by, for example, the value of the special symbol process flag stored in the RAM area where the power is backed up. If the special symbol is changing, a special symbol power failure recovery command and a display control command for designating the left and right symbols are transmitted to the display control means mounted on the symbol control board 80 (step S86, S87). Here, the left and right symbols designated by the display control command are symbols that should have been stopped and displayed due to the special symbol fluctuation that was performed when the power supply was stopped.

  When receiving the special symbol power failure recovery command, the display control means performs a predetermined notification process. For example, the variable display device 9 displays that a power failure has occurred. Based on the various information that was backed up, the gaming state returns to the state prior to the stop of power supply.After that, when the special symbol change period ends, the gaming control means issues a confirmation command to the display control means. Send. Based on the receipt of the confirmation command, the display control means is in a state where the next special symbol can be changed.

  If the special symbol is not changing, the CPU 56 performs a process of transmitting a display control command for designating the left and right middle symbols, a confirmation command, and a customer waiting demo command to the display control means (steps S88 to S90). ). The left and right symbols designated by the display control command are the symbols displayed on the variable display device 9 when the power supply is stopped.

  When the display control means receives the confirmation command, the display control means controls the variable display device 9 to display the special symbol designated by the display control command for designating the left and right middle symbols. Further, when the customer waiting demonstration command is received, control is performed so that the display state of the variable display device 9 such as the background is set to the standby display state.

  Thereafter, the CPU 56 clears the backup flag (step S91), that is, resets a flag indicating that a predetermined storage protection process has been executed when the previous power supply was stopped. Also, the saved values of various registers are read from the stack area and set in various registers (IX register, HL register, DE register, BC register) (step S92). That is, register restoration processing is performed. Each time each register is restored, the value of the stack pointer is decreased. In other words, the value of the stack pointer is updated to point to the previous address in the stack area. If the parity flag is not turned on, an interrupt permission state is set (steps S93 and S94). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S95).

  Then, the RET instruction is executed. When the RET instruction is executed, the CPU 56 realizes a program return operation by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state restoration process. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S92, the stack pointer indicating the stack area is executed when the power supply stop process by the NMI is started. Indicates the area where the program address is saved. That is, the return address stored in the stack area pointed to by the returned stack pointer is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, in response to the RET instruction subsequent to step S95, the process returns to the address where the NMI occurred when the power supply was stopped. That is, recovery control is executed based on the address data (program address data) saved in the stack area.

  When the timer interrupt occurs, the CPU 56 performs the register saving process (step S20), and then executes the game control process of steps S21 to S32 shown in FIG. In the game control process, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 33a, 24a, 29a, and 30a via the switch circuit 58. These state determinations are performed (switch processing: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs processing for setting a display control command related to the special symbol in a predetermined area of the RAM 55 and transmitting the display control command (special symbol command control processing: step S28). Further, a process for transmitting a display control command by setting a display control command related to the normal symbol in a predetermined area of the RAM 55 is performed (normal symbol command control process: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21, and 21A in response to a drive command in order to open or close the variable winning ball device 15 or the opening / closing plate 20, or to switch the game ball passage in the special winning opening. To do.

  Then, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals of the prize opening switches 33a, 24a, 29a, 30a (step S32). Specifically, a payout control command indicating the number of winning balls is output to the payout control board 37 in response to detection of winning based on the winning opening switch 33a, 24a, 29a, 30a being turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of prize balls. Thereafter, the contents of the register are restored (step S33), and the interrupt permission state is set (step S34).

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  20 and 21 are flowcharts showing a processing example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910. When a non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 sets the address of the program executed when the non-maskable interrupt occurs (specifically, the next address after completion of execution) as a stack pointer. Is saved in the stack area pointed to by and the value of the stack pointer is increased. That is, the stack pointer value is updated to point to the next address in the stack area.

  In the power supply stop process, the CPU 56 saves the AF register (accumulator and flag register) in the stack area pointed to by the stack pointer (step S51). At this time, the value of the stack pointer is updated to point to the next address in the stack area. Further, the interrupt flag is copied to the parity flag (step S52). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether the interrupt is permitted or the interrupt prohibited state, and is in a control register built in the CPU 56. The on state of the interrupt flag indicates that the interrupt is prohibited. As described above, the parity flag is referred to in the gaming state restoration process. In the gaming state recovery process, if the parity flag is on, the interrupt permission state is not set.

  Further, the BC register, DE register, HL register, and IX register are saved in the stack area pointed to by the stack pointer (steps S54 to S57). At this stage, the address of the program, BC register, DE register, HL register, and IX register values that were being executed when the non-maskable interrupt occurred are sequentially stored in the stack area. Each time each register is saved, the value of the stack pointer is updated to point to the next address in the stack area. Further, the value of the stack pointer is saved in a predetermined area (stack pointer saving buffer) in the work area (step S58).

  Next, the backup specified value ("55H" in this example) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, parity data is created (steps S60 to S67). That is, first, the clear data (00) is set in the checksum data area (step S60), and the checksum calculation start address is set in the pointer (step S61). Also, the number of checksum calculations is set (step S62).

  Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S63). The calculation result is stored in the checksum data area (step S64), the pointer value is incremented by 1 (step S65), and the value of the checksum calculation count is decremented by 1 (step S66). The processes in steps S63 to S66 are repeated until the value of the checksum calculation count becomes 0 (step S67).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). Then, the inverted data is stored in the checksum data area (step S69). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S70). Thereafter, the built-in RAM 55 cannot be accessed. Therefore, even if a program runaway occurs as the voltage drops, the stored contents of the RAM will not be destroyed.

  Further, the CPU 56 sets the clear data (00) in an appropriate register (step S71), and sets the number of processes (in this example, “7”) in another register (step S72). Further, the address of the output port 0 is set in the IO pointer (step S73). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S74), the value of the IO pointer is incremented by 1 (step S75), and the value of the processing number is subtracted by 1 (step S77). The processes in steps S74 to S76 are repeated until the value of the number of processes becomes zero. As a result, clear data is set in all the output ports 0 to 6 (see FIGS. 13 and 14). As shown in FIGS. 13 and 14, in this example, “1” is in the on state and “00” that is the clear data is set in each output port, so that all the output ports are in the off state.

  Therefore, after the processing for saving the game state (in this example, checksum generation and RAM access prevention) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the gaming state.

  Since each output port is turned off immediately after the processing for saving the gaming state is executed, it is reliably prevented that a situation that does not match the saved gaming state occurs. In other words, in a gaming machine having a variable winning ball device such as a pachinko gaming machine, the position of the variable winning hole in the variable winning ball device and the installation position of the winning port switch for detecting a winning are determined due to mounting. It must be separated to some extent. If the output port, in particular the output port that outputs the signal for opening the variable winning ball device, is not turned off immediately, the power supply will stop when the power supply is stopped, even though the variable prize opening has been won. There may be a situation in which the execution of the process is started and the winning opening switch is not detected. In that case, it is not stored that there was a winning in the variable winning opening. In other words, the gaming state that is actually occurring (the winning has been) does not match the saved gaming state. However, in this embodiment, since the output port is cleared and the variable winning ball device is closed, it is reliably prevented that a situation inconsistent with the saved gaming state occurs.

  In addition, since the output port can be cleared in the process of stopping power supply that is executed before the electric component can be driven, before the electric component can be driven. Each electric component controlled by the game control means can be put into an appropriate operation stop state. For example, the operation of the electrical component is stopped after the operation of the electrical component is stopped, such as closing the open large winning opening and closing the open variable winning ball device 15. be able to. Therefore, it is possible to wait for the restoration of power supply in an appropriate stop state. When the clear process for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  In this embodiment, the power supply stop process is executed according to the NMI. However, the power supply stop signal is connected to the maskable terminal of the CPU 56 and the power supply stop process is executed by the maskable interrupt process. May be. Alternatively, a power-off signal may be input to the input port and the power supply stop process may be executed according to the input port check result.

  FIG. 22 is an explanatory diagram showing an address map of the RAM area in this embodiment. As shown in FIG. 22, the head of the RAM area is assigned to the backup flag area. A checksum buffer area is allocated at the end. An area from the backup flag to the checksum buffer corresponds to a work area, and a stack area is set in an area after the checksum buffer. In this embodiment, the entire RAM area is backed up.

  FIG. 23 is an explanatory diagram for explaining an example of a checksum creation method. However, in the example shown in FIG. 23, the size of the data in the backup RAM area is 3 bytes for simplicity. In the power supply stop process based on the power supply voltage drop, as shown in FIG. 23, initial data (00 (H) in this example) is set as checksum data. Next, an exclusive OR of “00 (H)” and “F0 (H)” is taken, and an exclusive OR of “16 (H)” is taken with the result. Further, an exclusive OR of the result and “DF (H)” is taken. Then, a value (“C6 (H)” in this example) obtained by logically inverting the result (“39 (H)” in this example) is set in the checksum buffer.

  FIG. 23 shows a state where the data “39 (H)” before the logic inversion is stored in the checksum buffer for easy explanation. Note that 00 (H) as the initial data is a value corresponding to the clear data for the checksum data set in step S60, but in practice, the exclusive OR with 00 (H) is before and after the operation. And the value does not change, it is not necessary to perform an exclusive OR operation with 00 (H).

  In this embodiment, the checksum buffer is stored at the last address of the backup RAM area (variable data storage means). Therefore, for example, when checking whether there is an error in the program of the checksum creation method, it is possible to easily check it. This is because it is sufficient to confirm whether or not the value of the final address in the RAM area is correct. In this embodiment, the checksum calculation start address is an address where a backup flag is set, and the checksum calculation final address is the last address in the prize ball control flag buffer (see FIG. 22). . Therefore, if the last address in the backup RAM area is used as the checksum buffer area after the prize ball control flag buffer, there is no waste in the RAM area.

  In consideration of ease of confirmation and prevention of waste of the RAM area, the first address of the backup RAM area may be used as the checksum buffer area.

  Further, at the start of power supply to the gaming machine, it is determined whether or not the parity check is OK (step S9 in FIG. 16). In this determination, parity data generation processing (steps S71 to S77) in the power supply stop processing is performed. ) Is performed, and if the processing result, that is, the operation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

  Although the last or first address of the backup RAM area is used as the checksum buffer area here, the checksum buffer area may be allocated to an intermediate area of the backup RAM area. In this embodiment, the checksum is generated based on the work area data. However, the checksum may be generated including the stack area data.

  Further, in this embodiment, at the start of power supply, a checksum is generated by the same process as the process at the time of power supply stop, and the generated checksum is compared with the checksum stored in the backup RAM. Other methods may be used. For example, using the checksum stored in the backup RAM as an initial value, the calculation is performed for each data that is a calculation target in the power supply stop process, and if the calculation result matches a predetermined value (for example, 00 (H)), the parity is You may make it determine with check OK. The check data for the parity check is not limited to the checksum, and other check data may be used as long as it can be determined whether the contents of the backup RAM are properly stored.

  FIG. 24 is a timing chart showing a state of a power supply voltage drop or an NMI signal (= power supply cut-off signal: power supply stop signal) when power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. In this example, when the voltage drops to +22 V, a power cut-off signal is output from the power monitoring IC 902 mounted on the power board 910 (becomes a low level).

  The power-off signal is introduced into the electrical component control board (in this embodiment, the main board 31 and the payout control board 37) and input to the NMI terminals of the CPU 56 and the payout control CPU 371. The CPU 56 and the payout control CPU 371 execute predetermined power supply stop processing by NMI processing.

  When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the system reset circuit mounted on the main board 31 and the payout control board 37 becomes low level, and the CPU 56 and payout control CPU 371 enters a system reset state. Note that the CPU 56 and the payout control CPU 371 have completed the power supply stop process before being set to the system reset state.

  When the voltage value of VSL is further decreased to be lower than a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot be operated on each substrate. However, at least the main board 31 and the payout control board 37 execute the power supply stop process, and the CPU 56 and the payout control CPU 371 are in the system reset state.

  As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, and the voltage drops when the voltage of the power supply falls below a predetermined value. Generates a signal (power failure detection signal). As shown in FIG. 24, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stop process.

  In this case, the power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, but the timing for generating the power-off signal is the electrical component control that operates with the IC drive voltage. The monitoring target voltage may not be the highest voltage of the power source VSL as long as the operation time for the means to perform the predetermined power supply stop process is ensured. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off signal can be generated at such a timing that the operation time for the electrical component control means to perform the predetermined power supply stop process is ensured. .

  In this case, as described above, the monitoring target voltage is preferably a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped. That is, since the voltage (switch voltage) supplied to the various switches of the gaming machine is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor a voltage higher than at least the switch voltage.

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an ON state. As shown in FIG. 25, the switch timer is provided for the number N of detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 12. Further, in the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (from top to bottom shown in FIG. 15).

  FIG. 26 is a flowchart illustrating a processing example of the switch process in step S21 in the game control process. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs data input to the input port 0 (step S101). Next, “8” is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

  FIG. 27 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, the switch timer pointed to by the pointer (switch timer address is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S124). Data of input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S125), that is, if the detection signal of the winning opening switch 33a is on, the switch timer value is incremented by 1 (step S127). If the value after addition is not 0, the addition value is returned to the switch timer (steps S128 and S129). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0”, that is, if the detection signal of the winning opening switch 33a is in the OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S130) and subtracts 1 from the number of processes (step S131). If the number of processes is not 0, the process returns to step S122. Then, the processes of steps S122 to S132 are repeated.

  The processes in steps S122 to S132 are repeated for the number of processes, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially checked to determine whether it is on or off. If it is ON, the value of the corresponding switch timer is incremented by one.

  The CPU 56 inputs the data input to the input port 1 in step S105 of the switch process. Next, “4” is set as the processing number (step S106), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S107). Then, a switch check processing subroutine is called (step S108).

  In the switch check processing subroutine, since the above-described processing is executed, the processing in steps S122 to S132 is repeated for the number of processing, that is, four times, and the detection signal of the switch input to the 4 bits of the input port 1 during that time. Then, a check process is sequentially performed to determine whether the state is on or off. If the state is on, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

  28 to 30 are flowcharts showing an example of the prize ball process in step S31 in the game control process. In this embodiment, in the prize ball processing, it is determined whether or not the prize opening switches 33a, 24a, 29a, 30a, the count switch 23, and the start opening switch 14a to be paid out are surely turned on. When turned on, control is performed so that a payout control command indicating the number of award balls is sent to the payout control board 37, and it is determined whether the full tank switch 48 and the ball shortage switch 187 are turned on reliably. Processing such as control to send a predetermined payout control command to the payout control board 37 is performed.

  In the prize ball process, the CPU 56 sets “1” as the offset of the input determination value table (step S150), and sets “9” as the offset of the address of the switch timer (step S151). The offset “1” in the input determination value table (see FIG. 32) means that the second data “50” in the input determination value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “9” designates the switch timer corresponding to the full switch 48. Means. Then, a switch-on check routine is called (step S152).

  The input determination value table is a ROM area in which a determination value for determining that the switch has been turned on when it is detected how many times it is continuously turned on is set for each switch. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 32, the input determination value table includes “2”, “50”, “250”, “30”, “250”, “1” in order from the top, that is, in order from the smallest address value. The judgment value is set. In the switch-on check routine, the judgment value set at the address determined by the head address and the offset value in the input judgment value table is compared with the value of the switch timer determined by the head address and the offset value of the switch timer. If they match, for example, a switch-on flag is set.

  An example of a switch-on check routine is shown in FIG. In the switch-on check routine, if the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch on determination value “50”, the switch on flag is set (step S153), so the full tank flag is set. (Step S154). Although not explicitly shown in FIG. 28, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

  Further, the CPU 56 sets “2” as the offset of the input determination value table (step S156), and sets “0A (H)” as the offset of the switch timer address (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “0A (H)” is designated by the switch timer corresponding to the ball break switch 187. Means that Then, a switch-on check routine is called (step S158).

  In the switch-on check routine, if the value of the switch timer corresponding to the ball-out switch 187 matches the ball-out switch-on determination value “250”, the switch-on flag is set (step S159). It is set (step S160). Although not explicitly shown in FIG. 28, a switch-off timer corresponding to the ball-out switch 187 is prepared, and when the value becomes 50, the ball-out flag is reset.

  Then, the CPU 56 confirms whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command which is a payout control command for instructing the payout control board 37 that payout should be stopped. This is a state in which the payout stop flag is set. If it is not in the payout stop state, it is confirmed whether or not the above-described ball-out state flag or full tank flag is turned on (step S202).

  When either of them changes to the ON state, a payout stop state flag is set (step S203), a command transmission table relating to a payout stop state designation command is set (step S204), and command set processing is called (step S205). . In step S204, the head address of the command transmission table (ROM) storing the payout control command of the payout stop state designation command is set as the address of the command transmission table. In the command transmission table relating to the payout stop state designation command, INT data described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set. In step S202, when one of the flags is already in the on state and the other flag is in the on state, the processes in steps S203 to S205 are not performed.

  If it is in the payout stopped state, it is checked whether both the ball-out state flag and the full tank flag are turned off (step S206). When both are turned off, the payout stop flag is reset (step S207), the command transmission table relating to the payable state designation command is set (step S208), and the command setting process is called (step S209). In step S208, the start address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payout enable state designation command, INT data, data of the first byte of the payout control command, and data of the second byte of the payout control command, which will be described later, are set.

  Further, the CPU 56 sets “0” as the offset of the input determination value table (step S221), and sets “0” as the offset of the switch timer address (step S222). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “0” designates the switch timer corresponding to the winning port switch 33a. Means. Also, “4” is set as the number of repetitions (step S223). Then, a switch-on check routine is called (step S224).

  In the switch-on check routine, the CPU 56 sets the head address of the input determination value table (see FIG. 32) (step S281). Then, an offset is added to the address (step S282), and a switch-on determination value is loaded from the address after the addition (step S283).

  Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the address after the addition (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the value of the switch timer corresponding to the switch is loaded.

  Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, a switch-on flag is set (step 128).

  In this case, in the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value “2” (step S225). The switch check-on routine is executed for the number of repetitions initially set (step S228, S229) while the offset of the switch timer address is updated (step S230). For 24a, 29a and 30a, the value of the corresponding switch timer is compared with the switch-on determination value “2”.

  When the switch-on flag is set, “10” as the number of prize balls to be paid out is set in the ring buffer (step S226). Then, 10 is added to the stored value of the total winning ball number storage buffer (step S227). When data is written to the ring buffer, the write pointer is incremented. When data is written to the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

  The total winning ball number storage buffer is a buffer for storing a cumulative value of the number of winning balls instructed to the payout control means (however, subtracted when paying out), and is formed in the backup RAM. In this embodiment, when data is written to the ring buffer, an addition process is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, the number of prize balls corresponding to the payout control command to be output may be added to the value stored in the total prize ball number storage buffer.

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S231), and sets “4” as the offset of the switch timer address (step S232). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “4” designates the switch timer corresponding to the start port switch 14a. Means. Then, a switch-on check routine is called (step S233).

  In the switch-on check routine, if the value of the switch timer corresponding to the start port switch 14a matches the switch-on determination value “2”, the switch-on flag is set (step S234). When the switch-on flag is set, “6” as the number of prize balls to be paid out is set in the ring buffer (step S235). Further, 6 is added to the stored value of the total winning ball number storage buffer (step S236).

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S241), and sets “5” as the offset of the switch timer address (step S242). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “5” indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, a switch-on check routine is called (step S243).

  In the switch-on check routine, if the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, “15” as the number of prize balls to be paid out is set in the ring buffer (step S245). Further, 15 is added to the stored value of the total winning ball number storage buffer (step S246).

  If data exists in the ring buffer (step S247), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (next area of the ring buffer). (Step S249), a command transmission table relating to the number of winning balls is set (Step S250), and command set processing is called (Step S251). The operation of the command set process will be described in detail later.

  In step S250, the head address of the command transmission table (ROM) in which the payout control command relating to the number of winning balls is stored is set as the address of the command transmission table. In the command transmission table relating to the number of winning balls, INT data (01 (H)) described later, data of the first byte of the payout control command (F0 (H)), and data of the second byte of the payout control command are set. ing. However, “80 (H)” is set as the second byte data.

  As described above, when the game control means tries to output a payout control command for instructing the number of prize balls to the payout control board 37, the command transmission table address setting and the transmission buffer setting regarding the number of prize balls are performed. . Then, a payout control command is sent to the payout control board 37 based on the command transmission table related to the number of winning balls and the setting contents of the transmission buffer by command set processing. In step S247, whether or not there is data can be confirmed by the difference between the write pointer and the read pointer. However, a counter indicating the number of unprocessed data in the ring buffer is provided, and there is data by the count value. It may be confirmed whether or not.

  Then, when the content of the total prize ball number storage buffer is not 0, that is, when there is still a prize ball remaining, the CPU 56 turns on a prize ball paying-in flag (steps S252 and S253).

  Further, when the winning ball payout flag is on (step S254), the CPU 56 monitors the number of winning balls actually paid out from the ball paying device 97 and subtracts the stored value of the total winning ball number storage buffer. The number of winning balls to be subtracted is performed (step S255). When the prize ball paying flag changes from on to off, a lamp control command for instructing lighting of the prize ball lamp 51 is sent to the lamp control board 35.

  In this embodiment, even when the payout is stopped (steps S201 and S206), the processing of steps S221 to S251 is executed. That is, the game control means can send out a payout control command for instructing the number of prize balls even when the payout is stopped. That is, a command for instructing the number of prize balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is canceled, the payout of the prize balls can be started early. Further, the game control means does not require a large storage area for storing the number of winning balls based on winning in the payout stop state.

  Next, a method for sending a control command from the game control means to each electric component control means will be described. When a control command is to be output from the game control means to another electrical component control board (sub board), the head address of the command transmission table is set. FIG. 33A is an explanatory diagram showing a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

  Although the EXT data itself may be set in the area of the command data 2, the command data 2 may be set with data for designating the address of the table storing the EXT data. . For example, if bit 7 (work area reference bit) of command data 2 is 0, it indicates that EXT data itself is set in command data 2. Such EXT data is data in which bit 7 is 0. In this embodiment, if the work area reference bit is 1, it indicates that the contents of the transmission buffer are used as EXT data. If the work area reference bit is 1, the other 7 bits may be configured to indicate an offset for designating an address of a table storing EXT data.

  FIG. 33B is an explanatory diagram showing a configuration example of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is “1”, it indicates that a payout control command should be sent. Accordingly, the CPU 56 sets “01 (H)” in the INT data, for example, in the prize ball process (step S31 of the main process). Bit 1 in the INT data indicates whether or not a display control command should be sent to the symbol output control board 80. If bit 1 is “1”, it indicates that a display control command should be sent. Accordingly, the CPU 56 sets “02 (H)” in the INT data, for example, in the special symbol command control process (step S27 of the main process).

  Bits 2 and 3 of the INT data are bits indicating whether or not a lamp control command and a sound control command should be sent, respectively, and the CPU 56 performs special symbol process processing when it is time to send those commands. Etc., INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MODE data and EXT data are set to the command data 1 and the command data 2.

  In this embodiment, a ring buffer and a transmission buffer are prepared for the payout control command as shown in FIG. In the prize ball processing, when the prize ball payout condition is established, the number of prize balls according to the established condition is sequentially set in the ring buffer. Further, when a payout control command relating to the number of prize balls is sent, one piece of data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 33C, data corresponding to 12 payout control commands can be stored in the ring buffer. That is, there are 12 buffers. Note that the number of buffers in the ring buffer may be a number corresponding to the number of winning openings for generating a prize ball. This is because even when simultaneous winnings occur, it is possible to store payout control command data based on each winning.

  FIG. 34 is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to another electrical component control board. In this embodiment, the control command has a 2-byte configuration, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”. As described above, the control command serving as a command to the electrical component control board is composed of a plurality of data and can be distinguished from each other by the first bit. Note that the command form shown in FIG. 34 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used. 34 illustrates the payout control command sent to the payout control board 37, but the control commands sent to other electrical component control boards have the same configuration.

  FIG. 35 is a timing chart showing the relationship between the 8-bit control signals CD0 to CD7 and the INT signal that constitute the control command for each electrical component control means. As shown in FIG. 35, when the period indicated by A elapses after MODE or EXT data is output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data. The INT signal, which is a signal indicating the above, is set to a high level (ON data). Further, when the period indicated by B elapses thereafter, the INT signal is set to low level (off data). Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the second byte of data is transmitted to the output port after a period indicated by C. Regarding the second byte data, the periods A and B are the same as in the first byte. In this way, the capture signal is output for each of the MODE and EXT data.

  The period A is a period required for the CPU 56 to prepare for sending a command, that is, a process required to set a send command in the buffer, and a period for stabilizing data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, the INT signal as the capture signal is output after a predetermined period (period A: part of the off output period) has elapsed. The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the off-output period) is a period set so that the electrical component control means can reliably capture data. During the period of B and C, the data on the signal line does not change. That is, the data output is maintained until the period of B and C elapses.

  In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are the same command. It is sent out using a transmission processing routine (common module). Therefore, the period of B and C, that is, the period from when the INT signal related to the first byte rises to when the second byte data starts to be transmitted is longer than the reception processing time in the electrical component control means that takes the longest time for command reception processing. Is set to be longer.

  Each electrical component control means detects that the INT signal has risen, and starts a 1-byte data capture process, for example, by an interrupt process.

  Since the period of B and C is longer than the reception processing time in the electrical component control means that takes the longest time for command reception processing, even if the game control means controls the command transmission process for each electrical component control means with the common module Any electric component control means can reliably receive a control command from the game control means.

  The CPU 56 is ready to send the next data after a predetermined period of time has elapsed after executing the INT signal output process. During the predetermined period (B and C periods), the data is sent before the INT signal output process. Is longer than the period (period A) from when the INT signal starts to be output. As described above, the period A is a stabilization period in the command signal line, and the periods B and C are periods for securing a time required for the receiving side to capture data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can reliably receive the command, and the transmission of one command is completed. This also has the effect of shortening the time required for.

  FIG. 36 is an explanatory diagram showing an example of the contents of the payout control command. In the example shown in FIG. 36, the command FF00 (H) with MODE = FF (H) and EXT = 00 (H) is a payout control command (payout enable state designation command) for instructing that payout is possible. is there. A command FF01 (H) with MODE = FF (H) and EXT = 01 (H) is a payout control command (payout stop state designation command) for instructing that payout should be stopped. A command F0XX (H) with MODE = F0 (H) is a payout control command for designating the number of winning balls. “XX”, which is EXT, indicates the number of payouts.

  When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout payout and ball lending are stopped, and when the payout control command of FF00 (H) is received, the payout ball payout And you can rent a ball. When a payout control command for designating the number of prize balls is received, prize ball payout control is performed according to the number designated by the received command.

  The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the level of the INT signal changes. In this example, “recognizable only once” means that in each of the first and second bytes of the payout control signal. Accordingly, the INT signal is output in a pulse shape (rectangular wave shape) only once.

  When a control command for each electrical component control board is output to the corresponding output port (output ports 1 to 4), any one of the bits 0 to 3 of the output port 0 is “1” ( However, the bit arrangement in the INT data and the bit arrangement in the output port 0 correspond to each other. Accordingly, when a control command is sent to each electric component control board, the INT signal can be easily output based on the INT data.

  FIG. 37 is a flowchart illustrating a processing example of command set processing (steps S205, S209, and S251). The command set process is a process including a command output process and an INT signal output process. In the command set process, the CPU 56 first saves the address of the command transmission table (the contents of the pointer as the transmission signal instruction means) to the stack or the like (step S331). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for a command transmission process to be described later. Also, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1.

  Therefore, the CPU 56 reads the command data 1 and sets it as the argument 2 (step S334). The argument 2 is also input information for a command transmission process to be described later. Then, the command transmission processing routine is called (step S335).

  FIG. 38 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set as the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the port 1 address for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the port 1 address is the output port address for outputting the payout control signal. The addresses of ports 2 to 4 are the addresses of output ports for outputting display control signals, lamp control signals, and audio control signals.

  Next, the CPU 56 shifts the comparison value to the right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether or not the carry bit has become 1 (step S355). When the carry bit becomes 1, it means that the rightmost bit in the INT data is “1”. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit is set to 1 in the first shift process.

  When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S 356). Since the address of port 1 is set as the IO address when the first shift processing is performed, MODE data of the payout control command is output to port 1 at that time.

  Next, the CPU 56 adds 1 to the IO address (step S357) and subtracts 1 from the number of processes (step S358). If port 1 is indicated before addition, the address of port 2 is set as the IO address by the addition processing for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0, returns to step S354. In step S354, the shift process is performed again.

  In the second shift process, the value of bit 1 in the INT data is pushed out, and the carry flag is set to “1” or “0” depending on the value of bit 1. Therefore, it is checked whether or not it is specified that the display control command should be sent. Similarly, it is checked whether or not the lamp control command and the sound control command are to be sent by the third and fourth shift processes. Thus, when each shift process is performed, the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process is included in the IO address. Is set.

  Therefore, when the carry flag becomes “1”, a control command is sent to the corresponding output port (port 1 to port 4). That is, a single common module can perform control command transmission processing for each electric component control means.

  In addition, since it is determined to which electrical component control means the control command should be output only by the shift processing, the process for determining to which electrical component control means the control command should be output is simplified. It has become.

  Next, the CPU 56 reads the content of the argument 1 in which the INT data before the start of the shift process is stored (step S360), and outputs the read data to the port 0 (step S361). In this embodiment, the address of port 0 is a port for outputting an INT signal for each control signal, and bits 0 to 4 of port 0 are a payout control INT signal, a display control INT signal, and a ramp, respectively. This is a port for outputting a control INT signal and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 is “1”. It has become. Therefore, the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

  Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and subtracts one by one until the value becomes 0 (steps S363 and S364). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S365), and the data is output to port 0 (step S366). Therefore, the INT signal becomes low level. Then, a predetermined value is set in the wait counter (step S362), and 1 is subtracted one by one until the value becomes 0 (steps S368 and S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time taken in steps S367 to S369 to the subsequent processing time (the time required for the control to output EXT data if MODE data is output at this time). ) Is added. Thus, even if commands are sent continuously by setting the period C, there is a predetermined period after the completion of the output of one command until the next command transmission is started. As a result, it is possible to easily identify the breaks between successive commands on the side of the electric component control means that receives the commands, and each command is reliably received.

  Therefore, the value set in the wait counter in step S367 is a value such that the period C is sufficient to ensure that all electrical component control means that are the control command reception target perform the command reception process. is there. The value set in the wait counter is a value such that the period C is longer than the time required for the processing in steps S357 to S359 (corresponding to the period A). If it is desired to make the period A longer, wait processing for creating the period A (for example, processing for setting a predetermined value in the weight counter and performing subtraction until the value of the weight counter becomes 0) is performed. Do.

  As described above, the MODE data of the first byte of the control command is transmitted. Therefore, the CPU 56 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the command data 2 area of the third byte is designated. The CPU 56 loads the contents of the indicated command data 2 into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S339). If not 0, the contents of the transmission buffer are loaded into the argument 2 (step S341). When the extension data is used when the value of the work area reference bit is “1”, the head address of the command extension data address table is set in the pointer, and the command data is set in the pointer. The address is calculated by adding 2 bits 6 to 0. Then, the data of the area pointed to by the address is loaded into the argument 2.

  Since data capable of specifying the number of winning balls is set in the transmission buffer, the data is set in the argument 2. If the extension data is used when the value of the work area reference bit is “1”, the command extension data address table contains EXT data that can be sent to the electrical component control means. Set sequentially. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table corresponding to the contents of the command data 2 is loaded into the argument 2.

  Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, the EXT data is transmitted at the same timing as the transmission of MODE data.

  As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte configuration is transmitted to the corresponding electrical component control means. The electrical component control means starts the capture process of the control command when the rising edge of the INT signal is detected. For any electrical component control means, a new signal from the game control means is signaled before the capture process is completed. There is no output on the line. That is, reliable command reception processing is performed in each electric component control means. In addition, each electric component control means may start taking in the control command at the falling edge of the INT signal. Further, the polarity of the INT signal may be reversed from that shown in FIG.

  In this embodiment, in the prize ball processing, when the prize ball payout condition is satisfied, data capable of specifying the number of prize balls is stored in a ring buffer capable of storing a plurality of data at the same time, and the number of prize balls is designated. When the payout control command is sent, the data in the ring buffer area pointed to by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of winning ball payout conditions are satisfied at the same time, data capable of specifying the number of winning balls based on the satisfaction of these conditions is stored in the ring buffer, so there is no problem in command output processing based on the satisfaction of each condition. Executed.

  Furthermore, in this embodiment, both a payout stop state designation command or a payout enable state designation command and a command indicating the number of prize balls can be sent out within one prize ball process. That is, a plurality of commands can be sent within one control period activated every 2 ms. In this embodiment, a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, payout control command) to each control means. When data that can specify a control command is set in the ring buffer of the control command, lamp control command, and sound control command, a plurality of display control commands, lamp control commands, and sound control commands are performed in one command control process. It is also possible to configure so that That is, a plurality of control commands can be sent simultaneously (meaning in the start cycle of the game control process, that is, the 2 ms timer interrupt process). Since the sending timing of these control commands is generated at the same time in the progress of the game effect, it is convenient to have such a configuration. However, since the payout control command is generated regardless of the progress of the game effect, it is generally not sent simultaneously with the display control command, the lamp control command, and the sound control command.

  FIG. 39 is a flowchart showing an example of the winning ball number subtraction process. In the winning ball number subtraction process, the CPU 56 first loads the stored value of the total winning ball number storage buffer (step S381). Then, it is confirmed whether or not the stored value is 0 (step S382). If 0, the process ends.

  If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the load value is compared with the ON determination value (in this case, “2”) (step S384). If they match (step S385), it is assumed that the prize ball count switch 301A has been turned on, that is, one game ball has been paid out from the ball payout device 97, and the stored value in the total prize ball number storage buffer is set. 1 is subtracted (step S386).

  Also, the value of the prize ball information counter is incremented by 1 (step S387). If the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information output counter is incremented by 1 (step S389), and the value of the prize ball information counter is incremented by -10 (step S390). The value of the prize ball information output counter is referred to in the information output process (step S29) in the game control process shown in FIG. 19, and if the value is 1 or more, the prize ball signal (bit of output port 5) 7: See FIG. 14), one pulse is output. Therefore, in this embodiment, each time ten game balls are paid out as prize balls, one prize ball signal is output to the outside of the gaming machine.

  When the value stored in the total prize ball number storage buffer becomes 0 (step S391), the prize ball paying-in flag is cleared (step S392), and a lamp control command is sent to notify that there is no prize ball remaining number. After command data indicating that the prize ball lamp 51 is turned off is set in the command transmission table (step S393), a lamp control command sending process is executed (step S394).

  Next, payout control means will be described as an example of electrical component control means other than game control means.

  FIG. 40 is a block diagram showing an example of the configuration around the payout control CPU 371. As shown in FIG. 40, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. Yes. Therefore, the payout control CPU 371 can confirm the occurrence of the stop of power supply to the gaming machine by the non-maskable interrupt process.

  The INT signal from the main board 31 is connected to the CLK / TRG2 terminal of the payout control CPU 371. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 built in the payout control CPU 371 is down-counted. When the register value becomes 0, an interrupt occurs. Therefore, if the initial value of the timer counter register CLK / TRG2 is set to “1”, an interrupt is generated according to the input of the INT signal.

  Although the system reset circuit 975 is also mounted on the payout control board 37, in this embodiment, the reset IC 976 in the system reset circuit 975 outputs an output to the external capacitor for a predetermined time determined by the capacity when the power is turned on. The output is set to a low level and the output is set to a high level when a predetermined time has elapsed. Further, the reset IC 976 monitors the power supply voltage of VSL, and when the voltage value becomes a predetermined value (for example, +9 V) or less, the reset IC 976 sets the output to a low level. Therefore, when the power supply to the gaming machine is stopped, the payout control CPU 371 is system reset by the signal from the reset IC 976 becoming low level.

  The predetermined value for the reset IC 976 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the payout control CPU 371 to operate for a while. In addition, since the reset IC 976 is configured to monitor a voltage higher than the voltage required by the payout control CPU 371 (in this example, +5 V), the monitoring range for the voltage required by the payout control CPU 371 is used. Can be spread. Therefore, more precise monitoring can be performed. The system reset circuit 975 corresponds to second power supply monitoring means.

  While power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, and is used for a gaming machine such as a power failure. The contents are preserved even if the power supply is stopped. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to restore the payout control state at the time of the power failure when recovering from the power failure.

  In the configuration shown in FIG. 40, the system reset circuit 975 outputs a low level during a period determined by the capacitance of the capacitor when power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, as in the case of the main board 31 shown in FIG. 9, a circuit configuration that generates a plurality of reset release timings may be used.

  FIG. 41 is an explanatory diagram showing assignment of output ports in this embodiment. As shown in FIG. 41, the output port C (address 00H) is an output port for a drive signal or the like output to the payout motor 289. The output port D (address 01H) is an output port for a display control signal output to the error display LED 374 which is a 7 segment LED. The output port E (address 02H) is an output port for outputting a drive signal output to the sorting solenoid 310 and an EXS signal and a PRDY signal for the card unit 50.

  FIG. 42 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 42, the input port A (address 06H) is an input port for taking in an 8-bit payout control signal of the payout control command sent from the main board 31. In addition, detection signals of the winning ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 are supplied with a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 detection signal from the card unit 50.

  FIG. 43 is a flowchart showing the main processing of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM). In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a payout control process is executed.

  Further, another channel (channel 2 in this embodiment) of the built-in CTC is used as an interrupt generation channel for receiving a payout control command from the game control means, and this channel is used in the counter mode. Used in. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to the counter mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set.

  The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on the count-up of the CTC channel 2 (CH2) is an interrupt that occurs when the value of the timer counter register CLK / TRG2 described above becomes “0”. Therefore, for example, in step S705, the initial value “1” is set in the timer counter register CLK / TRG2 as the specific register. Further, the count value of the timer counter register CLK / TRG2 as the specific register is decremented by 1 at the rise or fall of the signal input to the CLK / TRG2 terminal. Decrease selection can be made. In this embodiment, setting is made such that the count value of the timer counter register CLK / TRG2 is -1 at the rising edge of the signal input to the CLK / TRG2 terminal.

  An interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Used as an interrupt. Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, the CH3 register is set to a value corresponding to 2 ms as an initial value.

  Interrupts based on CTC CH2 count-up have a higher priority than interrupts based on CH3 count-up. Therefore, when the count-up occurs simultaneously, the interrupt based on the CH2 count-up, that is, the interrupt that triggers the execution of the command reception interrupt process is given priority.

  Next, the payout control CPU 371 checks the state of the output signal of the clear switch 921 input via the input port B (see FIG. 42) only once (step S707). In the confirmation, when ON is detected, the payout control CPU 371 executes normal initialization processing (steps S711 to S713). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Note that in the input port 372, the ON state of the clear switch signal is at a high level. Further, the payout control means does not have to make the determination in step S707.

  As with the CPU 56 of the main board 31, the payout control CPU 371 also determines that the switch detection signal is on, for example, when the on state is at least 2 ms (the first process of the process activated every 2 ms). If the detection signal is turned on immediately before the detection in (1), the switch is not considered to be turned on unless it is continued. However, when the clear switch 921 is detected to be turned on, on / off is determined by a single on determination. That is, during the initialization request detection determination period for the payout control CPU 371 to determine whether or not the clear switch 921 as the operation means is in a predetermined operation state, the prize ball count switch as the game medium detection means or the like The period is different from the game medium detection determination period for determining that the medium has been detected.

  If the clear switch 921 is not in the ON state, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S708). For example, as with the processing of the CPU 56 of the main board 31, whether or not backup data exists is confirmed by whether or not the backup flag that is set when power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

  After confirming that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area. If the power supply is restored after a power outage such as an unexpected power failure, the data in the backup RAM area should have been stored, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of stopping the power supply, and therefore the initialization process that is executed at the time of power-on is executed instead of the recovery from an insufficient power failure.

  If the check result is normal (step S709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power supply is stopped (step S710). Then, it returns to the address indicated by the PC (program counter) stored in the backup RAM area.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated every 2 ms (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713).

  In this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, a timer interrupt flag indicating that a timer interrupt has occurred is set as shown in FIG. 44 (step S772). If it is detected in the main process that the timer interrupt flag is set (step S714), the timer interrupt flag is reset (step S751), and the payout control process (steps S751 to S760) is executed. The

  In the timer interrupt, as shown in FIG. 44, the interrupt permission state is first set (step S771). Therefore, the interrupt is permitted during the timer interrupt process, and the payout control command receiving process based on the input of the INT signal can be preferentially executed.

  In the payout control process, the payout control CPU 371 first determines whether or not a switch such as the prize ball count switch 301A or the ball lending count switch 301B input to the input port 372b is turned on (switch process: step S752). .

  Next, the payout control CPU 371 sets the payout stop state when the payout stop state designation command is received from the main board 31, and cancels the payout stop state when the payout possible state designation command is received (payout stop state). State setting process: Step S753). Also, the received payout control command is analyzed, and processing according to the analysis result is executed (command analysis execution processing: step S754). Further, a prepaid card unit control process is performed (step S755).

  Next, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756). At this time, the payout control CPU 371 sets the ball sorting member 311 to the ball lending side by the sorting solenoid 310.

  Further, the payout control CPU 371 performs prize ball control processing for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball sorting member 311 to the prize ball side by the sorting solenoid 310. Then, a drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of rotations is performed. (Step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control them. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing for outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

  The output port C shown in FIG. 41 is accessed in the payout motor control process (step S758) in the payout control process. The output port D is accessed by error processing (step S759) in the payout control processing. The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

  FIG. 45 is a flowchart illustrating an example of the payout state recovery process in step S710. In the payout state recovery process, the payout control CPU 371 first performs a stack pointer return process (step S731). The value of the stack pointer is saved in a predetermined RAM area (power backed up) in a power supply stop process described later. Therefore, in step S731, the RAM area value is set in the stack pointer to return. Note that the register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

  Next, the payout control CPU 371 clears the backup flag (step S732), that is, resets a flag indicating that a predetermined storage protection process has been executed when the previous power supply was stopped. Also, the saved values of various registers are read from the stack area and set in the various registers (step S733). That is, register restoration processing is performed. If the parity flag is not turned on, an interrupt permission state is set (steps S734 and S735). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S736).

  Then, the RET instruction is executed, but the return destination here is not the part that called out the payout state recovery process. This is because, in step S731, the stack pointer is restored, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, in response to the RET instruction subsequent to step S736, the process returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

  46 and 47 are flowcharts showing a processing example of a non-maskable interrupt process (NMI process: power supply stop process) executed in response to a power-off signal from the power supply board 910. FIG.

  In the power supply stop process, the payout control CPU 371 saves the AF register in a predetermined backup RAM area (step S801). Further, the interrupt flag is copied to the parity flag (step S802). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether the interrupt is permitted or interrupt disabled, and is in a control register built in the payout control CPU 371. The on state of the interrupt flag indicates that the interrupt is prohibited. As described above, the parity flag is referred to in the gaming state restoration process. In the payout state recovery process, if the parity flag is in the on state, the interrupt permission state is not set.

  Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S804 to S808).

  Next, the backup specified value ("55H" in this example) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, processing similar to that of the CPU 56 of the main board 31 is performed to create parity data and store it in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the built-in RAM cannot be accessed.

  Further, the payout control CPU 371 sets clear data (00) in an appropriate register (step S821), and sets the number of processes (in this example, “3”) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S824), the value of the IO pointer is incremented by 1 (step S825), and the value of the processing number is subtracted by 1 (step S827). The processes in steps S824 to S826 are repeated until the value of the number of processes becomes zero. As a result, clear data is set to all the output ports C to E (see FIG. 41). As shown in FIG. 41, in this example, “1” is on and clear data “00” is set to each output port, so all output ports are off.

  Therefore, after the processing for saving the control state (in this example, checksum generation and RAM access prevention) is executed, each output port is immediately turned off. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the payout control state.

  Since each output port is turned off immediately after the process for saving the control state is performed, it is reliably prevented that a situation that does not match the saved gaming state occurs. In addition, since the output port can be cleared during the power supply stop process before the electric component becomes incapable of being driven, it is controlled by the dispensing control means before the electric component becomes incapable of being driven. Each electric component can be put into an appropriate operation stop state. For example, the operation of the electrical component can be disabled after the operation of the electrical component is stopped, such as the operation of the payout motor 289 in the drive state is stopped. Therefore, it is possible to wait for restoration of power supply in an appropriate stop state.

  When the clear process for the output port is completed, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  FIG. 48 is an explanatory diagram showing an example of use of the RAM built in the payout control CPU 371. In this example, a total number storage (for example, 2 bytes) and a lending ball number storage are formed in the backup RAM area. The total number storage stores the total number of prize balls paid out instructed from the main board 31 side. The rented ball number storage stores the number of balls that have not been paid out. Note that all RAM areas in which data used in the payout control process are stored may be backed up.

  Then, for example, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in the prize ball control process (step S757), the content is increased in the total number memory by the indicated number. . In addition, in the ball lending control process (step S756), every time a ball lending request signal is received from the card unit 50, the content is increased in the lending ball number storage by the number of one unit (for example, 25). Further, the payout control CPU 371 reduces the value of the total number memory by 1 when the prize ball count switch 301A detects one prize ball payout in the prize ball control process, and one ball rental count switch 301B in the ball rental control process. When the lending ball payout is detected, the value of the lending ball number storage is reduced by one.

  Therefore, the number of unpaid prize balls and the number of rented balls are stored in a backup RAM area capable of holding the contents for a predetermined period. Therefore, even if an unexpected power supply stop such as a power failure occurs, the award ball processing and the ball lending processing can be resumed based on the stored contents of the backup RAM area if the power supply is restored within a predetermined period. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is performed based on the number of unpaid prize balls and the number of rented balls at the time of the power supply stop, and given to the player The disadvantage can be reduced.

  FIG. 49 is an explanatory diagram showing a configuration example of a reception buffer for storing a payout control command received from the main board 31. In this example, a ring buffer type reception buffer capable of storing six 2-byte payout control commands is used. Therefore, the reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

  FIG. 50 is a flowchart showing a payout control command reception process by an interrupt process. The payout control INT signal from the main board 31 is input to the CLK / TRG2 terminal of the payout control CPU 371. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 50 is started. The payout control CPU 371 is a CPU having a structure such that when an interrupt occurs, a maskable interrupt does not occur unless the interrupt is permitted by software.

  Although the command reception process of the payout control unit will be described here, the same command reception process is executed in the display control unit, the lamp control unit, and the sound control unit. In this embodiment, the initial setting is made such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the CLK / TRG2 terminal rises. That is, an interrupt is generated at the rise of the INT signal. However, the initial setting may be performed such that the value of the timer counter register CLK / TRG2 is set to -1 when the input of the CLK / TRG2 terminal falls. In other words, initial settings may be made such that an interrupt occurs at the falling edge of the INT signal.

  In other words, if an interrupt is generated at the level change timing (edge) of a pulsed (rectangular wave) INT signal as an acquisition signal, the edge may be a rising edge or a falling edge. Good. In any case, the interrupt is generated at the level change timing (edge) of the pulsed (rectangular wave) INT signal as the capture signal. By doing so, it becomes possible to receive a command promptly at the stage where command fetch is instructed. Since the output of the INT signal is on standby until the period A (FIG. 35) elapses, the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output. Therefore, the payout control means receives the payout control command satisfactorily.

  In the payout control command reception process, the payout control CPU 371 first saves each register in the stack (step S850). Next, data is read from the input port 372a (see FIG. 10) assigned to input of the payout control command data (step S851). Then, it is confirmed whether or not it is the first byte of the 2-byte payout control command (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is “1”. The first bit is “1”, which should be the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 34). Therefore, if the first bit is “1”, the payout control CPU 371 determines that the valid first byte has been received, and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step S31). S853).

  If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not it has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

  If the first byte has already been received, it is confirmed whether or not the first bit of the received 1 byte is “0”. If the first bit is “0”, it is determined that the valid second byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The leading bit “0” should be the EXT byte (second byte) of the payout control command having a two-byte configuration (see FIG. 34). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends unless the first bit of the data received as the second byte is “0”. If “N” is determined in step S854, the process in step S856 is not performed, so the next received command is stored in the buffer area where the command received this time should have been stored. The

  When the second byte of command data is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether or not the command reception counter is 12 or more (step S857). If it is 12 or more, the command reception number counter is cleared (step S858). Thereafter, the saved register is restored (step S859), and finally, interrupt permission is set (step S859).

  Interrupts are disabled during command reception interrupt processing. As described above, since the interrupt is enabled during the 2 ms timer interrupt processing, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt processing is executed with priority. The Even if a 2 ms timer interrupt occurs during command reception interrupt processing, the interrupt processing is awaited. Thus, in this embodiment, the processing priority of command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during command reception processing, the maximum time required for command reception processing is determined. If the configuration is such that another interrupt process can be executed during the command reception process, it is difficult to estimate the longest time required for the command reception process. Since the longest time required for the command reception process is determined, it is possible to accurately determine how long the period C (see FIG. 35) in the command transmission process of the game control means should be.

  The payout control command has a 2-byte configuration, and the first byte (MODE) and the second byte (EXT) can be immediately distinguished on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

  In this embodiment, in the command reception interrupt process, the received command is controlled to be stored in the reception buffer. The payout stop state setting process (see FIG. 52) and the command analysis execution process (see FIG. 53) described later are performed. May be executed in the command reception interrupt process. As such, in the case of executing the command reception interrupt process up to the command determination process for determining the command in the reception buffer, the determination of the command is also executed quickly.

  FIG. 51 is a flowchart illustrating an example of the switch processing in step S751. In the switch process, the payout control CPU 371 checks whether or not the prize ball count switch 301A indicates the on state (step S751a). If the on state is indicated, the payout control CPU 371 increments the prize ball count switch on counter by 1 (step S751b). The prize ball count switch on counter is a counter for counting the number of times the on state of the prize ball count switch 301A is detected.

  Then, the value of the prize ball count switch-on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. If it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number memory) by −1 (step S751d).

  When it is confirmed in step S751a that the prize ball count switch 301A is not in the on state, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, it is checked whether or not the ball lending count switch 301B indicates the on state (step S751f). If the on state is indicated, the payout control CPU 371 increments the ball lending count switch on counter by 1 (step S751g). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B is turned on.

  Then, the value of the ball lending count switch-on counter is checked (step S751h). If the value is 2, it is determined that one lending ball has been paid out. If it is determined that one lending ball has been paid out, the payout control CPU 371 decrements the lending ball unpaid-out number counter (the number of lending balls stored in the lending ball number storage) (step S751i). ).

  When it is confirmed in step S751f that the ball lending count switch 301B is not in the on state, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

  FIG. 52 is a flowchart showing an example of the payout stop state setting process in step S753. In the payout stop state setting process, the payout control CPU 371 checks whether or not there is a reception command in the reception buffer (step S753a). If there is a reception command in the reception buffer, it is checked whether or not the received payout control command is a payout stop state designation command (step S753b). If it is a payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S753c).

  If it is confirmed in step S753b that the received command is not a payout stop state designation command, it is confirmed whether or not the received payout control command is a payout enable state designation command (step S753d). If it is a payout enable state designation command, the payout stop state is canceled (step S753e).

  FIG. 53 is a flowchart illustrating an example of the command analysis execution process in step S754. In the command analysis execution process, the payout control CPU 371 checks whether or not there is a reception command in the reception buffer (step S754a). If there is a received command, it is checked whether or not the received payout control command is a payout control command for designating the number of winning balls (step S754b). The payout control CPU 371 determines in step S754b for the received command stored at the address in the receiving buffer pointed to by the read pointer as the command instruction means. Further, after the determination, the value of the read pointer is incremented by one. When the address pointed to by the read pointer exceeds the address of the reception command buffer 12 (see FIG. 49), the value of the read pointer is updated to point to the reception command buffer 1.

  If the received payout control command is a payout control command for designating the number of winning balls, the number instructed by the payout control command is added to the total number memory (step S754c). That is, the payout control CPU 371 stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number memory).

  The payout control CPU 371 performs subtraction of the command reception number counter and reception command shift processing in the reception buffer, if necessary. Further, the payout stop state setting process and the command analysis execution process may be repeated until the value of the read pointer matches the latest command storage position in the reception buffer. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is “3”, there are three unprocessed received commands, but the process is repeated until they match. , There are no outstanding received commands. That is, all received commands stored in the reception buffer are read and processed in a single process.

  FIG. 54 is a flowchart showing an example of the prepaid card unit control process in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not a VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Also, the payout control CPU 371 checks whether or not the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CPU 371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S755d).

  If the VL signal is detected to be off 125 times (2 ms × 125 = 250 ms) continuously by the above processing, the ball firing prohibited state is set.

  If the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the discharge control CPU 371 stops outputting the firing control signal (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to enable the drive motor 94 (step S755g). .

  55 and 56 are flowcharts showing an example of the ball lending control process in step S756. In this embodiment, the maximum value of the continuous payout number is set as one unit (for example, 25) of the lending ball, but the maximum value of the continuous payout number may be another number.

  In the ball lending control process, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S511). If the lending ball is being paid out, the process proceeds to the ball lending process shown in FIG. Whether or not the lending ball is being paid out is determined by the state of a ball lending process flag which will be described later. If the rental ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout, the payout control CPU 371 checks whether or not a ball lending request has been received from the card unit 50 (step S513). If there is a request, the ball lending process flag is turned on (step S514), and 25 (number of ball lending units: here 100 yen) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the sorting solenoid 310 is driven to set the ball sorting member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S518), and the process proceeds to the ball lending process shown in FIG.

  Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized acceptance. The ball lending process flag is set in the backup RAM area.

  FIG. 56 is a flowchart showing a ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch processing in step S751, it is confirmed whether or not a game ball has been paid out based on the detection signal from the ball lending count switch 301B. Is not done.

  In the ball lending control process, the payout control CPU 371 checks whether or not it is during the lending ball passage waiting time (step S519). If it is not during the lending ball passage waiting time, the lending ball is paid out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be finished (whether the payout operation of one unit has been finished) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522) and sets the lending ball passage waiting time (step S523).

  If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 checks whether or not the lending ball passage waiting time has ended (step S524). The rental ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all lending balls of one unit have been paid out, so that the card unit 50 can accept the next lending request. The EXS signal is turned off (step S525). Further, the distribution solenoid is turned off (step S526), and the ball lending process flag is turned off (step S527). If the last payout ball does not pass the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. In this embodiment, the winning ball and the lending are performed by the same payout device.

  After turning off the EXS signal indicating acceptance of a ball lending request, if the BRQ signal, which is a ball lending request signal, is turned on again within a predetermined period, the ball lending process is continued without turning off the sorting solenoid and the dispensing motor. You may make it do. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be executed continuously.

  The contents of the rental ball number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Accordingly, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

  FIG. 57 and FIG. 58 are flowcharts showing an example of the prize ball control process in step S757. In this example, the maximum value of the continuous payout number is the same as the unit of the lending ball (for example, 25), but the maximum value of the continuous payout number may be another number.

  In the winning ball control process, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S531). Whether or not the ball lending is being paid out is determined by the state of the ball lending process flag. If the ball is not paid out, it is confirmed whether or not the prize ball is being paid out (step S532). If the prize ball is being paid out, the process proceeds to the process in the prize ball shown in FIG. Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout is found, the payout control CPU 371 checks whether or not there is a ball lending preparation request from the card unit 50 (step S533). Whether or not there is a ball lending preparation request is determined by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

  If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of winning balls (the number of unpaid winning balls) stored in the total number memory is 0 (step S534). . If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on a prize ball processing flag (step S535), and whether or not the value of the total number memory is 25 or more. Confirmation is made (step S536). The prize ball processing flag is set in the backup RAM area.

  When the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate the payout motor 289 until paying out 25 game balls. In order to output 25, the payout operation of 25 is set (step S537). If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate until all the game balls stored in the total number memory are paid out. In order to output the total number delivery operation (step S538). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is in the off state, the ball distribution member below the ball dispensing device 97 is set to the prize ball side. Then, the process proceeds to a process during payout of prize balls in the prize ball control process shown in FIG.

  FIG. 58 is a flowchart showing an example of a process during a prize ball in the payout control process by the payout control CPU 371. In the winning ball control process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch process of step S751, it is confirmed whether or not a game ball has been paid out based on the detection signal of the prize ball count switch 301A. Therefore, in the prize ball control process, the total number memory is subtracted. Is not done.

  In the processing during the winning ball, the payout control CPU 371 checks whether or not it is during the waiting time for winning ball passing (step S540). If it is not during the waiting time for passing the prize ball, the prize ball is paid out (step S541), and whether or not the driving of the payout motor 289 should be terminated (whether a predetermined number of payout operations of 25 or less than 25 has been completed). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the award ball passage waiting time (step S544). The award ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

  If it is during the winning ball passage waiting time in step S540, the payout control CPU 371 checks whether or not the winning ball passage waiting time has ended (step S545). When the prize ball passing waiting time ends, all the prize balls set in step S537 or step S538 have been paid out. Therefore, the payout control CPU 371 turns off the award ball processing flag if the award ball passage waiting time has ended (step S546). If the last payout ball does not pass the prize ball count switch 301A before the prize ball passage waiting time elapses, a prize ball path error is determined.

  In this embodiment, the ball lending is prioritized over the winning ball processing according to the determinations in steps S511 and S531, but the winning ball processing may be prioritized over the ball lending.

  The contents of the total number storage and the rented ball number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the payout process based on the contents of the total number storage.

  The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but may manage each prize ball number (for example, 15, 10, or 6). Good. For example, a number counter corresponding to each award ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When a prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, a subtraction process is performed in the payout control process). Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored during a predetermined period, the payout control CPU 371 can continue the prize ball payout process based on the contents of each number counter.

  In this embodiment, the payout control means detects that the INT signal related to the payout control signal has risen, and starts a 1-byte data take-in process by an interrupt process, for example. Since a receiving ring buffer (in this example, a reception buffer) capable of storing a plurality of payout control commands is provided, the next payout control command is received after the payout control command is received and before the control based on the command is started. Even if the command is received, the command is not received by the payout control means.

  Further, as shown in the flowcharts of FIGS. 28 to 30, the game control means is configured to be able to execute the command set process of step S251 even in the payout stop state (step S201). . Therefore, even when the payout is stopped, when a winning is detected, a payout control command indicating the number of payouts is sent to the payout control means.

  In the payout control means, the interruption process is started even when the payout is stopped, so that the payout control means can receive the payout control command even when the payout is stopped. While the payout is stopped, payout processing according to the received payout control command is stopped, but since a receiving ring buffer capable of storing a plurality of payout control commands is provided, it is sent out from the game control means. The payout control command does not disappear in the payout control means.

  In the payout control means, a command reception number counter is used as an address instruction means for indicating in which area in the reception ring buffer the transmission command is stored. Therefore, it is easy to determine which area should be used.

  In the above embodiment, the RAM is used as the fluctuation data storage means. However, as the fluctuation data storage means, a storage means other than the RAM may be used as long as it is an electrically rewritable storage means. Good.

  Similarly to the RAM in the game control means and the payout control means, the RAM in the sound control means, the lamp control means, and the display control means may have a portion that is backed up.

  Furthermore, in the above embodiment, the power supply monitoring means is provided on the power supply board 910, and the circuit for generating a signal for system reset is provided on the electrical component control board. It may be done.

  As described above, the game control means and the payout control means as the electrical component control means are the fluctuation data storage means (for example, RAM) that is backed up by the backup power source as the storage holding power supply means in the power supply stop process. Parity check is performed on the area () to save the parity data as check data, and when the power supply is resumed, if the parity data is correctly stored, the state recovery process is performed. When the power supply is resumed, the parity check is performed again, the check result is compared with the stored parity data, and the state restoration process is performed when the two match. If the stored contents of the fluctuation data storage means backed up by the backup power supply change while the power supply is stopped, the check result of the parity check again does not match the stored parity data. Therefore, it is possible to prevent the state restoration process from being executed based on erroneous stored contents.

  In addition, the electrical component control means sets a parity flag indicating that the power supply stop process has been performed in the power supply stop process, and when the power supply is resumed, the state is changed according to the state of the parity flag. Since it is determined whether to perform the recovery process or the initialization process, it is possible to reliably determine whether to perform the state recovery process by a simple method. As a result, it is possible to reliably utilize the control state saved by the power supply stop process.

  In addition, the game control means, in the game state recovery process, a payout enable state designation command for designating prohibition of the payout of the game ball from the ball payout device 97, or a payout stop state designation command for designating permitting the payout Is output to the payout control means, so that after the start of power supply, state information (payout information, ball lending information, prize ball information, launch information, etc.) between the game control means and the payout control means ) Can be avoided. As a result, malfunction due to the payout control means can be prevented.

  In the above embodiment, at the start of power supply, the game control means transmits a payout stop state designation command or a payable state designation command to the payout control means, but other commands may be transmitted. For example, notification of whether or not a hitting ball can be fired by the hitting operation handle 5, information on error and error cancellation, and the like are notified. With such a configuration, it is possible to avoid a discrepancy in recognition of the current situation between the game control means and the payout control means after the start of power supply. As a result, appropriate game control can be performed.

  In the above embodiment, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are possible according to the payable state designation command. Although the state has been returned to the state, the payout stop instruction for the winning ball and the payout stop instruction for the ball lending may be separate commands, and the payout stop canceling instruction for the prize ball and the payout stop canceling instruction regarding the ball lending may be separate commands. In such a configuration, after the start of power supply, there is a discrepancy in the recognition of the current situation regarding the award ball stop / stop release and the ball lending stop / stop release between the game control means and the payout control means. Can be avoided.

  In the above embodiment, the payout means is configured to execute both ball lending and prize ball payout. However, the present invention can be applied even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent. Can be applied. In that case, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent, if the payout control means is configured to control both mechanisms, 1 as in the above embodiment. One command can be configured to instruct stop / release of both ball lending and prize ball payout.

  Furthermore, when the power supply is started, the electrical component control means executes the state restoration process when the operation means is operated even if the control state stored in the power supply stop process remains. Initialize process without executing. Therefore, a game store clerk or the like can easily clear the stored state.

  In addition, when the state restoration process is completed, the microcomputer in the electric component control unit returns to the address stored in the stack area when the process for stopping power supply is executed, and resumes the execution of the program. Therefore, it is possible to easily return to the control state that was being executed when the power supply was stopped, and to reliably return to the control state that was being executed when the power supply was stopped.

  Further, in the power supply stop process, each output port is immediately set to the off state after the process for saving the gaming state is executed. As a result, it is reliably prevented that a situation that does not match the saved gaming state occurs.

  Note that the pachinko gaming machine 1 of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display device 9 based on the start winning is a combination of the predetermined symbols. The first type pachinko gaming machine that can be given to a player, but if there is a winning in a predetermined area of an electric accessory that is released based on a start winning, a second gaming value can be given to the player When a winning is given to a predetermined electric game that is released when a stop symbol of a symbol variably displayed based on a seed pachinko gaming machine or a start winning combination becomes a predetermined symbol combination, a predetermined right is generated or continued. The present invention can be applied even to a seed pachinko gaming machine.

  Furthermore, the present invention can be applied to a slot machine or the like provided with an electrical component for paying out the game medium, not limited to a pachinko game machine in which the game medium is a game ball.

  The above embodiment also discloses a gaming machine configured as follows.

  The electrical component control means may be configured to perform an initialization process for initializing the control state when it is determined that the stored content stored in the variation data storage means is not valid. The electrical component control means is configured to perform an initialization process to initialize the control state when it is determined that the stored content stored in the variation data storage means is not valid, so that the stored content changes. If this happens, the control state can be returned to the initial state by executing the initialization process.

  The check data is, for example, data calculated by performing a predetermined logical operation based on at least a part of the contents of the variation data storage unit. Since the check data is data calculated by performing a predetermined logical operation based on at least a part of the contents of the variation data storage means, the check data can be generated easily and in a short time.

  The variable data storage means may include a work area in which a storage area is determined for each data, and the check data may be generated based on the contents of the work area. The variable data storage means includes a work area in which a storage area is determined for each data, and check data is generated based on the contents of the work area. The check data can be generated in a short time.

  The check data generated by the power supply stop process is preferably stored in the work area. Since the check data generated in the power supply stop process is stored in the work area, the stored check data can be easily read out when the power supply is started.

  The variation data storage means may include a stack area for saving data in response to establishment of a predetermined condition, and the program address data may be stored in the stack area. Since the program address data is configured to be stored in the stack area, it becomes easy to restore the program address data when power supply is started.

  The stored contents of the variable data storage means include stack address data indicating the address of the stack area. When performing state recovery processing, the program address data is recovered by recovering the stack address data. May be. The stored contents of the variable data storage means include stack address data indicating the address of the stack area. When performing state recovery processing, the program address data is recovered by recovering the stack address data. Therefore, the process of restoring the program address data related to the address of the control program is easily realized.

  It is preferable that the contents of the register are saved in the stack area in the data saving process. Since the contents of the register are saved in the stack area in the data saving process, the contents of the register are saved in the same area as the program address data, thereby facilitating data management.

  The state restoration process may be configured to include a process of restoring the contents of the register. Since the state restoration process is configured to include a process for restoring the contents of the register, the contents of the register are also restored by the state restoration process, so that an accurate state restoration is performed.

  The stored content of the fluctuation data storage means includes interrupt status information indicating either one of an interrupt disabled state for prohibiting execution of a predetermined interrupt process or an interrupt enabled state for permitting execution, The state recovery process may be configured to include a recovery process of an interrupt prohibited state or an interrupt permitted state based on the interrupt state information. The stored content of the fluctuation data storage means includes interrupt status information indicating either one of an interrupt disabled state for prohibiting execution of a predetermined interrupt process or an interrupt enabled state for permitting execution, Since the state recovery process is configured to include the recovery process of the interrupt disabled state or interrupt enabled state based on the interrupt state information, accurate state recovery including the state of interrupt disabled or interrupt enabled is possible. Done.

  Power supply monitoring means for monitoring the state of a predetermined power supply and outputting a detection signal when the output of the power supply decreases and the detection condition is satisfied, and the electric component control means is configured to output power according to the detection signal from the power supply monitoring means. You may be comprised so that the process at the time of a supply stop may be performed. Power supply monitoring means for monitoring the state of a predetermined power supply and outputting a detection signal when the output of the power supply decreases and the detection condition is satisfied, and the electric component control means is configured to output power according to the detection signal from the power supply monitoring means. Since it is configured to execute the process at the time of supply stop, even if an unexpected power supply stop due to a power failure or the like occurs, it can be detected.

  The electrical component control means executes an electrical component control process for controlling the electrical component provided in the gaming machine based on the occurrence of a periodic timer interruption, and is required for the electrical component control process. A process for updating a counter used for game control may be executed in the surplus time, and interrupt processing may be set to be prohibited during the process for updating the counter in the surplus time. The electrical component control means executes an electrical component control process for controlling the electrical component provided in the gaming machine based on the occurrence of a periodic timer interruption, and is required for the electrical component control process. Since it is configured to execute the process of updating the counter used for game control in the surplus time, and set to disable interrupt during the process of updating the counter in the surplus time, the counter in the surplus time It is possible to prevent the occurrence of an interrupt during the update and a problem in updating the counter.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is a disassembled perspective view which shows the structural example of a ball dispensing apparatus. It is a front view which shows the part of the switch board installed in the game board. It is a block diagram which shows an example of a structure of a clear switch. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a symbol control board. It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a power supply board. It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows an example of the relationship between a backup flag and whether to perform a game state restoration process. It is a flowchart which shows a game state restoration process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a non-maskable interruption process (process at the time of an electric power supply stop). It is a flowchart which shows a non-maskable interruption process (process at the time of an electric power supply stop). It is explanatory drawing which shows the address map of RAM. It is explanatory drawing for demonstrating an example of the checksum production method. It is a timing diagram which shows the mode of the power supply fall and NMI signal at the time of the electric power supply stop to a game machine. It is explanatory drawing which shows the example of formation of the switch timer in RAM. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows a switch-on check process. It is explanatory drawing which shows the structural example of an input determination value table. It is explanatory drawing which shows one structural examples, such as a command transmission table. It is explanatory drawing which shows an example of the command form of a control command. It is a timing diagram showing the relationship between an 8-bit control signal and an INT signal constituting a control command. It is explanatory drawing which shows an example of the content of the payout control command. It is a flowchart which shows the process example of a command set process. It is a flowchart which shows a command transmission process routine. It is a flowchart which shows an example of a prize ball number subtraction process. It is a block diagram which shows the example of 1 structure around the payout control CPU for power supply monitoring and power supply backup. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a payout control board performs. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a payout state recovery process. It is a flowchart which shows a non-maskable interruption process (process at the time of an electric power supply stop). It is a flowchart which shows a non-maskable interruption process (process at the time of an electric power supply stop). It is explanatory drawing which shows one structural example of RAM in the payout control means. It is explanatory drawing which shows the example of 1 structure of a reception command buffer. It is a flowchart which shows the example of the command reception processing of CPU for payout control. It is a flowchart which shows the example of a switch process. It is a flowchart which shows the example of a payout stop state setting process. It is a flowchart which shows the example of a command analysis execution process. It is a flowchart which shows the example of a prepaid card unit control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a prize ball control process. It is a flowchart which shows the example of a prize ball control process.

Explanation of symbols

1 Pachinko machine 31 Main board 37 Payout control board 53 Basic circuit 55 RAM (variable data storage means)
56 CPU
371 CPU for payout control
910 Power supply board 916 Capacitor (memory supply power supply means)

Claims (3)

A gaming machine in which a player can play a predetermined game,
An operation means for outputting an operation signal according to the operation;
A game control microcomputer for controlling the progress of the game,
The game control microcomputer is:
Even if the power supply to the gaming machine is stopped by the backup power source, it has a RAM that holds data,
When power supply to the gaming machine stops, a power supply stop process for saving the control state is executed, and in the power supply stop process, designated data for indicating the presence of backup data is stored in the RAM. Set,
When the power supply is started, it is checked whether or not the operation signal from said operating means is inputted, when the operation signal from said operating means is not input has been confirmed, the designated data Is determined in accordance with the stored contents stored in the RAM on the condition that the specified data is determined to be stored in the RAM. perform state recovery process to restore, when it is confirmed that the operation signal from said operating means is inputted, the memory contents of the RAM area initialized without performing the determination,
After performing the initial setting process, the main routine is interrupted and started in response to a main routine that repeatedly executes a predetermined process and a maskable timer interrupt that occurs every predetermined time during the execution of the main routine. Interrupt routine ,
In the interrupt routine, a specific gaming state determination numerical value update process for updating a specific gaming state determination numerical value for determining whether or not to enter a specific gaming state within a predetermined range, and the specific gaming state at a predetermined time an initial value changing process for changing the initial value of the update of the determination number in numeric for initial value stored in a predetermined address of the RAM, for an initial value to update the numeric for the initial value stored in the predetermined address While executing game control processing including numerical value update processing,
Also in the main routine, as the predetermined process, an initial value numerical value update process for updating the initial value numerical value stored in the predetermined address is executed,
State in which the set, prevents interruption by the timer interrupt before starting the numerical value update process for the initial value in the main routine, you allow interruption by the timer interrupt after completion of the initial value for the numerical updating A gaming machine characterized by being set to . The game control microcomputer detects whether or not an operation signal from the operation means is input, and detects a request shorter than a game medium detection determination period for determining a detection signal from the game medium detection means for detecting a game medium. Check in the judgment period
The gaming machine according to claim 1. A payout control microcomputer that performs payout processing of prize game media based on payout control commands output from the game control microcomputer in accordance with a prize;
The dispensing control microcomputer is:
It has a payout control RAM that retains data even if power supply to the gaming machine is stopped by a backup power source,
When it is confirmed that an operation signal is input from the operation means when power supply is started, the storage contents of the payout control RAM are initialized,
Whether or not the operation signal from the operation means is input is confirmed in a request detection determination period shorter than the game medium detection determination period for determining the detection signal from the game medium detection means for detecting the game medium.
The gaming machine according to claim 1 or 2.

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