JP2007115981A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2007115981A
JP2007115981A JP2005307305A JP2005307305A JP2007115981A JP 2007115981 A JP2007115981 A JP 2007115981A JP 2005307305 A JP2005307305 A JP 2005307305A JP 2005307305 A JP2005307305 A JP 2005307305A JP 2007115981 A JP2007115981 A JP 2007115981A
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Japan
Prior art keywords
bonding
inner lead
substrate inner
substrate
wire
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Application number
JP2005307305A
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English (en)
Inventor
Mitsuhiro Nakao
光博 中尾
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Toshiba Corp
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Toshiba Corp
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Priority to JP2005307305A priority Critical patent/JP2007115981A/ja
Publication of JP2007115981A publication Critical patent/JP2007115981A/ja
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Abstract

【課題】パッケージ外形サイズの大型化を招くことなく、従来に比べて製造コストの低減を図ることのできる半導体装置を提供する。
【解決手段】基板１には、半導体チップ３の電極パッド４と同一ピッチで基板インナーリード２が配置されている。電極パッド４と基板インナーリード２とは、ワイヤ５で接続されている。基板インナーリード２と、電極パッド４には、夫々ボンディングボール７ｂが形成され、基板インナーリード２上のボンディングボール７ｂは、その径が基板インナーリード２の線幅より広い。
【選択図】図２

Description

本発明は、基板上に半導体チップが搭載され、半導体チップの電極パッドと基板の基板インナーリードとが電気的に接続された半導体装置に関する。
従来から、基板上に半導体チップが搭載され、半導体チップの電極パッドと基板インナーリードとが電気的に接続された半導体装置が知られている。また、基板上に搭載された半導体チップの上にさらに半導体チップを積層配置したチップ積層型半導体装置も知られている。
チップ積層型半導体装置は、チップサイズの比較的大きなメモリチップを複数段積み重ねたものが多く、基板との接続方法は全てワイヤボンディングを用いていた。しかし、近年ではロジックチップとメモリチップを混載させて積層する半導体装置等が開発されている。ロジックチップの場合、電極パッド数が３００〜５００パッドと非常に多く、ワイヤボンディングで接続すると、基板側にそのパッド数と同じ数の基板インナーリードが必要となる。このため、例えば図９に示すように、半導体チップ３の周囲に基板インナーリード２を放射状に設け、ワイヤ５でボンディングを行う技術が知られている（例えば、特許文献１参照。）。しかしながら、このような技術では、ワイヤボンディングでワイヤ５を基板側に結線するために使用する基板インナーリード２の面積が多く必要となり、半導体装置のパッケージ外形サイズが大型化してしまうという問題が発生する。また、半導体チップの電極パッドは、狭ピッチ化が進められており、１００μｍピッチ以下、例えば６０μｍピッチ等とされる傾向にある。このような狭いピッチに対応するためには、基板インナーリードの幅も狭くし、かつ狭いピッチで配置しなければならないため、通常のワイヤボンディングでは対応が困難になっている。
そこで、従来はロジックチップをフリップチップボンディング法を用いて基板インナーリードに接続する方法がとられている。しかし、フリップチップボンディングでは、チップ側電極にＡｕなどのバンプを形成し、更に基板インナーリードにもＳｎなどの電極バンプを形成するため、材料コストが非常に高くなるという問題がある。
特開平６−１６８９７８号公報
上述したとおり、従来技術では、コストの安いワイヤボンディング法を用いると、パッケージ外形サイズが大きくなってしまうという問題が発生し、フリップチップボンディング法を用いると製造コストが高くなってしまうという問題があった。
本発明は、上記課題を解決するためになされたもので、パッケージ外形サイズの大型化を招くことなく、従来に比べて製造コストの低減を図ることのできる半導体装置を提供することを目的とする。
本発明の一態様によれば、所定ピッチで形成された複数の電極パッドを有する半導体チップと、前記半導体チップの前記電極パッドと同一ピッチで形成された基板インナーリードを有し、前記半導体チップが搭載される基板とを具備し、前記電極パッドと前記基板インナーリードとが、ワイヤの両側にボンディングボールを形成するワイヤボンディングによって接続され、前記基板インナーリードの幅より、当該インナーリード上に形成された前記ボンディングボールの径が大きい半導体装置が提供される。
また、本発明の一態様によれば、所定ピッチで形成された複数の電極パッドを有する半導体チップと、前記半導体チップの前記電極パッドと同一ピッチで形成された基板インナーリードを有し、前記半導体チップが搭載される基板とを具備し、前記電極パッド又は前記基板インナーリード上に第１のボンディングボールを形成した後、前記基板インナーリード又は前記電極パッド上に第２のボンディングボールを形成し、当該第２のボンディングボールからワイヤを伸ばして前記第１のボンディングボールにボンディングするワイヤボンディングによって、前記電極パッドと前記基板インナーリードとが接続され、前記基板インナーリードの幅より、当該基板インナーリード上に形成された前記第１又は第２のボンディングボールの径が大きい半導体装置が提供される。
本発明によれば、パッケージ外形サイズの大型化を招くことなく、従来に比べて製造コストの低減を図ることのできる半導体装置を提供することができる。
以下、本発明の実施の形態について図面を参照して説明する。図１は、本発明の一実施形態に係る半導体装置の要部概略構成を拡大して示す図であり、図２，３は、図１の要部概略構成をさらに拡大して示す図である。
図１，２に示すように、基板１に搭載された半導体チップ３には、所定ピッチ（例えば６０μｍピッチ）で多数の電極パッド４が形成されている。一方、基板１には、半導体チップ３の周囲から外側へ延在するように、電極パッド４と同一ピッチで配置された基板インナーリード２が配置されている。
電極パッド４と、基板インナーリード２とは、ワイヤボンディングによって、ワイヤ（金属細線）５で接続されている。また、基板インナーリード２と、電極パッド４には、夫々後述するワイヤボンディング工程によって形成されたボンディングボール７ｂが形成されている。
上記ボンディングボール７ｂのうち、基板インナーリード２上に形成されたボンディングボール７ｂは、図２，３に示すように、その径（図３に示すＲ）が、基板インナーリード２の幅（図３に示すＷ）より大きくなるように（Ｒ＞Ｗとなるように）形成されている。これによって、線幅の狭い（例えば３０μｍ）基板インナーリード２であっても、ワイヤボンディングによって確実にワイヤ５を接続できるようになっている。
なお、電極パッド４に比べて、基板インナーリード２は、製造工程における精度が低いため、例えば、６０μｍピッチで配置するためには、３０μｍ程度の間隔を必要とし、このため線幅は３０μｍ程度となり、それ以上線幅を広げることは難しい。このように基板インナーリード２の線幅が狭い場合であっても、この線幅より径の大きいボンディングボール７ｂを設けることによって、確実にワイヤ５を接続できる。
次に、上記の電極パッド４と、基板インナーリード２とのワイヤボンディング工程について説明する。図４は、このようなワイヤボンディング工程の一例を示すものである。このワイヤボンディング工程では、まず図４（ａ）に示すように、キャピラリ６から突出させた金属細線（ワイヤ５）を放電によって球状化させたボール７ａを形成する。
次に、図４（ｂ）に示すように、形成したボール７ａを半導体チップ３の電極（電極パッド４）上に、超音波と荷重によって接合させて、ある一定の高さまでキャピラリ６を上昇させる。この後、図４（ｃ）に示すように、上昇させたキャピラリ６をある一定距離平行移動させて、再度先ほど接合させたボール上に接合させる。
しかる後、図４（ｄ）に示すように、再度キャピラリ６をある一定の高さに上昇させた後、ワイヤ５をクランプしてさらにキャピラリ６を上昇させる。クランプした状態でキャピラリ６を上昇させるので、ワイヤ５は破断しキャピラリ６先端からは、ある一定の長さのワイヤ５が残る。これらの工程によって、半導体チップ３の電極（電極パッド４）上にボンディングボール（第１のボンディングボール）７ｂが形成される。
次に、図４（ｅ）に示すように、キャピラリ６先端から残されたワイヤ５を、放電によってその先端を球状化させてボール７ａを形成する。この後、図４（ｆ）に示すように、キャピラリ６を、基板インナーリード２上に移動させる。
次に、図４（ｇ）に示すように、キャピラリ６を下降させ、基板インナーリード２上にボール７ａを接合させた後、キャピラリ６を上昇させる。これによって、基板インナーリード２上にボンディングボール（第２のボンディングボール）７ｂが形成される。
この後。図４（ｈ）に示すように、キャピラリ６をある最適な軌跡を描いて移動させて、先ほど形成した半導体チップ３上のボンディングボール７ｂ上にワイヤ５を接合させ、結線を行う。しかる後、図４（ｉ）に示すように、キャピラリ６をある一定の高さに上昇させた後、ワイヤ５をクランプしてさらにキャピラリ６を上昇させてワイヤ５を破断して、１つのワイヤ結線が終了する。
以上説明したワイヤボンディング工程により、例えば、６０μｍピッチ等の狭いピッチで基板インナーリード２及び電極パッド４が配置されている場合でも、これらをワイヤボンディングによって確実に接続することが可能となる。次に、図５を参照して他のワイヤボンディング工程の例について説明する。
このワイヤボンディング工程では、まず図５（ａ）に示すように、キャピラリ６から突出させたワイヤを放電によって球状化させたボール７ａを形成する。
次に、図５（ｂ）に示すように、形成したボール７ａを基板インナーリード２上に、超音波と荷重によって接合させて、ある一定の高さまでキャピラリ６を上昇させる。この後、図５（ｃ）に示すように、上昇させたキャピラリ６をある一定距離平行移動させて、再度先ほど接合させたボール上に接合させる。
しかる後、図５（ｄ）に示すように、再度キャピラリ６をある一定の高さに上昇させた後、ワイヤ５をクランプしてさらにキャピラリ６を上昇させる。クランプした状態でキャピラリ６を上昇させるので、ワイヤ５は破断しキャピラリ６先端からは、ある一定の長さのワイヤ５が残る。これらの工程によって、基板インナーリード２上にボンディングボール（第１のボンディングボール）７ｂが形成される。
次に、図５（ｅ）に示すように、キャピラリ６先端から残されたワイヤ５を、放電によってその先端を球状化させてボール７ａを形成する。この後、図５（ｆ）に示すように、キャピラリ６を、半導体チップ３の電極（電極パッド４）上に移動させる。
次に、図５（ｇ）に示すように、キャピラリ６を下降させ、半導体チップ３の電極（電極パッド４）上にボール７ａを接合させた後、キャピラリ６を上昇させる。これによって、半導体チップ３にボンディングボール（第２のボンディングボール）７ｂが形成される。
この後。図５（ｈ）に示すように、キャピラリ６をある最適な軌跡を描いて移動させ、先ほど形成した基板インナーリード２上のボンディングボール７ｂ上にワイヤ５を接合させて結線を行う。しかる後、図５（ｉ）に示すように、キャピラリ６をある一定の高さに上昇させた後、ワイヤ５をクランプしてさらにキャピラリ６を上昇させてワイヤ５を破断して、１つのワイヤ結線が終了する。
以上のように、インナーリード２側に先にボンディングボール７ｂを形成しておき、この後半導体チップ３の電極（電極パッド４）側にボンディングボール７ｂを形成してここからインナーリード２側に向けてワイヤ５の結線を行うようにしても良い。
図６は、他の実施形態の要部構成を拡大して示すもので、この実施形態では、基板インナーリード２上のボンディング点（ワイヤ５の結線位置）が、基板インナーリード２の長さ方向に沿って交互にずらして千鳥に配置されている。このような構成とすれば、ワイヤボンディングの際に、キャピラリ６が隣接する配線済みのワイヤ５と接触することを防止することができるので、確実に配線を行うことができ、半導体装置の信頼性の向上を図ることができる。
図７は、さらに他の実施形態の要部構成を拡大して示すもので、この実施形態では、電極パッド４が長方形形状に形成されている。そして、基板インナーリード２上のボンディング点（ワイヤ５の結線位置）が、基板インナーリード２の長さ方向に沿って交互にずらして千鳥に配置されているとともに、半導体チップ３の電極パッド４上のボンディング点（ワイヤ５の結線位置）も、電極パッド４の長手方向に沿って交互にずらして千鳥に配置されている。このような構成とすれば、ワイヤボンディングの際にキャピラリ６が隣接する配線済みのワイヤ５と接触することをより確実に防止することができるので、より確実に配線を行うことができる。
図８は、本発明をチップ積層型半導体装置に適用した実施形態の構成を示すものである。同図に示すように、基板１上に搭載された半導体チップ３は、ワイヤ５によるワイヤボンディングによって基板１に形成された基板インナーリード（図８には図示せず。）と電気的に接続されている。また、半導体チップ３は、複数積層されて配置されている。なお、前述したとおり、基板インナーリードは、半導体チップ３の電極パッド４同一ピッチで配置され、基板インナーリード上に形成されたボンディングボール７ｂの径は、基板インナーリードの幅より大きくなるように形成されている。このようなチップ積層型半導体装置に本発明を適用すれば、例えば、フリップチップボンディングを用いた場合に比べて半導体チップ３の外部との電気的接続の自由度が増大し、設計における自由度を拡大することができる。
以上説明したとおり各実施形態では、基板インナーリードが電極パッドと同一ピッチで配置されているので、パッケージ外形サイズの大型化を招くことがない。また、ワイヤボンディングによって半導体チップの電極パッドと基板インナーリードとの接続を行っているので、フリップチップボンディングを用いた従来の半導体装置に比べて製造コストの低減を図ることができる。なお、本発明は、上記した各実施形態に限定されるものではなく、各種の変形が可能であることは勿論である。
本発明の実施形態に係る半導体装置の要部概略構成を拡大して示す図。 図１の半導体装置の要部概略構成をさらに拡大して示す図。 図１の半導体装置の要部概略構成をさらに拡大して示す図。 ワイヤボンディング工程の例を説明するための図。 ワイヤボンディング工程の他の例を説明するための図。 本発明の半導体装置の他の実施形態の要部を拡大して示す図。 本発明の半導体装置の他の実施形態の要部を拡大して示す図。 本発明の半導体装置を積層型半導体装置に適用した実施形態を示す図。 従来の半導体装置の要部構成を示す図。
符号の説明
１……基板、２……基板インナーリード、３……半導体チップ、４……電極パッド、５……ワイヤ、７ｂ……ボンディングボール。

Claims (5)

  1. 所定ピッチで形成された複数の電極パッドを有する半導体チップと、
    前記半導体チップの前記電極パッドと同一ピッチで形成された基板インナーリードを有し、前記半導体チップが搭載される基板とを具備し、
    前記電極パッドと前記基板インナーリードとが、ワイヤの両側にボンディングボールを形成するワイヤボンディングによって接続され、
    前記基板インナーリードの幅より、当該インナーリード上に形成された前記ボンディングボールの径が大きいことを特徴とする半導体装置。
  2. 所定ピッチで形成された複数の電極パッドを有する半導体チップと、
    前記半導体チップの前記電極パッドと同一ピッチで形成された基板インナーリードを有し、前記半導体チップが搭載される基板とを具備し、
    前記電極パッド又は前記基板インナーリード上に第１のボンディングボールを形成した後、前記基板インナーリード又は前記電極パッド上に第２のボンディングボールを形成し、当該第２のボンディングボールからワイヤを伸ばして前記第１のボンディングボールにボンディングするワイヤボンディングによって、前記電極パッドと前記基板インナーリードとが接続され、
    前記基板インナーリードの幅より、当該基板インナーリード上に形成された前記第１又は第２のボンディングボールの径が大きいことを特徴とする半導体装置。
  3. 前記基板インナーリード上のボンディング点が、当該基板インナーリードの長さ方向に交互にずらして配置されていることを特徴とする請求項１又は２記載の半導体装置。
  4. 前記電極パッドが長方形形状に形成され、当該電極パッド上のボンディング点が当該電極パッドの長手方向に交互にずらして配置されていることを特徴とする請求項１〜３いずれか１項記載の半導体装置。
  5. 前記半導体チップの上に他の半導体チップが積層して配置されていることを特徴とする請求項１〜４いずれか１項記載の半導体装置。
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