JP2007067341A - Method of manufacturing circuit board - Google Patents

Method of manufacturing circuit board Download PDF

Info

Publication number
JP2007067341A
JP2007067341A JP2005255048A JP2005255048A JP2007067341A JP 2007067341 A JP2007067341 A JP 2007067341A JP 2005255048 A JP2005255048 A JP 2005255048A JP 2005255048 A JP2005255048 A JP 2005255048A JP 2007067341 A JP2007067341 A JP 2007067341A
Authority
JP
Japan
Prior art keywords
conductive
conduction
circuit wiring
conductive metal
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005255048A
Other languages
Japanese (ja)
Other versions
JP4624217B2 (en
Inventor
Takeshi Koda
猛 國府田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Mektron KK
Original Assignee
Nippon Mektron KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mektron KK filed Critical Nippon Mektron KK
Priority to JP2005255048A priority Critical patent/JP4624217B2/en
Priority to TW095131176A priority patent/TW200721929A/en
Priority to CN2006101422241A priority patent/CN1925725B/en
Publication of JP2007067341A publication Critical patent/JP2007067341A/en
Application granted granted Critical
Publication of JP4624217B2 publication Critical patent/JP4624217B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a circuit board with which double-sided conductive metal layers are surely conducted in a double-sided circuit board and further, a cross-sectional shape of circuit wiring is not made worse. <P>SOLUTION: In a method of manufacturing a circuit board including a conduction structure formed from a through-hole or a bottomed via-hole, a conductive material 4 is given by forming a conduction hole 3 on a double-sided metal-clad laminate including conductive metal layers 2 on both sides of an insulating base 1, a plating resist film 9 is formed excepting for said conduction hole 3 and a land 5 thereof, the plating resist film 9 is released and removed after conducting the conductive metal layers 2 and forming a circuit wiring pattern 10 by plating, and the circuit wiring pattern 10 is formed by removing the exposed conductive metal layers 2 and electrically separating the circuit wiring pattern 10. The step of forming a plating layer for conduction between the double-coated conductive layers and the step of forming a plating layer for circuit wiring formation are performed separately from each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、回路基板の製造方法に係わり、とくにめっきにより高密度回路の配線形成が成される両面回路基板の製造方法に関する。   The present invention relates to a method for manufacturing a circuit board, and more particularly, to a method for manufacturing a double-sided circuit board in which high-density circuit wiring is formed by plating.

回路配線形成に汎用されるエッチング手法では、配線の断面形状が台形となるため高密度化に限界がある。そこで、従来、より高密度回路形成に適しているめっきによる配線形成法が用いられている。   In the etching method widely used for forming circuit wiring, since the cross-sectional shape of the wiring becomes a trapezoid, there is a limit to increasing the density. Therefore, conventionally, a wiring forming method by plating suitable for forming a higher density circuit has been used.

その両面回路基板の製造法は、図4(1)から図5(7)に示される。すなわち、まず、図4(1)に示すように、絶縁ベース材21の両面に導電性金属層22を有する両面金属張積層板を用意し、次に、図4(2)に示すように、上記両面金属張積層板に対し貫通スルーホールまたは有底ビアホールによる導通用孔23を形成する。   The method for manufacturing the double-sided circuit board is shown in FIGS. 4 (1) to 5 (7). That is, first, as shown in FIG. 4 (1), a double-sided metal-clad laminate having conductive metal layers 22 on both sides of the insulating base material 21 is prepared, and then, as shown in FIG. 4 (2), Conductive holes 23 are formed by through-holes or bottomed via holes in the double-sided metal-clad laminate.

次いで、図4(3)に示すように、導通用孔23が形成された両面金属張積層板に対し導電性物質24を付与し、続いて、図4(4)に示すように、導電性物質24が付与された両面の導電性金属層22に対し、めっきレジスト膜25を形成する。   Next, as shown in FIG. 4 (3), a conductive material 24 is applied to the double-sided metal-clad laminate in which the conduction holes 23 are formed, and then, as shown in FIG. A plating resist film 25 is formed on the conductive metal layers 22 on both sides to which the substance 24 is applied.

この後、図5(5)に示すように、めっきレジスト膜25を有する両面金属張積層板に対しめっき手法により両面の導電性金属層22相互間の導通をとると共に、回路配線を形成するめっき26を得る。   Thereafter, as shown in FIG. 5 (5), the double-sided metal-clad laminate having the plating resist film 25 is electrically connected between the conductive metal layers 22 on both sides by a plating technique, and the circuit wiring is formed. 26 is obtained.

次に、図5(6)に示すように、めっきレジスト膜25を剥離除去して導電性金属層を露出させる。次いで、図5(7)に示すように、露出された両面の導電性金属層22を除去して回路配線パターン26を電気的に分離する(回路配線パターンを形成する)ことにより、両面回路配線基板を製造している。
特開平11-186716号公報 特開2003-158364号公報
Next, as shown in FIG. 5 (6), the plating resist film 25 is peeled and removed to expose the conductive metal layer. Next, as shown in FIG. 5 (7), by removing the exposed conductive metal layers 22 on both sides and electrically separating the circuit wiring pattern 26 (forming a circuit wiring pattern), double-sided circuit wiring. Manufactures substrates.
JP-A-11-186716 JP 2003-158364 A

一方、めっきレジスト膜を有する両面金属張積層板に対し、両面の導電性金属層間の導通をとるためにめっき手法により導電性物質を付与することがある。このとき、両面の金属層上にも導電性物質が残存するため、高密度回路における導電性金属層とめっきによる回路配線との密着強度の低下、または剥離が発生する。   On the other hand, a conductive material is sometimes applied to a double-sided metal-clad laminate having a plating resist film by a plating method in order to establish conduction between the conductive metal layers on both sides. At this time, since the conductive substance remains on the metal layers on both sides, the adhesion strength between the conductive metal layer and the circuit wiring due to plating in the high-density circuit is reduced or peeled off.

これらを解消するために、導電性物質の付与後に、両面の導電性金属上の導電性物質を除去するためのエッチング処理を行う工法がある。この場合、除去してはいけない導通用孔の内壁上の導電性物質までもが除去される可能性があり、厳格なエッチング量の管理が必要とされている。   In order to solve these problems, there is a method of performing an etching process for removing the conductive material on the conductive metals on both sides after the conductive material is applied. In this case, even the conductive material on the inner wall of the hole for conduction that should not be removed may be removed, and strict management of the etching amount is required.

他方、一般的なカーボンを成分とした導電性物質の付与を行う工法によりカーボンを成分とした導電性物質を付与する方法がある。しかし、この方法は、錫パラジウムコロイドを用いたダイレクトプレーティングによる導電性物質に比べて、小径の貫通スルーホールまたは有底ビアホールの場合に、両面の金属層間の導通を取るためのめっき処理に対する信頼性が低いという欠点がある。   On the other hand, there is a method of applying a conductive substance containing carbon as a component by a method of applying a conductive substance containing carbon as a general component. However, this method is more reliable than the conductive material by direct plating using tin-palladium colloid, in the case of small-diameter through-holes or bottomed via-holes, the reliability of the plating process for conducting between the metal layers on both sides. There is a disadvantage that the property is low.

さらに、図6に示すように、両面の導電性金属上に残存する回路配線パターン26と両面の導電性金属層22との間の導通孔23の配置により、両面の導電性金属層22相互間の導通孔23の内壁上めっき厚が大きく変化する場合には、両面の導電性金属層間の導通孔の内壁めっき厚、および部品実装上必要とされる回路配線の導体厚の規格を共に満足することが困難なことがある。その場合には、回路配線上において不要な領域にレジスト開口部を設け、電気力線の集中を回避(通称ダミーめっき)する方法が用いられる。   Further, as shown in FIG. 6, the arrangement of the conductive holes 23 between the circuit wiring patterns 26 remaining on the conductive metals on both surfaces and the conductive metal layers 22 on both surfaces allows the conductive metal layers 22 on both surfaces to be connected to each other. When the plating thickness on the inner wall of the conductive hole 23 greatly changes, both the inner wall plating thickness of the conductive hole between the conductive metal layers on both sides and the standard of the conductor thickness of the circuit wiring required for component mounting are satisfied. Can be difficult. In that case, a method of providing a resist opening in an unnecessary area on the circuit wiring and avoiding concentration of lines of electric force (commonly called dummy plating) is used.

しかし、この工法は、部品配置の設計的自由度が制限され、さらには、実装部品の性質から開口部を設けなければならない場合に適応できない。電気力線の集中を回避するためにめっき時の電流密度を下げることも一般的に知られているが、反面、電流密度を低下させることによるめっき処理時間の延長が生産性を低下させている。   However, this construction method is not applicable to the case where the degree of design freedom of component placement is limited, and furthermore, an opening must be provided due to the nature of the mounted component. Although it is generally known to reduce the current density during plating in order to avoid the concentration of electric field lines, on the other hand, the extension of the plating process time by reducing the current density reduces the productivity. .

また、両面の導電性金属層22相互間の導通孔23の内壁上めっき厚が薄い場合の、電気的信頼性の低下のみならず、導通孔23の内壁上のめっき厚がめっきレジスト膜除去後の回路配線パターン26の電気的な分離のエッチングで除去されるものよりも薄い場合には、図7に示すような導通不良27の発生も懸念されるため、各領域の導通孔23の内壁上めっき厚の確認を十分に行わなければならない負担が大きい。   Further, when the plating thickness on the inner wall of the conductive hole 23 between the conductive metal layers 22 on both sides is thin, the plating reliability on the inner wall of the conductive hole 23 is not reduced after the plating resist film is removed. When the thickness of the circuit wiring pattern 26 is thinner than that removed by the electrical separation etching, there is a concern that the conduction failure 27 as shown in FIG. 7 may occur, and therefore, on the inner wall of the conduction hole 23 in each region. The burden of having to fully check the plating thickness is large.

一方、図8に示すような導電性物質を付与する処理での、エッチング工程における絶縁ベース材21の露出防止のため、導電性金属層22の厚さをエッチング量に比べて十分大きなものとしなければならない。しかし、その結果、回路配線の断面形状が悪化する問題がある。   On the other hand, the thickness of the conductive metal layer 22 must be sufficiently larger than the etching amount in order to prevent the insulating base material 21 from being exposed in the etching process in the process of applying a conductive material as shown in FIG. I must. However, as a result, there is a problem that the cross-sectional shape of the circuit wiring deteriorates.

本発明は上述の点を考慮してなされたもので、両面回路基板における両面導電性金属層間の導通を確実にとり、しかも回路配線の断面形状を悪化させることのない回路基板の製造方法を提供することを目的とする。   The present invention has been made in consideration of the above-described points, and provides a method for manufacturing a circuit board that reliably establishes conduction between double-sided conductive metal layers in a double-sided circuit board and does not deteriorate the cross-sectional shape of circuit wiring. For the purpose.

上記課題を解決するため、本発明では、
絶縁ベース材の両面に導電性金属層を有する両面金属張積層板に導通用孔を形成して導電性物質を付与し、前記導通用孔及びそのランド部を除いてめっきレジスト膜を形成してめっき手法により前記導電性金属層間の導通および回路配線パターンの形成を行った後めっきレジスト膜を剥離除去し、露出された前記導電性金属層を除去して回路配線パターンを電気的に分離することにより回路配線パターンを形成する、貫通スルーホール或いは有底ビアホールによる導通構造を有する回路基板の製造方法において、
前記積層板に対し導電性物質を付与した後、前記導電性物質が付与された両面の導電性金属層に対し、前記導通用孔及びそのランド部を除いて両面導通用レジスト膜を形成し、
前記両面導通用レジスト膜を用いてめっきを施し前記導電性金属層間の導通をとり、
前記両面導通用レジスト膜を剥離除去し、
前記導通用孔及びそのランド部を含んで前記導電性金属層をエッチングにより薄くし、
前記導電性金属層に対し、回路配線パターン形成部及び導通用孔及びそのランド部を除いて回路配線用レジスト膜を形成し、
回路配線用レジスト膜を用いてめっきを施して回路配線パターンを形成した後、前記回路配線用レジスト膜を剥離除去して前記導電性金属層を露出し、
前記導電性金属層を除去して回路配線パターンを電気的に分離することにより回路配線パターンを形成する、
ことを特徴とする回路基板の製造法、
を提供する。
In order to solve the above problems, in the present invention,
A conductive hole is formed on a double-sided metal-clad laminate having a conductive metal layer on both sides of an insulating base material to provide a conductive material, and a plating resist film is formed except for the conductive hole and its land portion. After conducting conduction between the conductive metal layers and forming a circuit wiring pattern by a plating technique, the plating resist film is peeled and removed, and the exposed conductive metal layer is removed to electrically separate the circuit wiring pattern. In the method of manufacturing a circuit board having a conduction structure with a through-hole or a bottomed via hole, the circuit wiring pattern is formed by:
After applying a conductive substance to the laminate, a double-sided conductive resist film is formed on both sides of the conductive metal layer to which the conductive substance has been applied, except for the conductive hole and its land part,
Plating using the resist film for double-sided conduction and conducting between the conductive metal layers,
Stripping and removing the resist film for double-sided conduction,
The conductive metal layer including the conduction hole and the land portion thereof is thinned by etching,
A resist film for circuit wiring is formed on the conductive metal layer except for a circuit wiring pattern forming portion and a conduction hole and its land portion,
After plating using a circuit wiring resist film to form a circuit wiring pattern, the circuit wiring resist film is peeled off to expose the conductive metal layer,
Forming a circuit wiring pattern by removing the conductive metal layer and electrically separating the circuit wiring pattern;
A method of manufacturing a circuit board,
I will provide a.

本発明によれば、回路配線パターンを形成する際に不要となる両面の導電性金属層上の導電性物質を除去する際、導電性金属層間の導通は、めっき層によって保護されているため、両面の導電性金属層間の導通不良が発生せず、しかも厳格なエッチング量の管理も必要としないから生産性が良好である。   According to the present invention, when removing the conductive material on the conductive metal layers on both sides that are not required when forming the circuit wiring pattern, the conduction between the conductive metal layers is protected by the plating layer, There is no conduction failure between the conductive metal layers on both sides, and strict management of the etching amount is not required, so that productivity is good.

また、両面の導電性金属層間の導通のためのめっきと回路配線パターン形成のためのめっきとは分離して2度実施されるため、回路配線パターンの形成について部品実装上で要求される両面の導電性金属層の厚みを考慮する必要がなく、厚みを確保するためのめっき時の電流密度の低下、それによる生産性の低下を防止できる。   In addition, since the plating for conduction between the conductive metal layers on both sides and the plating for forming the circuit wiring pattern are performed twice separately, both sides of the circuit wiring pattern required for component mounting are formed. It is not necessary to consider the thickness of the conductive metal layer, and it is possible to prevent a decrease in current density during plating for ensuring the thickness and a decrease in productivity due to this.

そして、2度にわたってめっきが行われるため、導通信頼性を満足するめっき厚とすることができる上に、めっきレジスト膜を除去した後の、回路配線パターンを分離するためのエッチングによる導通不良の発生が解消される。しかも、めっき厚が十分に確保されるため、めっき厚の確認の負担もなくなる。   Since plating is performed twice, it is possible to obtain a plating thickness that satisfies the conduction reliability, and after the plating resist film is removed, the occurrence of poor conduction due to etching for separating the circuit wiring pattern. Is resolved. In addition, since the plating thickness is sufficiently secured, the burden of checking the plating thickness is eliminated.

さらに、回路配線パターンをめっき手法により形成する前に両面の導電性金属層を薄くするため、回路配線の断面形状を悪化させることも防止できる。   Furthermore, since the conductive metal layers on both sides are thinned before the circuit wiring pattern is formed by plating, it is possible to prevent the cross-sectional shape of the circuit wiring from being deteriorated.

以下、図1ないし図3を参照して本発明の実施形態1を説明する。   Embodiment 1 of the present invention will be described below with reference to FIGS.

実施形態1Embodiment 1

図1は、本発明の実施形態1における各工程を示したものである。   FIG. 1 shows each step in Embodiment 1 of the present invention.

まず、図1(1)に示すように、ポリイミドフィルム等の絶縁ベース材1の両面に厚さ4μmの銅箔を導電性金属層2として設けた両面金属張積層板を用意する。次いで、図1(2)に示すように、この両面金属張積層板に対しUV−YAGレーザーを照射して、貫通スルーホールとしての導通用孔3を形成する。   First, as shown in FIG. 1 (1), a double-sided metal-clad laminate in which a copper foil having a thickness of 4 μm is provided as a conductive metal layer 2 on both sides of an insulating base material 1 such as a polyimide film is prepared. Next, as shown in FIG. 1 (2), this double-sided metal-clad laminate is irradiated with a UV-YAG laser to form conduction holes 3 as through-holes.

次に、図1(3)に示すように、導通用孔3が形成された両面金属張積層板に対し、コンダクトロン処理等により導電性物質4を付与する。続いて、図1(4)に示すように、導電性物質4が付与された両面の導電性金属層2に対し、感光性ドライフィルム型レジスト(図示せず)をラミネートし、パターン露光および現像処理を行う。これにより、導通用孔3およびそのランド部5を除き、両面導通用レジスト膜6を形成する。   Next, as shown in FIG. 1 (3), the conductive material 4 is applied to the double-sided metal-clad laminate having the conduction holes 3 formed by conductron treatment or the like. Subsequently, as shown in FIG. 1 (4), a photosensitive dry film resist (not shown) is laminated on the conductive metal layers 2 to which the conductive material 4 is applied, and pattern exposure and development are performed. Process. Thereby, the resist film 6 for both-side conduction is formed except for the conduction hole 3 and its land portion 5.

次に、図2(5)に示すように、両面導通用レジスト膜6を有する両面金属張積層板に対し、硫酸銅めっき処理により両面の導電性金属層2相互間の導通用めっき7を形成する。本発明において、導電性物質の付与には、錫−パラジウムコロイドを用いたダイレクトプレーティングの導電化処理を用いることができる。   Next, as shown in FIG. 2 (5), conductive plating 7 between the conductive metal layers 2 on both sides is formed on the double-sided metal-clad laminate having the double-sided conductive resist film 6 by copper sulfate plating. To do. In the present invention, a conductive treatment of direct plating using a tin-palladium colloid can be used for imparting the conductive substance.

次いで、図2(6)に示すように、両面導通用レジスト膜6を剥離除去する。続いて、図2(7)に示すように、両面導通用レジスト膜6の除去後に、導通用孔3およびそのランド部5を含んだ両面の導電性金属層2を、過硫酸ソーダ系の混合液により3μmのエッチング処理を施し、1μmの厚みにまで薄くする。   Next, as shown in FIG. 2 (6), the double-sided conductive resist film 6 is peeled and removed. Subsequently, as shown in FIG. 2 (7), after removing the double-sided conductive resist film 6, the conductive metal layer 2 on both sides including the conductive hole 3 and its land portion 5 is mixed with a sodium persulfate-based mixture. Etching treatment of 3 μm is performed with the liquid, and the thickness is reduced to 1 μm.

ここで、両面導通用レジスト膜の除去後のエッチングとしては、導通用孔およびそのランド部を除く両面の導電性金属層上の不要な導電性物質を除去でき、しかもエッチング後には、絶縁ベース材の両面の導電性金属層が0.5μm以上で2.5μm以下の厚みとなる量とするとよい。また、両面の導電性金属層相互間の導通のための導通孔の内壁めっきの厚みは、両面導通用レジスト膜6の除去後のエッチング量の2倍以上であるとよい。   Here, as the etching after the removal of the resist film for double-sided conduction, unnecessary conductive materials on the conductive metal layers on both sides excluding the conduction hole and its land part can be removed, and after the etching, an insulating base material is obtained. It is preferable that the conductive metal layers on both sides have a thickness of 0.5 μm or more and 2.5 μm or less. The thickness of the inner wall plating of the conduction hole for conduction between the conductive metal layers on both sides is preferably at least twice the etching amount after the removal of the resist film 6 for both-side conduction.

この後、図2(8)に示すように、薄くされた両面の導電性金属層2に対し、感光性ドライフィルム型レジスト(図示せず)をラミネートし、パターン露光および現像処理を行うことにより、回路配線パターン形成部8および導通用孔3およびそのランド部5を除いて、回路配線用レジスト膜9を形成する。   Thereafter, as shown in FIG. 2 (8), a photosensitive dry film resist (not shown) is laminated on the thinned conductive metal layer 2 on both sides, and pattern exposure and development are performed. Then, a circuit wiring resist film 9 is formed except for the circuit wiring pattern forming portion 8 and the conduction hole 3 and its land portion 5.

次に、図3(9)に示すように、硫酸銅めっき手法により回路配線パターン10を形成する。次いで、図3(10)に示すように、回路配線用レジスト膜9を剥離除去し、導電性金属層2を露出させる。   Next, as shown in FIG. 3 (9), a circuit wiring pattern 10 is formed by a copper sulfate plating method. Next, as shown in FIG. 3 (10), the circuit wiring resist film 9 is peeled and removed to expose the conductive metal layer 2.

最後に、図3(11)に示すように、露出された両面の導電性金属層2をエッチングにより除去して回路配線パターン10を電気的に分離し、回路配線パターンを持った基板を形成する。   Finally, as shown in FIG. 3 (11), the exposed conductive metal layers 2 on both sides are removed by etching to electrically isolate the circuit wiring pattern 10 to form a substrate having the circuit wiring pattern. .

これを、実施例1によって更に具体的に説明する。   This will be described more specifically with reference to the first embodiment.

まず、ポリイミドフィルムの両面に銅箔を有する両面無接着型銅張積層板としての、新日鉄化学(株)製「エスパネックス」(厚さ25μm)を用意し、両面の導電性金属層の厚みが4μmとなるように、ハーフエッチング処理を行う。   First, “Espanex” (thickness 25 μm) manufactured by Nippon Steel Chemical Co., Ltd. as a double-sided non-adhesive copper-clad laminate with copper foil on both sides of the polyimide film is prepared, and the thickness of the conductive metal layers on both sides is Half-etching is performed so that the thickness becomes 4 μm.

次いで、UV−YAGレーザーにより、開口径50μmのスルーホールを形成した。次に、コンダクトロン処理により導電性物質の付与を行う。   Next, a through hole with an opening diameter of 50 μm was formed by a UV-YAG laser. Next, a conductive substance is applied by conductron treatment.

続いて、20μm厚の感光性ドライフィルムをラミネートし、パターン露光および現像を行うことにより、導通用孔およびそのランド部を除き両面導通用レジスト膜を形成する。この後、硫酸銅めっき処理により両面の導電性金属層間の導通として、厚さが8μm以上で12μm以下のめっきを得る。   Subsequently, a photosensitive dry film having a thickness of 20 μm is laminated, and pattern exposure and development are performed to form a double-sided conductive resist film excluding the conductive holes and the land portions thereof. Then, plating with a thickness of 8 μm or more and 12 μm or less is obtained as conduction between the conductive metal layers on both sides by copper sulfate plating treatment.

次に、苛性ソーダにより両面導通めっき用レジスト膜を剥離除去する。次いで、導通用孔およびそのランド部を含めて両面の導電性金属層を、過硫酸ソーダ系の混合液による3μmのエッチング処理により、1μmの厚みにまで薄くする。この処理により、導電性物質を除去する。   Next, the resist film for double-sided conductive plating is peeled and removed with caustic soda. Next, the conductive metal layers on both sides including the conduction hole and the land portion thereof are thinned to a thickness of 1 μm by an etching process of 3 μm with a sodium persulfate mixed solution. By this treatment, the conductive material is removed.

続いて、感光性ドライフィルム型レジストをラミネートし、パターン露光および現像処理を行うことにより、回路配線パターン形成部および導通用孔ならびにそのランド部を除いて、回路配線用レジスト膜を形成する。   Subsequently, by laminating a photosensitive dry film type resist and performing pattern exposure and development processing, a circuit wiring resist film is formed except for the circuit wiring pattern forming portion, the conduction hole and the land portion thereof.

この後、硫酸銅めっき手法により、導体厚が9μm以上で10μm以下の回路配線パターンを得る。この処理により、両面の導電性金属層の導通用めっき厚を、15μm以上で20μm以下とすることができる。次いで、苛性ソーダにより回路配線用レジスト膜を剥離除去して導電性金属層を露出させる。   Thereafter, a circuit wiring pattern having a conductor thickness of 9 μm or more and 10 μm or less is obtained by a copper sulfate plating method. By this treatment, the conductive plating thickness of the conductive metal layers on both sides can be set to 15 μm or more and 20 μm or less. Next, the circuit wiring resist film is peeled and removed with caustic soda to expose the conductive metal layer.

最後に、露出された両面の導電性金属層を過硫酸ソーダ系の混合液によるエッチング処理により除去して回路配線パターンを電気的に分離し、高密度な回路配線パターンを持つ回路配線基板を得る。   Finally, the exposed conductive metal layers on both sides are removed by etching with a mixed solution of sodium persulfate to electrically separate the circuit wiring patterns to obtain a circuit wiring board having a high-density circuit wiring pattern. .

本発明の一実施形態を示す工程断面図。Process sectional drawing which shows one Embodiment of this invention. 図1に続く工程断面図。Process sectional drawing following FIG. 図2に続く工程断面図。Process sectional drawing following FIG. 従来の製造方法を示す工程断面図。Sectional drawing which shows the conventional manufacturing method. 図4に続く工程断面図。Process sectional drawing following FIG. 従来の製造方法による回路基板の断面図。Sectional drawing of the circuit board by the conventional manufacturing method. 従来の製造方法による回路基板の断面図。Sectional drawing of the circuit board by the conventional manufacturing method. 従来の製造方法による回路基板の断面図。Sectional drawing of the circuit board by the conventional manufacturing method.

符号の説明Explanation of symbols

1 絶縁ベース材
2 導電性金属層
3 導通用孔
4 導電性物質
5 導通用孔ランド部
6 両面導通用レジスト膜
7 導通用めっき
8 回路配線パターン形成部
9 回路配線用レジスト膜
10 回路配線パターン
21 絶縁ベース材
22 導電性金属層
23 導通用孔
24 導電性物質
25 めっきレジスト膜
26 回路配線パターン
27 エッチングによる導通不良
DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Conductive metal layer 3 Conductive hole 4 Conductive substance 5 Conductive hole land part 6 Double-sided conductive resist film 7 Conductive plating 8 Circuit wiring pattern forming part 9 Circuit wiring resist film 10 Circuit wiring pattern 21 Insulating base material 22 Conductive metal layer 23 Conductive hole 24 Conductive substance 25 Plating resist film 26 Circuit wiring pattern 27 Conduction failure due to etching

Claims (4)

絶縁ベース材の両面に導電性金属層を有する両面金属張積層板に導通用孔を形成して導電性物質を付与し、前記導通用孔及びそのランド部を除いてめっきレジスト膜を形成してめっき手法により前記導電性金属層間の導通および回路配線パターンの形成を行った後めっきレジスト膜を剥離除去し、露出された前記導電性金属層を除去して回路配線パターンを電気的に分離することにより回路配線パターンを形成する、貫通スルーホール或いは有底ビアホールによる導通構造を有する回路基板の製造方法において、
前記積層板に対し導電性物質を付与した後、前記導電性物質が付与された両面の導電性金属層に対し、前記導通用孔及びそのランド部を除いて両面導通用レジスト膜を形成し、
前記両面導通用レジスト膜を用いめっきを施して前記導電性金属層間の導通をとり、
前記両面導通用レジスト膜を剥離除去し、
前記導通用孔及びそのランド部を含んで前記導電性金属層をエッチングにより薄くし、
前記導電性金属層に対し、回路配線パターン形成部及び導通用孔及びそのランド部を除いて回路配線用レジスト膜を形成し、
回路配線用レジスト膜を用いてめっきを施して回路配線パターンを形成した後、前記回路配線用レジスト膜を剥離除去して前記導電性金属層を露出し、
前記導電性金属層を除去して回路配線パターンを電気的に分離することにより回路配線パターンを形成する、
ことを特徴とする回路基板の製造法。
A conductive hole is formed on a double-sided metal-clad laminate having a conductive metal layer on both sides of an insulating base material to provide a conductive material, and a plating resist film is formed except for the conductive hole and its land portion. After conducting conduction between the conductive metal layers and forming a circuit wiring pattern by a plating technique, the plating resist film is peeled and removed, and the exposed conductive metal layer is removed to electrically separate the circuit wiring pattern. In the method of manufacturing a circuit board having a conduction structure with a through-hole or a bottomed via hole, the circuit wiring pattern is formed by:
After applying a conductive substance to the laminate, a double-sided conductive resist film is formed on both sides of the conductive metal layer to which the conductive substance has been applied, except for the conductive hole and its land part,
Applying plating using the resist film for double-sided conduction to take conduction between the conductive metal layers,
Stripping and removing the resist film for double-sided conduction,
The conductive metal layer including the conduction hole and the land portion thereof is thinned by etching,
A resist film for circuit wiring is formed on the conductive metal layer except for a circuit wiring pattern forming portion and a conduction hole and its land portion,
After plating using a circuit wiring resist film to form a circuit wiring pattern, the circuit wiring resist film is peeled off to expose the conductive metal layer,
Forming a circuit wiring pattern by removing the conductive metal layer and electrically separating the circuit wiring pattern;
A method of manufacturing a circuit board.
請求項1記載の回路基板の製造方法において、
両面導通用レジスト膜除去後のエッチングは、導通用孔およびそのランド部を除く両面の導電性金属層上の不要な導電性物質を除去でき、さらにエッチング後には絶縁ベース材の両面の導電性金属層が0.5μm以上で2.5μm以下の厚みとなる量とすることを特徴とする回路基板の製造方法。
In the manufacturing method of the circuit board of Claim 1,
Etching after removing the resist film for double-sided conduction can remove unnecessary conductive material on the conductive metal layers on both sides except for the conduction hole and its land, and after etching, the conductive metal on both sides of the insulating base material A method for producing a circuit board, characterized in that the layer has a thickness of 0.5 μm or more and 2.5 μm or less.
請求項1記載の回路基板の製造方法において、
両面金属張積層板に対しめっき手法による両面の導電性金属層間導通のための導通孔の内壁めっき厚みは、請求項2に記載のエッチング量の2倍以上であることを特徴とする回路基板の製造方法。
In the manufacturing method of the circuit board of Claim 1,
The thickness of the inner wall plating of the conductive hole for conductive metal interlayer conduction on both sides by the plating method on the double-sided metal-clad laminate is at least twice the etching amount according to claim 2. Production method.
請求項1記載の回路基板の製造方法において、
導通用孔が形成された両面金属張積層板に対し導電性物質を付与することにより形成される導電性物質層は、錫パラジウムコロイドを用いたダイレクトプレーティングであることを特徴とする回路基板の製造方法。
In the manufacturing method of the circuit board of Claim 1,
A conductive material layer formed by applying a conductive material to a double-sided metal-clad laminate in which a hole for conduction is formed is a direct plating using a tin-palladium colloid. Production method.
JP2005255048A 2005-09-02 2005-09-02 Circuit board manufacturing method Active JP4624217B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005255048A JP4624217B2 (en) 2005-09-02 2005-09-02 Circuit board manufacturing method
TW095131176A TW200721929A (en) 2005-09-02 2006-08-24 Method for manufacturing circuit substrate
CN2006101422241A CN1925725B (en) 2005-09-02 2006-09-01 Method for manufacturing circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005255048A JP4624217B2 (en) 2005-09-02 2005-09-02 Circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JP2007067341A true JP2007067341A (en) 2007-03-15
JP4624217B2 JP4624217B2 (en) 2011-02-02

Family

ID=37818110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005255048A Active JP4624217B2 (en) 2005-09-02 2005-09-02 Circuit board manufacturing method

Country Status (3)

Country Link
JP (1) JP4624217B2 (en)
CN (1) CN1925725B (en)
TW (1) TW200721929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010016334A (en) * 2008-07-02 2010-01-21 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
WO2022097481A1 (en) * 2020-11-05 2022-05-12 Dic株式会社 Laminate for semi-additive manufacturing and printed wiring board using same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783332B (en) * 2009-01-16 2012-01-25 日月光半导体制造股份有限公司 Circuit board and preparation process thereof
CN102427670A (en) * 2011-11-08 2012-04-25 汕头超声印制板(二厂)有限公司 Method for thinning copper layer of printed circuit board
CN104105361B (en) * 2014-05-07 2018-08-31 深圳市环基实业有限公司 A kind of method of circuit board selective electroplating conductive hole
CN108235598B (en) * 2017-12-13 2019-10-18 深南电路股份有限公司 A kind of special gold plated pads manufacturing method
WO2020130101A1 (en) * 2018-12-20 2020-06-25 日立化成株式会社 Wiring board and production method for same
CN111712065B (en) * 2020-07-08 2022-08-12 高德(江苏)电子科技股份有限公司 Machining process for avoiding fracture of copper in holes of rigid-flex board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216648A (en) * 1993-01-14 1994-08-05 Sumitomo Electric Ind Ltd Strain correcting circuit
JPH11346060A (en) * 1998-04-01 1999-12-14 Mitsui Mining & Smelting Co Ltd Manufacture of printed wiring board
JP2000282245A (en) * 1999-03-30 2000-10-10 Ebara Udylite Kk CONDITIONER COMPOSITION AND METHOD FOR INCREASING AMOUNT OF Pd-Sn COLLOIDAL CATALYST TO BE ADSORBED USING THE SAME
JP2004335704A (en) * 2003-05-07 2004-11-25 Internatl Business Mach Corp <Ibm> Printed-circuit board and method for manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1223247C (en) * 1998-09-18 2005-10-12 范蒂科股份公司 Method for producing etched circuit
CN1494120A (en) * 2002-10-28 2004-05-05 华泰电子股份有限公司 Metal electroplating method of integrated circuit packaging substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216648A (en) * 1993-01-14 1994-08-05 Sumitomo Electric Ind Ltd Strain correcting circuit
JPH11346060A (en) * 1998-04-01 1999-12-14 Mitsui Mining & Smelting Co Ltd Manufacture of printed wiring board
JP2000282245A (en) * 1999-03-30 2000-10-10 Ebara Udylite Kk CONDITIONER COMPOSITION AND METHOD FOR INCREASING AMOUNT OF Pd-Sn COLLOIDAL CATALYST TO BE ADSORBED USING THE SAME
JP2004335704A (en) * 2003-05-07 2004-11-25 Internatl Business Mach Corp <Ibm> Printed-circuit board and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010016334A (en) * 2008-07-02 2010-01-21 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
WO2022097481A1 (en) * 2020-11-05 2022-05-12 Dic株式会社 Laminate for semi-additive manufacturing and printed wiring board using same
JPWO2022097481A1 (en) * 2020-11-05 2022-05-12

Also Published As

Publication number Publication date
CN1925725B (en) 2010-11-03
CN1925725A (en) 2007-03-07
JP4624217B2 (en) 2011-02-02
TW200721929A (en) 2007-06-01
TWI357291B (en) 2012-01-21

Similar Documents

Publication Publication Date Title
JP4624217B2 (en) Circuit board manufacturing method
TWI692284B (en) Printed wiring board and its manufacturing method
TW200950616A (en) High density package substrate and method for fabricating the same
JP2017504193A (en) Method for forming segment via for printed circuit board
JP6778667B2 (en) Printed wiring board and its manufacturing method
JP2012227557A (en) Manufacturing method of printed circuit board
JP2009283671A (en) Method of manufacturing printed-wiring board
JP4488187B2 (en) Method for manufacturing substrate having via hole
JP2013106034A (en) Manufacturing method of printed circuit board
JPH1187931A (en) Manufacture of printed circuit board
JP4972753B2 (en) Method for manufacturing printed circuit board
JP2010205801A (en) Method of manufacturing wiring board
KR20100109698A (en) Method of manufacturing a printed circuit board
JPH1187886A (en) Production of printed wiring board
JP4056492B2 (en) Circuit board manufacturing method
JP2000124615A (en) Multilayer printed wiring board and its manufacture
JP2004158703A (en) Printed wiring board and method for manufacturing the same
WO2024084994A1 (en) Printed wiring board
KR100771352B1 (en) Fabricating method of printed circuit board
KR101085476B1 (en) Manufacturing method for printed circuit board
JP2008021784A (en) Printed circuit board equipped with fine wiring circuit and its manufacturing method
JP2006049642A (en) Method of manufacturing double-sided interconnection tape carrier and tape carrier manufactured thereby
JP5312831B2 (en) Method for manufacturing printed wiring board
JP2003304066A (en) Multilayer printed wiring board and its manufacturing method
KR20100068747A (en) Manufacturing method for printed circuit board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080325

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100825

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100827

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100916

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101008

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101102

R150 Certificate of patent or registration of utility model

Ref document number: 4624217

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131112

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250