JP2007036283A - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP2007036283A
JP2007036283A JP2006269552A JP2006269552A JP2007036283A JP 2007036283 A JP2007036283 A JP 2007036283A JP 2006269552 A JP2006269552 A JP 2006269552A JP 2006269552 A JP2006269552 A JP 2006269552A JP 2007036283 A JP2007036283 A JP 2007036283A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
lead
protruding electrode
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006269552A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007036283A5 (enrdf_load_stackoverflow
Inventor
Kenji Toyosawa
健司 豊沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2006269552A priority Critical patent/JP2007036283A/ja
Publication of JP2007036283A publication Critical patent/JP2007036283A/ja
Publication of JP2007036283A5 publication Critical patent/JP2007036283A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)
JP2006269552A 2006-09-29 2006-09-29 半導体装置 Pending JP2007036283A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006269552A JP2007036283A (ja) 2006-09-29 2006-09-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006269552A JP2007036283A (ja) 2006-09-29 2006-09-29 半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2002357089A Division JP4271435B2 (ja) 2002-12-09 2002-12-09 半導体装置

Publications (2)

Publication Number Publication Date
JP2007036283A true JP2007036283A (ja) 2007-02-08
JP2007036283A5 JP2007036283A5 (enrdf_load_stackoverflow) 2008-04-10

Family

ID=37795055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006269552A Pending JP2007036283A (ja) 2006-09-29 2006-09-29 半導体装置

Country Status (1)

Country Link
JP (1) JP2007036283A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8339561B2 (en) 2008-01-21 2012-12-25 Samsung Electronics Co., Ltd. Wiring substrate, tape package having the same, and display device having the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01217931A (ja) * 1988-02-26 1989-08-31 Hitachi Ltd フリップチップ
JPH07335692A (ja) * 1994-06-10 1995-12-22 Toshiba Micro Comput Eng Corp 半導体集積回路装置
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法
JP2000269611A (ja) * 1999-03-16 2000-09-29 Casio Comput Co Ltd フレキシブル配線基板
JP2000286291A (ja) * 1999-03-30 2000-10-13 Kyocera Corp 半導体素子の実装構造体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01217931A (ja) * 1988-02-26 1989-08-31 Hitachi Ltd フリップチップ
JPH07335692A (ja) * 1994-06-10 1995-12-22 Toshiba Micro Comput Eng Corp 半導体集積回路装置
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法
JP2000269611A (ja) * 1999-03-16 2000-09-29 Casio Comput Co Ltd フレキシブル配線基板
JP2000286291A (ja) * 1999-03-30 2000-10-13 Kyocera Corp 半導体素子の実装構造体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8339561B2 (en) 2008-01-21 2012-12-25 Samsung Electronics Co., Ltd. Wiring substrate, tape package having the same, and display device having the same
KR101457335B1 (ko) * 2008-01-21 2014-11-04 삼성전자주식회사 배선기판, 이를 갖는 테이프 패키지 및 표시장치

Similar Documents

Publication Publication Date Title
JP4271435B2 (ja) 半導体装置
US6525422B1 (en) Semiconductor device including bump electrodes
KR20010078040A (ko) 플렉시블배선기판 및 그 제조방법 및 플렉시블배선기판을구비한 표시장치
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
US7439611B2 (en) Circuit board with auxiliary wiring configuration to suppress breakage during bonding process
US7893550B2 (en) Semiconductor package comprising alignment members
JP2005079581A (ja) テープ基板、及びテープ基板を用いた半導体チップパッケージ、及び半導体チップパッケージを用いたlcd装置
US7508073B2 (en) Wiring board, semiconductor device using the same, and method for manufacturing wiring board
JP4171492B2 (ja) 半導体装置およびその製造方法
JP2007103430A (ja) 配線基板
CN101499453B (zh) 配线电路基板及其制造方法
JP2005252227A (ja) フィルム基板およびその製造方法と画像表示用基板
JP4935758B2 (ja) Tabテープの製造方法ならびに配線板の製造方法
JP2010177493A (ja) 電子ディバイス装置、およびその端子接続方法
JP2007036283A (ja) 半導体装置
JP4488073B2 (ja) 電気接続装置
TW200824057A (en) Semiconductor package and display apparatus
JP2013026291A (ja) 半導体装置
JP4123371B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP4348260B2 (ja) 半導体装置実装用基材
JP4461961B2 (ja) 表示モジュール
JP2007258281A (ja) フレキシブル配線基板およびその接続構造
JP2005203388A (ja) 半導体装置およびその製造方法
JP4241324B2 (ja) 半導体装置及びその製造方法
JP2004328001A (ja) 配線基板

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080226

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080804

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090818

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091016

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20101005