JP2007036063A - Manufacturing method of multilayer substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a reliable multilayer substrate where conductive patterns on an upper layer and a lower layer are surely connected, even if the lines of a conductive pattern, or the intervals between lines are narrow. <P>SOLUTION: The manufacturing method includes a process where an insulating layer 10 is arranged on the surface of a substrate 12 on which a conductive pattern 13 is formed, a process where an arranged surface of the insulating layer 10 is processed to provide a groove 5 and a via hole 2 that connects to the groove 5, and also connects to the conductive pattern 13 of the lower layer; and a process where a conductive layer is formed at the groove 5 and the via hole 2, and the processed conductive layer is connected to the conductive pattern 13 of the lower layer as a conductive pattern. By repeating these processes, a multilayer substrate is formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer substrate in which a plurality of substrates are stacked to form one multilayer substrate.

  In recent years, a multi-layer substrate in which conductive layers formed of a conductor (hereinafter referred to as “conductive pattern”) and insulating layers made of a resin are alternately stacked has been widely used. The upper and lower conductive patterns of the multilayer substrate are connected by via holes (holes). The via hole is formed with reference to an alignment mark provided in advance.

FIG. 2 is a diagram showing a manufacturing process of a semi-additive method used in a manufacturing process of a semiconductor package (high-density printed circuit board), where (a1) to (a4) are cross-sectional views, and (b1) to (b4). ) Is a plan view corresponding to (a1) to (a4).
In addition to the conductive pattern 13, several (for example, four) alignment marks 11 are formed on the upper surface of the base material 12 serving as a core, and the insulating layer 10 is laminated (laminated) on the upper side by adhesion or the like.
First, as shown in FIG. 2 (a1), the alignment mark 11 formed on the surface of the base material 12 is imaged by a camera, and the coordinates of the respective center positions of the alignment mark 11 are obtained by image processing to obtain this substrate. After determining the relationship between the coordinate system and the processing coordinate system, the optical axis of the laser is positioned at the center of the conductive pattern 13, for example, and the via hole 2 is formed in the insulating layer 10 by irradiating the laser. When imaging the alignment mark 11, if the insulating layer 10 is opaque, the alignment mark 11 is exposed on the surface by machining or the like, and if the insulating layer 10 is transparent or nearly transparent, the insulating layer 10 is removed. The alignment mark 11 is imaged without being deleted.
Next, as shown in FIG. 2 (a2), a resist 15 is applied to the surface 10a of the insulating layer 10 in which the via hole 2 is formed, and further, an alignment mark 11 (or a laser is applied to the insulating layer 10 by laser). The mask 16 is arranged with reference to the formed alignment mark). In this state, ultraviolet rays are irradiated from above in the drawing of the mask 16 to expose the resist 15 in portions not covered by the mask 16 (here, land formation portions and conductive pattern formation portions).
Next, the resist 15 exposed by chemical treatment is removed. As a result, as shown in FIG. 2A3, the resist 15 remains on the insulating layer surface 10a except for the land forming portion and the conductive pattern forming portion.
Next, as shown in FIG. 2A4, the resist 15 removal portion is subjected to copper plating to form the conductive pattern 8 and the land 9. At this time, the lower conductive pattern 13 and the upper conductive pattern 8 are electrically connected by the copper plating layer formed on the inner wall portion of the via hole 2. Thereafter, the remaining resist 15 is removed by chemical treatment.

  The density of printed circuit boards for semiconductor packages is increasing year by year, and the line width of a conductive pattern and the distance to an adjacent conductive pattern (hereinafter referred to as “line interval”) are becoming narrower. Along with this, the diameters of lands and via holes have also become smaller.

In order to securely connect the lower conductive pattern and the upper conductive pattern, it is necessary to arrange a via hole at a position where both overlap in the height direction.
For this reason, in the prior art, the manufacturing cost of the mask becomes expensive. In addition, since the mask and the substrate 12 expand and contract as the temperature changes, the via holes and the conductive patterns must have a sufficient line width and line spacing, and the via holes can be reduced in diameter and conductive. It was difficult to make the line width and line spacing of the sex pattern 10 μm or less, respectively.

  The object of the present invention is to solve the above-mentioned problems, and even when the line width and line interval of the conductive pattern are narrow, the upper layer and the lower layer conductive pattern are securely connected, and the multilayer substrate has excellent reliability as a product. To provide a manufacturing method.

  In order to solve the above-mentioned problems, the present invention provides a step of disposing an insulating layer on the surface of a substrate on which a conductive pattern is formed, a groove on the surface of the disposed insulating layer, and the lower layer connected to the groove and the lower layer A step of processing a hole to be connected to the conductive pattern, and a step of forming a conductive layer in the processed groove and hole and connecting the formed conductive layer as a conductive pattern to the lower conductive pattern are repeated. Forming a multi-layer substrate.

  According to the present invention, even when the line width and line interval of the conductive pattern are narrow, the upper layer conductive pattern and the lower layer conductive pattern can be reliably connected. Can be manufactured.

Hereinafter, the present invention will be described with reference to the drawings.
FIG. 1 is a view showing a manufacturing process of a multilayer substrate according to the present invention, wherein (a1) to (a3) are sectional views, and (b1) to (b3) are plan views corresponding to (a1) to (a3). It is.
As shown in FIG. 2A1, several alignment marks 11 (for example, four) are formed on the upper surface of the base material 12 serving as the core in addition to the conductive pattern 13, and the insulating layer 10 is laminated thereon. Has been.
First, the alignment mark 11 formed on the surface of the base material 12 is imaged with a camera, the coordinates of the center position of each alignment mark 11 are obtained by image processing, and the relationship between the coordinate system of this substrate and the processing coordinate system Then, the optical axis of the laser is positioned at the center of the conductive pattern 13, for example, and the laser 1 is irradiated to form the via hole 2 in the insulating layer 10.

  Next, as shown in FIG. 2A2, a shallow hole 6 for forming a land whose axis is coaxial with the axis of the via hole 2 is formed in the via hole 2 by a laser 4 having a beam diameter larger than that of the laser 1. It is formed on the outer periphery. Further, the groove 5 for forming the conductive pattern is processed by the laser 3 whose beam diameter is smaller than that of the laser 1. The depth of the groove 5 is formed such that the bottom surface is substantially the same as or slightly deeper than the bottom surface of the shallow hole 6, and one end in the longitudinal direction overlaps the shallow hole 6.

  Next, as shown in FIG. 4A3, copper is plated on the groove 5 and the shallow hole 6 processed by the laser, and the land 5 and the conductive pattern are formed by filling the groove 5 and the shallow hole 6 with copper. At the same time, the conductive pattern in the lower layer and the conductive pattern in the land and the groove 5 are connected by copper filled in the via hole 2. In addition, copper plating is performed in the following procedures, for example. That is, a copper underlayer is formed on the entire surface of the insulating layer surface 10a including the inner wall surface of the via hole 2, the inner wall surface of the shallow hole 6, the bottom surface of the groove 5, and the inner wall surface by electroless copper plating. Next, the copper layer formed on the surface of the insulating layer surface 10a excluding the inner wall of the via hole 2, the inner wall of the shallow hole 6, the bottom surface of the groove 5 and the inner wall surface is removed by soft etching or polishing, and further the electroless copper Plating is performed. In this way, the inner wall surface of the via hole 2, the inner wall surface of the shallow hole 6, the bottom surface and the inner wall surface of the groove 5 can be filled with copper.

  Hereinafter, when the substrate is further laminated, a new insulating layer 10 is disposed on the upper side of the illustrated insulating layer 10 and the above operation is repeated.

  If the height of the copper surface filling the via hole 2, the shallow hole 6 and the groove 5 is made lower than the insulating layer surface 10a, it is ensured when the next insulating layer is disposed by adhesion or the like. Not only can the bonding be performed, but also the unevenness of the surface of the multilayer substrate as a product can be reduced as compared with the case where the height of the copper surface is higher than that of the insulating layer surface 10a.

  Instead of performing the copper plating treatment, the paste may be solidified by heat treatment or the like after the conductive paste is filled into the via hole 2, the groove 5 and the shallow hole 6.

  As described above, according to the present invention, the via hole 2, the shallow hole 6 and the groove 5 are formed in the same process, so that positioning errors hardly occur, and the conductive pattern formed in the groove 5 and the lower layer are formed. The conductive pattern can be reliably connected electrically. Therefore, the reliability of the multilayer substrate as a product can be improved.

  In addition, since a mask for exposure is not required, processing is facilitated and processing efficiency can be improved.

  Here, the via holes, lands, and grooves are processed by laser, but other methods may be used.

It is a figure which shows the manufacture process of the multilayer board | substrate which concerns on this invention. It is a figure which shows the manufacturing process of the conventional multilayer substrate.

Explanation of symbols

2 Via hole 5 Groove 10 Insulating layer 12 Substrate 13 Conductive pattern

Claims (6)

The manufacturing method of a multilayer substrate characterized by forming a multilayer substrate by repeating the process of the following ac.
a. A step of disposing an insulating layer on the surface of the substrate on which the conductive pattern is formed.
b. A step of processing a groove on the surface of the insulating layer disposed and a hole connected to the groove and connected to the conductive pattern in the lower layer;
c. Forming a conductive layer in the processed groove and hole, and connecting the formed conductive layer as a conductive pattern to the underlying conductive pattern;   The method for manufacturing a multilayer substrate according to claim 1, wherein the holes and grooves are processed by a laser.   The method for manufacturing a multilayer substrate according to claim 1, wherein the hole is formed based on an alignment mark formed in the lower substrate.   The method for manufacturing a multilayer substrate according to claim 1, wherein the conductive layer is formed by conductive plating.   The method for manufacturing a multilayer substrate according to claim 1, wherein the conductive layer is formed of a conductive paste.   2. The method for manufacturing a multilayer substrate according to claim 1, further comprising a step of removing a portion of the formed conductive layer higher than the surface of the insulating layer after the step c, and then moving to the step a. .

Images