JPH10200236A - Manufacturing method of wiring board - Google Patents

Manufacturing method of wiring board

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Publication number
JPH10200236A
JPH10200236A JP35906696A JP35906696A JPH10200236A JP H10200236 A JPH10200236 A JP H10200236A JP 35906696 A JP35906696 A JP 35906696A JP 35906696 A JP35906696 A JP 35906696A JP H10200236 A JPH10200236 A JP H10200236A
Authority
JP
Japan
Prior art keywords
insulating film
wiring
insulation film
conductive paste
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35906696A
Other languages
Japanese (ja)
Inventor
Yasuaki Seki
保明 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP35906696A priority Critical patent/JPH10200236A/en
Publication of JPH10200236A publication Critical patent/JPH10200236A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance the plainness of an insulation film to improve the forming accuracy of a fine wiring, by forming trenches for a circuit pattern into the insulation film, using a laser beam machine, applying a conductive paste to the insulation film, heat treating it and polishing insulation film surface. SOLUTION: A laser beam is radiated on the surface of an insulation film 3 above a first layer wiring 2 to bore vias 5, thereby exposing this wiring 2. The beam is radiated on other area of the insulation film 3 for forming a second layer wiring to form openings (trenches) 6. A conductive paste 7 contg. conductor metal particles dispersed in an org. solvent is applied to the surface of the film 3 to fill the paste 7 in the vias 5 and openings 6 and heated in a low pressure atmosphere to gasify the org. solvent in the paste 7 and bake the particles in the paste 7. Excessive baked metal particles on the surface of the film 3 are removed by polishing.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、配線基板の製造方
法に関し、特にその回路パターンの形成方法に関するも
のである。
The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of forming a circuit pattern.

【0002】[0002]

【従来の技術】導電体として導電ペーストを用いて回路
パターンを形成して配線基板を製造する方法は、メッキ
やエッチングいう化学的な処理を伴わないことから廃液
処理等を含めた付帯設備が不必要であるため、配線基板
を安価に製造でき、広く採用されるようになってきてい
る。この導電ペーストを用いた配線基板の製造方法の具
体例としては、周知のスクリーン印刷法によるものの
他、例えば、特開平8−37376号公報に開示された
ものがある。
2. Description of the Related Art A method of manufacturing a wiring board by forming a circuit pattern using a conductive paste as a conductor does not involve chemical treatments such as plating and etching, so that additional equipment including waste liquid treatment is not required. Because of the necessity, a wiring board can be manufactured at low cost and has been widely adopted. Specific examples of a method of manufacturing a wiring board using the conductive paste include a method disclosed in Japanese Patent Application Laid-Open No. 8-37376, in addition to a known screen printing method.

【0003】そこで、同公報に開示されている多層回路
基板の製造方法について図2を参照して説明する。図2
は、同公報に開示されている多層回路基板の製造工程を
示す断面図である。まず、図2(a)に示すように、窒
化アルミニウム、シリコン等よりなる絶縁基板1の上に
一層目の配線2を形成する。その後に、絶縁基板1の上
に20μm程度の厚さの絶縁膜3を形成し、その絶縁膜
3によって一層目の配線2を覆うようにする。絶縁膜3
としてポリイミドを使用する場合には、液状のポリイミ
ドを絶縁基板1の上にスピンコーティングし、これを加
熱固化して絶縁膜3を形成する。
[0003] A method of manufacturing a multilayer circuit board disclosed in the publication will be described with reference to FIG. FIG.
FIG. 2 is a cross-sectional view showing a manufacturing process of the multilayer circuit board disclosed in the publication. First, as shown in FIG. 2A, a first-layer wiring 2 is formed on an insulating substrate 1 made of aluminum nitride, silicon, or the like. Thereafter, an insulating film 3 having a thickness of about 20 μm is formed on the insulating substrate 1, and the first wiring 2 is covered with the insulating film 3. Insulating film 3
When a polyimide is used as the material, a liquid polyimide is spin-coated on the insulating substrate 1, which is heated and solidified to form the insulating film 3.

【0004】この後に、図2(b)に示すように、例え
ば熱可塑性ポリイミドからなる厚さ20μm程度の保護
フィルム4を絶縁膜3の上に貼り付ける。次に、図2
(c)に示すように、一層目の配線2の一部の上にある
保護フィルム4と絶縁膜3にエキシマレーザを照射し、
それらの照射領域に孔を開ける。これによって、絶縁膜
3に20μm×20μmの大きさのビアホール5を形成
する。
Thereafter, as shown in FIG. 2B, a protective film 4 made of, for example, thermoplastic polyimide and having a thickness of about 20 μm is attached on the insulating film 3. Next, FIG.
As shown in (c), the protective film 4 and the insulating film 3 on a part of the first-layer wiring 2 are irradiated with an excimer laser.
Drill holes in those irradiation areas. As a result, a via hole 5 having a size of 20 μm × 20 μm is formed in the insulating film 3.

【0005】続いて、エキシマレーザの照射エネルギー
を低減し、保護フィルム4のうち二層目の配線を形成し
ようとする領域にそのエキシマレーザを照射する。これ
により、保護フィルム4のうち二層目の配線に沿った部
分に開口部(溝)6を形成する。
[0005] Subsequently, the irradiation energy of the excimer laser is reduced, and the region of the protective film 4 where the second-layer wiring is to be formed is irradiated with the excimer laser. Thus, an opening (groove) 6 is formed in a portion of the protective film 4 along the second-layer wiring.

【0006】その後、図2(d)に示すように、金や銀
パラジウムのような導電体の金属超微粒子を有機溶媒に
分散させてなる導電ペースト7を保護フィルム4上に塗
布するとともに、その導電ペースト7をビアホール5と
開口部6の中に充填する。続いて、絶縁基板1を減圧雰
囲気中で300℃程度の温度で加熱して、導電ペースト
7中の有機溶媒を気化させるとともに、導電ペースト7
中の金属超微粒子を焼成させて膜形状にする。
Thereafter, as shown in FIG. 2D, a conductive paste 7 made by dispersing a metal ultrafine particle of a conductor such as gold or silver palladium in an organic solvent is applied on the protective film 4, and The conductive paste 7 is filled into the via hole 5 and the opening 6. Subsequently, the insulating substrate 1 is heated in a reduced-pressure atmosphere at a temperature of about 300 ° C. to vaporize the organic solvent in the conductive paste 7 and
The ultrafine metal particles are fired to form a film.

【0007】次に、保護フィルム4を絶縁膜3から剥が
すと、図2(e)に示すように、絶縁膜3のビアホール
5内にはビア8が形成され、絶縁膜3の上には、金属超
微粒子の焼成物からなる二層目の配線9が形成される。
Next, when the protective film 4 is peeled from the insulating film 3, a via 8 is formed in the via hole 5 of the insulating film 3 as shown in FIG. A second-layer wiring 9 made of a fired metal ultrafine particle is formed.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、この製
造方法では、図2(e)に示すように表面に凹凸ができ
るため、この上に更に絶縁膜を形成して三層目の配線を
形成して多層化を図る場合に、絶縁膜の充分な平面性が
得られず、微細配線を精度良く形成することが困難であ
る。また、この表面に部品を実装しようとした場合に
も、凹凸があるためその実装性が阻害されるという問題
もある。
However, in this manufacturing method, since the surface has irregularities as shown in FIG. 2E, an insulating film is further formed thereon to form a third-layer wiring. In the case of multi-layering, sufficient planarity of the insulating film cannot be obtained, and it is difficult to accurately form fine wiring. In addition, there is also a problem that even when an attempt is made to mount a component on this surface, the unevenness impairs the mountability.

【0009】[0009]

【課題を解決するための手段】本発明は、上記問題点に
鑑みなされたものであり、請求項1に係る発明は、「絶
縁膜にレーザ加工機を用いて回路パターン用の溝を形成
する工程と、導電性物質の超微粒子を溶媒中に分散させ
てなる導電ペーストを該絶縁膜の上に塗布する工程と、
熱処理により塗布された該導電ペーストの該溶媒を除去
するとともに該導電性物質の超微粒子を焼成する工程
と、該絶縁膜の表面を研磨する工程とを有する配線基板
の製造方法。」を提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and the invention according to claim 1 is directed to forming a groove for a circuit pattern in an insulating film by using a laser processing machine. And applying a conductive paste formed by dispersing ultrafine particles of a conductive substance in a solvent on the insulating film,
A method for manufacturing a wiring board, comprising: a step of removing the solvent of the conductive paste applied by heat treatment and baking ultra-fine particles of the conductive substance; and a step of polishing a surface of the insulating film. ”.

【0010】[0010]

【発明の実施の形態】以下、図1を参照して本発明の実
施の形態について説明する。図1は、本発明の配線基板
の製造方法の製造工程を示す断面図である。本発明に係
る配線基板は、例えばエポキシ樹脂製、ガラス繊維強化
エポキシ樹脂製などの平板状の絶縁基板1を基台として
用いる。そして、図1(a)に示すように、この絶縁基
板1の表面上に一層目の配線2を形成する。一層目の配
線2の形成方法の詳細は省略するが、例えば、以下のよ
うにすればよい。すなわち、絶縁基板1の上に予め銅箔
が積層された所謂銅張り積層板を使用し、この銅箔にド
ライフィルムを張り付けてフォトマスクを通して紫外光
で露光し、更に、1%炭酸ソーダ水溶液によって現像し
た後、塩化第二銅水溶液でエッチング処理する。そして
エッチング処理終了後、ドライフィルムを剥離して一層
目の配線2を得る。
Embodiments of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a wiring board according to the present invention. The wiring board according to the present invention uses a flat insulating substrate 1 made of, for example, epoxy resin or glass fiber reinforced epoxy resin as a base. Then, as shown in FIG. 1A, a first-layer wiring 2 is formed on the surface of the insulating substrate 1. Although the details of the method of forming the first-layer wiring 2 are omitted, for example, the following method may be used. That is, a so-called copper-clad laminate in which a copper foil is previously laminated on the insulating substrate 1 is used, a dry film is attached to the copper foil, exposed to ultraviolet light through a photomask, and further exposed to a 1% aqueous sodium carbonate solution. After the development, an etching treatment is performed with an aqueous cupric chloride solution. After completion of the etching process, the dry film is peeled off to obtain the first-layer wiring 2.

【0011】次に、図1(b)に示すように、一層目の
配線2を形成した絶縁基板1の上に絶縁膜3を塗布・形
成する。この絶縁膜3は、酸化剤に対して難溶性を示す
液状の樹脂を主体とし、この樹脂(樹脂液)の中に酸化
剤に対して可溶性を示す無機粉末を分散させて積層して
いる。更に、この樹脂(樹脂液)の中にはこの他、機械
加工時の耐衝撃性を持たせるための応力緩和剤とか、添
加剤などを少量含ませている。
Next, as shown in FIG. 1B, an insulating film 3 is applied and formed on the insulating substrate 1 on which the first-layer wiring 2 is formed. The insulating film 3 is mainly composed of a liquid resin that is hardly soluble in an oxidizing agent, and is formed by dispersing an inorganic powder that is soluble in the oxidizing agent in the resin (resin liquid). In addition, the resin (resin liquid) contains a small amount of a stress relaxing agent or an additive for imparting impact resistance during machining.

【0012】後述するように、絶縁膜3の上に導電ペー
スト7を塗布する前に、絶縁膜3を化学粗化処理するに
際して有害物を使用することなく、無害な過マンガン酸
塩を主とした酸化剤で化学粗化処理ができるよう、絶縁
膜3の材料を予め下記のように選定している。また、絶
縁膜3内の無機粉末は、後述するように酸化剤を用いて
絶縁膜3の表面を粗面化する際に、酸化剤により絶縁体
層3の表面に露出した無機粉末が溶け出して表面アラサ
が形成されるものであり、表面アラサ及びレーザ加工を
加味して無機粉末(炭酸カルシウム)の粒径を15μm
以下(平均粒径:1μm〜5μmで、より好ましくは2
μm〜4μmが良い)、また含有量を15〜35重量部
にそれぞれ設定している。
As will be described later, before applying the conductive paste 7 on the insulating film 3, harmless permanganate is mainly used without using harmful substances when chemically roughening the insulating film 3. The material of the insulating film 3 is selected in advance as follows so that the chemical roughening treatment can be performed with the oxidizing agent. When the surface of the insulating film 3 is roughened by using an oxidizing agent as described later, the inorganic powder exposed on the surface of the insulating layer 3 by the oxidizing agent dissolves out. The surface roughness of the inorganic powder (calcium carbonate) is 15 μm in consideration of the surface roughness and laser processing.
The following (average particle size: 1 μm to 5 μm, more preferably 2 μm
μm to 4 μm is good), and the content is set to 15 to 35 parts by weight, respectively.

【0013】ここで、上記絶縁膜3の材料を更に詳しく
述べると、 .酸化剤に対して難溶性を示す樹脂(樹脂液)とし
て、例えば、 ビスフェノールA系エポキシ樹脂…… 100重量部 硬化剤 …… 10重量部 .酸化剤に対して可溶性を示す無機粉末として、 炭酸カルシウム(平均粒径:1μm〜5μm)……15〜35重量部 .機械加工時の耐衝撃性を持たせる材料として、 応力緩和剤(ポリブタジエン) ……10〜20重量部 .その他の材料として、 添加剤 …… 少量 を用意し、〜に示した複数の上記材料を液状状態で
十分拡散させた後、一層目の配線2を形成した絶縁基板
1の上にカーテンコート法とかスクリーン印刷法などを
用いて50μm〜100μm程度の厚さで塗布して、更
に約150°Cの炉中で40分程度時間かけて熱硬化さ
せることにより、絶縁膜3が形成される。本実施の形態
では75μm程度に厚さに形成してある。
Here, the material of the insulating film 3 will be described in more detail. Examples of the resin (resin liquid) having low solubility in an oxidizing agent include, for example, bisphenol A-based epoxy resin 100 parts by weight Curing agent 10 parts by weight. As an inorganic powder that is soluble in an oxidizing agent, calcium carbonate (average particle size: 1 μm to 5 μm)... 15 to 35 parts by weight. As a material for imparting impact resistance during machining, a stress relieving agent (polybutadiene): 10 to 20 parts by weight. As other materials, a small amount of an additive is prepared, and after a plurality of the above-mentioned materials are sufficiently diffused in a liquid state, a curtain coating method or the like is formed on the insulating substrate 1 on which the first-layer wiring 2 is formed. The insulating film 3 is formed by applying a thickness of about 50 μm to 100 μm using a screen printing method or the like, and further thermally curing it in a furnace at about 150 ° C. for about 40 minutes. In this embodiment, the thickness is set to about 75 μm.

【0014】次に、図1(c)に示すように、絶縁基板
1に形成した一層目の配線2と、絶縁膜3の上に形成す
る二層目の配線9とを電気的に接続するために、一層目
の配線2の上方で絶縁膜3の表面側の所定の位置からレ
ーザ光を照射して、ビアホール5を穿設し、一層目の配
線2を露出させる。また、この時同様に、絶縁膜3上の
その他の二層目の配線を形成すべき位置にもレーザ光を
照射して開口部(溝)6を形成する。一般にレーザ光は
無機物には余り適さないといわれているが、ここでは、
絶縁膜3内に含有した炭酸カルシウムの粉末の粒径及び
含有量を上記したように設定し、下記に示す条件下でレ
ーザ光を照射することによりビアホール5を容易に穿設
できる。
Next, as shown in FIG. 1C, the first layer wiring 2 formed on the insulating substrate 1 and the second layer wiring 9 formed on the insulating film 3 are electrically connected. To this end, a laser beam is irradiated from a predetermined position on the surface side of the insulating film 3 above the first-layer wiring 2, a via hole 5 is formed, and the first-layer wiring 2 is exposed. Similarly, at this time, the openings (grooves) 6 are formed by irradiating the laser light to other positions on the insulating film 3 where the second-layer wirings are to be formed. It is generally said that laser light is not very suitable for inorganic substances, but here,
By setting the particle size and content of the calcium carbonate powder contained in the insulating film 3 as described above, and irradiating a laser beam under the following conditions, the via hole 5 can be easily formed.

【0015】また、ビアホール5の断面形状は、一層目
の配線2側のランドが細径で、二層目の配線9側のラン
ドが太径のテーパ形状となるようにし、後述するように
ビアホール5の中に導電ペースト7を充填し易くしてい
る。この点は、開口部6も同様である。このテーパ形状
は、レーザ光の焦点位置の制御、パルス幅の制御、レー
ザ光のエネルギー密度の制御、パルスエネルギーの制御
等により実現することができる。
The cross-sectional shape of the via hole 5 is such that the land on the wiring 2 side of the first layer has a small diameter and the land on the wiring 9 side of the second layer has a tapered shape with a large diameter. 5 is easily filled with the conductive paste 7. This is the same for the opening 6. This tapered shape can be realized by controlling the focal position of the laser light, controlling the pulse width, controlling the energy density of the laser light, controlling the pulse energy, and the like.

【0016】配線基板加工用のレーザ光としては、種々
提案されているが、絶縁膜3にビアホール5や開口部6
を穿設する場合のレーザ光としては、短パルスCO2レ
ーザと、KrFレーザとが使用可能である。実用的には
レーザ光源の入手の容易性、加工時間の迅速性などから
短パルスCO2レーザが最適である。ここで、レーザ光
をパルス的に照射する理由は、絶縁膜3に対して過剰な
熱エネルギーを加えることなく、絶縁膜3の熱変形を防
止できる程度の熱エネルギーを加えるためであり、短パ
ルスCO2レーザ光のパルス間隔は例えば0.003秒
〜0.02秒程度に設定している。
Various laser beams for processing a wiring board have been proposed, but a via hole 5 and an opening 6 are formed in the insulating film 3.
As a laser beam for forming a hole, a short pulse CO2 laser and a KrF laser can be used. Practically, a short-pulse CO2 laser is optimal because of the availability of a laser light source and the quick processing time. Here, the reason for irradiating the laser light in a pulsed manner is to apply thermal energy to the insulating film 3 without applying excessive thermal energy to the insulating film 3 to prevent thermal deformation of the insulating film 3. The pulse interval of the CO2 laser beam is set to, for example, about 0.003 to 0.02 seconds.

【0017】また、絶縁膜3にビアホール5や開口部6
を穿設するレーザ加工法には、コンフォーマルマスク
法、マスクイメージング法、コンタクトマスク法、ダイ
レクトイメージング法等があるが、マスクイメージング
法とダイレクトイメージング法とが好適である。
Also, via holes 5 and openings 6 are formed in insulating film 3.
There are a conformal mask method, a mask imaging method, a contact mask method, a direct imaging method, and the like as a laser processing method for forming a hole, and the mask imaging method and the direct imaging method are preferable.

【0018】このようにして、ビアホール5や開口部6
を穿設した後、絶縁基板1の上に形成した絶縁膜3の表
面、ビアホール5の内壁、開口部6の内壁を粗面化する
ために、過マンガン酸塩を主とした酸化剤を用いて酸化
剤処理(化学粗化処理)を施す。
Thus, the via hole 5 and the opening 6
Then, in order to roughen the surface of the insulating film 3 formed on the insulating substrate 1, the inner wall of the via hole 5, and the inner wall of the opening 6, an oxidizing agent mainly containing permanganate is used. Oxidizing agent treatment (chemical roughening treatment).

【0019】ここで、酸化剤処理として、第1工程の潤
滑化に、カセイソーダ、溶剤、他、の水溶液 第2工程の粗面化に、過マンガン酸カリウム(過マンガ
ン酸塩)、カセイソーダ、他、の水溶液 第3工程の酸洗に、硫酸、他、の水溶液 を用いている。
Here, as the oxidizing agent treatment, an aqueous solution of caustic soda, a solvent, etc. is used for lubrication in the first step, and potassium permanganate (permanganate), caustic soda, etc. An aqueous solution of sulfuric acid or another is used in the third step of pickling.

【0020】とくに、酸化剤処理時(化学粗化処理時)
に、先に説明したように、絶縁膜3の表面、ビアホール
5の内壁、開口部6の内壁の一部には、酸化剤に対して
難溶性を示す樹脂と、酸化剤に対して可溶性を示す炭酸
カルシウムとが露出しているものの、露出した炭酸カル
シウムだけが過マンガン酸カリウム(過マンガン酸塩)
により容易に溶け出して粗面化される。
Particularly, at the time of oxidizing agent treatment (at the time of chemical roughening treatment)
As described above, the surface of the insulating film 3, the inner wall of the via hole 5, and a part of the inner wall of the opening 6 are made of a resin which is hardly soluble in the oxidizing agent and a resin which is slightly soluble in the oxidizing agent. Although the calcium carbonate shown is exposed, only the exposed calcium carbonate is potassium permanganate (permanganate)
It is easily melted and roughened.

【0021】上記過マンガン酸カリウム(過マンガン酸
塩)は、無害な酸化剤であり、酸化剤処理時(化学粗化
処理時)に何等の支障もなく、且つ、汎用性のある処理
システムを用いることができると共に、廃水処理に気を
使う必要もないことから環境汚染の問題を起こすことも
なく、ランニングコストが小となる。
The above-mentioned potassium permanganate (permanganate) is a harmless oxidizing agent, and has no trouble at the time of oxidizing agent treatment (at the time of chemical roughening treatment) and has a versatile treatment system. It can be used, does not need to pay attention to wastewater treatment, does not cause environmental pollution problems, and reduces running costs.

【0022】次に、図1(d)に示すように、金や銀パ
ラジウムのような導電体の金属超微粒子を有機溶媒に分
散させてなる導電ペースト7を絶縁膜3の表面に塗布
し、その導電ペースト7をビアホール5と開口部6の中
に充填する。続いて、これを減圧雰囲気中で300℃程
度の温度で加熱して、導電ペースト7中の有機溶媒を気
化させるとともに、導電ペースト7中の金属超微粒子を
焼成させる。
Next, as shown in FIG. 1D, a conductive paste 7 obtained by dispersing ultrafine metal particles of a conductor such as gold or silver palladium in an organic solvent is applied to the surface of the insulating film 3, The conductive paste 7 is filled into the via hole 5 and the opening 6. Subsequently, this is heated at a temperature of about 300 ° C. in a reduced-pressure atmosphere to evaporate the organic solvent in the conductive paste 7 and bake the ultrafine metal particles in the conductive paste 7.

【0023】次に、絶縁膜3の表面の余剰の焼成された
金属超微粒子を研磨して取り除く。この研磨は、例えば
バフ掛けによって行う。これにより、図1(e)に示す
ような配線基板を得る。
Next, excessive burned metal ultrafine particles on the surface of the insulating film 3 are removed by polishing. This polishing is performed, for example, by buffing. Thereby, a wiring board as shown in FIG. 1E is obtained.

【0024】以上説明した本発明の実施の形態に係る配
線基板の製造方法によれば、レーザを用いて、絶縁膜3
上に二層目の配線9やビア8を形成すべき開口部6又は
ビアホール5を穿設するため、これらの極めて高い位置
精度が実現でき、高密度な配線パターンを実現すること
ができる。具体的には、従来の例えばスクリーン印刷で
は、配線のパターン幅が250μm、パターン間の間隔
が500μm程度が限界であったの対し、本実施の形態
に係る製造方法によれば、配線のパターン幅は100μ
m、パターン間の間隔も100μmを実現することがで
きる。
According to the method of manufacturing a wiring board according to the embodiment of the present invention described above, the insulating film 3 is formed by using a laser.
Since the openings 6 or via holes 5 in which the second-layer wirings 9 and vias 8 are to be formed are formed thereon, extremely high positional accuracy can be realized, and a high-density wiring pattern can be realized. Specifically, in the conventional screen printing, for example, the wiring pattern width is limited to about 250 μm and the interval between the patterns is limited to about 500 μm, whereas according to the manufacturing method according to the present embodiment, the wiring pattern width is limited. Is 100μ
m, and the interval between patterns can be 100 μm.

【0025】また、ビアホール5と開口部6に導電ペー
スト7を充填し、焼成された余剰の金属超微粒子を研磨
して除去するため、その表面の平面度は極めて高いもの
とすることができる。この点についても例えば従来のス
クリーン印刷と比較するなら、スクリーン印刷では、平
坦度が10〜40μmであるのに対し、本実施の形態に
係る製造方法では10μm以下を実現することができ
る。
Further, since the conductive paste 7 is filled in the via hole 5 and the opening 6 and the burned excessive metal ultrafine particles are removed by polishing, the surface flatness can be made extremely high. Also in this regard, for example, when compared with the conventional screen printing, the flatness is 10 to 40 μm in the screen printing, whereas the flatness is 10 μm or less in the manufacturing method according to the present embodiment.

【0026】このため、図1(e)の絶縁膜3の上に更
に他の絶縁膜を形成し図1(c)以下のプロセスを繰り
返して多層化を図る場合にも各絶縁膜は充分な平坦度が
得られ高精度な微細配線の形成が可能となるとともに、
絶縁膜3上への部品の実装性も良好なものとなる。な
お、ここで説明した実施の形態では、一層目の配線2は
絶縁基板1上に積層された銅箔をエッチングして形成す
る例について説明したが、銅箔が積層されていない絶縁
基板1上にレーザにより開口部(溝)6を直接形成し、
これに導電ペーストを充填して二層目の配線9と同様の
処理を行うようにしてもよい。
For this reason, even when another insulating film is further formed on the insulating film 3 of FIG. 1E and the processes shown in FIG. Flatness is obtained and high-precision fine wiring can be formed.
The mountability of components on the insulating film 3 is also improved. In the embodiment described above, an example in which the first-layer wiring 2 is formed by etching a copper foil laminated on the insulating substrate 1 has been described, but the wiring 2 on the insulating substrate 1 on which no copper foil is laminated is described. The opening (groove) 6 is formed directly by laser at
This may be filled with a conductive paste to perform the same processing as that of the second-layer wiring 9.

【0027】また、ここで説明した実施の形態では、絶
縁基板1の片面に一層目の配線2と二層目の配線9を形
成したが、本発明は、これに限られることなく、絶縁基
板1の両面に各配線層を形成するようにしてもよいこと
は勿論である。
In the embodiment described here, the first-layer wiring 2 and the second-layer wiring 9 are formed on one surface of the insulating substrate 1, but the present invention is not limited to this. Needless to say, each wiring layer may be formed on both surfaces of one.

【0028】[0028]

【発明の効果】以上説明したように、本発明の配線基板
の製造方法によれば、レーザを用いて、絶縁膜上に配線
やビア等の回路パターン用の溝を穿設するため、これら
の極めて高い位置精度が実現でき、高密度な微細回路パ
ターンを実現することができ、パターンの幅や厚みが一
定になるため導体抵抗も安定する。
As described above, according to the method of manufacturing a wiring board of the present invention, grooves for wiring and circuit patterns such as vias are formed on an insulating film by using a laser. Extremely high positional accuracy can be realized, a high-density fine circuit pattern can be realized, and the width and thickness of the pattern become constant, so that the conductor resistance becomes stable.

【0029】また、これらの溝に導電ペーストを充填
し、熱処理した後、絶縁膜の表面を研磨して、余剰の金
属超微粒子を除去するようにしたため、その表面の平面
度を極めて高いものとすることができる。このため、基
板の多層化に際しても、高精度な微細配線の形成が可能
となるとともに、絶縁膜上への部品の実装性も良好なも
のとなる。
Further, after these grooves are filled with a conductive paste and heat-treated, the surface of the insulating film is polished to remove excess metal ultrafine particles, so that the flatness of the surface is extremely high. can do. For this reason, even when the substrate is multi-layered, highly accurate fine wiring can be formed, and the mountability of components on the insulating film is also improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の製造方法の製造工程を示す
断面図である。
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a wiring board according to the present invention.

【図2】特開平8−37376号公報に開示された多層
回路基板の製造工程を示す断面図である。
FIG. 2 is a sectional view showing a manufacturing process of a multilayer circuit board disclosed in Japanese Patent Application Laid-Open No. 8-37376.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 一層目の配線 3 絶縁膜 4 保護フィルム 5 ビアホール 6 開口部 7 導電ペースト 8 ビア 9 二層目の配線 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 First-layer wiring 3 Insulating film 4 Protective film 5 Via hole 6 Opening 7 Conductive paste 8 Via 9 Second-layer wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁膜にレーザ加工機を用いて回路パター
ン用の溝を形成する工程と、導電性物質の超微粒子を溶
媒中に分散させてなる導電ペーストを該絶縁膜の上に塗
布する工程と、熱処理により塗布された該導電ペースト
の該溶媒を除去するとともに該導電性物質の超微粒子を
焼成する工程と、該絶縁膜の表面を研磨する工程とを有
する配線基板の製造方法。
1. A step of forming a groove for a circuit pattern in an insulating film using a laser beam machine, and applying a conductive paste obtained by dispersing ultrafine particles of a conductive substance in a solvent on the insulating film. A method for manufacturing a wiring board, comprising: a step of removing the solvent of the conductive paste applied by heat treatment, baking ultra-fine particles of the conductive substance, and polishing a surface of the insulating film.
JP35906696A 1996-12-27 1996-12-27 Manufacturing method of wiring board Pending JPH10200236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35906696A JPH10200236A (en) 1996-12-27 1996-12-27 Manufacturing method of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35906696A JPH10200236A (en) 1996-12-27 1996-12-27 Manufacturing method of wiring board

Publications (1)

Publication Number Publication Date
JPH10200236A true JPH10200236A (en) 1998-07-31

Family

ID=18462565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35906696A Pending JPH10200236A (en) 1996-12-27 1996-12-27 Manufacturing method of wiring board

Country Status (1)

Country Link
JP (1) JPH10200236A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001070435A1 (en) * 2000-03-22 2001-09-27 Ebara Corporation Ultra fine composite metal particles
JP2003008178A (en) * 2001-06-25 2003-01-10 Sony Corp Manufacturing method of printed wiring board
JP2004253605A (en) * 2003-02-20 2004-09-09 Sumitomo Heavy Ind Ltd Printed wiring board and method for manufacturing it
JP2006024672A (en) * 2004-07-07 2006-01-26 Asahi Kasei Corp Manufacturing method for wiring circuit board
JP2006339365A (en) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd Wiring board, its manufacturing method, manufacturing method of multilayer laminated wiring board and forming method of via hole
JP2007036063A (en) * 2005-07-28 2007-02-08 Hitachi Via Mechanics Ltd Manufacturing method of multilayer substrate
JP2009081194A (en) * 2007-09-25 2009-04-16 Sanyo Electric Co Ltd Light emitting module and its manufacturing method
WO2009119680A1 (en) * 2008-03-25 2009-10-01 イビデン株式会社 Printed wiring board and method for producing the same
US20110097553A1 (en) * 2009-10-23 2011-04-28 Jong Kuk Hong Trench substrate and method of fabricating the same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6743395B2 (en) 2000-03-22 2004-06-01 Ebara Corporation Composite metallic ultrafine particles and process for producing the same
US6871773B2 (en) 2000-03-22 2005-03-29 Ebara Corp. Composite metallic ultrafine particles and process for producing the same
WO2001070435A1 (en) * 2000-03-22 2001-09-27 Ebara Corporation Ultra fine composite metal particles
JP2003008178A (en) * 2001-06-25 2003-01-10 Sony Corp Manufacturing method of printed wiring board
JP2004253605A (en) * 2003-02-20 2004-09-09 Sumitomo Heavy Ind Ltd Printed wiring board and method for manufacturing it
JP4651319B2 (en) * 2004-07-07 2011-03-16 旭化成イーマテリアルズ株式会社 Method for manufacturing printed circuit board
JP2006024672A (en) * 2004-07-07 2006-01-26 Asahi Kasei Corp Manufacturing method for wiring circuit board
JP2006339365A (en) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd Wiring board, its manufacturing method, manufacturing method of multilayer laminated wiring board and forming method of via hole
JP2007036063A (en) * 2005-07-28 2007-02-08 Hitachi Via Mechanics Ltd Manufacturing method of multilayer substrate
JP2009081194A (en) * 2007-09-25 2009-04-16 Sanyo Electric Co Ltd Light emitting module and its manufacturing method
WO2009119680A1 (en) * 2008-03-25 2009-10-01 イビデン株式会社 Printed wiring board and method for producing the same
KR101160498B1 (en) * 2008-03-25 2012-06-28 이비덴 가부시키가이샤 Printed wiring board and method for producing the same
US8263878B2 (en) 2008-03-25 2012-09-11 Ibiden Co., Ltd. Printed wiring board
JP5238801B2 (en) * 2008-03-25 2013-07-17 イビデン株式会社 Printed wiring board and manufacturing method thereof
US20110097553A1 (en) * 2009-10-23 2011-04-28 Jong Kuk Hong Trench substrate and method of fabricating the same
JP2011091351A (en) * 2009-10-23 2011-05-06 Samsung Electro-Mechanics Co Ltd Trench substrate, and method of manufacturing the same

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