JP2010225973A - Manufacturing method of multilayer circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily manufacture a wiring pattern of each layer of a multilayer circuit board with sufficient positional accuracy. <P>SOLUTION: The manufacturing method of the multilayer circuit board includes (A) a process to form at least one alignment mark for forming a via hole for connecting electrically a laminated body and an inner layer substrate simultaneously with the formation of a conductor wiring circuit of an inner layer material, (B) a process to laminate a laminated body so as to expose the alignment mark when laminating the laminated body on the conductor wiring circuit, (C) a process to form the via hole in the laminated body using at least one of the alignment mark formed at the inner layer material as alignment, (D) a process to form the conductor wiring circuit using at least one via hole formed at the laminated body as the alignment, and furthermore, simultaneously with the formation of the conductor circuit to form at least one alignment mark for the formation off the via hole on the inner layer substrate in order to electrically be connect with the laminated body further laminated on the conductor wiring circuit, and (E) a process to repeat the process (B)-(D) until reaching the required number of wiring layers. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer circuit board in which a multilayer body including an insulating layer made of a resin such as polyimide and a conductor layer is bonded, and a method for manufacturing a semiconductor package using the multilayer circuit board.

  In recent years, along with demands for downsizing, lightening, and high functionality of electronic devices, high density integration of semiconductors and high speed operation clocks are progressing. On the other hand, in semiconductor packages and printed wiring boards that mount semiconductors, high density, miniaturization, high speed, etc. are desired. Miniaturization of wiring circuit patterns, lightening of core substrates, and low dielectric constant of insulating layers Development such as rate improvement is progressing. For example, in a wiring circuit, a wiring width of 20 μm or less is possible by shifting from a subtractive method to a semi-additive method. Thus, with the progress of semiconductors, circuit boards are being developed for higher density, multilayers, and higher transmission.

  In addition, as a multilayer technology for such a circuit board, a so-called build-up method is generally known, in which an insulating resin layer and a conductor layer are alternately laminated as outer layers on the inner layer core substrate one by one, and blind vias are used. This is a technique for electrically connecting an inner layer circuit pattern and an outer layer circuit pattern. In this case, the method for forming the via hole can be broadly divided into two methods: a method of forming a via hole using a laser in a non-photosensitive insulating resin and a photo via using a photosensitive insulating resin.

  In such a build-up method, it is necessary to accurately align the via hole in the outer layer with respect to the land portion of the circuit pattern in the inner layer. In particular, it is clear that the alignment accuracy becomes increasingly severe as the density increases. Therefore, several inventions and devices have been disclosed in order to perform the above alignment with higher accuracy.

For example, as an example, the outer layer is laminated in the order of the insulating layer and the conductor layer so that the alignment mark formed on the inner layer circuit board is not covered, and the via hole and the outer layer circuit pattern are formed based on the alignment mark formed on the inner layer circuit board. A manufacturing method of a build-up multilayer circuit board that is easy to form is disclosed (see, for example, Patent Document 1, “Manufacturing method of multilayer circuit wiring board”).
According to this, a through-hole punched out by a mold is formed at the end of the inner layer circuit board, via holes and conductor circuit patterns to be produced on the inner layer board, and further on the laminated body sequentially stacked on the front and back of the inner layer circuit board A through hole is used as an alignment mark for forming a via hole and a conductor circuit pattern to be manufactured. According to the above method, the circuit density can be increased, accumulation of position errors does not occur, the alignment accuracy between the inner layer circuit wiring and the outer layer circuit wiring is increased, and good interlayer connection is possible (Patent Document 1). ).

Further, as another method, the alignment of the outer via blind via hole and the inner bottom land is named as “method of forming via hole in circuit board manufacturing substrate, circuit board and multilayer wiring board and circuit board manufacturing substrate”. A via hole forming method for manufacturing a circuit board by a build-up method that can be performed with high accuracy has been proposed.
According to this, the alignment mark and the auxiliary alignment mark are formed on the inner layer circuit board, and the insulating layer and the conductor layer are laminated so that the auxiliary alignment mark is exposed. Thereafter, the auxiliary alignment mark is used, and the insulating layer and the conductor layer above the alignment mark are removed by laser light. Since the alignment mark is formed in the conductor circuit formation region, the alignment reference is close to that of the via hole, so that it is possible to form a via hole with a better position system (Patent Document 2).

As another method, a build-up method capable of accurately forming the position of the circuit pattern to be laminated with respect to the inner layer circuit board under the name of “method for manufacturing multilayer wiring board and semiconductor package and long wiring board”. A method for manufacturing a multilayer wiring board according to the above has been proposed.
According to this, after forming a 1st alignment mark with a circuit pattern in the 1st laminated body, and laminating | stacking a 2nd laminated body so that 1st alignment may be exposed to a 1st laminated body, 1st The second via alignment and via hole are formed on the second stacked body using the above alignment, and the circuit pattern is formed on the second stacked body using the second alignment. By using the alignment mark formed in the lower layer by the above method, an upper layer via hole is formed, and the upper layer circuit pattern is formed using the via hole as an alignment mark. The position of the circuit pattern of the layer can be formed with high accuracy (Patent Document 3).

JP 2004-71749 A JP 2003-243781 A JP 2007-299842 A

However, in the invention disclosed in Patent Document 1 described above, since the through holes prepared in advance in the inner layer base material are used as alignment marks for forming circuit patterns and via holes every time they are stacked, The number of times exposed to etching increases. For this reason, the copper foil at the edge portion of the through hole is excessively etched, and the shape collapses, so that erroneous recognition occurs at the time of alignment recognition in the processing apparatus, and there is a problem that the positional accuracy is lowered.
In the invention disclosed in Patent Document 2, since the alignment mark is once covered with the insulating layer and the conductor layer, the manufacturing process is complicated by adding a step of removing the upper portion by laser light and exposing the alignment mark. There was a problem.

  In addition, in the invention disclosed in Patent Document 3, in order to perform the stacking so as to expose the alignment mark formed in the lower layer, the width of the stack (in the direction perpendicular to the transport direction) increases as the number of stacks increases. It is necessary to gradually reduce the length). For this reason, the effective area that can be used as a multilayer circuit board becomes narrower as the number of layers increases, and there are problems in that the number of layers is limited and productivity is reduced.

  The present invention has been made in view of the above points, and in a multilayer circuit board that has been increased in the number of layers, it is a laminate that is stacked on an inner circuit board using alignment marks that are produced on the inner circuit board. The upper via hole and the lower layer can be aligned with a laminated body having the same width even when the body (upper layer) via hole and the inner layer (lower layer) circuit pattern land portion can be aligned with high accuracy. An object of the present invention is to provide a method for manufacturing a high-layer circuit board capable of maintaining a high alignment accuracy with the bottom land.

In order to solve the above-mentioned problems, a method for manufacturing a multilayer circuit board according to the present invention is an inner layer in which conductors are electrically connected by filled vias in an inner layer material having conductors on both sides of an insulating layer, and a conductor wiring circuit is formed from the conductors. A method for producing a multilayer circuit board comprising: laminating a laminate including an insulating layer and a conductor layer on one or both sides of an inner layer substrate on a substrate; and forming via holes and conductor wiring circuits on the laminate, It includes the following steps.
A. Forming at least one alignment mark for forming a via hole for electrically connecting the laminate and the inner layer material simultaneously with the formation of the conductor wiring circuit of the inner layer material;
B. A step of laminating the laminate so that the alignment mark is exposed when the laminate is laminated on the conductor wiring circuit;
C. Using at least one of the alignment marks formed on the inner layer material as an alignment, and forming a via hole in the laminate.
D. At least one of the via holes formed in the laminate is used as an alignment to form a conductor wiring circuit, and at the same time as the conductor wiring circuit is formed, it is electrically connected to the laminate further laminated on the conductor wiring circuit. Forming at least one alignment mark for forming a via hole on the inner layer substrate.
E. A step of repeating the steps B to D until the required number of wiring layers is obtained.
According to such a method of manufacturing a multilayer circuit board, the first alignment mark used for via-hole processing on the first laminate is formed on the inner layer base material simultaneously with the formation of the wiring circuit pattern on the inner layer base material. Therefore, the circuit pattern formed on the inner layer substrate and the via hole on the first stacked body can be manufactured with good positional accuracy. Further, since the wiring circuit pattern is formed in the Nth (N = natural number) stacked body, the N + 1th alignment mark used for via-hole processing on the N + 1th stacked body is formed on the inner layer substrate. The circuit pattern formed in the Nth stacked body and the via hole on the (N + 1) th stacked body can be manufactured with good positional accuracy.
Also, in such a method for manufacturing a multilayer circuit board, it is possible to accurately form a via hole in the multilayer body by exposing the alignment pattern mark on the inner layer board when the multilayer body is laminated on the conductor wiring circuit. It is said. Further, when a laminate is further laminated on the conductor wiring circuit formed on the laminate, a laminate having a width equal to or greater than that of the previous laminate can be used.
Further, in such a method for manufacturing a multilayer circuit board, since a conductor wiring circuit is formed using at least one via hole formed in the laminated body as an alignment mark, a conductor wiring circuit is formed in accordance with the position of the via hole. I can do it.

Further, in the present invention, when forming the conductor wiring circuit of the inner layer substrate, when the laminated body laminated on the inner layer substrate is the first laminated body, the second laminated layer laminated on the first laminated body. The conductor layer in the region where the alignment mark for via hole formation of the outermost layer stack is disposed from the body, the insulating layer is exposed, and the conductor wiring circuit of the Nth (N = natural number) layer stack Is formed, the conductor layer in the region where the alignment mark for via hole formation of the outermost layer stack is disposed is removed in advance from the (N + 2) th layer stack, and the insulating layer is exposed.
This is because the region of the inner layer substrate where the second to outermost alignment marks are arranged is frequently exposed to the plating process when the filled via is formed, thereby preventing the conductor thickness from becoming unstable.
In such a method of manufacturing a multilayer circuit board, the second to outermost alignment marks formed on the inner layer board can be formed, the mark shape is prevented from being deformed, and the second or more stacked layers are formed. When the via hole processing is performed on the body, the alignment mark can be recognized with high accuracy.

  Further, in the present invention, the inner layer substrate and the laminate are supplied by a tape-like long substrate, and the laminate is sequentially laminated on the inner substrate by a reel-to-reel method. This is a manufacturing method.

  According to the present invention, in the process of manufacturing a multilayer circuit board, the alignment marks formed on the inner layer substrate are used for positioning of via holes on the stacked body sequentially stacked on the inner layer substrate. It becomes possible to produce a multi-layer circuit board by sequentially laminating the base materials. Further, since the alignment mark is produced for each layer, the positions of via holes and conductor wiring circuit patterns produced in each layer and the positions of upper via holes with respect to the lower wiring circuit patterns can be formed with high accuracy.

It is a top view which shows the elongate circuit board based on embodiment of this invention. FIG. 2 is a YY sectional view of FIG. 1 showing a configuration of the long circuit board shown in FIG. 1. (A)-(d) is a figure which shows the manufacturing method of a multilayer circuit board, and is a top view explaining the process of forming an alignment mark in an inner layer board | substrate. It is a top view of an elongate wiring board, and is a top view which shows an example of the manufacturing method considered when utilizing this invention. (A) to (e) are cross-sectional views for explaining a method of manufacturing a multilayer circuit board. (F) to (h) are cross-sectional views illustrating a method for manufacturing a multilayer circuit board. (I)-(j) is sectional drawing explaining the manufacturing method of a multilayer circuit board.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to FIGS.
FIG. 1 is a plan view showing a state in which a sheet-like second laminate is laminated on a sheet-like inner layer base material in a long circuit board. In addition, the X direction and the Y direction orthogonal to each other indicated by arrows in the figure are the length direction of the long circuit board (lateral direction in the figure) and the width direction of the long wiring board (up and down direction in the figure), respectively. To do. 2 is a cross-sectional view (cross-sectional view taken along line YY in FIG. 1) when the long circuit board of FIG. 1 is cut in the width direction.

First, as shown in FIG. 2, the inner layer base material A is formed by forming conductor layers 2a and 2b on both surfaces of a flexible insulating layer 3, and conductor wiring circuit patterns 2a and 2b are formed. Has been. The circuit patterns 2 a and 2 b are electrically connected by the via hole 4. Holes 1a and 1b penetrating from the front surface to the back surface are formed at both ends in the Y direction of the inner layer base material A, and penetrate at least on the line extending in the Y direction through the center of the multilayer circuit board 22 in the X direction. A hole 1a is formed.
For example, in FIG. 1, the through hole 1 a is formed on a line extending in the Y direction through the center of the multilayer circuit board 22 in the Y direction, and the through hole 1 b is formed at a point-symmetrical position with respect to the center of the multilayer circuit board 22. Has been.
The alignment mark 6a is formed at a point-symmetrical position with respect to the center of the multilayer circuit board 22 when the circuit pattern of the inner layer base material A is formed. Further, the alignment mark 11a is formed at a point-symmetrical position with respect to the center of the multilayer circuit board 22 when the circuit pattern on the first stacked body Ba is formed. The lower surface side alignments 6b and 11b are formed in the same manner as the upper surface side described above.

  The laminates Ba and Bb laminated on both surfaces of the inner layer base material A are composed of flexible insulating layers 7a and 7b and conductor layers 8a and 8b, and the conductor layers 8a and 8b are formed with circuit patterns. ing. In addition, via holes 9a and 9b are formed in the stacked bodies Ba and Bb, respectively, and the holes are filled with metal. The circuit patterns 8a and 8b and the circuit patterns 2a and 2b of the inner layer base material A are electrically connected to each other. Is made. The alignment marks 10a and 10b on the front and back laminates Ba and Bb are formed by penetrating the laminates Ba and Bb at the same time as forming the via holes 9a and 9b, and passing through the center in the X direction of the multilayer circuit board 22 in the Y direction. It is formed on a line extending to In addition, the alignment marks 11a and 11b are formed by etching the conductor layers 2a and 2b of the inner layer base material A in advance at a point-symmetrical position with respect to the center of the multilayer circuit board 22 when the circuit patterns of the stacked bodies Ba and Bb are formed. It is formed on the regions 5a and 5b from which the insulating layer 3 has been removed.

Laminated bodies Ca and Cb respectively laminated on the laminated bodies Ba and Bb are composed of flexible insulating layers 12a and 12b and conductor layers 13a and 13b, and circuit patterns are formed on the conductor layers 13a and 13b. ing. In addition, via holes 14a and 14b are formed in the stacked bodies Ca and Cb, and the metal is filled in the holes. The circuit patterns 13a and 13b and the circuit patterns 8a and 8b of the stacked bodies Ba and Bb are electrically connected. Has been.
The alignment marks 15a and 15b of the laminated bodies Ca and Cb on the front and back sides are formed by penetrating the laminated bodies Ca and Cb at the same time as forming the via holes 14a and 14b, and passing through the center in the X direction of the multilayer circuit board 22 in the Y direction. It is formed on a line extending to In addition, the alignment marks 16a and 16b are preliminarily etched on the conductor layers 2a and 2b of the inner layer base material A in a point-symmetrical position with respect to the center of the multilayer circuit board 22 when the circuit patterns of the laminated bodies Ca and Cb are formed. It is formed on the regions 5a and 5b where the insulating layer 3 is removed and exposed.

The stacked bodies Da and Db stacked on the stacked bodies Ca and Cb respectively include flexible insulating layers 17a and 17b and conductor layers 18a and 18b. The conductor layers 18a and 18b have circuit patterns formed thereon. ing. The stacked bodies Da and Db are formed with via holes 19a and 19b, and the holes are filled with metal. The circuit patterns 19a and 19b and the circuit patterns 13a and 13b of the stacked bodies Ca and Cb are electrically connected. Has been.
The alignment marks 20a and 20b of the laminated bodies Da and Db on both sides are formed by penetrating the laminated bodies Da and Db at the same time as forming the via holes 19a and 19b, and passing through the center in the X direction of the multilayer circuit board 22 in the Y direction. It is formed on a line extending to
In FIG. 2, circuit patterns 2a and 2b of the inner layer substrate, circuit patterns 9a and 9b of the stacked bodies Ba and Bb, circuit patterns 13a and 13b of the stacked bodies Ca and Cb, and circuit patterns 18a and 18b of the stacked bodies Da and Db. May be formed in different patterns.

  The multilayer circuit board 22 is a rectangular area inside the alignment marks 20a and 20b formed on the innermost side in the Y direction, and is used by being separated from a long circuit board.

Next, a method for manufacturing the multilayer circuit board 22 will be described.
First, the inner layer substrate A is processed. As shown in FIG. 3, alignment marks for forming circuit patterns 2a and 2b on both surfaces of the inner substrate A are prepared. A through hole 1a penetrating the inner substrate A is formed by punching using a mold, and this is used as an alignment mark. At the same time, the through-hole 1b is formed and used as an alignment mark for forming the via hole 4 that conducts the wiring circuit pattern on both surfaces of the inner layer substrate A.

  Via holes 4 are formed in the inner layer substrate A using the through holes 1b, metal is filled in the via holes 4 by plating, and both surfaces are electrically connected, and then circuit patterns 2a and 2b are formed using the through holes 1a. At the same time, the regions 5a and 5b where the alignment marks 11a and 11b used when processing the stacked bodies Ca and Cb and the alignment marks 16a and 16b used when processing the stacked bodies Da and Db are formed on both surfaces of the inner substrate A are insulated. The conductor layers 2a and 2b are removed so that the layer 3 is exposed. This is performed in order to prevent the shape of the alignment marks 11a, 11b, 16a, and 16b to be formed later from collapsing.

  After the via hole processing and the pattern circuit formation of the inner layer substrate A are completed, the laminated bodies Ba and Bb composed of the insulating layer 7 and the conductor layer 8 are respectively exposed so that the alignment marks 6a and 6b formed on the inner layer base material A are exposed. Laminate on the front and back. Via holes 9a and 9b are formed in the stacked bodies Ba and Bb by the alignment marks 6a and 6b, and at the same time, alignment marks 10a and 10b for forming circuit patterns of the stacked bodies Ba and Bb are formed. After processing the via holes, the via holes 9a and 9b are filled with metal by plating to establish electrical connection between the laminate B and the inner layer base material A. At this time, the regions 5a and 5b where the insulating layer 3 is exposed are also plated, so that the conductor thickness is the same as that of the stacked bodies Ba and Bb.

The circuit patterns on the stacked body Ba and Bb are formed using the alignment marks 10a and 10b. Since the alignment marks 10a and 10b are formed by via hole processing of the stacked bodies Ba and Bb, respectively, the positional accuracy of the circuit patterns 8a and 8b and the via holes 9a and 9b is good. Further, the processing of the via holes 9a and 9b uses the alignment marks 6a and 6b, and the alignment marks 6a and 6b are formed simultaneously with the circuit pattern formation of the inner layer base material A. Therefore, the positional accuracy of the via holes 9a and 9b formed in the stacked bodies Ba and Bb and the circuit pattern 2 of the inner layer base material A is also good.
On the other hand, simultaneously with the formation of the circuit patterns 8a and 8b, the copper foils in the regions 5a and 5b forming the alignment used for alignment in via-hole processing are etched on the subsequent laminated body to expose the insulating layer 3. Then, alignment marks 11a and 11b are formed in the regions 5a and 5b so as not to overlap with the alignment marks 6a and 6b. The alignment marks 11a and 11b may be formed anywhere within the regions 5a and 5b, respectively, but are preferably formed next to the alignment marks 6a and 6b with respect to the X direction.

  After the processing of the via holes and the formation of the wiring circuit pattern of the stacked bodies Ba and Bb are completed, the stacked bodies Ca and Cb composed of the insulating layers 12a and 12b and the conductor layers 13a and 13b are formed on the inner layer base material A. Laminate on the front and back surfaces so that 11a and 11b are exposed. Via holes 14a and 14b are formed in the stacked bodies Ca and Cb from the alignment marks 11a and 11b. After processing the via hole, plating is performed on both sides, and the via holes 14a and 14b are filled with metal to establish electrical connection between the stacked bodies Ca and Cb and the stacked bodies Ba and Bb. Here, since the alignment marks 11a and 11b are formed next to the alignment marks 6a and 6b, those having the same width as the stacked bodies Ba and Bb can be used.

  The circuit patterns of Ca and Cb on the laminate are formed using alignment marks 15a and 15b. Since the alignment marks 15a and 15b are respectively formed by via hole processing of the stacked bodies Ca and Cb, the positional accuracy of the circuit patterns 13a and 13b and the via holes 14a and 14b is good.

Furthermore, the processing of the via holes 14a and 14b uses the alignment marks 11a and 11b, and the alignment marks 11a and 11b are formed simultaneously with the formation of the circuit patterns of the stacked bodies Ba and Bb. Therefore, the positional accuracy of the via holes 14a and 14b formed in the stacked bodies Ca and Cb and the circuit patterns 8a and 8b of the stacked bodies Ba and Bb is also good.
On the other hand, at the same time as forming the circuit patterns 13a and 13b, the alignment marks 16a and 16b are formed in the regions 5a and 5b so as not to overlap the alignment marks 6a and 6b. The alignment marks 16a and 16b may be formed anywhere within the regions 5a and 5b, respectively, but are preferably formed next to the alignment marks 6a, 6b, 11a, and 11b with respect to the X direction.

  After the completion of the processing of the via holes and the formation of the wiring circuit pattern of the stacked bodies Ca and Cb, the stacked bodies Da and Db including the insulating layers 17a and 17b and the conductor layers 18a and 18b are formed on the inner layer base material A. Laminate on the front and back so that 16a and 16b are exposed. Via holes 19a and 19b are formed in the stacked bodies Da and Db from the alignment marks 16a and 16b. After processing the via hole, plating is performed on both sides, and the via holes 19a and 19b are filled with metal to establish electrical connection between the stacked bodies Da and Db and the stacked bodies Ca and Cb. Here, since the alignment marks 16a and 16b are formed next to the alignment marks 6a and 6b, those having the same width as the stacked bodies Ba, Bb, Ca, and Cb can be used.

  The circuit patterns of the stacked bodies Da and Db are formed using the alignment marks 20a and 20b, respectively. Since the alignment marks 20a and 20b are formed by via hole processing of the stacked bodies Ca and Cb, the positional accuracy of the circuit patterns 18a and 18b and the via holes 19a and 19b is good. Furthermore, the processing of the via holes 19a and 19b uses alignment marks 18a and 18b, and the alignment marks 16a and 16b are formed simultaneously with the formation of the circuit patterns of the stacked bodies Ca and Cb. Therefore, the positional accuracy of the via holes 19a and 19b formed in the stacked bodies Da and Db and the circuit patterns 13a and 13b of the stacked bodies Ca and Cb is also good.

The regions 5a and 5b of the inner layer substrate for forming the alignment marks for processing the via holes of each stacked body are prepared by previously preparing regions where the insulating layer 3 is exposed, whereby the conductor thicknesses of the stacked bodies Ba and Bb are formed. The following conductor layers can be obtained. Therefore, the alignment marks 11a and 11b can be formed simultaneously with the formation of the circuit patterns of the stacked bodies Ba and Bb, and the alignment marks 16a and 16b can be formed simultaneously with the formation of the circuit patterns of the stacked bodies Ca and Cb. On the other hand, when the regions 5a and 5b in which the insulating layer 3 is exposed in the present invention are not formed, the regions 5a and 5b are formed with a conductor layer thicker than the conductor thickness of the stacked bodies Ba, Bb, Ca, and Cb. When the circuit patterns of the bodies Ba, Bb, Ca, and Cb are formed, it becomes difficult to form the alignment marks 11a, 11b, 16a, and 16b at the same time.
Therefore, in the present invention, the alignment mark can be formed on the inner layer base material without causing the alignment mark shape to collapse. Furthermore, since it becomes possible to laminate | stack without reducing the width | variety of a laminated body and the effective area | region which can be used as a product part can be maintained, even when the number of lamination | stacking is increased, as shown in FIG. Can be produced efficiently. In addition, the upper and lower layer circuit patterns can be accurately connected because the upper layer via holes are always processed using the alignment marks formed in the lower layer circuit pattern.

The vertical width of the laminate composed of the insulating layer films 7a and 7b and the conductor layer films 8a and 8b laminated on the inner layer substrate A is not particularly limited, and both end portions of the inner layer base material A in the vertical width. The alignment marks formed on the substrate may be stacked so as not to be covered.
Arbitrary shapes of alignment marks can be used when forming circuit patterns or processing via holes. For example, circular, donut-shaped, square-shaped, well-shaped, etc., can be checked at the center or at a specific position. Any shape can be used. In particular, a circular shape and a donut shape are preferable.
As a method for forming the alignment mark, a photolithography method, a drilling method, or the like can be used. Examples of the photolithography method include formation of an alignment mark by a photoresist, and an alignment mark formation method by an additive method, a semi-additive method, and a subtractive method. In this method, the shape of the alignment mark can be arbitrarily designed. Further, depending on the process, the circuit pattern and the alignment mark can be formed at the same time, and in this case, the number of processes can be reduced. Examples of the drilling process include a drilling process, a laser process, or a punching process using a mold, but the shape of the hole serving as the alignment mark is limited to a circle.
The manufacturing method of the multilayer circuit board 22 is not limited to a single-wafer inner layer board, but can also be applied to a roll-to-roll continuous production method using a tape-like flexible board.
The multilayer circuit board 22 is a case where the circuit pattern has upper and lower four layers, but can be widely applied to higher multilayer circuit boards such as upper and lower five layers and six layers.
Example 1

Next, with reference to FIGS. 5, 6 and 7, an embodiment of the method for manufacturing a multilayer circuit board according to the present invention will be described.
As shown in FIG. 5 (a), a tape-like polyimide base material with double-sided copper foil (inner layer base material A in which copper foils of conductor layers 2a and 2b are attached to both sides of polyimide as the insulating layer 3) By punching with a mold, a through hole 1 as a through hole was formed, and alignment of via hole processing and circuit pattern formation was performed.

  Alignment was performed using the through-hole alignment 1 as a reference, and laser irradiation was performed from the copper foil to the boundary between the polyimide and the lower copper foil to form a via hole 4. Thereafter, plating was performed to form a filled via that fills the via hole with plating, and the conductor layers 2a and 2b were electrically connected. A positive resist for forming a circuit pattern was applied to the surface of the inner layer base material A, and alignment of the through hole alignment 1 and the alignment of the photomask was performed. Thereafter, the exposed portion of the photosensitive resin is removed by batch development, the etching resist is removed by the etching solution, the exposed copper foil is chemically etched, and the unnecessary etching resist is peeled off. As shown in b), circuit patterns were formed on the conductor layers 2a and 2b. At the same time, the alignment marks 6a and 6b used for via hole processing of the stacked bodies Ba and Bb are manufactured, and the regions 5a and 5b for forming alignment used for alignment in via hole processing on the subsequent stacked body are copper. The foil was etched so that the insulating layer 3 was exposed.

  After forming the circuit pattern of the inner layer base material A, tape-shaped polyimide base materials Ba and Bb with a single-sided copper foil, each of which was a laminate, were laminated by lamination. At that time, the alignment marks 6a and 6b prepared on both surfaces of the inner layer base material A were not covered. Next, alignment is performed with reference to the alignment marks 6a and 6b, and laser irradiation is performed from the copper foil of the laminated bodies Ba and Bb to the boundary between the polyimide and the copper foil of the inner layer base material, as shown in FIG. Via holes 9a and 9b were formed. At the same time, via alignments 10a and 10b used to form resist circuit patterns on the stacked bodies Ba and Bb were formed.

  As shown in FIG. 5D, plating was performed, and the via holes 9a and 9b were filled vias that fill the via holes with plating, and were electrically connected to the inner layer base material A. And the positive resist for circuit pattern formation was apply | coated to the surface of laminated body Ba and Bb, and alignment of via alignment 10a, 10b and alignment of a photomask was performed. Thereafter, the exposed portion of the photosensitive resin is removed by batch development, the etching resist is removed with an etching solution, the exposed copper foil is chemically etched, and the unnecessary etching resist is peeled off. As shown in e), circuit patterns were formed on the conductor layers 8a and 8b. At the same time, the alignment marks 11a and 11b used for the via hole processing of the stacked bodies Ca and Cb are manufactured, and the regions 5a and 5b for forming the alignment used for alignment in the via hole processing on the subsequent stacked body are made of copper. The foil was etched so that the insulating layer 3 was exposed.

After the circuit patterns of the laminated bodies Ba and Bb were formed, lamination was performed by laminating tape-like single-sided copper foil-attached base materials Ca and Cb, which are laminated bodies. At that time, a single-sided copper foil-attached polyimide base material having the same width as the laminated bodies Ba and Bb was used so that the alignment marks 11a and 11b produced on both surfaces of the inner layer base material A were not covered. Next, alignment is performed with reference to the alignment marks 11a and 11b, and laser irradiation is performed from the copper foil of the laminated bodies Ca and Cb to the boundary between the polyimide and the copper foil of the laminated bodies Ba and Bb, as shown in FIG. Thus, the via holes 14a and 14b were formed. At the same time, via alignments 15a and 15b used for forming a resist circuit pattern on the stacked bodies Ca and Cb were formed.
Plating is performed, and the via holes 14a and 14b are filled vias that fill the via holes with plating, and are electrically connected to the stacked bodies Ba and Bb. A positive resist for forming a circuit pattern was applied to the surfaces of the stacked bodies Ca and Cb, and alignment of the via alignments 15a and 15b and the photomask was aligned in each of the stacked bodies Ca and Cb. Thereafter, the exposed portion of the photosensitive resin is removed by batch development, the etching resist is removed with an etching solution, the exposed copper foil is chemically etched, and the unnecessary etching resist is peeled off. As shown in g), circuit patterns were formed on the conductor layers 13a and 13b. At the same time, alignment marks 16a and 16b used for via hole processing of the stacked bodies Da and Db were produced.

After the circuit patterns of the laminated bodies Ca and Cb were formed, lamination was performed by laminating tape-shaped single-sided copper foils Da and Db with a copper foil, which are laminated bodies, respectively. At that time, a single-sided copper foil-attached polyimide base material having the same width as the laminates Ca and Cb was used so that the alignment marks 16a and 16b produced on both surfaces of the inner layer base material A were not covered. Next, alignment is performed with reference to the alignment marks 16a and 16b, and laser irradiation is performed from the copper foil of the laminated bodies Da and Db to the boundary between the polyimide and the copper foil of the laminated bodies Ca and Cb, as shown in FIG. 6 (h). Thus, the via holes 19a and 19b were formed. At the same time, via alignments 20a and 20b used for forming a resist circuit pattern on the stacked bodies Da and Db were formed.
Plating is performed, and the via holes 19a and 19b are filled vias that fill the via holes with plating, and are electrically connected to the stacked bodies Ba and Bb. A positive resist for forming a circuit pattern was applied to the surfaces of the stacked bodies Da and Db, and alignment of the via alignments 20a and 20b and the photomask was performed in each of the stacked bodies Da and Db. Thereafter, the exposed portion of the photosensitive resin is removed by batch development, the etching resist is removed with an etching solution, the exposed copper foil is chemically etched, and the unnecessary etching resist is peeled off. As shown in i), circuit patterns were formed on the conductor layers 18a and 18b.

  As shown in FIG. 7 (j), since the outermost layer Da is connected to the semiconductor chip and the outermost layer Db is connected to the printed wiring board, opening pads are formed on the circuit patterns of the outermost layers Da and Db. Thus, solder resist patterns 21a and 21b were formed. From the above, a long circuit board having a total of eight wiring structures, four layers vertically in the stacking direction, was completed. When this value was separated into pieces at a predetermined position, a semiconductor package 22 having a multilayer circuit was obtained.

  As described above, the invention described in claims 1 and 6 of the present invention is a method of manufacturing a multilayer circuit board by buildup, and wiring is performed on at least the front and back of an insulating layer such as a multilayer printed wiring board or a semiconductor package. The present invention is also applicable when manufacturing a long circuit board having a multilayer circuit having two or more layers having a pattern.

1a, 1b ... through hole (through hole alignment),
2a, 2b: Conductor layer or conductor wiring circuit (on inner layer substrate),
3, 7a, 7b, 12a, 12b, 17a, 17b ... insulating layer,
4, 9a, 9b, 14a, 14b, 19a, 19b ... via holes,
5a, 5b ... regions where the insulating layer is exposed,
6a, 6b ... alignment mark (alignment mark for via hole processing on the first laminate),
8a, 8b: Conductor layer or conductor wiring circuit (on the first laminate),
10a, 10b... Via holes (circuit pattern forming alignment marks on the first laminate),
11a, 11b ... alignment mark (alignment mark for via hole processing on the second laminate),
13a, 13b ... conductor layer or conductor wiring circuit (on the second laminate),
15a, 15b ...... via hole (alignment mark for forming a circuit pattern on the second laminate),
16a, 16b ... alignment mark (alignment mark for via hole processing on the third laminate),
18a, 18b ... conductor layer or conductor wiring circuit (on the third laminate),
20a, 20b: via holes (alignment marks for circuit pattern formation on the third laminate),
21a, 21b ... Solder resist,
22 …… Multilayer circuit board
A ... Inner layer substrate,
Ba, Bb ... the first laminate,
Ca, Cb ... the second laminate,
Da, Db: Third laminated body.

Claims (3)

In the inner layer material having conductors on both sides of the insulating layer, conductors are electrically connected by filled vias, and a laminate including the insulating layer and the conductor layer is formed on the inner layer substrate on which the conductor wiring circuit is formed from the conductor. A method for producing a multilayer circuit board, comprising: laminating on one side or both sides and then forming via holes and conductor wiring circuits in the laminate, comprising the following steps.
A. Forming at least one alignment mark for forming a via hole for electrically connecting the laminate and the inner layer substrate simultaneously with the formation of the conductor wiring circuit of the inner layer material;
B. A step of laminating the laminate so that the alignment mark is exposed when the laminate is laminated on the conductor wiring circuit;
C. Using at least one of the alignment marks formed in the inner layer material as alignment, and forming a via hole in the stacked body.
D. At least one of the via holes formed in the laminate is used as an alignment to form a conductor wiring circuit, and at the same time as the conductor wiring circuit is formed, it is electrically connected to the laminate further laminated on the conductor wiring circuit. Forming at least one alignment mark for forming a via hole on the inner layer substrate.
E. A step of repeating the steps B to D until the required number of wiring layers is obtained.   When forming the conductor wiring circuit of the inner layer substrate, when the laminated body laminated on the inner layer substrate is the first laminated body, the outermost layer is laminated from the second laminated body laminated on the first laminated body. In the formation of the conductor wiring circuit of the Nth (N = natural number) laminate, the conductor layer in the region where the alignment mark for forming the via hole in the body is disposed is removed in advance, the insulating layer is exposed, 2. The multilayer circuit board according to claim 1, wherein a conductor layer in a region where an alignment mark for via hole formation of the outermost layer stack is disposed is removed in advance from the N + 2 layered body to expose the insulating layer. Method.   2. The multilayer circuit board according to claim 1, wherein the inner layer substrate and the laminated body are sequentially bonded to the inner layer substrate by a reel-to-reel method in which the laminated body is supplied by a tape-like long substrate. Method.

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