JP2002111204A - Method of manufacturing multilayered wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing multilayered wiring board by which alignment accuracy can be improved even when alignment marks formed on a multilayered wiring board have flaws. SOLUTION: The method of manufacturing multilayered wiring board includes a step of forming an insulating layer on an insulating substrate on which a first wiring layer is formed, a step of forming holes for alignment marks so that the centers of three or more circles may be arranged on the same circumference by laser beam processing, and a step of forming holes for via holes in the insulating layer. The method also includes a step of forming a conductor layer to contain the holes for alignment marks on the insulating layer and forming a resist layer on the conductor layer and only selecting three or more circles from among a plurality of circles by using a mask, and then, calculating the center coordinates of the circles arranged on the circumference and performing exposure by making alignment by using the center coordinates. In addition, the method also includes a step of developing the resist layer and a step of forming wiring by etching the conductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer wiring board, and more particularly to a method of manufacturing a multilayer wiring board having alignment marks used for aligning a photomask and a substrate.

[0002]

2. Description of the Related Art Multilayer wiring boards are becoming denser in the formation of via holes and wirings, and accordingly, it is required to improve the alignment accuracy between a photomask and a substrate.

As shown in FIG. 6, the alignment mark and the alignment method on the build-up substrate are based on the center coordinates (1) of the alignment mark provided on the left and right sides of the mask.
The midpoint connecting (2) to the center point (3) and the center coordinates (4) and (5) of the alignment marks provided on the left and right of the build-up board
This is done by matching (6), and the distance between the middle points (shift amount)
Is within the allowable value, it is determined that the alignment is completed.

[0004] Factors that hinder the improvement of the alignment accuracy due to the manufacturing process include panel plating, resist coating, exposure / development, after forming a core layer pattern, laminating a build-up resin, and forming a via hole with a UV-YAG laser. In the subtractive method of performing etching or the semi-additive method of performing flash plating, resist coating, exposure / development, pattern plating and flash etching, alignment marks are used during each step before exposure and during transport of build-up substrates between each step. Is caused by the fact that the visibility of the alignment mark on the substrate in the exposure step is reduced.

If there is a flaw in the alignment mark portion of the build-up substrate, the center coordinate (8) of the alignment mark (7) is deviated from the correct center coordinate (9) as shown in FIG. For this reason, the center coordinates of the alignment mark cannot be recognized with high accuracy, and there is a disadvantage that the alignment error of the substrate becomes large.

In order to solve this problem, it is conceivable to improve each process such as resin lamination and laser processing and to improve the transportation between the processes. However, since the occurrence of scratches on the alignment mark is irregular, it is required to improve the visibility of the alignment mark without depending on other processes.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multi-layered wiring board which has an alignment mark even if it has a flaw. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board in which an alignment mark capable of accurately detecting the alignment mark and improving the alignment accuracy between the mask and the substrate in the exposure step is formed.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the invention of claim 1 provides (a) forming an insulating layer on an insulating substrate on which a first wiring layer is formed. Process. (B) forming a hole for an alignment mark by laser processing the insulating layer so that at least three or more circles or regular polygons are arranged on the circumference; (C) forming via holes in the insulating layer simultaneously with or separately from the step (b). (D)
Forming a conductive layer by plating on the insulating layer so as to include a hole for an alignment mark and a hole for a via hole; (E) forming a resist layer on the conductor layer, using a mask, selecting, from the plurality of circles or regular polygons, only three or more circles or regular polygons having the same shape or an approximation, and A step of calculating the center coordinates of a circle around the circumference, performing alignment with the center coordinates, and performing exposure.
(F) a step of developing the resist layer; (G1) a step of forming a wiring by etching the conductor layer exposed from the resist; Alternatively, instead of the step (g1), (g2) a step of plating on the conductor layer exposed from the resist, removing the resist, and performing soft etching to form a wiring. And a method for manufacturing a multilayer wiring board.

That is, in order to solve the above problem, the present invention arranges a plurality of center coordinates of a perfect circle alignment mark on the circumference of the perfect circle, and selects the same shape or approximation from among the multiplicity of alignment marks. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board, wherein only alignment marks are selected, and center coordinates of concentric circles consisting of these center coordinates and coordinates approximate to the center coordinates are used for alignment.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view showing a cross section of an embodiment of a method for manufacturing a multilayer wiring board according to the present invention.
First, as shown in FIG. 1A, a wiring pattern 52 is formed on an insulating substrate 51 made of a rigid material such as a glass epoxy substrate.
To form In this case, a method of forming a wiring pattern by etching using a double-sided copper-clad glass epoxy substrate may be simple. Subsequently, as shown in FIG. 1B, an epoxy resin is applied to form an insulating layer 53, and via holes are formed in the insulating resin using a laser such as a carbon dioxide laser, a YAG laser, and an excimer laser. . At this time, a hole 70 for an alignment mark is formed. Alternatively, it may be formed in another step. The figure shows only one alignment mark hole. FIG. 2 shows the structure of the alignment mark of this embodiment.

Then, as shown in FIG. 1C, the insulating layer 53 is formed.
Form copper foil by electroless plating and electrolytic plating on top,
A via hole 55 is provided, a resist layer is formed on the formed copper foil, exposed through a photomask, developed, and etched to form a wiring pattern 56. On this occasion,
The electroless plating is performed for imparting conductivity to the insulating layer so that the electrolytic plating can be performed. At this time, the alignment of the photomask is performed using the alignment mark holes formed with the copper foil. For the formation of the wiring pattern, the conductor layer exposed from the resist is etched, a subtractive method for forming the wiring, plating is performed on the conductor layer exposed from the resist, the resist is peeled off, soft etching is performed, and the wiring is formed. Any of the forming semi-additive methods can be applied.

Next, as shown in FIG.
7 is formed on the entire surface to form a via hole and an alignment hole (a position different from the position of the previous alignment hole, not shown). The method of formation may be the same as the method used in the step of FIG. Further, a through hole 58 for a through hole is formed using a drill. And FIG.
Plating is performed in the same process as in FIG.
Then, a through hole 60 is formed (FIG. 1E). In this case, it is preferable that the diameter of the through hole 60 is as small as possible so as not to hinder the formation of the wiring pattern at high density.

Subsequently, a wiring pattern 61 is formed by exposure and etching. The alignment is performed in the same manner as described above, using an alignment hole formed at a position different from the previous position. At this time, the copper foil on the surface opposite to the surface on which the surface wiring layer is formed is simultaneously etched to form the power supply layer pattern 62. Then, the wiring pattern 61 and the power supply layer pattern 62
Is provided, and a printed wiring board is completed (FIG. 1F).

The shape of the alignment mark composed of a perfect circle in the present invention is preferably a perfect circle because it is easy to process by laser and the center coordinates of the mark can be easily obtained. An embodiment of the alignment method of the method for manufacturing a multilayer wiring board according to the present invention will be described. In FIG. 2, the shape of the alignment mark used on the circumference is a perfect circle as an example of the present invention.
In the structure of the alignment mark according to the present invention, a plurality of center coordinates of the alignment mark formed of a perfect circle or a regular polygon are arranged on the circumference of the perfect circle. In FIG. 2, alignment marks composed of perfect circles of the same shape are relatively 0 ° (18), 60 ° (19), 120 ° (2 °) on the circumference of the perfect circle.
0), 180 ° (21), 240 ° (22) and 300 ° (23) are shown.

As shown in FIG. 3, when the alignment mark (24) constituting the alignment mark on the circumference of a perfect circle composed of multiple points is a perfect circle, the diameter d is about 50 to 100 μm. The size is the same for a regular polygon. In addition, a multi-point alignment mark on a circle (2
6) The diameter D is about 250 to 400 μm.

Next, FIG. 4 shows a case where a photomask and a substrate are aligned using an alignment mark structure. First, from among the alignment marks (28 to 33) constituting an alignment mark consisting of multiple points, alignment marks (28, 29, 30, 31, and
By selecting 33), the center coordinates (35) of a circle (34) having the center coordinates of these alignment marks on the circumference can be used as the alignment coordinates. Alignment mark 3
2, even if the shape is distorted due to a defect at the time of manufacturing, the alignment can be satisfactorily performed without affecting the alignment.

In the alignment mark structure shown in FIG. 5, an alignment mark constituting a perfect circular alignment mark having the same shape is relatively 0 ° (3 °)
6), 45 ° (37), 90 ° (38), 135 ° (39), 180 ° (4
0), 225 ° (41), 270 ° (42), and 315 ° (43) are provided with a total of eight alignment marks. Increasing the number of alignment marks on the circumference enables more accurate alignment.

[0018]

EXAMPLES Examples and comparative examples are shown below. <Example> A size of 340mm x 340mm, thickness 18μ on both sides
A double-sided copper-clad laminate to which a copper foil of m was attached was prepared, and the copper foil on both sides was etched to form a wiring pattern. Then, an insulating resin (PSR-4000, manufactured by Taiyo Ink Mfg. Co., Ltd.) was applied to both surfaces and thermally cured to form an insulating layer having a thickness of 25 μm. Next, the multi-point alignment mark shown in FIG. 2 was formed on the insulating resin (PSR-4000, manufactured by Taiyo Ink Manufacturing Co., Ltd.) using a UV-YAG laser. This consists of six pieces and a diameter of 8 on a circumference of 400 μm in diameter.
The insulating resin is removed from the 0 μm circle. Then, electroless copper plating was performed at a thickness of 0.3 μm, and electrolytic copper plating was performed at 10 μm. Further, a negative photosensitive resist was applied to a film thickness of 10 to 15 μm by dip coating. On the mask side, as an alignment mark, at a position corresponding to the center of the circle having a diameter of 400 μm, a diameter of 100
A black circle of μm was formed. The alignment mark is
Two portions were formed at diagonal positions on both the semiconductor device substrate side and the mask side. Then, both alignment marks were used to expose and develop using an exposure device. As a result, a portion where the resist having a diameter of 100 μm was removed was formed at the center of the alignment mark on the semiconductor device substrate side.

<Comparative Example> In the comparative example, only differences from the embodiment will be described. First, an alignment mark having the shape shown in FIG. 6 was used as an alignment mark on the semiconductor device substrate side. That is, using a UV-YAG laser, the insulating resin in a circular portion having a diameter of 800 μm was removed. As the alignment mark on the mask side, the center of the 800 μm circle coincides with the center of the circle, and the inside diameter is 1600 μm and the outside diameter is 1
A 700 μm donut-shaped black circle was formed. In this case, also in this case, the alignment mark is provided on the semiconductor device substrate side.
The mask side was also formed at two diagonal positions. Then, both alignment marks were used to expose and develop using an exposure device. As a result, the inner diameter is 1600 around the alignment mark on the semiconductor device substrate side.
A part where the doughnut-shaped resist having an outer diameter of 1 μm and an outer diameter of 1700 μm was removed was formed.

The alignment accuracy obtained as described above was evaluated. A 3D measuring device (3D CNC image measuring device QUICK VISION, manufactured by Mitutoyo) was used for the measurement. First,
In the embodiment, three or more circles having an approximate shape are selected from six circles constituting the alignment mark on the semiconductor device substrate side, and a circle passing through the center thereof is determined. Was calculated. Since the alignment marks are diagonal, the midpoint was calculated.
On the other hand, the center coordinates of a circle having a diameter of 100 μm from which the resist was removed were calculated. Also in this case, since the alignment marks are diagonal, the midpoint was calculated. If the alignment accuracy is high, the calculated shift amount of the coordinates between the midpoints is small. In the comparative example, the center coordinates of a circle having a diameter of 800 μm, which is an alignment mark on the semiconductor device substrate side, were calculated.
The center of a donut shape having an outer diameter of 0 μm and an outer diameter of 1700 μm was calculated. Then, similarly to the example, the midpoint of each of the diagonal alignment marks was calculated. 2 for the example
Four samples were prepared, and for the comparative example, four samples were prepared, and the above measurement was performed. The shift amount (s) is
Represents the average value of the distance between the midpoints calculated as described above, and σ is the standard deviation of the shift amount. The following are the measurement results. (Example) s = 0.0023 mm 3σ = 0.0021 (Comparative Example) s = 0.0145 mm 3σ = 0.0113 As a result, it was confirmed that the alignment accuracy was improved by changing the shape of the alignment mark.

[0021]

According to the present invention, even when the surface of the build-up substrate has a flaw, the alignment mark can be accurately detected and the alignment between the photomask and the substrate in the exposure step can be performed with high accuracy. .

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a cross section of an embodiment of a method for manufacturing a multilayer wiring board according to the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of an alignment mark structure according to the present invention.

FIG. 3 is an explanatory diagram showing an embodiment of alignment mark selection according to the present invention.

FIG. 4 is an explanatory view showing an embodiment of an alignment mark structure according to the present invention.

FIG. 5 is an explanatory view showing an embodiment of an alignment mark structure according to the present invention.

FIG. 6 is an explanatory view showing a conventional alignment mark and an alignment method.

FIG. 7 is an explanatory diagram showing a conventional alignment mark when there is a flaw on the surface of a build-up substrate.

[Explanation of symbols]

(1), (2) Alignment marks provided on the left and right of the photomask and their center coordinates (3) Midpoint (4), (5) Alignment marks provided on the left and right of the build-up substrate and their center coordinates (6) ) Midpoint (7) Alignment mark (8), (9) Center coordinate of alignment mark (10) Through hole (11) Multilayer printed wiring board (12) Through hole plating (13) Hole filling resin (14) Core pattern layer (15) Insulating resin (16) Via hole (17) Copper pattern of build-up layer (18)-(19) Alignment mark (24) Alignment mark (26) Circle (28)-(33) Alignment mark (34) Circle ( 35) Alignment position (36) to (43) Alignment mark (51) Insulating substrate (52) Wiring pattern (53) Insulating layer (54) Via hole forming portion (55) Via hole (56) Wiring pattern (57) Insulating layer (58) Through hole (59) Via hole (60) Through hole (61) Wiring pattern (62) Power supply layer Pattern (63) Solder resist (70) Hole for alignment mark d: Diameter of circle D: Diameter of circle

Claims (1)

[Claims] (A) forming an insulating layer on an insulating substrate on which a first wiring layer is formed; (B) forming a hole for an alignment mark by laser processing the insulating layer so that at least three or more circles or regular polygons are arranged on the circumference; (C) forming via holes in the insulating layer simultaneously with or separately from the step (b). (D) forming a conductor layer by plating on the insulating layer so as to include an alignment mark hole and a via hole; (E) forming a resist layer on the conductor layer, using a mask, selecting, from the plurality of circles or regular polygons, only three or more circles or regular polygons having the same shape or an approximation, and A step of calculating the center coordinates of a circle around the circumference, performing alignment with the center coordinates, and performing exposure. (F) a step of developing the resist layer; (G1) etching the conductor layer exposed from the resist,
Step of forming wiring. Alternatively, instead of the step (g1), (g2) a step of plating on the conductor layer exposed from the resist, removing the resist, and performing soft etching to form a wiring. A method for manufacturing a multilayer wiring board, comprising performing the steps of: