JP2012209284A - Method of manufacturing wiring substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of an operation of positioning a wiring substrate being manufactured when patterning is performed on the wiring substrate.SOLUTION: There is provided a method of manufacturing a wiring substrate 10 comprising the steps of: (A) forming a first positioning mark 60 including a first figure and a second figure on a wiring substrate formation plate which is to be a wiring substrate; (B) causing a positioning device to perform an operation to identify the first figure; (C) causing the positioning device to perform an operation to identify the second figure when the positioning device has determined that the first figure cannot be identified in step (B); and (D) causing the positioning device to position the wiring substrate formation plate based on a position of the first figure identified in step (B) when the positioning device has determined that the first figure can be identified in step (B), and causing the positioning device to position the wiring substrate formation plate based on the second figure identified in step (C) when the positioning device has determined that the first figure cannot be identified in step (B).

Description

  The present invention relates to a method for manufacturing a wiring board.

  Conventionally, wiring boards for mounting electronic components such as semiconductor chips are known. At the time of manufacturing such a wiring board, it is necessary to position the wiring board during manufacturing when performing desired patterning on the wiring provided on the wiring board. For such positioning, a configuration in which a positioning mark is provided on a wiring board that is being manufactured has been proposed (for example, see Patent Document 1).

JP-A-2005-244182 JP 2005-252155 A

  Positioning of the wiring board using such a positioning mark is generally performed by imaging the positioning mark using reflected light or transmitted light and performing image processing to recognize a predetermined positioning mark. However, when positioning with such a positioning mark, the positioning mark may not be well recognized for various reasons. As described above, if the positioning marks are not read well, it is not possible to proceed to the patterning process, and the yield at the time of manufacturing the wiring board due to the members that cannot recognize the positioning marks well. Inconvenience such as lowering may occur. Therefore, further improvement in the reliability of the operation for recognizing the positioning mark has been desired.

  The present invention has been made to solve the above-described conventional problems, and it is an object of the present invention to improve the reliability of the positioning operation of the wiring board during manufacturing when patterning the wiring board.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A method for manufacturing a wiring board, comprising:
(A) forming a first positioning mark including a first graphic and a second graphic on a wiring board forming plate for forming the wiring board;
(B) a step in which the positioning device performs an operation of identifying the first graphic;
(C) When the positioning device determines that the first graphic cannot be identified in the step (B), an operation of identifying the second graphic;
(D) When the positioning device determines that the first graphic can be identified in the step (B), the wiring board forming board is based on the position of the first graphic identified in the step (B). When it is determined that the first graphic cannot be identified in the step (B), the wiring board forming board is positioned based on the second graphic identified in the step (C). Process,
A method of manufacturing a wiring board comprising:

  According to the method for manufacturing a wiring board described in Application Example 1, when positioning the wiring board forming plate, the first graphic is used by using the first positioning mark including the first graphic and the second graphic. Since the second graphic is identified when it cannot be identified, the reliability of the positioning operation can be improved.

[Application Example 2]
In the method for manufacturing a wiring board according to Application Example 1, each of the first graphic and the second graphic includes a plurality of dots and is formed by connecting dots constituting the first graphic. A method of manufacturing a wiring board, wherein a dot constituting the second graphic is not included in the region. According to the method for manufacturing a wiring board described in Application Example 2, it is possible to suppress the influence of the other graphic during the operation of identifying one of the first graphic and the second graphic. .

[Application Example 3]
The method for manufacturing a wiring board according to Application Example 1, wherein each of the first graphic and the second graphic includes a plurality of dots, and one of the first graphic and the second graphic. Dots other than the common dots constituting the other figure are not included in the area formed by connecting dots other than the common dots common to the dots constituting the other figure among the dots constituting the figure. A method for manufacturing a wiring board. According to the method for manufacturing a wiring board described in Application Example 3, it is possible to suppress the influence of the other graphic during the operation of identifying one of the first graphic and the second graphic. .

[Application Example 4]
4. The method for manufacturing a wiring board according to any one of Application Examples 1 to 3, wherein the operation of identifying the first graphic in the step (B) is performed by obtaining a center of the first graphic to obtain the first graphic. The operation of identifying the position of the second graphic in the step (C) identifies the position of the second graphic by obtaining the center of the second graphic. A method of manufacturing a wiring board which is an operation. According to the method for manufacturing a wiring board described in Application Example 4, the wiring board forming plate can be positioned by obtaining the center of each figure.

[Application Example 5]
A method for manufacturing a wiring board according to Application Example 4, wherein the center of the first graphic and the center of the second graphic are at the same position. According to the method for manufacturing a wiring board described in Application Example 5, in order to perform positioning by obtaining the same center regardless of which figure is used, the processing content for positioning using the obtained center is changed. There is no need to do. Therefore, the complexity of the processing for positioning can be suppressed.

[Application Example 6]
6. The method for manufacturing a wiring board according to any one of Application Examples 1 to 5, wherein the step (A) is performed at any one of four corners of the wiring board forming plate formed in a rectangular shape. A second positioning mark having at least one of a shape and a size different from that of the first positioning mark is formed, and the first positioning mark is formed at one or more of the four corners where the second positioning mark is not formed. A method of manufacturing a wiring board, which is a step of forming a positioning mark. According to the method for manufacturing a wiring board described in Application Example 6, when the wiring board forming board is positioned, the wiring board forming board is recognized even if the wiring board forming board is arranged in an incorrect direction. Is possible.

[Application Example 7]
The wiring board manufacturing method according to any one of Application Examples 1 to 6, wherein in the step (A), the first positioning mark is formed on one surface of the wiring board forming plate, and the wiring Forming a third positioning mark having at least one of a shape and a size different from that of the first positioning mark on the other surface of the substrate forming plate, wherein the step (D) includes the first positioning mark; A method of manufacturing a wiring board, wherein positioning is performed on the one surface of the wiring board forming plate when the first or second graphic constituting the positioning mark is identified. According to the method for manufacturing a wiring board described in Application Example 7, when the wiring board forming board is positioned, the wiring board forming board is recognized even if the front and back sides are incorrectly arranged. Is possible.

[Application Example 8]
8. The method for manufacturing a wiring board according to any one of Application Examples 1 to 7, wherein the step (A) includes excavating an insulator layer formed on a surface of the wiring board forming plate to perform the first positioning. A step of forming a mark, wherein the step (B) further includes forming the wiring board including the first positioning mark on the wiring board forming plate prior to the operation of identifying the first graphic. A wiring for performing a step (E) of forming a resist layer covering the surface of the plate, and exposing the resist layer based on a result of the positioning after the positioning in the step (D) A method for manufacturing a substrate. According to the method for manufacturing a wiring board described in Application Example 8, even when a resist layer that covers the positioning mark is provided, the reliability of the positioning operation can be improved, and the position when the resist layer is exposed. Deviation can be suppressed.

  The present invention can be realized in various forms other than those described above. For example, the present invention can be realized in the form of an alignment method for a wiring board forming plate, a wiring board forming board having a positioning mark, or the like.

2 is a schematic cross-sectional view illustrating a schematic configuration of a wiring board 10. FIG. 2 is a plan view showing a wiring board 10. FIG. 2 is a plan view showing a schematic configuration of a connection wiring board 15; FIG. 5 is an explanatory view showing a manufacturing process of the wiring board 10. FIG. 5 is an explanatory diagram showing a configuration of a positioning mark 60. FIG. It is explanatory drawing which shows the position alignment process of a wiring board formation board. It is explanatory drawing showing an example of the 2nd positioning mark. 6 is an explanatory diagram showing a configuration of a positioning mark 260. FIG. FIG. 10 is an explanatory diagram illustrating a configuration of a positioning mark 360.

A. Wiring board configuration:
FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a wiring board 10 according to a first embodiment of the present invention. In this embodiment, there is a feature in a positioning mark to be described later used in the manufacturing process of the wiring board 10. First, the overall configuration and the entire manufacturing process of the wiring board 10 will be described.

  The wiring board 10 is a build-up board formed by alternately laminating a plurality of conductor layers and insulator layers (dielectric layers) having a predetermined pattern on both surfaces of the plate-like core 20. On the first surface S1 of the plate-shaped core 20, a first conductor layer CL1, a first insulator layer (dielectric layer) IL1, a second conductor layer CL2, a second insulator layer (dielectric layer) IL2, The third conductor layer CL3 is sequentially formed. Here, the first conductor layer CL1 and the second conductor layer CL2 are connected via the via conductor 30 formed on the inner wall of the via hole 30h, and the second conductor layer CL2 and the third conductor layer CL3 are They are connected via via conductors 32 formed on the inner wall of the via hole 32h. Part of the third conductor layer CL3 constitutes a metal terminal pad 34. The first conductor layer CL1, the first insulator layer IL1, the second conductor layer CL2, the second insulator layer IL2, and the third conductor layer CL3 form a first wiring stacked portion WL1.

  Similarly, on the second surface S2 of the plate-shaped core 20, the fourth conductor layer CL4, the third insulator layer (dielectric layer) IL3, the fifth conductor layer CL5, the fourth insulator layer (dielectric layer). ) IL4 and sixth conductor layer CL6 are sequentially formed. Here, the fourth conductor layer CL4 and the fifth conductor layer CL5 are connected via the via conductor 40 formed on the inner wall of the via hole 40h, and the fifth conductor layer CL5 and the sixth conductor layer CL6 are The via holes are connected via via conductors 42 formed on the inner wall of the via hole 42h. Part of the fifth conductor layer CL6 constitutes a metal terminal pad 44. The fourth conductor layer CL4, the third insulator layer IL3, the fifth conductor layer CL5, the fourth insulator layer IL4, and the sixth conductor layer CL6 form the second wiring stacked portion WL2.

  Solder resist layers 36 and 46 are provided on the third conductor layer CL3 on the first surface S1 side of the wiring substrate 10 and on the sixth conductor layer CL6 on the second surface S2 side, respectively. The solder resist layers 36 and 46 have openings 36a and 46a at positions corresponding to the respective metal terminal pads so as to expose the metal terminal pads 34 and 44, respectively. Solder bumps 38 are provided on the metal terminal pads 34 provided in the third conductor layer CL3. The solder bump 38 has a structure for flip-chip connecting electronic components such as a semiconductor chip.

  Further, a through hole 22 is formed in the plate-like core 20, and a through hole conductor 24 for conducting the core conductor layers CL 1 and CL 4 is formed on the inner wall surface thereof. The through hole 22 is filled with a hole filling material 26 made of a resin such as an epoxy resin.

  The said plate-shaped core 20 can be comprised with a heat resistant resin board (for example, bismaleimide-triazine resin board) and a fiber reinforced resin board (for example, glass fiber reinforced epoxy resin). The first to sixth conductor layers can be formed of a conductive material such as metal, for example, copper (Cu). The first to fourth insulator layers and the solder resist layers 36 and 46 can be formed of an insulating material such as a thermosetting resin. The pattern (planar shape) of each conductor layer and the number of conductor layers and insulating layers to be laminated can be arbitrarily set.

  FIG. 2 is a plan view showing a state in which the wiring board 10 is viewed from the surface side on which the solder bumps 38 are provided. As shown in FIG. 2, the wiring substrate 10 includes a chip mounting area 50 at the center thereof. In the chip mounting area 50, a plurality of solder bumps 38 are arranged in a grid at predetermined intervals. FIG. 1 is an enlarged view of a part of the chip mounting area 50 in the section 1-1 of FIG.

  In this embodiment, the wiring board 10 is manufactured by producing a connecting wiring board 15 in which a plurality of wiring boards 10 are connected and dividing the connecting wiring board 15. Therefore, each process for manufacturing the wiring board 10, that is, a process of forming each layer on the plate-like core 20 is collectively performed on the entire connection wiring board 15. FIG. 3 is a plan view showing a schematic configuration of the connection wiring board 15. In the following description, the wiring board 10 being manufactured is referred to as a wiring board forming plate. In particular, in this embodiment, since the wiring board 10 is manufactured as the connection wiring board 15 as described above, the connection wiring board 15 being manufactured is referred to as a wiring board forming plate. During the manufacturing of the connection wiring board 15, a positioning mark 60 is formed in a non-product part (a part where the wiring board 10 is not formed) in the outer peripheral region of the wiring board forming plate. FIG. 3 shows a position where the positioning mark 60 is provided on the connection wiring board 15. In this embodiment, one positioning mark 60 is provided at each of the four corners of the rectangular wiring board forming plate. A specific configuration of the positioning mark 60 will be described later. In the case where the wiring boards 10 are manufactured individually one by one, the positioning mark 60 may be provided on each wiring board 10.

B. Wiring board manufacturing method:
FIG. 4 is an explanatory view showing a manufacturing process of the wiring board 10. When manufacturing the wiring substrate 10, first, a plate-like member such as a heat-resistant resin plate to be the plate-like core 20 is prepared, and the plate-like member is drilled to form the through hole 22 (step S100). . Drilling can be performed by drilling, laser processing, or punching. Thereafter, the first conductor layer CL1, the fourth conductor layer CL4, and the through hole conductor 24 are formed by pattern plating, and the through hole 22 is filled with the filling material 26 (step S110).

  Next, a resin film is bonded (laminated) so as to cover the first conductor layer CL1, and the bonded resin film is cured to form the first insulator layer IL1 (step S120). The resin film can be formed of a thermosetting resin mixed with silica filler or the like. In this embodiment, prior to the bonding of the resin film, the surface of the first conductor layer CL1 is subjected to a roughening process for improving the adhesion with the resin film.

  Thereafter, the first insulator layer IL1 is excavated to form via holes 30h and positioning marks 60 in a predetermined pattern in the first insulator layer IL1 (step S130). The excavation processing of the first insulator layer IL1 can be performed, for example, by laser irradiation. In laser irradiation, various laser processing machines such as an excimer laser, a carbon dioxide gas laser, and an Nd-YAG laser can be used. The positioning mark 60 formed in step S130 is used when forming the second conductor layer CL2 formed on the first insulator layer IL1. A specific configuration of the positioning mark 60 will be described later.

  Next, a resist layer is formed on the first insulator layer IL1 after the excavation process (step S140). In this embodiment, the resist layer is formed by laminating (laminating) a dry film resist on the first insulator layer IL1.

  In this embodiment, prior to the formation of the resist layer, a desmear process is performed in which the inside of the via hole 30h and the positioning mark 60 are cleaned using a chromic acid solution or an alkaline potassium permanganate solution. Further, in this embodiment, after the desmear process, the surface layer portion of the first conductor layer CL1 exposed in the via hole 30h and the positioning mark 60 is removed by soft etching, and then the electroless Cu is formed on the first insulator layer IL1. A plating layer is formed, and a resist layer is formed on the electroless Cu plating layer. The soft etching is a process for removing the roughened portion of the surface layer portion of the first conductor layer CL1 and improving the plating depositability in the electroless Cu plating step. For soft etching, for example, sulfuric acid or hydrochloric acid can be used.

  After the resist layer is formed on the first insulator layer IL1, exposure and development are performed to pattern the resist layer (step 150). The positioning mark 60 provided on the first insulator layer IL1 is used when patterning the resist layer. Specifically, light is irradiated from above the resist layer, the reflected light is detected by an imaging device such as a CCD camera, and the positioning mark 60 is imaged. Then, the wiring board forming plate is positioned based on the position information of the positioning marks 60 derived from the image data obtained by imaging, and the relative alignment between the wiring board forming plate and the exposure mask is performed. The exposure mask is previously patterned according to the shape of the second conductor layer CL2 to be formed. After the exposure mask is arranged at a predetermined position by alignment, the dry film resist is exposed and developed. Thereby, the dry film resist can be patterned so as to cover a region other than the region where the second conductor layer CL2 is to be formed.

  Thereafter, electrolytic Cu plating is performed using the patterned resist layer as a plating resist to form the via conductor 30 on the inner wall of the via hole 30h, and the second conductor layer CL2 is formed on the first insulator layer IL1 (step S160). ). That is, the second conductor layer CL2 is formed by forming an electrolytic Cu plating layer in a portion not covered with the dry film resist on the first insulator layer IL.

  After the second conductor layer CL2 and the via conductor 30 are formed, the dry film resist is removed using a chemical solution (step S170). In this embodiment, after the dry film resist is removed, the electroless Cu plating layer formed as a base plating layer for forming the electrolytic Cu plating layer is removed by quick etching.

  In this embodiment, prior to the formation of the resist layer, an electroless plating layer as a base plating layer is formed and the second conductor layer CL2 is formed of an electrolytic plating layer. However, the entire second conductor layer CL2 is formed. May be formed of an electroless plating layer. In this case, it is not necessary to form an electroless plating layer prior to the formation of the resist layer.

  After removing the resist layer in step S170, the second insulator layer IL2 and the third conductor layer CL3 are formed by performing the same processes as in steps S120 to S170 (step S180). At this time, in the process corresponding to step S130, the positioning mark 60 is formed together with the via hole 32h in the second insulator layer IL2. In the step corresponding to step S150, the positioning mark 60 is used to position the wiring board forming board and align it with the exposure mask.

  Thereafter, the same process as steps S120 to S170 is repeated twice for the second surface S2 of the plate-like core 20 to thereby provide the third insulator layer IL3, the fifth conductor layer CL5, the fourth step. Insulator layer IL4 and sixth conductor layer CL6 are formed (step S190). Also in this case, in the process corresponding to step S130, the positioning mark 60 is formed together with the via hole 40h or 42h in the third insulator layer IL3 or the fourth insulator layer IL4. In the step corresponding to step S150, the positioning mark 60 is used to position the wiring board forming board and align it with the exposure mask.

  Thereafter, the solder resist layer 36 is formed on the third conductor layer CL3, and the solder resist layer 46 is formed on the sixth conductor layer CL6. Further, a solder bump 38 is formed (step S200). In this step S200, after forming the solder resist layers 36, 46, openings 36a, 46a are provided in the respective solder resist layers. Then, Ni / Au plating is applied to the third conductor layer CL3 or the sixth conductor layer CL6 exposed in the openings 36a and 46a to form metal terminal pads 34 and 44. Thereafter, solder bumps 38 are formed on the metal terminal pads 34. In order to form the solder bump, for example, the reflow process may be performed by filling the opening 36a with a solder paste by a screen printing method or the like, or disposing a solder ball in the opening 36a.

  Thereafter, the wiring board 10 can be obtained by dividing the connection wiring board 15 at a predetermined position (step S210).

C. Configuration for alignment:
Hereinafter, the positioning mark 60 will be described in detail. FIG. 5 is an explanatory diagram showing the configuration of the positioning mark 60 provided at a predetermined position of the wiring board forming plate of the present embodiment. The positioning mark 60 has a shape in which a plurality of concave portions (hereinafter also referred to as dots) having a circular cross section are combined. Specifically, the positioning mark 60 includes eight first dots 61 and eight second dots 62. Each of these dots is formed by excavating an insulator layer (for example, the first insulator layer IL1 in step S130) provided on the surface of the wiring board forming plate by laser irradiation or the like. The depth of each dot can be set to an arbitrary depth with the depth corresponding to the thickness of the insulator layer being the maximum value. The diameter of each dot can be set to, for example, 50 μm or more and 100 μm or less.

  The first dots 61 and the second dots 62 are respectively arranged on a specific circumference. In the present embodiment, a circle specified by the first dot 61 (a circle in which the center of the first dot 61 exists on the circumference and indicated as a circle In by a one-dot chain line in FIG. 5) and a second dot 62 A specified circle (a circle in which the center of the second dot 62 exists on the circumference and indicated as a circle Out by a one-dot chain line in FIG. 5) is a concentric circle. In FIG. 5, the center of the concentric circle is indicated as O. The circle In has a smaller diameter than the circle Out, and the circle In is disposed inside the circle Out. All the first dots 61 are arranged in the area A1 indicated by the broken line in FIG. 5, and all the second dots 62 are arranged outside the area A1. Hereinafter, the aggregate of the first dots 61 is also referred to as a first graphic, and the aggregate of the second dots 62 is also referred to as a second graphic. In the present embodiment, eight first dots 61 and eight second dots 62 are provided, but the number of dots may be different. Since each figure has at least three or more dots, a circle can be specified and its center can be obtained.

  FIG. 6 is an explanatory diagram showing a process of aligning the wiring board forming plate. In this embodiment, as described above, the positioning mark 60 is used for specifying the position of the wiring board forming plate and performing relative alignment between the wiring board forming plate and the exposure mask. Such a positioning device for positioning the wiring board forming plate and aligning with the exposure mask is obtained by controlling and imaging each of the imaging device such as a CCD camera for imaging the positioning mark 60 and the positioning device. And a control unit including a computer for processing the image data to be processed. Each process shown in FIG. 6 is sequentially performed in each part of the positioning device. In the following, the alignment using the positioning mark 60 formed on the first insulator layer IL1 in step S130 will be described, but the alignment using the positioning mark 60 formed on the other insulator layer is similarly performed. It is.

  When performing the process of aligning the wiring board forming board, first, each positioning mark 60 formed on the wiring board forming board is imaged (step S300). And the control part with which a positioning device is provided processes the image data obtained by imaging, and identifies a 1st figure (step S310).

  The image processing executed in step S310 can include a binarization process, for example. It is only necessary that the position, range, shape, etc. of each first dot 61 constituting the first graphic can be specified by processing the image data. As an operation for identifying the first graphic in step S310, in this embodiment, the position of the first graphic is identified by deriving the position of the center O of the first graphic.

  Thereafter, the control unit determines whether or not the first graphic has been identified in all the positioning marks 60 (step S320). In order to derive the position of the center O of the first graphic and identify the first graphic, each first dot 61 is recognized as a circle by image processing, the center of each first dot 61 is derived, It is necessary to derive a circle In in which the center of one dot 61 exists on the circumference and to derive the position of the center of the circle In. Therefore, for example, when each first dot 61 cannot be recognized as a circle to the extent that the center can be obtained, or when the position of the center of each derived first dot 61 varies to the extent that a specific circle In cannot be derived. Cannot identify the first graphic. Even if there is a dot that cannot be recognized well in the first dots 61 constituting the first graphic, the position of the center of the circle In is determined using the remaining dots that can be recognized well. It is good also as accepting the operation to derive.

  As one of the factors that makes it impossible to identify the first figure as described above, when laminating the dry film resist on the first insulator layer IL1, the dry film resist is formed as a recess. Following the shape of the dot 61 can be mentioned. That is, the dry film resist enters the first dot 61. The dry film resist is generally a blue transparent film, but when the dry film resist follows the first dots 61 in this way, a shadow is formed inside the outer periphery of the first dots 61. In this state, when the first graphic is imaged from the dry film resist and binarization processing is performed, for example, the shadowed portion of the dry film resist is recognized as black, and the first dot 61 The boundary may be recognized as an ellipse, for example. In such a case, the center position of the first dot 61 may or may not be derived at a shifted position. As a result, the position of the center of the circle In may be derived at a shifted position or may not be derived.

  Alternatively, the position where the first dots 61 are formed on the wiring board forming board is due to variations in the thickness of each insulating layer and conductor layer provided on the wiring board forming board laminated with the dry film resist, expansion and contraction of the wiring board forming board, and the like. There is also a possibility of shifting in various directions. Thus, even when the formation positions of the first dots 61 are deviated, the first figure may not be recognized well. In addition, in the wiring board forming board, the first figure may not be recognized even if there is a scratch in the position where the first dot 61 is formed or in the vicinity of the first dot 61.

  After the operation of identifying the first graphic in step S310, the control unit determines whether or not the first graphic can be identified (step S320). When the first graphic can be identified, the wiring board forming plate is positioned and aligned with the exposure mask based on the position of the derived center O of the first graphic (step S350). The process for is completed.

  When it is determined in step S320 that the first graphic cannot be identified, the control unit processes the image data obtained by imaging to identify the second graphic (step S330). Here, the operation of imaging the second graphic may be performed separately from the operation of imaging the first graphic. In step S330 of this embodiment, as in step S310, the position of the center O of the second graphic is derived as the operation for identifying the second graphic.

  After the operation of identifying the second graphic in step S330, the control unit determines whether or not the second graphic can be identified (step S340). When the second figure can be identified, the wiring board forming board is positioned and aligned with the exposure mask based on the position of the derived center O of the second figure (step S350). The process for is completed. When it is determined in step S340 that the second graphic cannot be identified, the control unit determines that alignment using the wiring board forming board currently being processed cannot be performed (step S360). The positioning operation with respect to the wiring board forming board is stopped.

  According to the method of manufacturing the wiring board of the present embodiment configured as described above, the positioning mark 60 including the first graphic and the second graphic is used when positioning the wiring board forming plate. . Therefore, even if the wiring board forming plate cannot be satisfactorily positioned by image processing using the result of imaging the first graphic, the wiring board is formed using the result of imaging the second graphic. It is possible to align the plates. Therefore, the reliability of the operation of recognizing the positioning mark and aligning the wiring board forming plate can be improved. That is, the positioning mark is not well identified, and it is impossible to proceed to the patterning process, or the positional deviation in the identified positioning mark can be suppressed.

  In this embodiment, since the positioning mark 60 includes the first graphic and the second graphic, when the first positioning operation fails and the second positioning operation is performed, 1 An image obtained by imaging at a time can be used. Therefore, the operation related to imaging can be simplified. In addition, even when imaging the first graphic and imaging the second graphic are performed separately, it is not necessary to move the imaging apparatus greatly or at all, and the operation related to imaging is simplified. Can be

  Furthermore, in this embodiment, the circle In specified by the first dots 61 constituting the first graphic and the circle Out specified by the second dots 62 constituting the second graphic are concentric circles. The complexity of processing for positioning and alignment can be suppressed. That is, no matter which figure is used, since the same center O is obtained for positioning and positioning, it is not necessary to change the processing contents for positioning and positioning using the center O. Note that the center of the first graphic and the center of the second graphic can be set at different positions. Even in such a case, the first and By providing the second graphic, the same effect of suppressing the movement of the imaging device can be obtained when the graphic identification operation is performed again.

  In the present embodiment, the first graphic provided in the positioning mark 60 is disposed within the area A1, and the second graphic is disposed outside the area A1. That is, the second graphic forming the second graphic is formed in an area A1 formed by connecting the first dots 61 constituting the first graphic (specified so that all the first dots 61 are included therein). Dot 62 is not included. In this way, since the area where the first graphic is provided does not overlap with the area where the second graphic is provided, the influence of the other graphic can be suppressed during the identification operation of either graphic. It becomes.

  In the present embodiment, the first graphic and the second graphic are formed by an assembly of a plurality of dot-shaped concave portions. Therefore, when laminating the dry film resist on the insulator layer, the dry film resist can be prevented from entering each dot. For this reason, it is possible to obtain an effect of suppressing the positioning mark identification failure due to the dry film resist entering the positioning mark and the positional deviation of the identified positioning mark.

  In this embodiment, the first graphic provided on the inner side is used first, and the second graphic provided on the outer side is used when redoing the graphic identification operation. However, the reverse order is also possible. good. However, when the wiring board forming board expands and contracts, the effect of expansion and contraction becomes smaller in the figure having a smaller area. For this reason, it is more desirable to first use the inner figure (first figure) that can be expected to identify the figure with higher accuracy.

D. Second embodiment:
In the first embodiment, the same positioning marks 60 are formed at the four corners of the wiring board forming plate, but different configurations may be used. For example, the second is different in at least one of shape and size from the positioning mark 60 (hereinafter also referred to as the first positioning mark 60) provided at any of the four corners of the wiring board formation at the other location. The positioning mark may be formed. Such a configuration will be described as a second embodiment.

  FIG. 7 is an explanatory diagram showing an example of a second positioning mark 160 having a shape different from that of the first positioning mark 60 shown in FIG. The second positioning mark 160 differs from the first positioning mark 60 in that the diameter of the first dots 61 constituting the first graphic is smaller than the diameter of the second dots 162 constituting the second graphic. ing. In the wiring board forming board of the second embodiment, such a second positioning mark 160 is formed at one of the four corners, and the first positioning mark 60 is formed at the other part. In the second positioning mark, instead of the above-described configuration, the diameter of the first dots constituting the first graphic may be larger than the diameter of the second dots constituting the second graphic.

  When such a second positioning mark 160 is used, when identifying the first or second graphic in step S310 or step S330, a graphic that is different from the other parts at a predetermined position in the four corners. It may be determined at the same time whether or not (the graphic provided in the positioning mark 160) is identified. With such a configuration, an error is recognized even when the wiring board forming plate is arranged in an incorrect direction (for example, reverse direction) during the positioning and positioning operations of the wiring board forming plate. It becomes possible. Therefore, it is possible to suppress patterning in the wrong direction.

  The second positioning mark can be variously modified as long as at least one of the shape and the size is different from that of the first positioning mark, and the same effect as the second embodiment shown in FIG. 7 can be obtained. can get. For example, in the second positioning mark, at least one of the diameters of the first dots constituting the first graphic and the second dots constituting the second graphic corresponds to the first corresponding to the first positioning mark 60. You may form larger than the dot 61 or the 2nd dot 62, or smaller. Further, instead of the configuration in which the diameter of the dots is changed or in addition to the configuration in which the diameter of the dots is changed, the diameters of the circle In and the circle Out specified by the constituent dots in each figure are determined from the first positioning mark 60. May be larger or smaller. Further, the first positioning mark and the second positioning mark may be different in both shape and size.

  It should be noted that the positions of the positioning marks that are different in shape and size from the other positioning marks may be two in the four corners, but preferably one. If there is only one place, for example, the wiring board forming plate has a substantially square shape, and even if it can be arranged in any orientation during the alignment operation, it becomes easy to notice an orientation error.

E. Third embodiment:
As described above, when the second conductor layer CL2 or the third conductor layer CL3 is formed on the first surface S1 of the plate core 20, the positioning mark is also formed on the second surface S2. It is also used when forming the layer CL5 or the sixth conductor layer CL6. Therefore, the positioning mark used for alignment when forming the conductor layer on the first surface S1 and the positioning mark used for alignment when forming the conductor layer on the second surface S2 are shaped and large. At least one of them may be different. With such a configuration, it is possible to recognize an error even when the wiring board forming plate is mistakenly arranged on the front and back sides when positioning and positioning the wiring board forming plate. . Therefore, it is possible to suppress patterning on the wrong surface.

  Here, as an example of the configuration in which the shape of the positioning mark is different between the front and back, for example, the first positioning mark 60 shown in FIG. In this surface, a configuration in which the second positioning marks 160 shown in FIG. 7 are formed at the four corners. Also, as a configuration in which the size of the positioning mark is different between the front and back, the diameter of each dot provided in the positioning mark formed on one surface is made larger than the diameter of each dot provided in the positioning mark formed on the other surface. A configuration can be mentioned. Alternatively, the diameter of the circle In and the circle Out in the positioning mark formed on one surface may be larger than the diameter of the circle In and the circle Out in the positioning mark formed on the other surface. Further, the positioning mark formed on one surface and the positioning mark formed on the other surface may be different in both shape and size.

  Further, the third embodiment and the second embodiment may be combined. That is, on each surface, a positioning mark having a shape and a size different from that of a positioning mark provided at another location is provided at any one of the four corners. Then, the shape and size of the positioning mark provided at the corresponding position may be different between one surface and the other surface of the wiring board forming plate. With such a configuration, it is possible to easily recognize an error in the orientation of the wiring board forming plate and an error in the front and back during the alignment operation of the wiring board forming plate.

F. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

F1. Modification 1 (Modification of the structure of the positioning mark):
In the first to third embodiments, the positioning marks are a first graphic that is an aggregate of the first dots that can identify the circle In and a second graphic that is an aggregate of the second dots that can identify the circle Out. Although it is a combination, it may have a different configuration. FIG. 8 is an explanatory diagram showing the configuration of a positioning mark 260 as an example of a positioning mark having a figure that does not specify a circle.

  As shown in FIG. 8, the positioning mark 260 is similar to the positioning mark 60, and includes a first figure that is an aggregate of a plurality (9 in FIG. 8) of the first dots 61 and a plurality of (8 in FIG. ) Of the second dot 62, and a second graphic. Similar to the positioning marks 60, the second dots 62 are arranged on the circumference of the circle Out. The first dots 61 are arranged on the cross In indicated by the alternate long and short dash line in FIG. When such a positioning mark 260 is used, when the first graphic is identified in step S320, for example, the center of each first dot 61 is obtained and the center of each first dot 61 is connected. The center O of the cruciform In (specified by the first dot 61) may be derived. Further, when the second graphic is identified in step S330, the center of each second dot 62 is obtained, and the center of the circle Out obtained by connecting the centers of the second dots 62 may be derived.

  Even when the positioning mark 260 as described above is used, the same effect as in the first embodiment can be obtained. That is, the reliability of the operation of recognizing the positioning mark and aligning the wiring board forming plate can be improved. Further, by forming each figure as an aggregate of a plurality of dots, it is possible to suppress the occurrence of misalignment due to the dry film resist entering the positioning mark. In addition, the second dot 62 is not included in the area A2 formed by connecting the first dots 61 constituting the first graphic (defined so that all the first dots 61 are included therein). In the operation of identifying one of the figures, the influence of the other figure can be suppressed.

  In FIG. 8, the dots forming the second graphic are not included in the region formed by connecting the dots forming the first graphic, but may be configured differently. For example, a common dot may exist between the first graphic and the second graphic. In this case, in the area formed by connecting the dots constituting one of the first figure and the second figure, the other one other than the common dots common to the dots constituting the other figure The dots constituting the figure may not be included. FIG. 9 is an explanatory diagram showing the configuration of a positioning mark 360 which is an example of such a positioning mark.

  In the positioning mark 360 shown in FIG. 9, the first graphic is an aggregate of the first dots 61 and the common dots 63, and the second graphic is an aggregate of the second dots 62 and the common dots 63. The area A3 formed by connecting the first dot 61 and the common dot 63 constituting the first graphic does not include the second dots 62 other than the common dot 63 constituting the second graphic. When such a positioning mark 360 is used, when the first graphic is identified in step S320, for example, the centers of the first dots 61 and the common dots 63 are obtained, and the first dots 61 and the common dots 63 are obtained. What is necessary is just to derive the center O of the cross In obtained by connecting the centers of 63. When identifying the second graphic in step S330, the center of each second dot 62 and common dot 63 is obtained, and the circle Out obtained by connecting the centers of each second dot 62 and common dot 63 is obtained. What is necessary is just to derive a center. Even in such a configuration, since the dots constituting each of the first graphic and the second graphic are arranged in different regions except for the common dot 63, at the time of the identification operation of either one of the graphics It is possible to suppress the influence of the other graphic.

  In the positioning marks 60, 160, 260, and 360, the first graphic and the second graphic share the same center O as the center, but the center of the first graphic and the center of the second graphic are different. It may be a position. Moreover, it is good also as a structure other than arrange | positioning one figure in the internal area | region of the other figure. Further, positioning may be performed by obtaining a specific point other than the center of each figure that can be uniquely derived from each figure. Alternatively, the cross-sectional shape of the dots constituting each figure may be a shape other than a circle. Regardless of the configuration, the first graphic and the second graphic are provided in the vicinity of one positioning mark, so that the movement of the imaging device is suppressed and the positioning mark identification operation is performed again. It becomes possible to do. When obtaining the center of each figure, the center of the figure can be the center of rotation when the figure is rotationally symmetric.

  In addition, the positioning marks 60, 160, 260, and 360 include the first graphic and the second graphic, but may include three or more graphics. In this case, it is possible to repeat the positioning operation twice or more by sequentially identifying three or more figures in the same manner as in the embodiment.

  Further, the positions where the positioning marks are provided on the wiring board component board may be two or three of the four corners instead of all four corners. Alternatively, at least one of the positioning marks provided at a plurality of locations on the surface of the wiring board forming plate may be provided at a location other than any of the four corners.

F2. Modified example 2 (modified wiring board manufacturing process):
In the first to third embodiments, the positioning mark provided on the insulator layer is used for patterning the resist layer in step S150 and the like, and a dry film resist is used as the resist layer. It may be used. Even in the case of using a liquid resist, if the resist layer is formed so as to cover the positioning mark, the resist layer may be uneven on the positioning mark when the resist is dried, and displacement may occur when the positioning mark is identified. Therefore, by using a positioning mark including a figure that is an aggregate of dots, it is possible to suppress misalignment caused by unevenness generated in the resist layer.

  In the first to third embodiments, the positioning mark is imaged with reflected light. However, the positioning mark according to the present application can also be applied when imaging with transmitted light. In the first to third embodiments, contact exposure is performed in which an exposure mask is brought into close contact with the wiring board forming plate. However, non-contact exposure (for example, proximity exposure or projection exposure) may be employed. good. Even when non-contact exposure is employed, the positioning mark according to the present application can be applied to alignment during exposure. Furthermore, a direct drawing exposure method in which a wiring pattern is directly drawn on a resist layer with a laser beam or the like based on data stored in advance without using an exposure mask may be employed. In any case, by applying the positioning mark of the present invention at the time of positioning for wiring patterning, the same effect as improving the reliability of the operation of positioning the wiring board forming plate can be obtained. It is done. In the case of adopting the direct drawing exposure method, the measures described in the second or third embodiment are adopted because countermeasures against the orientation of the wiring board forming plate and the front and back errors at the time of exposure are particularly important. It is desirable to do.

  In the first to third embodiments, the semi-additive method is used when patterning the wiring (conductor layer). However, a full additive method or a subtractive method may be used. Also in this case, the positioning mark according to the present application can be used when positioning the wiring board forming plate for patterning.

F3. Modification 3 (deformation of the wiring board):
The wiring substrate obtained by the manufacturing method described in the first to third embodiments is a printed wiring substrate (so-called organic substrate, what is called an organic package) including a plate-like core 20 and a resin insulator layer as an insulator layer. However, the present invention may be applied to different types of wiring boards. In addition, the present invention may be applied in a manufacturing process of a wiring board other than a multilayer board manufactured by a build-up method. For example, in the case of a printed wiring board (ceramic wiring board) having a ceramic layer as an insulator layer, for alignment when arranging a mask for forming a wiring pattern on a green sheet to be a ceramic insulator layer The positioning may be performed by forming a positioning mark similar to the embodiment on the green sheet. The present invention can be widely applied in alignment for patterning when manufacturing a wiring board.

DESCRIPTION OF SYMBOLS 10 ... Wiring board 15 ... Connection wiring board 20 ... Plate-shaped core 22 ... Through-hole 24 ... Through-hole conductor 26 ... Filler material 30, 32, 40, 42 ... Via conductor 30h, 32h, 40h ... Via hole 34, 44 ... Metal terminal Pad 36, 46 ... Solder resist layer 36a ... Opening 38 ... Solder bump 50 ... Chip mounting area 60, 160, 260, 360 ... Positioning mark 61 ... First dot 62, 162 ... Second dot 63 ... Common dot

Claims (8)

A method for manufacturing a wiring board, comprising:
(A) forming a first positioning mark including a first graphic and a second graphic on a wiring board forming plate for forming the wiring board;
(B) a step in which the positioning device performs an operation of identifying the first graphic;
(C) When the positioning device determines that the first graphic cannot be identified in the step (B), an operation of identifying the second graphic;
(D) When the positioning device determines that the first graphic can be identified in the step (B), the wiring board forming board is based on the position of the first graphic identified in the step (B). When it is determined that the first graphic cannot be identified in the step (B), the wiring board forming board is positioned based on the second graphic identified in the step (C). Process,
A method of manufacturing a wiring board comprising: It is a manufacturing method of the wiring board according to claim 1,
Each of the first graphic and the second graphic includes a plurality of dots, and a dot constituting the second graphic is formed in an area formed by connecting dots constituting the first graphic. A method for manufacturing a wiring board, which is not included. It is a manufacturing method of the wiring board according to claim 1,
Each of the first graphic and the second graphic includes a plurality of dots, and constitutes the other graphic of the dots constituting one graphic of the first graphic and the second graphic. A method of manufacturing a wiring board, wherein a dot other than the common dots constituting the other graphic is not included in an area formed by connecting dots other than the common dots common to the dots. A method for manufacturing a wiring board according to any one of claims 1 to 3,
The operation of identifying the first graphic in the step (B) is an operation of identifying the position of the first graphic by obtaining the center of the first graphic,
The operation of identifying the second graphic in the step (C) is an operation of identifying the position of the second graphic by obtaining the center of the second graphic. It is a manufacturing method of the wiring board according to claim 4,
A method of manufacturing a wiring board, wherein the center of the first graphic and the center of the second graphic are at the same position. A method for manufacturing a wiring board according to any one of claims 1 to 5,
In the step (A), the second positioning is different from the first positioning mark at any one of the four corners of the wiring board forming plate formed in a rectangular shape. A method for manufacturing a wiring board, comprising forming a mark and forming the first positioning mark at one or more locations in the four corners where the second positioning mark is not formed. It is a manufacturing method of the wiring board in any one of Claims 1 thru | or 6, Comprising:
In the step (A), the first positioning mark is formed on one surface of the wiring board forming plate, and the first positioning mark is formed on the other surface of the wiring board forming plate. Forming a third positioning mark having at least one of a shape and a size different from each other,
In the step (D), when the first or second graphic constituting the first positioning mark is identified, positioning is performed on the one surface of the wiring board forming plate. Method. A method for manufacturing a wiring board according to any one of claims 1 to 7,
The step (A) is a step of excavating an insulator layer formed on the surface of the wiring board forming plate to form the first positioning mark,
In the step (B), prior to the operation of identifying the first graphic, a resist layer covering the surface of the wiring board forming plate including the first positioning mark is further formed on the wiring board forming board. Comprising the step of forming,
After the positioning is performed in the step (D), the step (E) of performing exposure of the resist layer based on the positioning result is performed.

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