JP2007012894A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a pattern for peeling-off prevention that can correspond to the further microfabrication of a wiring layer and the reduction of a dielectric constant of an interlayer insulating film, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device having a multilayered wiring structure is composed so that a plurality of insulating films 2-7 are formed on a semiconductor substrate 1, wiring 32, 42, 52, 62, and 72 embedded in a plurality of the insulating films 3-7 are provided, and a plurality of the insulating films 3, 4 are those using materials having low dielectric constants. A through-hole penetrating all the insulating films 2-7 is formed at the corner of the semiconductor device. A through-via 10 is formed at the whole through-hole. By this, it is possible to prevent the insulating films from peeling off. Effects of the peeling-off prevention are significant since the through-via does not have a part where a via and the wiring are connected with a cap layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure using a low dielectric constant material for an insulating film, and more particularly to a semiconductor device capable of preventing peeling of the insulating film due to mechanical or thermal stress and a method for manufacturing the same. It is.

  As the digital society progresses, there is a growing demand for higher functionality and higher speed of semiconductor devices. Along with the large scale and high integration of such semiconductor devices, the number of wiring layers and the size of wiring layers are increasing. In recent years, low dielectric constant materials with lower dielectric constants than conventional oxide dielectrics such as silicon oxide films and silicon nitride films in order to suppress parasitic capacitance caused by miniaturization of wiring and to cope with higher speed of semiconductor devices Has been used for insulating films. Low dielectric constant materials have significant differences in physical properties such as low Young's modulus, low hardness, high coefficient of thermal expansion, and low adhesion at the insulating film interface compared to conventional oxide film dielectrics. The difference in physical characteristics increases as the dielectric constant decreases.

  For this reason, in a semiconductor device using a low dielectric constant material, peeling occurs at the boundary surface of the insulating film at the chip corner portion due to thermal stress at the time of sealing or after sealing. In particular, such delamination is likely to occur at the interface between an oxide dielectric dielectric film and a low dielectric constant material dielectric film having different physical characteristics. The separation of the insulating film causes leakage between wires and disconnection, which is fatal for the semiconductor device.

  As a method for preventing the peeling of the insulating film at the chip corner, there is a method in which wiring that is not connected to the internal circuit is arranged in the wiring layer, and a wiring pattern in which the wiring is connected by vias is arranged in the chip corner and strengthened. is there. Hereinafter, the wiring pattern will be described with reference to FIGS. 10 and 11 using a dual damascene process as an example.

  FIG. 10 is a cross-sectional view of wiring and vias. As shown in FIG. 10, there is a cap layer 100 such as a SiC film between the insulating film 2a and the insulating film 3a, between the wiring 32a and the insulating film 3a, between the via 31a and the insulating film 3a, and between the via 31a and the lower layer wiring 22a. Has a barrier metal 101 such as TaN. Compared with the adhesiveness between the insulating film 2a and the cap layer 100 between the insulating film 3a, the connection at the TaN film 101 between the via 31a and the lower layer wiring 22a has high adhesiveness. Therefore, the wiring pattern in which the wirings 22a and 32a are connected by the via 31a can prevent the insulating films 3a and 2a from peeling off and progressing.

  FIG. 11 is a cross-sectional view of a chip corner portion where a wiring pattern for preventing peeling is arranged. 1 is a semiconductor substrate, 2 to 7 are insulating films, 8 is a seal ring, 9 is an internal circuit, 21 is a contact plug, 31, 41, 51, 61 and 71 are vias, 32, 42, 52, 62 and 72 are wiring It is. Reference numeral 17 denotes a wiring that is not connected to the internal circuit of the peeling prevention wiring pattern and its connection via. The seal ring 8, the wiring not connected to the internal circuit 9 and the connection via 17 are made of the same layer as the wiring layer constituting the internal circuit 9.

As shown in FIG. 12A, the wiring pattern is formed by forming an insulating film by CVD and simultaneously forming the via hole and the wiring groove of the internal circuit 9 by etching to form the wiring groove and the via hole of the wiring pattern 17. Then, as shown in FIG. 12B, the wiring and vias of the wiring pattern 17 are formed simultaneously with the formation of the vias and wirings of the internal circuit 9 by electrolytic plating.
JP 2004-153015 A

  The miniaturization of wiring layers and the reduction of dielectric constant of insulating films continue to advance. When the wiring layer is further miniaturized, the wiring pattern of the chip corner portion for preventing peeling is formed at the same time as the internal circuit. Therefore, the via of the wiring pattern for preventing peeling is also miniaturized. As a result, since the wiring and via are originally connected by the cap layer, the connection area between the via and the wiring, which is a weak part, is smaller than that of the single wiring part and via, and the effect of preventing the peeling of the wiring pattern is achieved. It becomes weak. Further, by using a material having a lower dielectric constant for the insulating film, the adhesion is deteriorated and the thermal stress applied to the insulating film is increased. For this reason, even if the wiring pattern is arranged at the corner, the insulating film is peeled off.

  Accordingly, an object of the present invention is to provide a semiconductor device having an anti-peeling pattern that can cope with further miniaturization of a wiring layer and a lower dielectric constant of an insulating film, and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a plurality of insulating films stacked on a semiconductor substrate, and wiring embedded in at least a part of the plurality of insulating films, A semiconductor device having a multilayer wiring structure using a low dielectric constant material for some or all of a plurality of insulating films,
The corner portion of the semiconductor device has a through hole penetrating all the insulating films, and the entire through hole has a through via.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a plurality of insulating films stacked on a semiconductor substrate; and a wiring embedded in at least a part of the plurality of insulating films. A semiconductor device having a multilayer wiring structure using a dielectric constant material,
The corner portion of the semiconductor device has a through hole penetrating all the insulating films and the semiconductor substrate, and the entire through hole has a through via.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: a plurality of insulating films stacked on a semiconductor substrate; and a wiring embedded in at least a part of the plurality of insulating films. A semiconductor device having a multilayer wiring structure using a dielectric constant material,
The corner portion of the semiconductor device has a through hole that penetrates all of the insulating film, and the through end portion reaches the inside of the semiconductor substrate but does not penetrate, and the entire through hole has a through via.

The semiconductor device according to claim 4 includes a plurality of insulating films stacked on a semiconductor substrate and wiring embedded in at least a part of the plurality of insulating films, and the plurality of insulating films include a low dielectric constant material. A semiconductor device having a multilayer wiring structure using a plurality of types of materials,
A corner portion of the semiconductor device has a through-hole penetrating a plurality of types of insulating films among a plurality of insulating films,
A through via is provided in the entire through hole.

  According to a fifth aspect of the present invention, in the through via according to the first, second, third, or fourth aspect, the through via is disposed outside the seal ring.

  According to a sixth aspect of the present invention, in the through via according to the first, second, third, fourth, or fifth aspect, the through via has a wiring in the uppermost layer of the through via.

  According to a seventh aspect of the present invention, in the through via according to the first, second, third, fourth, fifth, or sixth aspect, the through via is formed of an insulator.

  A semiconductor device according to an eighth aspect is the semiconductor device according to any one of the first to seventh aspects, wherein the plurality of insulating films use a low dielectric constant material for a part or all of them.

10. The method of manufacturing a semiconductor device according to claim 9, wherein a step of forming an insulating film on the semiconductor substrate, a step of forming a via hole in the insulating film, a step of forming a wiring groove in the insulating film, and a via in the via hole A method of manufacturing a semiconductor device, including a step of forming a wiring and a step of forming a wiring in a wiring groove, and forming a multilayer wiring structure in which a plurality of insulating films are stacked by repeating each step,
A through hole penetrating a part or all of the insulating film is collectively formed in a corner portion of the semiconductor device, and a through via is formed in the entire through hole.

11. The method of manufacturing a semiconductor device according to claim 10, wherein a step of forming an insulating film on the semiconductor substrate, a step of forming a via hole in the insulating film, a step of forming a wiring groove in the insulating film, and a via in the via hole A method of manufacturing a semiconductor device, including a step of forming a wiring and a step of forming a wiring in a wiring groove, and forming a multilayer wiring structure in which a plurality of insulating films are stacked by repeating each step,
Through holes that penetrate part or all of the insulating film are formed part by part for each insulating film at the same time as the formation of via holes and wiring grooves at the corners of the semiconductor device.
A through via is formed in the entire through hole.

  According to the semiconductor device of the first aspect of the present invention, the corner portion of the semiconductor device has a through-hole penetrating all the insulating films, and the through-via formed in the through-hole at the same time. Progress can be prevented. Furthermore, the through vias formed in a lump that is a pattern for preventing peeling does not have a portion where the via and the wiring are connected by the cap layer, so the strength is stronger than the wiring pattern in which the wiring is connected by the via, and the effect of preventing peeling is large.

  According to the semiconductor device of the second aspect, since the corner portion of the semiconductor device has the through holes penetrating all the insulating films and the semiconductor substrate, and the through vias formed in the through holes at once, Since the connection with the via is not the connection with the cap layer, and the connection area between the through via and the semiconductor substrate is widened, not only the insulation film is peeled off but also the effect of preventing the occurrence and progress of the peeling of the semiconductor substrate and the insulation film. Can be increased.

  According to a third aspect of the present invention, the semiconductor device has a through-hole that penetrates all the insulating films in the corner portion of the semiconductor device and reaches a part of the semiconductor substrate but does not penetrate. Since the through vias formed in a lump are provided, it is possible to prevent the peeling of the insulating film and the peeling and peeling of the semiconductor substrate and the insulating film. Further, since the through via is not so long as to penetrate the semiconductor substrate, the through hole and the through via can be easily formed with a relatively small size and high accuracy.

  According to the semiconductor device of the fourth aspect, the corner portion of the semiconductor device has a through-hole penetrating a plurality of types of insulating films, and has a through-via formed in the through-hole at a time, so peeling is likely to occur. Separation of the boundary surface between different types of insulating films can be prevented with a minimum number of through-vias, and the through-holes and the through-vias can be easily formed with high precision and accuracy.

  According to the semiconductor device of the fifth aspect, since the through via is arranged outside the seal ring, the through via is arranged near the corner of the semiconductor device that is a starting point of the peeling, compared to the case where the through via is arranged in the seal ring. Thus, the effect of preventing peeling can be strengthened.

  According to the semiconductor device of the sixth aspect, since the through via has a wiring structure in the uppermost layer, the insulating film is pressed from above, and the effect of preventing peeling can be strengthened.

  According to the semiconductor device of the seventh aspect, since the through via is formed of an insulator, the through via is not charged, and even if the wiring pattern of the internal circuit is formed near the through via, Will not be affected.

  According to the semiconductor device of the eighth aspect, since the peeling prevention effect is large, it is effective even when the insulating film is a low dielectric constant material.

  According to the method for manufacturing a semiconductor device according to claim 9, through holes penetrating a part or all of the insulating film of the multilayer wiring structure are collectively formed in the corner portion of the semiconductor device, and through vias are collectively formed in the through holes. Since they are formed, the sizes and compositions of the through holes and the vias are not affected by the sizes and compositions of the internal circuit vias and wiring layers.

  According to the method for manufacturing a semiconductor device according to claim 10, formation of a via hole of an internal circuit and formation of a wiring groove are formed in a corner portion of the semiconductor device with a through hole penetrating an insulating film of a part or all of the multilayer wiring structure. Since it is formed at the same time, a device capable of forming a deep through-hole is not required, and a through-hole penetrating all the insulating films can be formed by a device for forming a normal multilayer wiring structure.

  All the embodiments of the present invention will be described with reference to a dual damascene process semiconductor device in which the wiring layer is composed of, for example, a two-layer insulating film of a low dielectric constant material and a four-layer insulating film of an oxide dielectric.

  The structure of the 1st Embodiment of this invention is demonstrated using FIG. FIG. 1A is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1A, a seal ring 8 is disposed at the periphery of the semiconductor device region, and a through via 10 is disposed in the vicinity thereof. FIG. 1B is a schematic cross-sectional view along the line AA ′ of FIG. 1A showing the structure of the semiconductor device according to the first embodiment of the present invention. An internal circuit 9 is disposed inside the seal ring 8 and the through via 10. Insulating films 2, 3, 4, 5, 6, and 7 are stacked on a semiconductor substrate 1 on which a transistor is formed. The insulating films 3 and 4 have a laminated structure of an insulating film made of a low dielectric constant material and a cap layer such as SiC, and the insulating films 2, 5, 6, and 7 are oxide dielectric insulating films and cap layers. It has a structure. A contact plug 21 is embedded in the insulating film 2. Vias and wirings are embedded in the insulating films 3, 4, 5, 6, and 7, respectively. For example, vias 31 and wirings 32 are embedded in the insulating film 3. Similarly, in the other insulating films 4 to 7, 41, 51, 61, and 71 are vias, and 42, 52, 62, and 72 are wirings. Further, there is a barrier metal between the via and the wiring immediately below the via 41 and between the via 41 and the wiring 32, and between the via and wiring and the surrounding insulating film between the insulating film 3 and the via 31 / wiring 32. is there. The internal circuit 9 and the seal ring 8 are made of a combination of vias and wiring. The through via 10 penetrates all the insulating films 2 to 7, and there is a barrier metal between the insulating films 2 to 7 and the through via 10, and between the through via 10 and the semiconductor substrate 1.

  Next, the first manufacturing method of the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, as shown in FIG. 2A, a semiconductor device having a multilayer wiring structure having a plurality of insulating films is formed. The formation method depends on the material in the case of the wiring layer of the insulating film 3 made of the low dielectric constant material, but the insulating film made of the low dielectric material is formed by, for example, spin coating, and then the SiC of the cap layer is formed by, for example, CVD. A film is formed. Next, a via hole and a wiring groove are formed by photolithography and etching. Next, a barrier metal TaN film and a Cu seed film are formed by sputtering, for example. Next, a Cu film is deposited on the Cu seed film by electrolytic plating, and the via 31 and wiring 32 of the internal circuit 9 and the via and wiring of the seal ring 8 are formed. Next, the Cu film and the barrier metal are removed until the SiC film of the insulating film 3 is exposed by, for example, the CMP method. The wiring layer of the insulating film 4 made of a low dielectric constant material is formed in the same manner. In the case of the wiring layer of the oxide dielectric insulating film 5, an oxide dielectric insulating film is formed by, for example, a CVD method, and then, a cap layer SiC film is formed by, for example, the CVD method. Next, a via hole and a wiring groove are formed by photolithography and etching. Next, a barrier metal TaN film and a Cu seed film are formed by sputtering, for example. Next, a Cu film is deposited on the Cu seed film by electrolytic plating, and the via 51 and wiring 52 of the internal circuit 9 and the via and wiring of the seal ring 8 are formed. Next, the Cu film and the barrier metal are removed until the SiC film of the insulating film 5 is exposed, for example, by the CMP method. The wiring layers of the oxide dielectric insulating films 6 and 7 are formed in the same manner. The oxide dielectric insulating film 2 is formed in the same manner except that the wiring layer is not formed.

  As shown in FIG. 2B, for example, a Bosch process in which deep etching is performed by alternately forming etching and forming a protective film on a semiconductor device having a multilayer wiring structure having a plurality of insulating films formed as described above is used. Thus, the through holes 11 penetrating all the insulating films 2 to 7 are formed. If the Bosch process is used, it is possible to form a through hole having a width of 4 μm if the depth is 80 μm and a width of 25 μm if the depth is 180 μm. Since the total thickness of the insulating films 2 to 7 on the semiconductor substrate 1 is 10 μm to 20 μm, the through hole 11 having a size of 1 to 2 μm can be formed. Next, as shown in FIG. 2C, a barrier metal TaN film and a Cu seed film are formed by sputtering, for example. Next, a Cu film is deposited on the Cu seed film by electrolytic plating to form a through via 10.

  Next, the second manufacturing method of the semiconductor device according to the present embodiment will be explained with reference to FIGS. Since this manufacturing method is almost the same as the method for forming the semiconductor device having the multilayer wiring structure described in the first manufacturing method, only the differences will be described in detail. As shown in FIG. 3A, first, a via hole, a wiring groove, and a part of the through hole are formed in the insulating film 3 by photolithography and etching. Next, the via hole, the wiring groove, and a part of the through hole are filled with a material that can be easily etched, such as the resist film 33. The resist film is etched until the insulating film 3 is exposed. Next, only the resist film in the via hole and the wiring groove is etched by photolithography and etching. For example, a TaN film of barrier metal and a Cu seed film are formed by sputtering. Next, a Cu film is deposited on the Cu seed film by electrolytic plating to form a via and a wiring. Next, the Cu film and the barrier metal are removed until the SiC film of the insulating film 3 is exposed by, for example, the CMP method. By this method, as shown in FIG. 3B, the wiring 32 and the via 31 of the internal circuit 9 and a part of the through hole filled with a material that can be easily etched such as a resist film and the via and wiring of the seal ring 8 are formed. The By repeating this, a multilayer wiring structure is formed as shown in FIG. The insulating film 2 is formed in the same manner except that the wiring layer is not formed. Finally, the through holes can be formed by etching the resist films 23, 33, 43, 53, 63, and 73 buried in the through holes. Here, a TaN film of barrier metal and a Cu seed film are formed by sputtering. Next, a Cu film is deposited on the Cu seed film by electrolytic plating to form a through via.

The structure of the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 4, the through via 12 penetrates the semiconductor substrate 1.
The manufacturing method of the semiconductor device according to the present embodiment is almost the same as the first manufacturing method of the first embodiment. The difference is that deep etching by a Bosch process is performed to the final semiconductor substrate 1 having a thickness of 200 μm, for example. The through via 12 is formed there, and the through via 12 is exposed to the back surface during back grinding.

  The structure of the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a schematic sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 5, the through via 13 partially reaches the semiconductor substrate 1, but does not penetrate.

  The manufacturing method of the semiconductor device according to the present embodiment is substantially the same as the first manufacturing method of the first embodiment. The difference is that deep etching by a Bosch process is performed to a depth of, for example, 10 μm into the semiconductor substrate 1. The point is that a through via 13 is formed there.

  The structure of the fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a schematic sectional view showing the structure of a semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 6, the through via 14 penetrates the insulating film 2 made of an oxide dielectric and the insulating film 3 made of a low dielectric constant material.

  The first manufacturing method of the semiconductor device according to the present embodiment is almost the same as the first manufacturing method of the first embodiment, and the difference is that the deep etching by the Bosch process is performed after the formation of the insulating film 3, and there is This is the point at which the through via 14 is formed.

  The second manufacturing method of the semiconductor device according to the present embodiment is almost the same as the second manufacturing method of the first embodiment, and the difference is that an easily etched material such as a resist film embedded in the through hole is etched. Is performed after the insulating film 3 is formed, and the through via 14 is formed there.

  The structure of the fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 7, the through via 10 is disposed outside the seal ring 8. The fifth embodiment can also be applied to the other embodiments described above and the embodiments described later.

  The structure of the sixth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a plan view showing the structure of the semiconductor device according to the sixth embodiment of the present invention. FIG. 8B is a schematic cross-sectional view along the line BB ′ in FIG. In the first embodiment, as shown in FIG. 8B, the wiring 72 is formed in the uppermost layer portion of the through via 15. Note that the sixth embodiment can also be applied to the other embodiments described above and the embodiments described later.

  The structure of the seventh embodiment of the present invention will be described with reference to FIG. FIG. 9 is a schematic sectional view showing the structure of the semiconductor device according to the seventh embodiment of the present invention. In each of the embodiments described above, the through via 16 formed of an insulator is disposed as shown in FIG.

  The semiconductor device manufacturing method according to the present embodiment is the same as the first manufacturing method and the second manufacturing method of the first embodiment up to the formation of the through hole, and the through via 16 is an insulator. In the case of a dielectric film, the through via 16 is formed by CVD, and the oxide dielectric film formed on the insulating film 7 is removed by CMP, for example, until the insulating film 7 is exposed.

  In the above embodiment, only a part of the insulating film using the low dielectric constant material is used. However, in other embodiments except the fourth embodiment, the insulating film on the semiconductor substrate is entirely made of the low dielectric constant material. You may form by the insulating film using this.

  INDUSTRIAL APPLICABILITY The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have an effect that the effect of preventing the peeling of the insulating film in the multilayer wiring structure is large, and the semiconductor device in which the wiring using the low-dielectric material interlayer insulating film is miniaturized Useful for manufacturing.

(A) is a partial top view of the semiconductor device concerning the 1st Embodiment of this invention, (b) is the sectional view on the AA 'line of figure (a) which shows arrangement | positioning of a penetration via. It is process sectional drawing related to the 1st manufacturing method of the semiconductor device concerning the 1st Embodiment of this invention. It is process sectional drawing concerning the 2nd manufacturing method of the semiconductor device concerning the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device concerning the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device concerning the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device concerning the 4th Embodiment of this invention. It is a top view of the semiconductor device concerning the 5th Embodiment of this invention. (A) is the fragmentary top view of the semiconductor device concerning the 6th Embodiment of this invention, (b) is the BB 'sectional view taken on the line. It is sectional drawing of the semiconductor device concerning the 7th Embodiment of this invention. It is a figure which shows the cross section of wiring and a via | veer. It is sectional drawing of the semiconductor device which has arrange | positioned the conventional wiring pattern of peeling prevention. It is process sectional drawing concerning the manufacturing method of the semiconductor device which has arrange | positioned the conventional wiring pattern of peeling prevention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 3, 4, 5, 6, 7 Insulating film 8 Seal ring 9 Internal circuit 10, 12, 13, 14, 15, 16 Through-via
11 Through-hole 17 Wiring pattern 21, 21 a, 31, 31 a, 41, 51, 61, 71 for preventing peeling Via 22, 22 a, 32, 32 a, 42, 52, 62, 72 Wiring 23, 33, 73 Resist film 100 Cap layer 101 Barrier metal

Claims (10)

A semiconductor device having a multilayer wiring structure comprising a plurality of insulating films stacked on a semiconductor substrate, and wiring embedded in at least a part of the plurality of insulating films,
A semiconductor device having a through hole penetrating all the insulating films in a corner portion of the semiconductor device, and having a through via in the entire through hole. A semiconductor device having a multilayer wiring structure comprising a plurality of insulating films stacked on a semiconductor substrate, and wiring embedded in at least a part of the plurality of insulating films,
A semiconductor device having a through hole penetrating all the insulating films and the semiconductor substrate in a corner portion of the semiconductor device, and having a through via in the entire through hole. A semiconductor device having a multilayer wiring structure comprising a plurality of insulating films stacked on a semiconductor substrate, and wiring embedded in at least a part of the plurality of insulating films,
The corner of the semiconductor device has a through hole that penetrates all of the insulating film and has a penetrating end that reaches the inside of the semiconductor substrate but does not penetrate, and the entire through hole has a through via. A semiconductor device. A semiconductor having a multilayer wiring structure comprising a plurality of insulating films stacked on a semiconductor substrate and wirings embedded in at least a part of the plurality of insulating films, wherein the plurality of insulating films use a plurality of types of materials A device,
The corner portion of the semiconductor device has a through-hole penetrating over a plurality of types of the insulating films among the plurality of insulating films,
A semiconductor device having a through via in the entire through hole.   5. The semiconductor device according to claim 1, 2, 3, or 4, wherein the through via is disposed outside the seal ring.   6. The semiconductor device according to claim 1, 2, 3, 4, or 5, wherein the through via has a wiring in an uppermost layer of the through via.   The semiconductor device according to claim 1, wherein the through via is formed of an insulator in the through via according to any one of claims 1, 2, 3, 4, 5, or 6.   The semiconductor device according to claim 1, wherein a low dielectric constant material is used for a part or all of the plurality of insulating films. Forming an insulating film on the semiconductor substrate; forming a via hole in the insulating film; forming a wiring groove in the insulating film; forming a via in the via hole; and the wiring groove Forming a wiring on the semiconductor device, and repeating the above steps to form a multilayer wiring structure in which a plurality of the insulating films are stacked,
A manufacturing method of a semiconductor device, wherein through holes penetrating a part or all of the insulating film are collectively formed in a corner portion of the semiconductor device, and a through via is formed in the entire through hole. Forming an insulating film on the semiconductor substrate; forming a via hole in the insulating film; forming a wiring groove in the insulating film; forming a via in the via hole; and the wiring groove Forming a wiring on the semiconductor device, and repeating the above steps to form a multilayer wiring structure in which a plurality of the insulating films are stacked,
Forming a through-hole penetrating a part or all of the insulating film for each insulating film at the same time as forming the via hole and the wiring groove in the corner portion of the semiconductor device;
A method of manufacturing a semiconductor device, wherein a through via is formed in the entire through hole.

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