JP2005327875A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of preventing the film peeling of an interlayer film and preventing a fault due to it. <P>SOLUTION: The semiconductor integrated circuit device comprises a semiconductor chip provided with the interlayer film, and an insulating film formed on the outer side of wiring provided inside the semiconductor chip and formed so as to cover the boundary of the interlayer film and the upper layer of the interlayer film, the boundary of the interlayer film and the lower layer of the interlayer film or the surface of a part where the interlayer film is removed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device.

  In recent years, delays in wiring portions (delays due to wiring resistance) have become prominent in LSIs due to progress in miniaturization. For this reason, copper (Cu) having lower wiring resistance has been used as a wiring material instead of conventional aluminum (Al).

  Furthermore, in order to reduce the wiring capacitance, a low dielectric constant (low-k) film having a low dielectric constant k and k ≦ 3.0 is laminated on the silicon substrate as an interlayer film, and is formed on the silicon substrate. It is possible to reduce crosstalk (electrical mutual interference) between the formed wirings.

  As such an LSI using a low-k film as an interlayer film, for example, the one disclosed in Patent Document 1 is known.

  According to Patent Document 1, a first insulating film containing at least one of H 2 O, OH, C, or hydrocarbon is formed, and the first insulating film is subjected to a heat treatment to thereby form the first insulating film. At least one of H 2 O, OH, C, or hydrocarbon is released from the first insulating film to form a porous insulating film, and a second insulating film is formed on the porous insulating film. An insulating film is formed and a low-k film is formed.

  According to the above conventional technique, by adopting the low-k film as the interlayer film, it is possible to reduce the capacitance between wirings and reduce the signal delay time.

  However, the low-k film has low adhesion strength with the film formed on the lower layer or the upper layer (for example, a diffusion prevention film), and film peeling is likely to occur at the interface between the low-k film and the lower-layer or upper layer of the low-k film. . Further, due to characteristics such as low density of the low-k film itself, film peeling easily occurs in the low-k film. This film peeling occurs even in a non-low-k interlayer film, for example, a film using SiO 2 as an interlayer film, but is more likely to occur when a low-k film is used as the interlayer film.

Therefore, if the LSI is damaged and film peeling occurs in the low-k film or at the interface with the lower or upper layer of the low-k film, the internal wiring of the LSI is disconnected due to the film peeling. It was. In particular, in the LSI dicing process, there is a problem that the end of the LSI facing the dicing line is damaged by dicing, and the interlayer film or the like is peeled off starting from this damage.
JP 2000-332010 A

  An object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing an interlayer film peeling of an LSI chip and preventing an LSI failure due to the interlayer film peeling.

  A semiconductor integrated circuit device according to an aspect of the present invention is formed outside a semiconductor chip including an interlayer film and a wiring provided in the semiconductor chip, and an interface between the interlayer film and an upper layer of the interlayer film, And an insulating film formed so as to cover an interface between the interlayer film and a lower layer of the interlayer film or a surface of a portion where the interlayer film is removed.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of preventing an LSI failure due to peeling of an interlayer film.

  Embodiments according to the present invention will be described below with reference to the drawings.

  An LSI according to a first embodiment of the present invention and a manufacturing method thereof will be described with reference to FIG. FIG. 1 shows a configuration example of an LSI according to the first embodiment of the present invention. FIG. 1 (a) is a top view of the LSI, and FIG. 1 (b) is an AA view of FIG. 1 (a). 'Cross-directional view, FIG.1 (c) is BB' direction sectional drawing of Fig.1 (a). Here, a case will be described in which the present invention is applied to an LSI having a two-layer Cu damascene wiring that employs a low dielectric constant (low-k) film having a dielectric constant k of k ≦ 3.0 as an interlayer film.

  In FIG. 1A, the LSI 10 has a reinforcing pattern 20, which is a restraining means for stopping the progress of the interlayer film peeling 40, arranged in a ring shape along the outer periphery of the LSI 10.

  As shown in FIG. 1B, the reinforcing pattern 20 includes an opening 20a having a depth reaching at least the first interlayer film 12, and an insulating film (SiO 2) 20b embedded in the opening 20a. It is the structure formed by.

  With reference to FIG. 1B, a manufacturing process of the LSI 10 including the reinforcing pattern 20 will be described. First, a first interlayer film 12 is deposited on a silicon (Si) substrate 11. A first wiring layer 21a made of Cu is formed on the first interlayer film 12 through a predetermined damascene process. A diffusion prevention film (for example, a SiCN film) 13 is deposited on the first wiring layer 21a and the first interlayer film 12, and then a low-k film (for example, a dielectric constant k is used as a second interlayer film). A SiOC film 14 having a low dielectric constant of k ≦ 3.0 is deposited. Thereafter, a via hole connected to the first wiring layer 21a is formed. Then, via a predetermined damascene wiring step, vias 21b and second wiring layer 21c are formed, and two layers of Cu damascene wiring 21 are formed. Thereafter, a diffusion prevention film 15 (for example, a SiCN film) is deposited. Subsequently, a passivation film 16 is deposited on the diffusion preventing film 15.

  Thereafter, an opening 20a having a depth reaching at least the first interlayer film 12 is formed in the outer peripheral portion of the LSI 10 by etching or laser. By this opening 20a, the interface between the diffusion prevention film 13 and the low-k film 14, the interface between the diffusion prevention film 15 and the low-k film 14, and the low-k film 14 are partially removed. From the surface, the low-k film 14, the interface between the diffusion prevention film 13 and the low-k film 14, and the interface between the diffusion prevention film 15 and the low-k film 14 are exposed. Further, an insulating film made of a material different from that of the low-k film 14, for example, a SiO 2 layer 20 b is deposited on the entire upper surface of the opening 20 a and the diffusion prevention film 15 by CVD or the like. At this time, the SiO2 layer 20b is deposited so as to cover at least the surface of the opening 20a, and the SiO2 layer 20b is deposited so that the low-k film 14 and other layers are not exposed from the opening 20a. Here, the SiO2 layer 20b is provided so as to be almost completely embedded in the opening 20a.

  Here, the opening 20a having a depth reaching at least the first interlayer film 12 is formed. This opening 20a is formed at the interface between the diffusion prevention film 13 and the low-k film 14, the diffusion prevention film 15, and the like. It may be formed by partially removing the interface with the low-k film 14 or the low-k film 14.

  In addition, although SiO 220b is deposited as the insulating film 20b covering the surface of the opening 20a, the insulating film is not limited to SiO 220b, and may be any insulating film having a lower hygroscopicity than the low-k film 14, such as SiN or polyimide. Good. Further, the insulating film 20b may be an insulating film that has stronger adhesion strength with the surface of the opening 20a than the low-k film 14.

  With the configuration as described above, even if the interlayer film peeling 40 occurs from the end portion (particularly, the corner portion) of the LSI 10, as shown in FIG. 1D, the interlayer film peeling 40 is caused by the opening 20a. It is possible to prevent the traveling to the inside of the opening 20a. Accordingly, not only at the time of assembly but also after the assembly process, LSI failure such as disconnection of the two-layer Cu damascene wiring 21 of the LSI 10 with the progress of the interlayer film peeling 40 can be prevented in advance. It is.

  If the opening 20a is formed so as to remove the interface between the diffusion prevention film 13 and the low-k film 14, film peeling at the interface between the low-k film 14 and the diffusion prevention film 13 can be suppressed. If the opening 20a is formed so as to partially remove the interface between the diffusion prevention film 15 and the low-k film 14, the opening 20a is formed at the interface between the low-k film 14 and the diffusion prevention film 15. The film peeling can be suppressed, and if the opening 20a is formed so as to remove a part of the low-k film 14, the film peeling in the low-k film 14 can be suppressed. Is possible. Note that the opening 20a shown in FIG. 1B suppresses film peeling at the interface between the diffusion prevention film 13 and the low-k film 14, and film peeling at the interface between the low-k film 14 and the diffusion prevention film 15. It is possible.

  Further, by covering the surface of the opening 20a with the SiO2 layer 20b, moisture enters the low-k film 14 exposed from the opening 20a to prevent a failure such as disconnection due to corrosion or the like of the two-layer Cu damascene wiring 21. Is possible.

  Further, as a reinforcing pattern 20 on the outer peripheral portion of the LSI 10, the opening 20a has a dielectric constant k higher than that of the low-k film 14 with k ≦ 3.0, for example, but SiO 2 that is an insulator with k = 4.2. Since the layer 20b is embedded, the performance as an interlayer insulating film of the LSI is not lost.

(Modification of Example 1)
An LSI manufacturing method according to a modification of the first embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.

  First, as in the first embodiment, a first interlayer film 12 is deposited on the Si substrate 11, and a first damascene wiring process is performed to form a first wiring layer 21a made of Cu. A diffusion prevention film (for example, SiCN film) 13 is deposited on the interlayer film 12 and the first wiring layer 21a.

  Subsequently, a first opening 20aa having a depth reaching the first interlayer film 12 is formed on the outer peripheral portion of the LSI 10 by etching, laser, or the like, and the first opening 20aa and the diffusion prevention film 13 are formed on the first opening 20aa. SiO2 is deposited on the entire surface by CVD. Thereafter, the surface is polished and planarized by CMP until the diffusion preventing film 13 is exposed. As a result, the first opening 20aa and the first SiO 2 layer 20ba that are part of the reinforcing pattern 20 are formed.

  Further, as in the first embodiment, a low-k film 14 as a second interlayer film is deposited on the diffusion prevention film 13 and the first SiO2 layer 20ba, and the via 21b and the second wiring layer 21c are deposited. After completing the two-layer Cu damascene wiring 21, a diffusion prevention film 15 is deposited.

  Next, a second opening 20ab connected to the first SiO2 layer 20ba is formed on the first SiO2 layer 20ba. At least a second opening 20ab is formed on the entire surface of the second opening 20ab and the diffusion prevention film 15. Then, SiO2 is deposited so as to cover the surface of the opening 20ab, and further polished by CMP until the diffusion prevention film 15 is exposed, thereby forming a second SiO2 layer 20bb. In this way, the reinforcing pattern 20 composed of the first opening 20aa and the first SiO2 layer 20ba and the second opening 20ab and the second SiO2 layer 20bb is completed.

  Thereafter, a passivation film 16 is formed on the entire surface of the diffusion preventing film 15 and the SiO2 layer 20bb.

  The LSI 10 produced by the manufacturing process of the modified example can be expected to have the same effect as the above-described embodiment by the reinforcing pattern 20 on the outer peripheral portion.

  Moreover, the manufacturing method according to the modified example is more effective when the area where the reinforcing pattern 20 can be arranged is small and the width of the reinforcing pattern 20 is small.

  That is, when the width of the reinforcing pattern 20 becomes fine, if the reinforcing pattern 20 is formed by the method described in the first embodiment, at least the low-k film 14 or the like exposed from the opening 20a having a high aspect ratio is formed. It becomes difficult to deposit the SiO2 layer 20b in the opening 20a so as to cover the surface. On the other hand, in the modified method, an opening is formed for each interlayer film, and SiO 2 is deposited in the opening. Therefore, the reinforcing pattern 20 can be easily formed as compared with the method of the embodiment.

  An LSI according to the second embodiment of the present invention will be described below with reference to FIGS. FIG. 3 shows an example of the structure of an LSI according to the second embodiment of the present invention. FIG. 3 (a) is a top view of the LSI, and FIG. 3 (b) is an AA view of FIG. 3 (a). FIG. 3C is a cross-sectional view in the direction of BB ′ in FIG. 3A, and FIG. 3D is a top view of the LSI when the interlayer film is peeled off from the corner portion. Here, a case will be described in which the present invention is applied to an LSI having a two-layer Cu damascene wiring that employs a low-k film as an interlayer film. In the drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 3A, the LSI 10 is provided with a dummy wiring pattern 80 having a ring-like structure as suppression means for stopping the progress of the interlayer film peeling 40 on the outer peripheral portion thereof. The dummy wiring pattern 80 is made of the same metal such as Cu as the two-layer Cu damascene wiring 21 that is the internal wiring of the LSI 10, but is electrically connected to the two-layer Cu damascene wiring 21 that is the internal wiring of the LSI 10. It has not been.

  As shown in FIG. 3B, the dummy wiring pattern 80 includes a first dummy wiring layer 80a provided in the first interlayer film 12 and a second dummy wiring provided in the low-k film 14. It has a structure comprising a layer 80c and a via 80b that reaches the first dummy wiring layer 80a from the second dummy wiring layer 80c through the first diffusion prevention film 13.

  FIG. 3C shows a cross-sectional view in the B-B ′ direction of FIG. As shown in FIG. 3C, the dummy wiring pattern 80 is such that the low-k film 14 is covered with the dummy wiring pattern 80 in a cross section when cut on the dummy wiring pattern 80 along the dummy wiring pattern 80. It is formed so that it may become a shape.

  By forming the dummy wiring pattern 80 on the four sides of the LSI 10, the low-k film 4 formed inside the dummy wiring pattern 80 by the dummy wiring pattern 80 is surrounded by the dummy wiring pattern 80. Shape.

  Thereby, the dummy wiring pattern is formed so that the low-k film 14 inside the dummy wiring pattern 80 and the low-k film 14 outside the dummy wiring pattern 80 do not come into contact with each other. It becomes possible to prevent problems such as moisture entering the formed low-k film 14 and corrosion or disconnection of the wiring of the LSI 10.

  FIG. 4 is a diagram illustrating an example of the dummy wiring pattern 80. 4 (a) to 4 (d) are enlarged views showing a plurality of types of dummy wiring patterns 80 in a part of the outer periphery of the LSI 10 surrounded by a broken-line circle in FIG. 3 (a). A dummy wiring pattern 80 shown in FIG. 4A has a wiring pattern meandering in a rectangular shape on the outer periphery of the LSI 10 and a linear wiring pattern on the inner side. A dummy wiring pattern 80 shown in FIG. 4B is obtained by arranging a plurality of wiring patterns meandering in a triangular shape in parallel. A dummy wiring pattern 80 shown in FIG. 4C is obtained by arranging a plurality of wiring patterns meandering in a rectangular shape in parallel. A dummy wiring pattern 80 shown in FIG. 4D is a plurality of linear wiring patterns arranged in parallel.

  The dummy wiring pattern 80 having the meandering wiring pattern shown in FIGS. 4A to 4C is dicing with the dummy wiring pattern 80 as compared with the linear dummy wiring pattern 80 shown in FIG. The area of the portion in contact with the damage 30 at the time is increased.

  Here, with reference to FIG. 3B, a manufacturing process of the LSI 10 including the dummy wiring pattern 80 will be described.

  First, the first interlayer film 12 is deposited on the Si substrate 11. A first damascene wiring layer 21a and a first dummy wiring layer 80a made of Cu are formed thereon through a predetermined damascene wiring process. A diffusion prevention film 13 is deposited thereon, and then a low-k film 14 as a second interlayer film is deposited. Thereafter, a contact via hole connected to the first wiring layer 21a and a contact via hole connected to the first dummy wiring layer 80a are formed. Then, a via 21b, a second wiring layer 21c, a via 80b, and a second dummy wiring layer 80c are formed through a predetermined damascene wiring process. As a result, the two-layer Cu damascene wiring 21 and the dummy wiring pattern 80 having substantially the same pattern as the two-layer Cu damascene wiring 21 are completed simultaneously.

  Thereafter, a diffusion prevention film 15 and a passivation film 16 are sequentially deposited. In this way, the LSI according to the present embodiment can be formed.

  In the LSI 10 produced by the manufacturing process described above, a dummy wiring pattern 80 having a ring-shaped structure on the outer peripheral portion is formed so as to cover the interface between the low-k film 14 and the diffusion prevention film 13. It becomes very strong against the interlayer film peeling 40 caused by the weak adhesion strength with the diffusion preventing film 13 due to the low density and the damage 30 caused by the dicing.

  As a result, even if the interlayer film peeling 40 occurs from the end portion (particularly corner portion) of the LSI 10, the interlayer film peeling 40 proceeds by the plurality of dummy wiring patterns 80 as shown in FIG. Can be stopped. Therefore, not only at the time of assembly but also after the assembly process, LSI failure such as disconnection of the two-layer Cu damascene wiring 21 inside the LSI 10 as the interlayer film peeling 40 progresses can be prevented. Is possible.

  Furthermore, by using a dummy wiring pattern 80 having a meandering wiring pattern as shown in FIGS. 4A to 4C, the area of the portion in contact with the damage 30 at the time of dicing is increased, and FIG. The interlayer film peeling 40 can be suppressed more firmly than the dummy wiring pattern 80 shown in FIG.

  Further, the dummy wiring pattern 80 is disposed along the outer periphery of the LSI 10 so as to cover the low-k film 14 inside the dummy wiring pattern 80 in a ring shape, thereby forming the low-k film 14 having high hygroscopicity. It is possible to prevent moisture and the like from being absorbed. Therefore, it is possible to prevent a failure such as a short circuit or disconnection due to a corrosion reaction of a metal such as the two-layer Cu damascene wiring 21.

  An LSI according to the third embodiment of the present invention will be described below with reference to FIG. FIG. 5 shows an example of the structure of an LSI according to the third embodiment of the present invention. FIG. 5A is a top view of the LSI 10, and FIGS. A corner portion enlarged view showing a plurality of examples of combinations of the corner guard 100 and the dummy wiring pattern 80 around the corner portion, FIG. 5 (f) is a corner portion enlarged view showing the shape of the corner guard 100, FIG. g) is a cross-sectional view in the AA ′ direction of FIG. Here, a case will be described in which the present invention is applied to an LSI having a two-layer Cu damascene wiring that employs a low-k film as an interlayer film. In this embodiment, a corner guard 100 is provided at the corner portion of the LSI shown in the second embodiment. In each figure, the same reference numerals are given to the same components as those in the first and second embodiments, and the description thereof will be omitted.

  In FIG. 5A, the LSI 10 is provided with a dummy wiring pattern 80 having a ring-like structure as a suppressing means for stopping the progress of the interlayer film peeling 40 on the outer peripheral portion, and each corner portion of the LSI 10 has a corner. A guard 100 is provided.

  As shown in FIG. 5G, the dummy wiring pattern 80 includes a first dummy wiring layer 80 a provided in the first interlayer film 12 and a second dummy wiring provided in the low-k film 14. It has a layer 80c and a two-layer damascene wiring 80 consisting of a via 80b extending from the second dummy wiring layer 80c through the first diffusion prevention film 13 to the first dummy wiring layer 80a.

  As shown in FIG. 5 (f), the corner guard 100 has a shape in which wirings are concentrated in the corner portion of the LSI 10, that is, a shape in which a large number of dummy wiring patterns 80 are spread in the corner portion of the LSI 10. As shown in FIGS. 5B to 5E, the corner guard 100 and the dummy wiring pattern 80 around the corner portion can be arranged.

  Note that the dummy wiring pattern 80 shown in FIGS. 4A to 4D and the corner guard 100 shown in FIGS. 5B to 5E may be combined. That is, the dummy wiring pattern 80 as shown in FIG. 4C is arranged as the dummy wiring pattern 80, the corner guard 100 as shown in FIG. It may be formed.

  Here, a manufacturing process of the LSI 10 including the dummy wiring pattern 80 and the corner guard 100 will be described with reference to FIG.

  First, the first interlayer film 12 is deposited on the Si substrate 11. A first damascene wiring layer 21a, a first dummy wiring layer 80a, and a first corner guard layer 100a made of Cu are formed thereon through a predetermined damascene wiring process. A diffusion prevention film (for example, a SiCN film) 13 is deposited thereon, and then a low-k film (for example, a SiOC having a low dielectric constant with a dielectric constant k of k ≦ 3.0 as a second interlayer film) Film) 14 is deposited. Thereafter, a contact via hole connected to the first wiring layer 21a, a contact via hole connected to the first dummy wiring layer 80a, and a contact via hole connected to the first corner guard layer 100a are formed. Then, via a predetermined damascene wiring process, the via 21b, the second wiring layer 21c, the via 80b, the second dummy wiring layer 80c, the via 100b, and the second corner guard layer 100c are formed. Thus, the two-layer Cu damascene wiring 21 and the dummy wiring pattern 80 and the corner guard 100, which are substantially the same pattern as the two-layer Cu damascene wiring 21, are completed at the same time.

  Thereafter, a diffusion prevention film 15 (for example, a SiCN film) and a passivation film 16 are sequentially deposited. In this way, the LSI according to the present embodiment can be formed.

  In the LSI 10 produced by the manufacturing process described above, a dummy wiring pattern 80 having a ring-shaped structure on the outer peripheral portion is formed so as to cover the interface between the low-k film 14 and the diffusion prevention film 13. It becomes very strong against the interlayer film peeling 40 caused by the weak adhesion strength with the diffusion preventing film 13 due to the low density and the damage 30 caused by the dicing.

  As a result, even if the interlayer film peeling 40 occurs from the end portion (particularly corner portion) of the LSI 10, it is possible to prevent the interlayer film peeling 40 from proceeding by the dummy wiring pattern 80. Therefore, not only during assembly but also after the assembly process, it is possible to prevent an LSI failure such as disconnection of the two-layer Cu damascene wiring 21 inside the LSI 10 with the progress of the interlayer film peeling 40. It becomes possible.

  Further, a corner guard 100 in which a plurality of dummy wiring patterns 80 are arranged is disposed at a corner portion of the LSI 10 that is easily damaged 30 caused by dicing and is likely to cause the interlayer film peeling 40. Thereby, it is possible to further suppress the generation of the interlayer film peeling 40 that occurs from the corner portion.

  The dummy wiring pattern 80 is disposed so as to surround the low-k film 14 in a ring shape along the outer periphery of the LSI 10, thereby preventing moisture and the like from being absorbed by the low-k film 14 having high hygroscopicity. be able to. Therefore, it is possible to prevent a failure such as a short circuit or disconnection due to a corrosion reaction of a metal such as the two-layer Cu damascene wiring 21.

  In this embodiment, as the corner guard 100, a dummy wiring pattern 80 having a shape in which a large number of dummy wiring patterns 80 are laid in the corner portion of the LSI 10 is used. However, the present invention is not limited to this. In this part, any material that can suppress the peeling of the low-k film 14 or can prevent moisture from entering the inside of the corner guard 100 may be used. For example, the corner guard of the LSI 10 may be provided with an opening 20a or a reinforcing pattern 20 as shown in the first embodiment to serve as a corner guard.

  Hereinafter, an LSI according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing an example of an LSI according to the fourth embodiment of the present invention. FIG. 6 (a) is a top view of the LSI, and FIG. 6 (b) is an AA view of FIG. 6 (a). 'Cross section. In this embodiment, the reinforcing pattern 20 shown in the first embodiment is arranged in a ring shape along the outer periphery of the semiconductor chip in the LSI shown in the second embodiment. In each figure, the same components as those in the first, second and third embodiments are designated by the same reference numerals, and the description thereof is omitted.

  In this embodiment, as shown in FIG. 6A, a ring-shaped dummy wiring pattern 80 formed so as to cover the low-k film 14 along the outer periphery of the LSI 10 is disposed on the outer periphery of the LSI 10. . Further, the reinforcing pattern 20 is arranged in a ring shape on the outer periphery of the LSI 10 outside the dummy wiring pattern 80.

  Here, with reference to FIG. 6B, a manufacturing process of the LSI 10 including the reinforcing pattern 20 and the dummy wiring pattern 80 will be described.

  First, the LSI 10 including the dummy wiring pattern 80 is formed outside the LSI 10 by the manufacturing method shown in the second embodiment.

  Thereafter, an opening 20a is formed in the outer periphery of the LSI 10 by etching or laser at the outer periphery of the dummy wiring pattern 80 as shown in the first embodiment, and the SiO2 layer 20b is formed in the opening 20a. The reinforcing pattern 20 is formed by deposition. As described above, the LSI according to this embodiment can be manufactured.

  Of course, the dummy wiring pattern 80 can be disposed as shown in FIGS.

  According to the fourth embodiment, even if the interlayer film peeling 40 occurs from the end portion (particularly, the corner portion) of the LSI 10, the interlayer film peeling 40 proceeds to the inside of the opening 20a by the opening 20a. Can be stopped. Accordingly, not only at the time of assembly but also after the assembly process, LSI failure such as disconnection of the two-layer Cu damascene wiring 21 of the LSI 10 with the progress of the interlayer film peeling 40 can be prevented in advance. It is.

  Further, by covering the surface of the opening 20a with the SiO2 layer 20b, moisture enters the low-k film 14 exposed from the opening 20a, thereby preventing failure such as disconnection due to corrosion of the two-layer Cu damascene wiring 21. It becomes possible.

  Further, a plurality of dummy wiring patterns 80 having a ring-shaped structure on the outer peripheral portion are formed so as to cover the interface between the low-k film 14 and the diffusion prevention film 13, and diffusion prevention due to the low density of the low-k film 14. It becomes very strong against the interlayer film peeling 40 caused by the weak adhesion strength with the film 13 and the damage 30 caused by dicing.

  Further, by arranging the dummy wiring pattern 80 so as to cover the low-k film 14 in a ring shape along the outer periphery of the LSI 10, moisture or the like is absorbed into the low-k film 14 having high hygroscopicity from the outside. Can be prevented. Therefore, it is possible to prevent a failure such as a short circuit or disconnection due to a corrosion reaction of a metal such as the two-layer Cu damascene wiring 21.

  Therefore, according to the present embodiment, by using both the reinforcing pattern 20 and the dummy wiring pattern 80, it becomes a suppression means for suppressing the progress of the interlayer film peeling 40.

(Modification of Example 4)
An LSI manufacturing method according to a modification of the fourth embodiment will be described with reference to FIG. FIG. 7 is a cross-sectional view taken along the line AA ′.

  First, as in the second embodiment, the first interlayer film 12 is deposited on the Si substrate 11, and after passing through a predetermined damascene wiring process, the first wiring layer 21a made of Cu and the first dummy wiring layer are formed. 80a, and a diffusion prevention film (for example, SiCN film) 13 is deposited on the first interlayer film 12 and the first wiring layer 21a.

  Subsequently, a first opening 20aa having a depth reaching the first interlayer film 12 is formed on the outer peripheral portion of the LSI 10 by etching, laser, or the like, and the first opening 20aa and the diffusion prevention film 13 are formed on the first opening 20aa. SiO2 is deposited on the entire surface by CVD. Thereafter, the surface is polished and planarized by CMP until the diffusion preventing film 13 is exposed. As a result, the first opening 20aa and the first SiO 2 layer 20ba that are part of the reinforcing pattern 20 are formed.

  Further, as in the second embodiment, a low-k film 14 as a second interlayer film is deposited on the diffusion prevention film 13 and the first SiO 2 layer 20ba, and contacts connected to the first wiring layer 21a. Via via 21b, second wiring layer 21c, contact via 80b connected to first dummy wiring layer 80a and second dummy wiring layer 80c to form two layers of Cu damascene wiring 21 and two layers of this After completing the dummy wiring 80 substantially the same as the Cu damascene wiring 21 at the same time, the diffusion prevention film 15 is deposited.

  Next, a second opening 20ab connected to the first SiO2 layer 20ba is formed on the first SiO2 layer 20ba. At least a second opening 20ab is formed on the entire surface of the second opening 20ab and the diffusion prevention film 15. Then, SiO2 is deposited so as to cover the surface of the opening 20ab, and further polished by CMP until the diffusion prevention film 15 is exposed, thereby forming a second SiO2 layer 20bb. In this way, the reinforcing pattern 20 composed of the first opening 20aa and the first SiO2 layer 20ba and the second opening 20ab and the second SiO2 layer 20bb is completed.

  Thereafter, a passivation film 16 is formed on the entire surface of the diffusion preventing film 15 and the SiO2 layer 20b.

  The LSI 10 produced by the manufacturing process of the modified example can be expected to have the same effect as the above-described embodiment by the reinforcing pattern 20 on the outer peripheral portion.

  The manufacturing method according to the modified example is more effective when the area where the reinforcing pattern 20 can be disposed is small and the width of the reinforcing pattern 20 is small. That is, when the width of the reinforcing pattern 20 becomes fine, if the reinforcing pattern 20 is formed by the method described in the fourth embodiment, at least the low-k film 14 exposed from the opening 20a having a high aspect ratio, etc. It becomes difficult to deposit the SiO2 layer 20b in the opening 20a so as to cover the surface. On the other hand, in the modified method, an opening is formed for each interlayer film, and SiO 2 is deposited in the opening. Therefore, the reinforcing pattern 20 can be easily formed as compared with the method of the embodiment.

  The LSI according to the fifth embodiment of the present invention will be described below with reference to FIG. FIG. 8 is a block diagram showing an example of an LSI according to a fifth embodiment of the present invention. FIG. 8A is a top view of the LSI, and FIG. 8B is an A-line in FIG. It is A 'sectional drawing. In this embodiment, the reinforcing pattern 20 shown in the first embodiment is arranged in a ring shape along the outer periphery of the semiconductor chip in the LSI shown in the third embodiment. In the drawings, the same components as those in the first to fourth embodiments are denoted by the same reference numerals, and the description thereof is omitted.

  In this embodiment, as shown in FIG. 8A, a dummy wiring pattern 80 is provided on the outer periphery of the LSI 10, and a corner guard 100 is formed at the corner of the LSI 10. Further, the reinforcing pattern 20 is arranged in a ring shape on the outer periphery of the LSI 10 outside the dummy wiring pattern 80 and the corner guard 100.

  Here, with reference to FIG. 8B, a manufacturing process of the LSI 10 including the reinforcing pattern 20, the dummy wiring pattern 80, and the corner guard 100 will be described.

  First, according to the manufacturing method shown in the third embodiment, a semiconductor integrated circuit device including the dummy wiring pattern 80 in the outer peripheral portion of the LSI 10 and the corner guard 100 in the corner portion of the LSI 10 is formed.

  Thereafter, an opening 20a is formed in the outer periphery of the LSI 10 by etching or laser at the outer periphery of the dummy wiring pattern 80 and the corner guard 100 as shown in the first embodiment. A SiO2 layer 20b is deposited on 20a. As described above, the LSI according to this embodiment can be manufactured.

  Of course, the dummy wiring pattern 80 can be arranged as shown in FIGS. 4A to 4D, and the corner guard 100 can be arranged as shown in FIGS. 5B to 5E. It is possible to arrange as described above.

  According to the fifth embodiment, even if the interlayer film peeling 40 occurs from the end part (particularly, the corner part) of the LSI 10, the interlayer film peeling 40 proceeds to the inside of the opening part 20a by the opening part 20a. Can be stopped. Accordingly, not only at the time of assembly but also after the assembly process, LSI failure such as disconnection of the two-layer Cu damascene wiring 21 of the LSI 10 with the progress of the interlayer film peeling 40 can be prevented in advance. It is.

  Further, by covering the surface of the opening 20a with the SiO2 layer 20b, moisture enters the low-k film 14 exposed from the opening 20a, thereby preventing failure such as disconnection due to corrosion of the two-layer Cu damascene wiring 21. It becomes possible.

  Further, a dummy wiring pattern 80 having a ring-shaped structure on the outer peripheral portion is formed so as to cover the interface between the low-k film 14 and the diffusion prevention film 13, and the diffusion prevention film 13 due to the low density of the low-k film 14. It becomes very strong against the interlayer film peeling 40 caused by the weak adhesion strength and the damage 30 caused by dicing.

  Further, the dummy wiring pattern 80 is disposed along the outer periphery of the LSI 10 so as to cover the low-k film 14 in a ring shape, thereby preventing moisture and the like from being absorbed into the low-k film 14 having high hygroscopicity. be able to. Therefore, it is possible to prevent a failure such as a short circuit or disconnection due to a corrosion reaction of a metal such as the two-layer Cu damascene wiring 21.

  Further, a corner guard 100 in which a plurality of dummy wiring patterns 80 are arranged is disposed at a corner portion of the LSI 10 that is easily damaged 30 caused by dicing and is likely to cause the interlayer film peeling 40. Thereby, it is possible to further suppress the generation of the interlayer film peeling 40 that occurs from the corner portion.

  Therefore, according to the present embodiment, by using the reinforcing pattern 20, the dummy wiring pattern 80, and the corner guard 100 together, the interlayer film peeling 40 due to damage during dicing can be suppressed.

(Modification of Example 5)
An LSI manufacturing method according to a modification of the fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view taken along line AA ′ of FIG. The LSI 10 including the reinforcing pattern 20, the dummy wiring pattern 80, and the corner guard 100 can also be formed as follows.

  With reference to FIG. 9, a manufacturing process of the LSI 10 including the reinforcing pattern 20, the dummy wiring pattern 80, and the corner guard 100 will be described.

  First, the first interlayer film 12 is deposited on the Si substrate 11. A first damascene wiring layer 21a, a first dummy wiring layer 80a, and a first corner guard layer 100a made of Cu are formed thereon through a predetermined damascene wiring process. Thereafter, a diffusion prevention film (for example, SiCN film) 13 is deposited on the entire surface on the first wiring layer 21a, the first dummy wiring layer 80a, and the first corner guard layer 100a.

  Thereafter, a first opening 20aa formed so as to at least partially eliminate the interface between the diffusion prevention film 13 and the low-k film 14 is formed on the outer peripheral portion of the LSI 10 by etching or laser. SiO2 is deposited on the entire surface of the opening 20aa and the diffusion barrier film 13 by the CVD method. Thereafter, the surface is polished and planarized by CMP until the diffusion preventing film 13 is exposed. Thereby, the first opening 20aa and the first SiO 2 layer 20ba, which are part of the reinforcing pattern 20, are formed.

  Subsequently, a low-k film (for example, a SiOC film having a low dielectric constant with a dielectric constant k of k ≦ 3.0) 14 is deposited as a second interlayer film. Thereafter, a contact via hole connected to the first wiring layer 21a, a contact via hole connected to the first dummy wiring layer 80a, and a contact via hole connected to the first corner guard layer 100a are formed. Then, via a predetermined damascene wiring process, the via 21b, the second wiring layer 21c, the via 80b, the second dummy wiring layer 80c, the via 100b, and the second corner guard layer 100c are formed. As a result, the two-layer Cu damascene wiring (two-layer Cu damascene wiring) 21 and the dummy wiring pattern 80 and the corner guard 100 that are substantially the same pattern as the two-layer Cu damascene wiring 21 are completed simultaneously. Thereafter, a diffusion preventing film 15 is deposited.

  Further, a second opening 20ab connected to the first SiO2 layer 20ba is formed on the first SiO2 layer 20ba, and at least the second opening 20ab and the entire surface of the diffusion prevention film 15 are formed on the second SiO2 layer 20ba. SiO2 is deposited so that the surface of the opening 20ab is covered with SiO2, and further polished by CMP until the diffusion prevention film 15 is exposed, thereby forming a second SiO2 layer 20bb. In this way, the reinforcing pattern 20 composed of the first opening 20aa and the first SiO2 layer 20ba and the second opening 20ab and the second SiO2 layer 20bb is completed. Thereafter, a passivation film 16 is deposited.

  In this way, an LSI having the reinforcing pattern 20, the dummy wiring pattern 80, and the corner guard 100 can be formed.

  The LSI manufacturing method according to the modified example of the fifth embodiment is effective when the area where the reinforcing pattern 20 can be arranged is small and the width of the reinforcing pattern 20 is small. That is, when the width of the reinforcing pattern 20 becomes fine, if the reinforcing pattern 20 is formed by the method described in the fifth embodiment, it is difficult to deposit SiO220b in the opening 20a having a high aspect ratio by the CVD method. Will come. At this time, an opening is formed for each interlayer film, and SiO 2 is deposited in the opening, so that the reinforcing pattern 20 can be easily formed as compared with the method of the embodiment.

1 is a configuration diagram showing an example of an LSI according to a first embodiment of the present invention. The block diagram which shows an example of LSI concerning the modification of the 1st Example of this invention. The block diagram which shows an example of LSI concerning the 2nd Example of this invention. The figure which shows an example of arrangement | positioning of the dummy wiring pattern which concerns on the 2nd Example of this invention. The figure which shows an example of arrangement | positioning of the corner guard which concerns on the 3rd Example of this invention. The block diagram which shows an example of LSI concerning the 4th Example of this invention. The block diagram which shows an example of the LSI which concerns on the modification of the 4th Example of this invention. The block diagram which shows an example of LSI concerning the 5th Example of this invention. The block diagram which shows an example of LSI which concerns on the modification of the 5th Example of this invention.

Explanation of symbols

10 LSI
11 Si substrate 12 First interlayer film 13, 15 Diffusion prevention film 14 low-k film (second interlayer film)
16 Passivation film 20 Reinforcement pattern 20a Opening 20b SiO2 layer (insulating film)
20aa 1st opening 20ab 2nd opening 20ba 1st SiO2 layer 20bb 2nd SiO2 layer 21 2 layer Cu damascene wiring 21a 1st wiring layer 21b Via 21c 2nd wiring layer 30 Damage 40 Interlayer film Stripping 80 Dummy wiring pattern 80a First dummy wiring layer 80b Via 80c Second dummy wiring layer 100 Corner guard 100a First corner guard layer 100b Via 100c Second corner guard layer

Claims (6)

A semiconductor chip with an interlayer film;
Formed outside the wiring provided in the semiconductor chip, the interface between the interlayer film and the upper layer of the interlayer film, the interface between the interlayer film and the lower layer of the interlayer film, or the portion where the interlayer film is removed A semiconductor integrated circuit device comprising: an insulating film formed to cover the surface. Further comprising a dummy wiring pattern formed outside the wiring provided in the semiconductor chip,
2. The semiconductor integrated circuit according to claim 1, wherein the dummy wiring pattern is formed so that the interlayer film inside the dummy wiring pattern does not contact the interlayer film outside the dummy wiring pattern. Circuit device. The semiconductor integrated circuit device according to claim 1, wherein a corner guard is provided at a corner portion of the semiconductor chip. Formed outside the wiring provided in the semiconductor chip, the interface between the interlayer film and the upper layer of the interlayer film, the interface between the interlayer film and the lower layer of the interlayer film, or the portion where the interlayer film is removed 4. The semiconductor integrated circuit device according to claim 1, wherein an insulating film formed so as to cover the surface is formed on an outer peripheral portion of the semiconductor chip. 5. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is an insulating film having lower hygroscopicity than the interlayer film. 6. 6. The semiconductor integrated circuit device according to claim 1, wherein the interlayer film is a low dielectric constant film.

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