JP2006114723A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, wherein a low dielectric constant film is used where failures will not occur due to film separation or cracks on an interface, in between an insulating film and an insulating film. <P>SOLUTION: A first wiring 106 is formed in a first insulating film 102 on a semiconductor substrate 101, and a second insulating film 107, a third insulating film 108, a fourth insulating film 109, and a fifth insulating film 110, are sequentially deposited on the first insulating film 102. Thereafter, a first through hole 112 is formed so as to thrust through, from the fifth insulating film 110 to the second insulating film 107 on the first wiring 106, and a second wiring 117 is formed in a second wiring groove 114, connecting to the first through hole 112. Also, a first prop 123 is formed in a second through hole 120 which thrusts through from the fifth insulating film 110 to the first insulating film 102. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a low dielectric constant film as an insulating film and a method for manufacturing the same.

  In recent years, with the high integration of semiconductor integrated circuits and the reduction in chip size, miniaturization of wiring and multilayer wiring have been promoted. As a result, the wiring interval is narrowed, and the wiring delay due to the increase in wiring resistance and capacitance cannot be ignored. For this reason, it is necessary to reduce the electric parasitic capacitance generated between the wirings in order to miniaturize the semiconductor integrated circuit. In order to reduce the electric parasitic capacitance between the wirings, it is necessary to reduce the relative dielectric constant of the interlayer insulating film or the specific resistance of the wiring material.

  In order to reduce the relative permittivity of the interlayer insulating film, a change from a silicon oxide film (relative permittivity: 4.2) to a fluorine-containing silicon oxide film (relative permittivity: 3.7) has been made. In particular, after 90 nm devices, an insulating film having a smaller relative dielectric constant than the fluorine-containing silicon oxide film (hereinafter referred to as a low dielectric constant film) is required. As the low dielectric constant film, a carbon-containing silicon oxide film or a coating film is used. An organic polymer or the like is used (see, for example, Patent Document 1 and Patent Document 2).

  FIG. 11 is a cross-sectional view showing a conventional semiconductor device using a low dielectric constant film.

  As shown in FIG. 11, a conventional semiconductor device using a low dielectric constant film includes an insulating film 2 formed on a semiconductor substrate 1 on which elements such as transistors are formed, and a wiring formed on the insulating film 2. A first wiring layer 51 including a first barrier metal 4 and a first wiring 6 made of a first metal film 5 embedded in a groove (not shown) is provided. Further, a second insulating film 7 formed on the insulating film 2 including the first wiring 6, a third insulating film 8 formed on the second insulating film 7, and a third insulating film A fourth insulating film 9 which is a low dielectric constant film formed on the film 8; a fifth insulating film 10 which is a low dielectric constant film formed on the fourth insulating film 9; A second barrier metal 15 and a second metal film 16 embedded in a wiring groove (not shown) formed in the fifth insulating film 10 and the fourth insulating film 9 on the upper part of the wiring 6. 2 wirings 17 and a first connection plug 18 integrally formed at the bottom of the second wiring 17 so as to electrically connect the first wiring 6 and the second wiring 17. A second wiring layer 52 is provided. In addition, a sixth insulating film 19 formed on the fifth insulating film 10 including the second wiring 17, a seventh insulating film 20 formed on the sixth insulating film 19, An eighth insulating film 21 that is a low dielectric constant film formed on the insulating film 20; a ninth insulating film 22 that is a low dielectric constant film formed on the eighth insulating film 21; A third barrier metal 27 and a third metal film 28 are embedded in a wiring groove (not shown) formed in the ninth insulating film 22 and the eighth insulating film 21 above the wiring 17. First wiring 29 and a second connection plug 30 integrally formed at the bottom of the third wiring 29 so as to electrically connect the second wiring 17 and the third wiring 29. 3 wiring layers 53 are provided.

  A conventional method for manufacturing a semiconductor device using a low dielectric constant film will be described below with reference to the drawings.

  FIG. 12A to FIG. 13C are cross-sectional views showing a manufacturing process of a semiconductor device using a conventional low dielectric constant film.

  First, as shown in FIG. 12A, a first wiring groove is formed on a first insulating film 2 formed on a semiconductor substrate 1 on which a semiconductor element such as a transistor is formed by photolithography and dry etching. 3 is formed.

  Next, as shown in FIG. 12B, tantalum nitride which becomes the first barrier metal 4 for preventing copper diffusion so as to fill the first wiring groove 3 on the first insulating film 2 by sputtering. A laminated film (not shown) of ride / tantalum and copper (not shown) to be the first metal film 5 are sequentially deposited. Thereafter, the multilayer film of copper and tantalum nitride / tantalum is polished by a CMP (Chemical Mechanical Polishing) method, and the multilayer film of copper and tantalum nitride / tantalum is formed in the first wiring groove 3. The first insulating film 2 is exposed to the part other than the first wiring groove 3 to leave the first wiring 6 composed of the first barrier metal 4 and the first metal film 5.

  Next, as shown in FIG. 12C, the second insulating film 7 and the third insulating film 8 are sequentially deposited on the first insulating film 2 including the first wiring 6 by the CVD method. .

  Next, as shown in FIG. 12D, a fourth insulating film 9 is deposited on the third insulating film 8 by the CVD method. Here, a low dielectric constant film is used as the fourth insulating film 9. Thereafter, the fourth insulating film 9 is polished and planarized by CMP.

  Next, as shown in FIG. 12E, a fifth insulating film 10 is deposited on the flattened fourth insulating film 9 by a CVD method. Here, a low dielectric constant film is used as the fifth insulating film 10.

  Next, as shown in FIG. 13A, a photoresist 11 having an opening above the first wiring 6 is formed on the fifth insulating film 10 by photolithography. Next, the fifth insulating film 10, the fourth insulating film 9, the third insulating film 8, and the second insulating film above the first wiring 6 are formed by dry etching using the photoresist 11 as a mask. 7 is removed and a through hole 12 is formed. Thereafter, the photoresist 11 is removed by ashing.

  Next, as shown in FIG. 13B, a photoresist 13 having an opening larger than the through hole 12 is formed on the first insulating layer 10 on the fifth insulating film 10 by photolithography. . Next, using the photoresist 13 as a mask, part of the fifth insulating film 10 and the fourth insulating film 9 above the first wiring 6 is removed by dry etching, and the second wiring groove 14 is removed. Form. Thereafter, the photoresist 13 is removed by ashing.

  Next, as shown in FIG. 13C, tantalum nitride / tantalum serving as a second barrier metal 15 for preventing copper diffusion so as to fill the through hole 12 and the second wiring groove 14 by sputtering. A laminated film (not shown) and copper (not shown) to be the second metal film 16 are sequentially deposited. Thereafter, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the through hole 12 and the second wiring groove 14, and the through hole 12 and The fifth insulating film 10 is exposed to a portion other than the second wiring trench 14 to form the second wiring 17 and the first connection plug 18 made of the second barrier metal 15 and the second metal film 16. To do. At this time, the first wiring 6 and the second wiring 17 are electrically connected by the first connection plug 18.

By repeating the steps shown in FIGS. 12C to 13C, a semiconductor device using a low dielectric constant film as shown in FIG. 11 is formed.
JP 2001-274239 A JP 2003-303880 A

  However, the following problems occur in a conventional semiconductor device using a low dielectric constant film. The low dielectric constant film is a porous film having pores of 1 to 10 nm in the film, and the mechanical strength is as low as 1/10 or less than that of a conventional TEOS film. Therefore, in a conventional semiconductor device using a low dielectric constant film, a second insulating film 7 serving as a cap film and a third insulating film 8 serving as a liner film are provided between interlayer insulating films that are low dielectric constant films. Therefore, a structure that improves the process controllability of the insulating film is used. Here, the semiconductor device formed by the damascene method has these liner films, interlayer insulating films, and cap films deposited in multiple layers, and there are many interfaces between the insulating films and the insulating films. ing. Since the low dielectric constant film is a hydrophobic film and the liner film is a hydrophilic film, the interface between the low dielectric constant film and the liner film is weak. Furthermore, an interface between the metal film and the liner film having a lower adhesion exists on the extended line of the interface between the low dielectric constant film and the liner film. Therefore, when polishing the upper layer of the multilayer wiring by the CMP method, when dicing in the assembly process of the semiconductor device, or when probing in the measurement test, as shown in FIG. 14, in the scribe line forming region or the wiring forming region. A load is applied in the vertical and horizontal directions of the wiring, vertical stress and shear stress are generated, and the interface between the fifth insulating film 10 and the sixth insulating film 19 which is a low dielectric constant film and the second wiring 17 Film peeling occurs at the interface with the sixth insulating film 19 or cracks occur in the second wiring 17. When the metal film is embedded in this film peeling, a wiring connection failure such as a short circuit between wirings is caused, and when a crack is generated, a non-conducting failure is caused.

  An object of the present invention is to provide a semiconductor device using a low dielectric constant film that does not cause defects due to film peeling or cracks at the interface between the insulating film and the insulating film and at the interface between the wiring and the insulating film, and a method for manufacturing the same. It is.

  The semiconductor device according to the present invention includes a first insulating film formed on a semiconductor substrate, a first wiring embedded in a first wiring groove formed in the first insulating film, and a first insulation. In a semiconductor device having a second insulating film formed on a film and a second wiring embedded in a second wiring groove formed in the second insulating film, the second insulating film and the second insulating film The first support column is provided to penetrate through one insulating film.

  The semiconductor device includes a third insulating film formed on the second insulating film, a third wiring embedded in a third wiring groove formed in the third insulating film, 3 and the second support column provided through the second insulating film, and at least a part of the side surface of the second support column is in contact with the first support column.

  The semiconductor device includes a third insulating film formed on the second insulating film, a third wiring embedded in a third wiring groove formed in the third insulating film, A fourth insulating film formed on the third insulating film, a fourth wiring embedded in a fourth wiring groove formed in the fourth insulating film, a fourth insulating film, and a third insulating film And a third column provided through the insulating film, and at least a part of the bottom surface of the third column is in contact with the first column.

  According to the semiconductor device of the present invention, it is possible to form the support pillars penetrating through the insulating film in which at least two wirings of the multilayer wiring are formed. Film peeling and cracks at the interface between the wiring and the insulating film can be prevented.

  The semiconductor device has a first connection plug integrally formed with the second wiring at the bottom of the second wiring, and the first connection plug is connected to the first wiring. Yes.

  In the semiconductor device, the second insulating film has a low dielectric constant film whose relative dielectric constant is smaller than 3.7.

  In the semiconductor device, the low dielectric constant film is a carbon-containing silicon oxide film.

  In the semiconductor device, the first support column is composed of a barrier metal and a metal film.

  In the semiconductor device, the first support column is connected to at least one of the first wiring and the second wiring.

  In the semiconductor device, the first support column is made of an insulating film having a relative dielectric constant higher than that of the low dielectric constant film.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step (a) of forming a first wiring groove in a first insulating film formed on a semiconductor substrate; and a first wiring in the first wiring groove. A step (b) of embedding, a step (c) of forming a second insulating film on the first insulating film after the step (b), and forming a second wiring trench in the second insulating film A step (d), a step (e) of embedding the second wiring in the second wiring trench, and a step (f) of forming a second insulating film and a support penetrating the first insulating film. .

  According to the method for manufacturing a semiconductor device according to the present invention, it is possible to form a pillar provided through an insulating film in which at least two wirings of multilayer wiring are formed. It is possible to prevent film peeling and cracks at the interface and between the wiring and the insulating film.

  In the method for manufacturing a semiconductor device, the second insulating film has a low dielectric constant film having a relative dielectric constant smaller than 3.7.

  In the method for manufacturing a semiconductor device, the low dielectric constant film is a carbon-containing silicon oxide film.

  In the method for manufacturing a semiconductor device, the step (f) includes a step (f1) of forming a through hole penetrating the second insulating film and the first insulating film, and a column made of a metal film is embedded in the through hole. Step (f2).

  Further, in the method of manufacturing the semiconductor device, after the step (d) and before the step (e), the through hole is formed, and the second wiring in the step (e) and the step (f2) are formed. The columns are formed at the same time in the same process.

  According to the semiconductor device manufacturing method of the present invention, the wiring connected to the semiconductor substrate and the insulating film in which at least two wiring layers of the multilayer wiring layers are formed in the multilayer wiring are provided. A support made of a metal film can be formed at the same time.

  Further, in the method for manufacturing the semiconductor device, the step (f) includes a step (f1) of forming a through hole penetrating the second insulating film and the first insulating film, and the ratio of the through hole to the through hole is lower than that of the low dielectric constant film. And a step (f2) of forming a support by embedding an insulating film having a high dielectric constant.

  According to the method for manufacturing a semiconductor device according to the present invention, since the insulating film is used for the support provided through the insulating film in which at least two of the multilayer wiring layers are formed, the multilayer wiring The dielectric constant can be reduced as compared with the case where a metal film is used for the support provided through the insulating film in which at least two wiring layers of the layers are formed.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to form a support made of a metal film or an insulating film provided through an insulating film in which at least two wiring layers of the multilayer wiring layer are formed. Therefore, it is possible to prevent film peeling and cracking at the interface between the insulating film and the insulating film and between the insulating film and the metal film, and to suppress the occurrence of wiring connection defects such as short circuit between wirings and non-conducting defects. can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
As a first embodiment, a case will be described in which a metal film is used as a support provided through an insulating film in which at least two wiring layers of a multilayer wiring layer are formed. FIG. 1 is a cross-sectional view showing a semiconductor device according to this embodiment. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  In the wiring formation region Rlogic, a first insulating film 102 formed on the semiconductor substrate 101 on which elements such as transistors are formed, and a wiring groove (not shown) formed in the first insulating film 102 are formed. It has a first wiring layer 501 composed of a buried first barrier metal 104 and a first wiring 106 made of a first metal film 105. The second insulating film 107 formed on the first insulating film 102 including the first wiring 106, the third insulating film 108 formed on the second insulating film 107, A fourth insulating film 109 which is a low dielectric constant film formed on the third insulating film 108, and a fifth insulating film 110 which is a low dielectric constant film formed on the fourth insulating film 109; The second barrier metal 115 and the second metal film 116 embedded in the wiring trench (not shown) formed in the fifth insulating film 110 and the fourth insulating film 109 on the first wiring 106. And a first connection plug 118 integrally formed at the bottom of the second wiring 117 so as to electrically connect the first wiring 106 and the second wiring 117. A second wiring layer 502 is provided. Further, a sixth insulating film 124 formed on the fifth insulating film 110 including the second wiring 117, a seventh insulating film 125 formed on the sixth insulating film 124, An eighth insulating film 126 which is a low dielectric constant film formed on the seventh insulating film 125, and a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126; The fourth barrier metal 128 and the fourth metal film embedded in the wiring trench (not shown) formed in the upper ninth insulating film 127 and the eighth insulating film 126 on the second wiring 117. And a second connection plug 131 integrally formed at the bottom of the third wiring 130 so as to electrically connect the second wiring 117 and the third wiring 130. A third wiring layer 503 is formed.

  In the scribe line region Scribe, a first insulating film 102 formed on the semiconductor substrate 101, a second insulating film 107 formed on the first insulating film 102, and a second insulating film 107 Formed on the third insulating film 108, the fourth insulating film 109, which is a low dielectric constant film formed on the third insulating film 108, and the fourth insulating film 109. The fifth insulating film 110, which is a low dielectric constant film, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, the second insulating film 107, and the first insulating film 102 That is, the third barrier metal 121 and the third metal film 122 embedded in a through hole (not shown) formed so as to penetrate through the insulating films of the second wiring layer 502 and the first wiring layer 501. The first support 123 and the first support 123 are The sixth insulating film 124 formed on the fifth insulating film 110, the seventh insulating film 125 formed on the sixth insulating film 124, and the seventh insulating film 125 An eighth insulating film 126 which is a formed low dielectric constant film, a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126, a ninth insulating film 127, The eighth insulating film 126, the seventh insulating film 125, the sixth insulating film 124, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, and the second insulating film 107, that is, The second pillar 134 made of the fifth barrier metal 132 and the fifth metal film 133 embedded in a through hole (not shown) that penetrates through the insulating films of the third wiring layer 503 and the second wiring layer 502. And have.

  In the present embodiment, the first support post 123 and the second support post 134 penetrate through an insulating film on which at least two wiring layers of the multilayer wiring layer are formed so as to penetrate deeper than that. May be. Moreover, the 1st support | pillar 123 and the 2nd support | pillar 134 should just penetrate at least 1 each wiring layer. Further, in order to prevent film peeling from the scribe line area Scribe, the first support post 123 and the second support post 134 are provided in the scribe line area Scribe, but film peeling from places other than the scribe line area Scribe, that is, In order to prevent film peeling from a region having a large wiring interval in the wiring formation region Rlogic, a support may be provided in the wiring formation region Rlogic. Further, in the present embodiment, the first column 123 and the second column 134 are not electrically connected to any of the first wiring 106, the second wiring 117, and the third wiring 130. Alternatively, it may be used as a connection wiring for connecting each wiring. For example, the first connection plug 118 is not formed by connecting the lower portion of the first support column 123 and the first wiring 106 and connecting the upper portion of the first support column 123 and the second wiring 117. In addition, the first wiring 106 and the second wiring 117 can be electrically wired.

  According to the present embodiment, the insulating film including the fragile low dielectric constant film has the support column made of the metal film provided through the insulating film in which at least two wiring layers of the multilayer wiring layers are formed. The semiconductor device having a multilayer structure can be reinforced, and film peeling or cracking at the interface between the lower insulating film and the insulating film and at the interface between the wiring and the insulating film due to vertical stress / shear stress generated during CMP of the upper layer Can be prevented. Accordingly, it is possible to suppress wiring connection failures such as a short circuit between wirings.

(Method for Manufacturing First Semiconductor Device According to First Embodiment)
A method for manufacturing the first semiconductor device according to the first embodiment of the present invention will be described. FIG. 2A to FIG. 3E are cross-sectional views showing manufacturing steps of the first semiconductor device according to the first embodiment of the present invention. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  First, as shown in FIG. 2A, in the wiring formation region Rlogic, a first insulating film 102 formed on a semiconductor substrate 101 on which a semiconductor element such as a transistor is formed is formed by a photolithography method and a dry etching method. Then, the first wiring groove 103 is formed.

  Next, as shown in FIG. 2B, tantalum nitride which becomes the first barrier metal 104 for preventing copper diffusion so as to fill the first wiring groove 103 on the first insulating film 102 by sputtering. A laminated film (not shown) of ride / tantalum and copper (not shown) to be the first metal film 105 are sequentially deposited. After that, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the first wiring groove 103, and other than the first wiring groove 103. The first insulating film 102 is exposed in the portion, and the first wiring 106 made of the first barrier metal 104 and the first metal film 105 is formed.

  Next, as illustrated in FIG. 2C, for example, a second insulating film 107 having a thickness of 30 nm and a thickness of 30 nm are formed on the first insulating film 102 including the first wiring 106 by a CVD method. The third insulating film 108 is sequentially deposited. Here, for example, a silicon nitride carbide film is used as the second insulating film 107, and a silicon oxycarbide film is used as the third insulating film 108.

  Next, as shown in FIG. 2D, a fourth insulating film 109 having a thickness of 600 nm, for example, is deposited on the third insulating film 108 by CVD. Here, for example, as the fourth insulating film 109, a carbon-containing silicon oxide film which is a low dielectric constant film is used. Thereafter, the fourth insulating film 109 is polished and planarized by a thickness of about 100 nm by a CMP method.

  Next, as shown in FIG. 2E, a fifth insulating film 110 of, eg, a 50 nm-thickness is deposited on the planarized fourth insulating film 109 by a CVD method. Here, for example, as the fifth insulating film 110, a silicon oxide film which is a low dielectric constant film is used.

  Next, as illustrated in FIG. 3A, a photoresist 111 having an opening above the first wiring 106 is formed on the fifth insulating film 110 by photolithography. Next, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, and the second insulating film above the first wiring 106 are formed by dry etching using the photoresist 111 as a mask. 107 is removed and a first through hole 112 is formed. Thereafter, the photoresist 111 is removed by ashing.

  Next, as shown in FIG. 3B, a photo having an opening larger in width than the first through hole 112 on the first insulating layer 106 on the fifth insulating film 110 by photolithography. A resist 113 is formed. Next, by dry etching, using the photoresist 113 as a mask, the thickness of about 250 nm of the fifth insulating film 110 and the fourth insulating film 109 on the first wiring 106 is removed, and the second wiring is removed. A groove 114 is formed. Thereafter, the photoresist 113 is removed by ashing.

  Next, as shown in FIG. 3C, tantalum nitride that becomes the second barrier metal 115 for preventing copper diffusion so as to fill the first through hole 112 and the second wiring groove 114 by sputtering. A copper / tantalum film (not shown) and copper (not shown) to be the second metal film 116 are sequentially deposited. Thereafter, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the first through hole 112 and the second wiring groove 114, The fifth insulating film 110 is exposed at portions other than the first through hole 112 and the second wiring groove 114, and the second wiring 117 and the first wiring made of the second barrier metal 115 and the second metal film 116 are formed. The connection plug 118 is formed. At this time, the first wiring 106 and the second wiring 117 are electrically connected by the first connection plug 118.

  Next, as shown in FIG. 3D, in the scribe line region Scribe, is the same as the first through hole 112 formed on the fifth insulating film 110 including the second wiring 117 by photolithography? A photoresist 119 having an opening larger than that is formed. Next, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, the second insulating film 107, and the first insulating film 102 are formed by dry etching using the photoresist 119 as a mask. And the second through hole 120 is formed. Thereafter, the photoresist 119 is removed by ashing.

  Next, as shown in FIG. 3 (e), a tantalum nitride / tantalum laminated film (FIG. 3) to be the third barrier metal 121 for preventing copper diffusion so as to fill the second through hole 120 by sputtering. (Not shown) and copper (not shown) to be the third metal film 122 are sequentially deposited. Thereafter, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the second through-hole 120, and other than the second through-hole 120. The fifth insulating film 110 is exposed in the portion, and the first support column 123 made of the third barrier metal 121 and the third metal film 122 is formed.

  By repeating the steps shown in FIGS. 2C to 3E, a semiconductor device using a low dielectric constant film as shown in FIG. 1 is formed. Note that the second through-hole 120 and the first support pillar 123 may penetrate deeper as long as they penetrate the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. Further, it is only necessary that at least one second through hole 120 and first support pillar 123 penetrate each wiring layer. In addition, in order to prevent film peeling from the scribe line area Scribe, the first support column 123 is provided in the scribe line area Scribe. In order to prevent film peeling from a region having a large wiring interval, a post may be provided in the wiring formation region Rlogic.

  According to the first method for manufacturing a semiconductor device of the present embodiment, it is possible to form the support column made of the metal film provided through the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. Therefore, it is possible to reinforce a semiconductor device having a stack of insulating films including a fragile low dielectric constant film, and an interface between a lower insulating film and an insulating film due to a normal stress / shear stress generated in the upper CMP process. In addition, film peeling and cracks at the interface between the wiring and the insulating film can be prevented. Therefore, it is possible to suppress wiring connection failures such as a short circuit between wirings.

(Method for Manufacturing Second Semiconductor Device According to First Embodiment)
A method for manufacturing the second semiconductor device according to the first embodiment of the present invention will be described. FIG. 4A to FIG. 5D are cross-sectional views illustrating manufacturing steps of the second semiconductor device according to the first embodiment of the present invention. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  First, as shown in FIG. 4A, in the wiring formation region Rlogic, a first insulating film 102 formed on a semiconductor substrate 101 on which a semiconductor element such as a transistor is formed is formed by a photolithography method and a dry etching method. Then, the first wiring groove 103 is formed.

  Next, as shown in FIG. 4B, tantalum nitride which becomes the first barrier metal 104 for preventing copper diffusion so as to fill the first wiring groove 103 on the first insulating film 102 by sputtering. A laminated film (not shown) of ride / tantalum and copper (not shown) to be the first metal film 105 are sequentially deposited. After that, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the first wiring groove 103, and other than the first wiring groove 103. The first insulating film 102 is exposed in the portion, and the first wiring 106 made of the first barrier metal 104 and the first metal film 105 is formed.

  Next, as shown in FIG. 4C, for example, a second insulating film 107 having a thickness of 30 nm and a thickness of 30 nm are formed on the first insulating film 102 including the first wiring 106 by a CVD method. The third insulating film 108 is sequentially deposited. Here, for example, a silicon nitride carbide film is used as the second insulating film 107, and a silicon oxycarbide film is used as the third insulating film 108.

  Next, as shown in FIG. 4D, a fourth insulating film 109 having a thickness of 600 nm, for example, is deposited on the third insulating film 108 by CVD. Here, for example, as the fourth insulating film 109, a carbon-containing silicon oxide film which is a low dielectric constant film is used. Thereafter, the fourth insulating film 109 is polished and planarized by a thickness of about 100 nm by a CMP method.

  Next, as shown in FIG. 4E, a fifth insulating film 110 having a thickness of, for example, 50 nm is deposited on the planarized fourth insulating film 109 by a CVD method. Here, for example, as the fifth insulating film 110, a silicon oxide film which is a low dielectric constant film is used.

  Next, as shown in FIG. 5A, a photoresist 111 having an opening above the first wiring 106 is formed on the fifth insulating film 110 by photolithography. Next, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, and the second insulating film above the first wiring 106 are formed by dry etching using the photoresist 111 as a mask. 107 is removed and a first through hole 112 is formed. Thereafter, the photoresist 111 is removed by ashing.

  Next, as shown in FIG. 5B, a photo having an opening larger in width than the first through hole 112 on the first insulating layer 106 on the fifth insulating film 110 by photolithography. A resist 113 is formed. Next, by dry etching, using the photoresist 113 as a mask, the thickness of about 250 nm of the fifth insulating film 110 and the fourth insulating film 109 on the first wiring 106 is removed, and the second wiring is removed. A groove 114 is formed. Thereafter, the photoresist 113 is removed by ashing.

  Next, as shown in FIG. 5C, in the scribe line region Scribe, the same as the first through hole 112 is formed on the fifth insulating film 110 including the second wiring trench 114 by photolithography. A photoresist 119 having an opening with a width larger than that is formed. Next, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, the second insulating film 107, and the first insulating film 102 are formed by dry etching using the photoresist 119 as a mask. And the second through hole 120 is formed. Thereafter, the photoresist 119 is removed by ashing.

  Next, as shown in FIG. 5D, a second barrier for preventing copper diffusion so as to fill the first through hole 112, the second wiring groove 114, and the second through hole 120 by sputtering. A metal 115, a tantalum nitride / tantalum laminated film (not shown) to be the third barrier metal 121, and a copper (not shown) to be the second metal film 116 and the third metal film 122 are sequentially deposited. . Thereafter, the multilayer film of copper and tantalum nitride / tantalum is polished by CMP, and copper and tantalum nitride / tantalum are placed in the first through hole 112, the second wiring groove 114, and the second through hole 120. The fifth insulating film 110 is exposed to a portion other than the first through hole 112, the second wiring groove 114, and the second through hole 120, leaving the second barrier metal 115 and the second The second wiring 117 and the first connection plug 118 made of the metal film 116 and the first support pillar 123 made of the third barrier metal 121 and the third metal film 122 are formed.

  By repeating the steps shown in FIGS. 4C to 5D, a semiconductor device using a low dielectric constant film as shown in FIG. 3 is formed. Note that the second through-hole 120 and the first support pillar 123 may penetrate deeper as long as they penetrate the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. Further, it is only necessary that at least one second through hole 120 and first support pillar 123 penetrate each wiring layer. In addition, in order to prevent film peeling from the scribe line area Scribe, the first support column 123 is provided in the scribe line area Scribe. However, film peeling from places other than the scribe line area Scribe, that is, in the wiring formation area Rlogic. In order to prevent film peeling from a region having a large wiring interval, a post may be provided in the wiring formation region Rlogic. Further, the order of the step of forming the second wiring groove 114 shown in FIG. 5B and the step of forming the second through hole 120 shown in FIG. 5C may be switched.

  According to the second method for manufacturing a semiconductor device of the present embodiment, it is possible to form the support column made of the metal film provided through the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. Therefore, it is possible to reinforce a semiconductor device having a stack of insulating films including a fragile low dielectric constant film, and an interface between a lower insulating film and an insulating film due to a normal stress / shear stress generated in the upper CMP process. In addition, film peeling and cracks at the interface between the wiring and the insulating film can be prevented. Therefore, it is possible to suppress wiring connection failures such as a short circuit between wirings. Further, according to the second method for manufacturing a semiconductor device of the present embodiment, the wiring connected to the semiconductor substrate and the insulating film in which at least two wiring layers of the multilayer wiring layers are formed in the multilayer wiring are penetrated. Thus, the number of steps can be reduced as compared with the first manufacturing method of the present embodiment.

(Modification 1 of the first embodiment)
As a first modification of the first embodiment, a case will be described in which a plurality of pillars penetrating two or more wiring grooves are in contact with the wiring layer in the vertical direction. FIG. 6 is a cross-sectional view showing a semiconductor device in Modification 1 of the present embodiment. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  In the wiring formation region Rlogic, a first insulating film 102 formed on the semiconductor substrate 101 on which elements such as transistors are formed, and a wiring groove (not shown) formed in the first insulating film 102 are formed. It has a first wiring layer 501 composed of a buried first barrier metal 104 and a first wiring 106 made of a first metal film 105. The second insulating film 107 formed on the first insulating film 102 including the first wiring 106, the third insulating film 108 formed on the second insulating film 107, A fourth insulating film 109 which is a low dielectric constant film formed on the third insulating film 108, and a fifth insulating film 110 which is a low dielectric constant film formed on the fourth insulating film 109; The second barrier metal 115 and the second metal film 116 embedded in the wiring trench (not shown) formed in the fifth insulating film 110 and the fourth insulating film 109 on the first wiring 106. And a first connection plug 118 integrally formed at the bottom of the second wiring 117 so as to electrically connect the first wiring 106 and the second wiring 117. A second wiring layer 502 is provided. Further, a sixth insulating film 124 formed on the fifth insulating film 110 including the second wiring 117, a seventh insulating film 125 formed on the sixth insulating film 124, An eighth insulating film 126 which is a low dielectric constant film formed on the seventh insulating film 125, and a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126; The fourth barrier metal 128 and the fourth metal film embedded in the wiring trench (not shown) formed in the upper ninth insulating film 127 and the eighth insulating film 126 on the second wiring 117. And a second connection plug 131 integrally formed at the bottom of the third wiring 130 so as to electrically connect the second wiring 117 and the third wiring 130. A third wiring layer 503 is formed.

  In the scribe line region Scribe, a first insulating film 102 formed on the semiconductor substrate 101, a second insulating film 107 formed on the first insulating film 102, and a second insulating film 107 Formed on the third insulating film 108, the fourth insulating film 109, which is a low dielectric constant film formed on the third insulating film 108, and the fourth insulating film 109. The fifth insulating film 110, which is a low dielectric constant film, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, the second insulating film 107, and the first insulating film 102 That is, the third barrier metal 121 and the third buried in a through hole (not shown) formed so as to penetrate the insulating film in which the second wiring layer 502 and the first wiring layer 501 are formed. A first support 123 made of a metal film 122 of A sixth insulating film 124 formed on the fifth insulating film 110 including the pillars 123, a seventh insulating film 125 formed on the sixth insulating film 124, and a seventh insulating film 125 An eighth insulating film 126 which is a low dielectric constant film formed on the substrate, a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126, and a ninth insulating film. The film 127, the eighth insulating film 126, the seventh insulating film 125, the sixth insulating film 124, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, and the second insulating film 107, that is, penetrates the insulating film in which the third wiring layer 503 and the second wiring layer 502 are formed, and is embedded in a through hole (not shown) formed adjacent to the first support column 123. The second support 1 made of the fifth barrier metal 132 and the fifth metal film 133 And a 4.

  Here, in the semiconductor device of Modification 1 of the present embodiment, the first support post 123 and the second support post 134 are in contact with the wiring layer in the vertical direction, that is, in the second wiring layer 502. The second column 134 is characterized in that at least a part of the side surface is in contact with the first column 123. As a result, moisture and contaminants generated before and after dicing can be prevented from entering the inside of the chip, so that an effect as a seal ring can be achieved.

  In addition, the manufacturing method of the modification 1 of this embodiment is basically the same as the manufacturing method shown in FIGS. 2A to 3E or FIGS. 4A to 5D of this embodiment. Therefore, the description is omitted. Further, in the present embodiment, the first support post 123 and the second support post 134 penetrate through an insulating film in which at least two wiring layers of the multilayer wiring layer are formed so as to penetrate beyond that depth. May be. Moreover, the 1st support | pillar 123 and the 2nd support | pillar 134 should just penetrate at least 1 each wiring layer. In the first modification of the present embodiment, the first support column 123 and the second support column 134 are provided in the scribe line area Scribe in order to prevent film peeling from the scribe line area Scribe. In order to prevent film peeling from other locations, that is, film peeling from a region having a large wiring interval in the wiring formation region Rlogic or the like, a post may be provided in the wiring formation region Rlogic.

(Modification 2 of the first embodiment)
As a second modification of the first embodiment, a case will be described in which a plurality of pillars penetrating two or more wiring grooves are in contact with the wiring layer in the horizontal direction. FIG. 7 is a cross-sectional view showing a semiconductor device according to Modification 2 of the present embodiment. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  In the wiring formation region Rlogic, a first insulating film 102 formed on the semiconductor substrate 101 on which elements such as transistors are formed, and a wiring groove (not shown) formed in the first insulating film 102 are formed. It has a first wiring layer 501 composed of a buried first barrier metal 104 and a first wiring 106 made of a first metal film 105. The second insulating film 107 formed on the first insulating film 102 including the first wiring 106, the third insulating film 108 formed on the second insulating film 107, A fourth insulating film 109 which is a low dielectric constant film formed on the third insulating film 108, and a fifth insulating film 110 which is a low dielectric constant film formed on the fourth insulating film 109; The second barrier metal 115 and the second metal film 116 embedded in the wiring trench (not shown) formed in the fifth insulating film 110 and the fourth insulating film 109 on the first wiring 106. And a first connection plug 118 integrally formed at the bottom of the second wiring 117 so as to electrically connect the first wiring 106 and the second wiring 117. A second wiring layer 502 is provided. Further, a sixth insulating film 124 formed on the fifth insulating film 110 including the second wiring 117, a seventh insulating film 125 formed on the sixth insulating film 124, An eighth insulating film 126 which is a low dielectric constant film formed on the seventh insulating film 125, and a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126; The fourth barrier metal 128 and the fourth metal film embedded in the wiring trench (not shown) formed in the upper ninth insulating film 127 and the eighth insulating film 126 on the second wiring 117. From the third wiring 130 made of 129 and the second connection plug 131 integrally formed at the bottom of the third wiring 130 so as to electrically connect the second wiring 117 and the third wiring 130. A third wiring layer 503 is provided. Further, a tenth insulating film 135 formed on the ninth insulating film 127 including the third wiring 130, an eleventh insulating film 136 formed on the tenth insulating film 135, A twelfth insulating film 137 that is a low dielectric constant film formed on the eleventh insulating film 136; a thirteenth insulating film 138 that is a low dielectric constant film formed on the twelfth insulating film 137; A sixth barrier metal 139 and a sixth metal film 140 embedded in a wiring groove (not shown) formed in the thirteenth insulating film 138 and the twelfth insulating film 137 on the third wiring 130. And a third connection plug 142 integrally formed at the bottom of the fourth wiring 141 so as to electrically connect the third wiring 130 and the fourth wiring 141. The fourth wiring layer 504 is configured.

  In the scribe line region Scribe, a first insulating film 102 formed on the semiconductor substrate 101, a second insulating film 107 formed on the first insulating film 102, and a second insulating film 107 Formed on the third insulating film 108, the fourth insulating film 109, which is a low dielectric constant film formed on the third insulating film 108, and the fourth insulating film 109. The fifth insulating film 110, which is a low dielectric constant film, the fifth insulating film 110, the fourth insulating film 109, the third insulating film 108, the second insulating film 107, and the first insulating film 102 That is, the third barrier metal 121 and the third buried in a through hole (not shown) formed so as to penetrate the insulating film in which the second wiring layer 502 and the first wiring layer 501 are formed. A first support 123 made of a metal film 122 of A sixth insulating film 124 formed on the fifth insulating film 110 including the pillars 123, a seventh insulating film 125 formed on the sixth insulating film 124, and a seventh insulating film 125 An eighth insulating film 126 which is a low dielectric constant film formed on the substrate, a ninth insulating film 127 which is a low dielectric constant film formed on the eighth insulating film 126, and a ninth insulating film. A tenth insulating film 135 formed on the film 127; an eleventh insulating film 136 formed on the tenth insulating film 135; and a low dielectric formed on the eleventh insulating film 136. A twelfth insulating film 137 that is a dielectric film, a thirteenth insulating film 138 that is a low dielectric constant film formed on the twelfth insulating film 137, a thirteenth insulating film 138, and a twelfth insulating film 137, eleventh insulating film 136, tenth insulating film 135, ninth insulating film 127, eighth insulating film 1 6, through the seventh insulating film 125 and the sixth insulating film 124, that is, through the insulating film in which the fourth wiring layer 504 and the third wiring layer 503 are formed, so as to be connected to the first support column 123. A seventh barrier metal 143 and a third column 145 made of a seventh metal film 144 are embedded in the formed through hole (not shown).

  Here, in the semiconductor device of Modification 2 of the present embodiment, the first support post 123 and the third support post 145 are in contact with the wiring layer in the horizontal direction, that is, at least of the third support post 145. It is characterized in that a part of the bottom surface is in contact with the first support column 123. As a result, moisture and contaminants generated before and after dicing can be prevented from entering the inside of the chip, so that an effect as a seal ring can be achieved.

  Note that the manufacturing method of Modification 2 of the present embodiment is basically the same as the manufacturing method shown in FIGS. 2A to 3E or FIGS. 4A to 5D of the present embodiment. Therefore, the description is omitted. Further, the first support post 123 and the third support post 145 may penetrate through an insulating film in which at least two wiring layers of the multilayer wiring layer are formed, so as to penetrate deeper than that. Moreover, the 1st support | pillar 123 and the 3rd support | pillar 145 should just penetrate at least 1 each wiring layer. In the second modification of the present embodiment, the first support column 123 and the third support column 145 are provided in the scribe line region Scribe in order to prevent film peeling from the scribe line region Scribe. In order to prevent film peeling from other locations, that is, film peeling from a region having a large wiring interval in the wiring formation region Rlogic or the like, a post may be provided in the wiring formation region Rlogic.

(Second Embodiment)
As a second embodiment, a case where an insulating film is used as a support that penetrates two or more wiring grooves will be described. FIG. 8 is a cross-sectional view showing the semiconductor device in the present embodiment. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  In the wiring formation region Rlogic, a first insulating film 202 formed on a semiconductor substrate 201 on which elements such as transistors are formed, and a wiring groove (not shown) formed in the first insulating film 202 are formed. It has a first wiring layer 501 composed of a buried first barrier metal 204 and a first wiring 206 made of a first metal film 205. Further, the second insulating film 207 formed on the first insulating film 202 including the first wiring 206, the third insulating film 208 formed on the second insulating film 207, A fourth insulating film 209 which is a low dielectric constant film formed on the third insulating film 208, and a fifth insulating film 210 which is a low dielectric constant film formed on the fourth insulating film 209; The second barrier metal 215 and the second metal film 216 embedded in a wiring groove (not shown) formed in the fifth insulating film 210 and the fourth insulating film 209 above the first wiring 206. And a first connection plug 218 integrally formed at the bottom of the second wiring 217 so as to electrically connect the first wiring 206 and the second wiring 217. A second wiring layer 502 is provided. In addition, a seventh insulating film 223 formed on the fifth insulating film 210 including the second wiring 217, an eighth insulating film 224 formed on the seventh insulating film 223, A ninth insulating film 225 which is a low dielectric constant film formed on the eighth insulating film 224; a tenth insulating film 226 which is a low dielectric constant film formed on the ninth insulating film 225; The third barrier metal 227 and the third metal film embedded in the wiring trench (not shown) formed in the upper tenth insulating film 226 and the ninth insulating film 225 on the second wiring 217 A second wiring plug 229 formed integrally with the bottom of the third wiring 229 so as to electrically connect the second wiring 217 and the third wiring 229 to each other. A third wiring layer 503 is formed.

  In the scribe line region Scribe, a first insulating film 202 formed on the semiconductor substrate 201, a second insulating film 207 formed on the first insulating film 202, and a second insulating film 207 Formed on the third insulating film 208, the fourth insulating film 209, which is a low dielectric constant film formed on the third insulating film 208, and the fourth insulating film 209. The fifth insulating film 210, which is a low dielectric constant film, the fifth insulating film 210, the fourth insulating film 209, the third insulating film 208, the second insulating film 207, and the first insulating film 202 That is, rather than the fourth insulating film 209 embedded in a through hole (not shown) formed so as to penetrate the insulating film in which the second wiring layer 502 and the first wiring layer 501 are formed. 1st support | pillar 2 which consists of the 6th insulating film 221 with a high relative dielectric constant 2, a seventh insulating film 223 formed on the fifth insulating film 210 including the first support pillar 222, an eighth insulating film 224 formed on the seventh insulating film 223, A ninth insulating film 225 which is a low dielectric constant film formed on the eighth insulating film 224 and a tenth insulating film 226 which is a low dielectric constant film formed on the ninth insulating film 225. The tenth insulating film 226, the ninth insulating film 225, the eighth insulating film 224, the seventh insulating film 223, the fifth insulating film 210, the fourth insulating film 209, and the third insulating film 208. And a second insulating film 207, that is, a first hole embedded in a through hole (not shown) formed so as to penetrate the insulating film in which the third wiring layer 503 and the second wiring layer 502 are formed. Eleventh insulating film having a relative dielectric constant higher than that of the fourth insulating film 209 and the ninth insulating film 225 And a second support column 232 consisting of 31.

  Here, in the semiconductor device of this embodiment, the relative dielectric constant of the sixth insulating film 221 is higher than the relative dielectric constants of the fourth insulating film 209 and the fifth insulating film 210 which are low dielectric constant films. 11 has a relative dielectric constant higher than that of the fourth insulating film 209, the fifth insulating film 210, the ninth insulating film 225, and the tenth insulating film 226, which are low dielectric constant films. However, it has characteristics. As a result, the insulating film including the fragile low-dielectric constant film is laminated because the column is formed of the insulating film provided through the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. The semiconductor device can be reinforced, and the peeling and cracking of the interface between the lower insulating film and the insulating film and the interface between the wiring and the insulating film due to the vertical stress / shear stress generated during CMP of the upper layer can be prevented. Is possible. Accordingly, it is possible to suppress a wiring connection failure such as a short circuit between the wirings.

  In the present embodiment, the first support pillar 222 and the second support pillar 232 penetrate through an insulating film in which at least two wiring layers of the multilayer wiring layer are formed, and penetrate through a depth greater than that. May be. In addition, it is sufficient that at least one first support 222 and second support 232 penetrate each wiring layer. Further, in order to prevent film peeling from the scribe line area Scribing, the first support post 222 and the second support post 232 are provided in the scribe line area Scribing, but film peeling from places other than the scribe line area Scribing, that is, In order to prevent film peeling from a region having a large wiring interval in the wiring formation region Rlogic, a support may be provided in the wiring formation region Rlogic.

(Method for Manufacturing Semiconductor Device According to Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. FIG. 9A to FIG. 10E are cross-sectional views showing a first manufacturing process of a semiconductor device according to the second embodiment of the present invention. In the drawing, the right side shows a wiring formation region Rlogic, and the left side shows a scribe line region Scribe.

  First, as shown in FIG. 9A, in the wiring formation region Rlogic, a first insulating film 202 formed on a semiconductor substrate 201 on which a semiconductor element such as a transistor is formed is formed by a photolithography method and a dry etching method. Then, the first wiring trench 203 is formed.

  Next, as shown in FIG. 9B, tantalum nitride which becomes the first barrier metal 204 for preventing copper diffusion so as to fill the first wiring groove 203 on the first insulating film 202 by sputtering. A laminated film (not shown) of ride / tantalum and copper (not shown) to be the first metal film 205 are sequentially deposited. Thereafter, the copper and tantalum nitride / tantalum laminated film is polished by CMP, leaving the copper and tantalum nitride / tantalum laminated film in the first wiring groove 203, and other than the first wiring groove 203. The first insulating film 202 is exposed in the portion, and the first wiring 206 made of the first barrier metal 204 and the first metal film 205 is formed.

  Next, as shown in FIG. 9C, for example, a second insulating film 207 having a thickness of 30 nm and a thickness of 30 nm are formed on the first insulating film 202 including the first wiring 206 by a CVD method. The third insulating film 208 is sequentially deposited. Here, for example, a silicon nitride carbide film is used as the second insulating film 207, and a silicon oxycarbide film is used as the third insulating film 208.

  Next, as shown in FIG. 9D, a fourth insulating film 209 having a thickness of 600 nm, for example, is deposited on the third insulating film 208 by a CVD method. Here, for example, as the fourth insulating film 209, a carbon-containing silicon oxide film which is a low dielectric constant film is used. Thereafter, the fourth insulating film 209 is polished and planarized by a thickness of about 100 nm by CMP.

  Next, as illustrated in FIG. 9E, for example, a fifth insulating film 210 having a thickness of 50 nm is deposited on the planarized fourth insulating film 209 by a CVD method. Here, for example, as the fifth insulating film 210, a silicon oxide film which is a low dielectric constant film is used.

  Next, as illustrated in FIG. 10A, a photoresist 211 having an opening above the first wiring 206 is formed on the fifth insulating film 210 by photolithography. Next, the fifth insulating film 210, the fourth insulating film 209, the third insulating film 208, and the second insulating film above the first wiring 206 are formed by dry etching using the photoresist 211 as a mask. 207 is removed, and a first through hole 212 is formed. Thereafter, the photoresist 211 is removed by ashing.

  Next, as shown in FIG. 10B, a photo having an opening wider than the first through-hole 212 on the first insulating layer 206 on the fifth insulating film 210 by photolithography. A resist 213 is formed. Next, by the dry etching method, using the photoresist 213 as a mask, the thickness of about 250 nm of the fifth insulating film 210 and the fourth insulating film 209 on the first wiring 206 is removed, and the second wiring is removed. A groove 214 is formed. Thereafter, the photoresist 213 is removed by ashing.

  Next, as shown in FIG. 10C, tantalum nitride serving as a second barrier metal 215 for preventing copper diffusion so as to fill the first through hole 212 and the second wiring groove 214 by sputtering. A copper / tantalum film (not shown) and copper (not shown) to be the second metal film 216 are sequentially deposited. Thereafter, the copper and tantalum nitride / tantalum laminated film is polished by CMP to leave the copper and tantalum nitride / tantalum laminated film in the first through hole 212 and the second wiring trench 214, The fifth insulating film 210 is exposed at portions other than the first through hole 212 and the second wiring groove 214, and the second wiring 217 and the first wiring 217 made of the second barrier metal 215 and the second metal film 216 are exposed. The connection plug 218 is formed. At this time, the first wiring 206 and the second wiring 217 are electrically connected by the first connection plug 218.

  Next, as shown in FIG. 10D, in the scribe line region Scribe, is the same as the first through hole 212 formed on the fifth insulating film 210 including the second wiring 217 by photolithography? A photoresist 219 having an opening larger than that is formed. Next, the fifth insulating film 210, the fourth insulating film 209, the third insulating film 208, the second insulating film 207, and the first insulating film 202 are formed by dry etching using this photoresist 219 as a mask. And the second through hole 220 is formed. Thereafter, the photoresist 219 is removed by ashing.

  Next, as shown in FIG. 10E, a sixth insulating film 221 is deposited by the CVD method so as to fill the second through hole 220. Here, as the sixth insulating film 221, a silicon oxide film-based insulating film having a higher relative dielectric constant than the fourth insulating film 209 and the fifth insulating film 210, which are low dielectric constant films, for example, a TEOS film (Relative permittivity: 4.2) or FSG film (relative permittivity: 3.7) is used. Thereafter, the sixth insulating film 221 is polished by CMP, leaving the sixth insulating film 221 in the second through hole 220, and the fifth insulating film 210 in a portion other than the second through hole 220. The column 222 made of the sixth insulating film 221 is formed.

  By repeating the steps shown in FIGS. 9C to 10E, the third wiring layer 503 is formed, and a semiconductor device using a low dielectric constant film as shown in FIG. 8 is formed. . Note that the second through-hole 220 and the first support pillar 222 may penetrate deeper as long as they penetrate the insulating film in which at least two wiring layers of the multilayer wiring layer are formed. In addition, it is only necessary that at least one second through hole 220 and column 222 penetrate each wiring layer. Further, in order to prevent film peeling from the scribe line area Scribe, the first support pillar 222 is provided in the scribe line area Scribe. However, film peeling from places other than the scribe line area Scribe, that is, in the wiring forming area Rlogic. In order to prevent film peeling from a region having a large wiring interval, a post may be provided in the wiring formation region Rlogic. Furthermore, also in this embodiment, it is possible to provide a semiconductor device having the same structure as that of the first modification of the first embodiment and the second modification of the first embodiment.

  According to the method for manufacturing a semiconductor device of the present embodiment, a support post made of an insulating film provided through an insulating film in which at least two wiring layers of the multilayer wiring layers are formed in the multilayer wiring is formed. Therefore, it is possible to reinforce a semiconductor device having a stack of insulating films including a fragile low dielectric constant film, and between the lower insulating film and the insulating film due to normal stress / shear stress generated in the upper CMP process. It is possible to prevent film peeling and cracks at the interface and the interface between the wiring and the insulating film. Therefore, it is possible to suppress wiring connection failures such as a short circuit between wirings. In addition, according to the method for manufacturing a semiconductor device of the present embodiment, since the insulating film is used for the support column provided through the insulating film in which at least two wiring layers of the multilayer wiring layer are formed, Compared to the first embodiment in which a metal film is used for a support provided penetrating through an insulating film in which at least two wiring layers of the multilayer wiring layer are formed, the dielectric constant can be reduced. Can be lowered.

  The semiconductor device of the present invention can be used in a semiconductor device using a low dielectric constant film and a manufacturing method thereof.

Sectional drawing which shows the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the 1st manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the 1st manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the 2nd manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the 2nd manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the modification 1 of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the modification 2 of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional view showing a conventional semiconductor device using a low dielectric constant film Sectional drawing which shows the manufacturing process of the semiconductor device using the conventional low dielectric constant film | membrane Sectional drawing which shows the manufacturing process of the semiconductor device using the conventional low dielectric constant film | membrane The figure for demonstrating the subject of the semiconductor device using the conventional low dielectric constant film | membrane

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 1st insulating film 103 1st wiring groove 104 1st barrier metal 105 1st metal film 106 1st wiring 107 2nd insulating film 108 3rd insulating film 109 4th insulating film 110 fifth insulating film 111 photoresist 112 first through hole 113 photoresist 114 second wiring groove 115 second barrier metal 116 second metal film 117 second wiring 118 first connection plug 119 photoresist 120 2nd through hole 121 3rd barrier metal 122 3rd metal film 123 1st support | pillar 124 6th insulating film 125 7th insulating film 126 8th insulating film 127 9th insulating film 128 4th Barrier metal 129 Fourth metal film 130 Third wiring 131 Second connection plug 132 Fifth barrier metal 1 33 5th metal film 134 2nd support | pillar 135 10th insulating film 136 11th insulating film 137 12th insulating film 138 13th insulating film 139 6th barrier metal 140 6th metal film 141 4th Wiring 142 Third connection plug 143 Seventh barrier metal 144 Seventh metal film 145 Third pillar 201 Semiconductor substrate 202 First insulating film 203 First wiring groove 204 First barrier metal 205 First Metal film 206 First wiring 207 Second insulating film 208 Third insulating film 209 Fourth insulating film 210 Fifth insulating film 211 Photoresist 212 First through hole 213 Photoresist 214 Second wiring groove 215 Second barrier metal 216 Second metal film 217 Second wiring 218 First connection plug 219 Photoresist 220 Second Through-hole 221 6th insulating film 222 1st support 223 7th insulating film 224 8th insulating film 225 9th insulating film 226 10th insulating film 227 3rd barrier metal 228 3rd metal film 229 3rd wiring 230 2nd connection plug 231 11th insulating film 232 2nd support | pillar 501 1st wiring layer 502 2nd wiring layer 503 3rd wiring layer

Claims (15)

Formed on the first insulating film formed on the semiconductor substrate, the first wiring buried in the first wiring groove formed in the first insulating film, and the first insulating film In the semiconductor device having the second insulating film formed and the second wiring embedded in the second wiring groove formed in the second insulating film,
A semiconductor device comprising: the second insulating film; and a first support column provided through the first insulating film. The semiconductor device according to claim 1,
A third insulating film formed on the second insulating film; a third wiring embedded in a third wiring groove formed on the third insulating film; and the third insulating film. And a second column provided through the second insulating film,
The semiconductor device, wherein at least a part of a side surface of the second support column is in contact with the first support column. The semiconductor device according to claim 1,
A third insulating film formed on the second insulating film;
A third wiring embedded in a third wiring groove formed in the third insulating film;
A fourth insulating film formed on the third insulating film;
A fourth wiring embedded in a fourth wiring groove formed in the fourth insulating film;
A third support column provided through the fourth insulating film and the third insulating film;
The semiconductor device according to claim 3, wherein at least a part of the bottom surface of the third support column is in contact with the first support column. The semiconductor device according to any one of claims 1 to 3,
The bottom of the second wiring has a first connection plug integrally formed with the second wiring,
The semiconductor device, wherein the first connection plug is connected to the first wiring. The semiconductor device of any one of Claims 1-4 WHEREIN:
The semiconductor device, wherein the second insulating film has a low dielectric constant film having a relative dielectric constant smaller than 3.7. The semiconductor device according to claim 5,
The semiconductor device, wherein the low dielectric constant film is a carbon-containing silicon oxide film. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device according to claim 1, wherein the first support column is made of a barrier metal and a metal film. The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein the first support column is connected to at least one of the first wiring and the second wiring. The semiconductor device according to claim 5 or 6,
The semiconductor device according to claim 1, wherein the first support column is made of an insulating film having a relative dielectric constant higher than that of the low dielectric constant film. A step (a) of forming a first wiring groove in a first insulating film formed on a semiconductor substrate;
A step (b) of embedding a first wiring in the first wiring groove;
(C) forming a second insulating film on the first insulating film after the step (b);
Forming a second wiring trench in the second insulating film (d);
Embedding a second wiring in the second wiring trench (e);
And (f) forming a pillar penetrating the second insulating film and the first insulating film. In the manufacturing method of the semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the second insulating film has a low dielectric constant film having a relative dielectric constant smaller than 3.7. In the manufacturing method of the semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the low dielectric constant film is a carbon-containing silicon oxide film. In the manufacturing method of the semiconductor device according to any one of claims 10 to 12,
The step (f) includes a step (f1) of forming a through hole penetrating the second insulating film and the first insulating film;
And a step (f2) of embedding a pillar made of a metal film in the through hole. In the manufacturing method of the semiconductor device according to claim 13,
After the step (d) and before the step (e), the through hole is formed,
The method of manufacturing a semiconductor device, wherein the formation of the second wiring in the step (e) and the formation of the support in the step (f2) are simultaneously performed in the same step. In the manufacturing method of the semiconductor device according to claim 11 or 12,
The step (f) includes a step (f1) of forming a through hole penetrating the second insulating film and the first insulating film;
And a step (f2) of forming the support by burying an insulating film having a higher dielectric constant than the low dielectric constant film in the through hole.

Images