JP2010003894A - Method for manufacturing semiconductor device, and the semiconductor device - Google Patents

Method for manufacturing semiconductor device, and the semiconductor device Download PDF

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JP2010003894A
JP2010003894A JP2008161641A JP2008161641A JP2010003894A JP 2010003894 A JP2010003894 A JP 2010003894A JP 2008161641 A JP2008161641 A JP 2008161641A JP 2008161641 A JP2008161641 A JP 2008161641A JP 2010003894 A JP2010003894 A JP 2010003894A
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film
insulating film
etching stopper
conductive pattern
semiconductor device
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Takeshi Ozawa
健 小澤
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NEC Electronics Corp
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NEC Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an unintended pin hole from being formed in an insulating film, even if a region with a low etching resistance is formed in an etching stopper film on the insulating film. <P>SOLUTION: The etching stopper film 230 is formed on the first insulating film 220. The etching stopper film is the film where the two films 232, 234 made of the same material are laminated. A first opening pattern 230a is formed in the etching stopper film, and the second insulating film 240 is formed on the etching stopper film. The second insulating film is etched with a mask pattern 52 as a mask, so as to form a groove 242, and the first insulating film is etched with the etching stopper film as a mask, so as to form a connection hole 220a. In the process, although the etching low-resistance region 234a is removed so as to form the groove 234b, but the probability of the lower film 232 being the low resistance region is low. Consequently, unintended opening is suppressed from being formed in the etching stopper film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、絶縁膜に溝及び孔を形成する工程を有する半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device including a step of forming grooves and holes in an insulating film.

配線溝とビアホールの両方を層間絶縁膜中に形成した後、配線溝とビアホールに同時に金属膜を埋め込んで多層配線を形成するデュアルダマシンプロセスは、工程数削減により製造コストを大きく低減できるという利点がある。デュアルダマシンプロセスの一つに、例えば特許文献１，２，３に例示された方法がある。この方法は、ビアとなる領域の配線層間のエッチングストッパー膜を先に加工してから配線層間絶縁膜を成膜し、その後層間絶縁膜のエッチングを行う事により、配線溝とビアホールを同時に形成するものである。   The dual damascene process, in which both the wiring trench and via hole are formed in the interlayer insulation film, and then the metal film is simultaneously buried in the wiring trench and via hole to form a multilayer wiring, has the advantage that the manufacturing cost can be greatly reduced by reducing the number of steps. is there. As one of the dual damascene processes, there are methods exemplified in Patent Documents 1, 2, and 3, for example. In this method, an etching stopper film between wiring layers in a region to be a via is processed first, then a wiring interlayer insulating film is formed, and then the interlayer insulating film is etched to simultaneously form a wiring groove and a via hole. Is.

特開平１１−３４５８７５号公報JP-A-11-345875 特開２００４−１４０１５１号公報JP 2004-140151 A 特開２００７−０８１２８４号公報Japanese Patent Laid-Open No. 2007-081284

図５及び図６の各図は、上記した特許文献に例示された方法における課題を説明するための図である。まず図５（ａ）に示すように、絶縁膜４００の表面に配線４１０，４１２を形成する。次いで絶縁膜４００及び配線４１０，４１２の上に、エッチングストッパー膜４２０、ビア層間絶縁膜４３０、エッチングストッパー膜４４０、及び配線層間絶縁膜４５０をこの順に積層する。エッチングストッパー膜４４０には、配線４１０上に位置する開口パターン４４４が形成されている。なおエッチングストッパー膜４４０を形成するとき、例えばパーティクルの付着や膜質の異常により、エッチング耐性が低い低耐性領域４４２が形成されることがある。   Each of FIGS. 5 and 6 is a diagram for explaining a problem in the method exemplified in the above-described patent document. First, as shown in FIG. 5A, wirings 410 and 412 are formed on the surface of the insulating film 400. Next, an etching stopper film 420, a via interlayer insulating film 430, an etching stopper film 440, and a wiring interlayer insulating film 450 are stacked in this order on the insulating film 400 and the wirings 410 and 412. In the etching stopper film 440, an opening pattern 444 located on the wiring 410 is formed. Note that when the etching stopper film 440 is formed, a low-resistance region 442 having low etching resistance may be formed due to, for example, adhesion of particles or abnormal film quality.

次いで図５（ｂ）に示すように、配線層間絶縁膜４５０上にマスクパターン４６０を形成し、マスクパターン４６０をマスクとしたエッチングを行う。これにより、配線層間絶縁膜４５０には配線溝４５２が形成され、かつビア層間絶縁膜４３０には開口パターン４４４の下に位置する接続孔４４４ａが形成される。エッチングストッパー膜４２０に低耐性領域４４２が形成されている場合は、低耐性領域４４２も除去されることがある。この場合、ビア層間絶縁膜４３０に、低耐性領域４４２の下方に位置するピンホール４４２ａが形成されることがある。   Next, as shown in FIG. 5B, a mask pattern 460 is formed on the wiring interlayer insulating film 450, and etching is performed using the mask pattern 460 as a mask. As a result, a wiring groove 452 is formed in the wiring interlayer insulating film 450, and a connection hole 444 a located under the opening pattern 444 is formed in the via interlayer insulating film 430. When the low resistance region 442 is formed in the etching stopper film 420, the low resistance region 442 may also be removed. In this case, a pinhole 442 a located below the low resistance region 442 may be formed in the via interlayer insulating film 430.

その後図６（ａ）に示すように、配線溝４５２の底面に位置するエッチングストッパー膜４４０及び接続孔４４４ａの底面に位置するエッチングストッパー膜４２０を除去する。ピンホール４４２ａが形成されている場合、ピンホール４４２ａの底面に位置するエッチングストッパー膜４２０も除去される。   Thereafter, as shown in FIG. 6A, the etching stopper film 440 located on the bottom surface of the wiring groove 452 and the etching stopper film 420 located on the bottom surface of the connection hole 444a are removed. When the pinhole 442a is formed, the etching stopper film 420 located on the bottom surface of the pinhole 442a is also removed.

次いで図６（ｂ）に示すように、配線溝４５２及び接続孔４４４ａに導電体を埋め込む。これにより、配線４７０及びビア４７２が形成される。ピンホール４４２ａが形成されている場合、ピンホール４４２ａの中にも導電体が埋め込まれ、ビア４７４が形成される。この場合、配線４７０はビア４７４を介して配線４１０と短絡してしまう。   Next, as shown in FIG. 6B, a conductor is embedded in the wiring groove 452 and the connection hole 444a. Thereby, the wiring 470 and the via 472 are formed. In the case where the pinhole 442a is formed, a conductor is embedded in the pinhole 442a, and a via 474 is formed. In this case, the wiring 470 is short-circuited with the wiring 410 through the via 474.

このように、上記した特許文献に記載した方法では、第１の絶縁膜（例えばビア層間絶縁膜）と第２の絶縁膜（例えば配線層間絶縁膜）の間に位置するエッチングストッパー膜にエッチング耐性が低い領域が形成された場合、この領域の下に、意図しないピンホールが形成されることがあった。このため、エッチングストッパー膜にエッチング耐性が低い領域が形成されても、意図しないピンホールが形成されないようにする技術が望まれる。   As described above, in the method described in the above-described patent document, the etching stopper film positioned between the first insulating film (for example, the via interlayer insulating film) and the second insulating film (for example, the wiring interlayer insulating film) is etched resistant. When a region having a low height is formed, an unintended pinhole may be formed under this region. For this reason, even if a region having low etching resistance is formed in the etching stopper film, a technique for preventing an unintended pinhole from being formed is desired.

本発明によれば、第１の絶縁膜を形成する工程と、
前記第１の絶縁膜の上に、互いに同一の材料からなる少なくとも２つの膜を積層したエッチングストッパー膜を形成する工程と、
前記エッチングストッパー膜に第１の開口パターンを形成する工程と、
前記エッチングストッパー膜上及び前記第１の開口パターン内に、第２の絶縁膜を形成する工程と、
前記第２の絶縁膜の上に、前記第１の開口パターンの上方に位置する第２の開口パターンを有するマスクパターンを形成する工程と、
前記マスクパターンをマスクとして前記第２の絶縁膜をエッチングし、引き続き前記エッチングストッパー膜をマスクとして前記第１の絶縁膜をエッチングすることにより、前記第２の絶縁膜に位置する溝、及び前記第１の絶縁膜に位置していて前記溝の底部から下方に延伸する孔を形成する工程と、
を備える半導体装置の製造方法が提供される。 According to the present invention, the step of forming the first insulating film;
Forming an etching stopper film in which at least two films made of the same material are laminated on the first insulating film;
Forming a first opening pattern in the etching stopper film;
Forming a second insulating film on the etching stopper film and in the first opening pattern;
Forming a mask pattern having a second opening pattern located above the first opening pattern on the second insulating film;
The second insulating film is etched using the mask pattern as a mask, and then the first insulating film is etched using the etching stopper film as a mask, whereby the groove located in the second insulating film, and the first Forming a hole located in the insulating film of 1 and extending downward from the bottom of the groove;
A method for manufacturing a semiconductor device is provided.

本発明によれば、前記エッチングストッパー膜は、同一の材料からなる少なくとも２つの膜を積層することにより形成されている。これら２つの膜それぞれにエッチング耐性の低い領域が形成されても、これらの領域が互いに重なる確率は低い。このため、前記エッチングストッパー膜にエッチング耐性が低い領域が形成されても、前記溝及び前記孔を形成する工程において、前記第１の絶縁膜に意図しないピンホールが形成されることを抑制できる。   According to the present invention, the etching stopper film is formed by laminating at least two films made of the same material. Even if regions with low etching resistance are formed in each of these two films, the probability that these regions overlap each other is low. For this reason, even if a region having low etching resistance is formed in the etching stopper film, it is possible to suppress the formation of unintended pin holes in the first insulating film in the step of forming the groove and the hole.

本発明によれば、第１の導電パターンと、
前記第１の導電パターンの上に位置する第１の層間絶縁膜と、
前記第１の層間絶縁膜の上に位置しており、同一の材料からなる少なくとも２つの膜を積層したエッチングストッパー膜と、
前記エッチングストッパー膜の上に位置する第２の層間絶縁膜と、
前記第２の層間絶縁膜に形成され、前記第１の導電パターンの上方に位置しており、底面に前記エッチングストッパー膜が露出している配線溝と、
前記第１の層間絶縁膜及び前記エッチングストッパー膜に形成され、前記配線溝の底面と前記第１の導電パターンをつなぐ接続孔と、
前記接続孔内及び前記配線溝に埋め込まれた第２の導電パターンと、
を備える半導体装置が提供される。 According to the present invention, a first conductive pattern;
A first interlayer insulating film located on the first conductive pattern;
An etching stopper film, which is located on the first interlayer insulating film and in which at least two films made of the same material are laminated;
A second interlayer insulating film located on the etching stopper film;
A wiring groove formed in the second interlayer insulating film, located above the first conductive pattern, and exposing the etching stopper film on a bottom surface;
A connection hole formed in the first interlayer insulating film and the etching stopper film and connecting a bottom surface of the wiring groove and the first conductive pattern;
A second conductive pattern embedded in the connection hole and in the wiring groove;
A semiconductor device is provided.

本発明によれば、第２の層間絶縁膜の上のエッチングストッパー膜にエッチング耐性が低い領域が形成されても、第２の層間絶縁膜に意図しないピンホールが形成されることを抑制できる。   According to the present invention, even when a region having low etching resistance is formed in the etching stopper film on the second interlayer insulating film, it is possible to suppress the formation of unintended pinholes in the second interlayer insulating film.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

図１〜図４の各図は、本発明の実施形態にかかる半導体装置の製造方法を示す断面図である。この半導体装置の製造方法は、以下の工程を有する。まず、第１の絶縁膜（ビア層間絶縁膜）２２０を形成する。次いで、第１の絶縁膜２２０の上に、エッチングストッパー膜２３０を形成する。エッチングストッパー膜２３０は、互いに同一の材料からなる少なくとも２つの膜２３２．２３４を積層した膜である。次いで、エッチングストッパー膜２３０に第１の開口パターン２３０ａを形成する。次いで、エッチングストッパー膜２３０上に、第２の絶縁膜（配線層間絶縁膜）２４０を形成する。次いで、第２の絶縁膜２４０上にマスクパターン５２を形成する。マスクパターン５２は、第１の開口パターン２３０ａの上方に位置する第２の開口パターン５２ａを有する。次いで、マスクパターン５２をマスクとして第２の絶縁膜２４０をエッチングし、引き続きエッチングストッパー膜２３０をマスクとして第１の絶縁膜２２０をエッチングする。これにより、第２の絶縁膜２４０に位置する溝２４２、及び第１の絶縁膜２２０に位置していて溝２４２の底部から下方に延伸する孔（接続孔）２２０ａが形成される。以下、詳細に説明する。   1 to 4 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. This method for manufacturing a semiconductor device includes the following steps. First, a first insulating film (via interlayer insulating film) 220 is formed. Next, an etching stopper film 230 is formed on the first insulating film 220. The etching stopper film 230 is a film in which at least two films 232.234 made of the same material are laminated. Next, a first opening pattern 230 a is formed in the etching stopper film 230. Next, a second insulating film (wiring interlayer insulating film) 240 is formed on the etching stopper film 230. Next, a mask pattern 52 is formed on the second insulating film 240. The mask pattern 52 has a second opening pattern 52a located above the first opening pattern 230a. Next, the second insulating film 240 is etched using the mask pattern 52 as a mask, and then the first insulating film 220 is etched using the etching stopper film 230 as a mask. As a result, a groove 242 located in the second insulating film 240 and a hole (connection hole) 220a located in the first insulating film 220 and extending downward from the bottom of the groove 242 are formed. Details will be described below.

まず図１（ａ）に示すように、層間絶縁膜１００の表面に、配線１２０，１２２を形成する。層間絶縁膜１００は、半導体基板などの基板（図示せず）上に形成されている。この基板には、トランジスタ（図示せず）が形成されている。本図に示す例において配線１２０，１２２はＣｕ配線であり、層間絶縁膜１００に埋め込まれている。配線１２０，１２２には、互いに異なる電圧（信号）が入力される。配線１２０は、例えばグラウンド配線であり、配線１２２は、例えばトランジスタのゲート電極に信号（ＶDD）を入力する配線である。 First, as shown in FIG. 1A, wirings 120 and 122 are formed on the surface of the interlayer insulating film 100. The interlayer insulating film 100 is formed on a substrate (not shown) such as a semiconductor substrate. A transistor (not shown) is formed on this substrate. In the example shown in the drawing, the wirings 120 and 122 are Cu wirings and are embedded in the interlayer insulating film 100. Different voltages (signals) are input to the wirings 120 and 122. The wiring 120 is, for example, a ground wiring, and the wiring 122 is, for example, a wiring that inputs a signal (V DD ) to the gate electrode of a transistor.

次いで層間絶縁膜１００上及び配線１２０，１２２上に、エッチングストッパー膜２１０をＣＶＤ法により形成する。エッチングストッパー膜２１０は、例えばＳｉＣＮ膜やＳｉＯＮ膜である。これらの膜の組成比は任意である。次いでエッチングストッパー膜２１０上に、ビア層間絶縁膜２２０をＣＶＤ法により形成する。ビア層間絶縁膜２２０は、例えば酸化シリコン膜又は酸化シリコン膜より誘電率が低い低誘電率絶縁膜である。低誘電率絶縁膜は、例えば比誘電率膜が３．３以下、好ましくは２．９以下の絶縁膜とすることができる。低誘電率膜としては、ＳｉＯＣの他に、ＨＳＱ（ハイドロジェンシルセスキオキサン）、ＭＳＱ（メチルシルセスキオキサン）、またはＭＨＳＱ（メチル化ハイドロジェンシルセスキオキサン）等のポリハイドロジェンシロキサン、ポリアリールエーテル（ＰＡＥ）、ジビニルシロキサンービスーベンゾシクロブテン（ＢＣＢ）、またはＳｉｌｋ（登録商標）等の芳香族含有有機材料、ＳＯＧ、ＦＯＸ(ｆｌｏｗａｂｌｅ ｏｘｉｄｅ)、サイトップ、またはＢＣＢ（Ｂｅｎｓｏｃｙｃｌｏｂｕｔｅｎｅ）等を用いることもできる。また、低誘電率絶縁膜としては、これらのポーラス膜を用いることもできる。   Next, an etching stopper film 210 is formed on the interlayer insulating film 100 and the wirings 120 and 122 by a CVD method. The etching stopper film 210 is, for example, a SiCN film or a SiON film. The composition ratio of these films is arbitrary. Next, a via interlayer insulating film 220 is formed on the etching stopper film 210 by a CVD method. The via interlayer insulating film 220 is, for example, a silicon oxide film or a low dielectric constant insulating film having a dielectric constant lower than that of the silicon oxide film. The low dielectric constant insulating film may be an insulating film having a relative dielectric constant film of 3.3 or less, preferably 2.9 or less, for example. As a low dielectric constant film, in addition to SiOC, polyhydrogensiloxane such as HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), or MHSQ (methylated hydrogen silsesquioxane), Aromatic-containing organic materials such as polyaryl ether (PAE), divinylsiloxane-bis-benzocyclobutene (BCB), or Silk (registered trademark), SOG, FOX (flowable oxide), Cytop, or BCB (Bencyclic cyclone) It can also be used. Moreover, these porous films can also be used as the low dielectric constant insulating film.

次いでビア層間絶縁膜２２０上に、第１の膜２３２をＣＶＤ法により形成する。第１の膜２３２は、例えばＳｉＣＮ膜やＳｉＯＮ膜である。これらの組成比は任意である。この工程において、第１の膜２３２には、例えばパーティクルの付着や膜質の異常により、エッチング耐性が低い低耐性領域２３２ａが形成されることがある。   Next, a first film 232 is formed on the via interlayer insulating film 220 by a CVD method. The first film 232 is, for example, a SiCN film or a SiON film. These composition ratios are arbitrary. In this step, a low-resistance region 232a having low etching resistance may be formed in the first film 232 due to, for example, adhesion of particles or abnormal film quality.

次いで図１（ｂ）に示すように、第１の膜２３２の形成を一端終了した後、半導体装置を成膜装置から搬出し、その後再び半導体装置を成膜装置に搬入する。その後、第１の膜２３２上に第２の膜２３４をＣＶＤ法により形成する。このようにして、第１の膜２３２及び第２の膜２３４からなるエッチングストッパー膜２３０が形成される。第２の膜２３４は、第１の膜２３２と同一の材料からなる。第２の膜２３４の組成比は、第１の膜２３２と同一であるのが好ましいが、異なっていても良い。第１の膜２３２及び第２の膜２３４の組成比は、たとえば原料ガスの比率を変更したり原料ガスそのものを変更することにより、調節することができる。この工程において、第２の膜２３４には、例えばパーティクルの付着や膜質の異常により、エッチング耐性が低い低耐性領域２３４ａが形成されることがある。しかし低耐性領域２３２ａ，２３４ａが互いに重なる可能性は低い。   Next, as shown in FIG. 1B, after the formation of the first film 232 is completed, the semiconductor device is unloaded from the film formation apparatus, and then the semiconductor device is loaded again into the film formation apparatus. Thereafter, a second film 234 is formed over the first film 232 by a CVD method. In this way, an etching stopper film 230 composed of the first film 232 and the second film 234 is formed. The second film 234 is made of the same material as the first film 232. The composition ratio of the second film 234 is preferably the same as that of the first film 232, but may be different. The composition ratio of the first film 232 and the second film 234 can be adjusted, for example, by changing the ratio of the source gas or changing the source gas itself. In this step, a low resistance region 234a having low etching resistance may be formed in the second film 234 due to, for example, adhesion of particles or abnormal film quality. However, there is a low possibility that the low-resistance regions 232a and 234a overlap each other.

第１の膜２３２は第２の膜２３４を形成する前に大気に晒される。このため、第１の膜２３２を形成した後、第２の膜２３４を形成する前に、第１の膜２３２の表面に自然酸化膜が形成されることがある。この場合、第２の膜２３４は、第１の膜２３２の自然酸化膜上に形成される。   The first film 232 is exposed to the atmosphere before forming the second film 234. Therefore, a natural oxide film may be formed on the surface of the first film 232 after the first film 232 is formed and before the second film 234 is formed. In this case, the second film 234 is formed on the natural oxide film of the first film 232.

次いで図２（ａ）に示すように、エッチングストッパー膜２３０上にマスクパターン５０を形成し、マスクパターン５０をマスクとしてエッチングストッパー膜２３０をエッチングする。これによりエッチングストッパー膜２３０には、開口パターン２３０ａが形成される。開口パターン２３０ａは、配線１２２の上方に位置する。   Next, as shown in FIG. 2A, a mask pattern 50 is formed on the etching stopper film 230, and the etching stopper film 230 is etched using the mask pattern 50 as a mask. As a result, an opening pattern 230 a is formed in the etching stopper film 230. The opening pattern 230 a is located above the wiring 122.

その後図２（ｂ）に示すように、マスクパターン５０を除去する。次いで、エッチングストッパー膜２３０上及び開口パターン２３０ａ内に、配線層間絶縁膜２４０をＣＶＤ法により形成する。配線層間絶縁膜２４０は、例えば酸化シリコン膜又は上記した低誘電率絶縁膜である。   Thereafter, as shown in FIG. 2B, the mask pattern 50 is removed. Next, a wiring interlayer insulating film 240 is formed on the etching stopper film 230 and in the opening pattern 230a by the CVD method. The wiring interlayer insulating film 240 is, for example, a silicon oxide film or the low dielectric constant insulating film described above.

次いで図３（ａ）に示すように、配線層間絶縁膜２４０上にマスクパターン５２を形成する。マスクパターン５２は、開口パターン５２ａを有する。開口パターン５２ａは開口パターン２３０ａより大きく、開口パターン２３０ａの上方に位置している。また開口パターン５２ａは、配線１２０の上方にも位置している。   Next, as shown in FIG. 3A, a mask pattern 52 is formed on the wiring interlayer insulating film 240. The mask pattern 52 has an opening pattern 52a. The opening pattern 52a is larger than the opening pattern 230a and is located above the opening pattern 230a. The opening pattern 52 a is also located above the wiring 120.

次いで図３（ｂ）に示すように、マスクパターン５２をマスクとして配線層間絶縁膜２４０をエッチングする。これにより配線層間絶縁膜２４０には、開口パターン５２ａの下に位置する溝２４２が形成される。本実施形態において溝２４２は配線溝であり、配線１２０，１２２それぞれの上方に位置する。   Next, as shown in FIG. 3B, the wiring interlayer insulating film 240 is etched using the mask pattern 52 as a mask. As a result, a trench 242 located under the opening pattern 52a is formed in the wiring interlayer insulating film 240. In the present embodiment, the groove 242 is a wiring groove and is located above the wirings 120 and 122.

その後、エッチングを続ける。これにより、開口パターン２３０ａの下に位置するビア層間絶縁膜２２０がエッチングされ、接続孔２２０ａが形成される。接続孔２２０ａは、溝２４２の底面と配線１２２をつなぐように形成される。この工程において、エッチングストッパー膜２３０を構成する第２の膜２３４の低耐性領域２３４ａは除去され、溝２３４ｂが形成されるが、溝２３４ｂの下に位置する第１の膜２３２が低耐性領域２３２ａである確率は低い。このため、本工程において、エッチングストッパー膜２３０に意図しない開口が形成されることは抑制される。   Thereafter, the etching is continued. As a result, the via interlayer insulating film 220 located under the opening pattern 230a is etched to form a connection hole 220a. The connection hole 220 a is formed so as to connect the bottom surface of the groove 242 and the wiring 122. In this step, the low resistance region 234a of the second film 234 constituting the etching stopper film 230 is removed and the groove 234b is formed, but the first film 232 located under the groove 234b is the low resistance region 232a. The probability of being is low. For this reason, in this step, formation of an unintended opening in the etching stopper film 230 is suppressed.

次いで、図４（ａ）に示すように、接続孔２２０ａの底部に位置するエッチングストッパー膜２１０を除去する。この工程において、溝２４２の底部に位置するエッチングストッパー膜２３０の第１の膜２３２及び第２の膜２３４も除去される。また、ビア層間絶縁膜２２０の表面のうち第１の膜２３２の低耐性領域２３２ａ及び第２の膜の低耐性領域２３４ａそれぞれの下方に位置していた部分には、凹部２２０ｂが形成される。   Next, as shown in FIG. 4A, the etching stopper film 210 located at the bottom of the connection hole 220a is removed. In this step, the first film 232 and the second film 234 of the etching stopper film 230 located at the bottom of the groove 242 are also removed. In addition, a recess 220b is formed in a portion of the surface of the via interlayer insulating film 220 located below the low resistance region 232a of the first film 232 and the low resistance region 234a of the second film.

次いで図４（ｂ）に示すように、溝２４２の側面及び底面、接続孔２２０ａの側面並びに底面、並びに配線層間絶縁膜２４０上に、バリアメタル膜（図示せず）、及びシートＣｕ膜（図示せず）を形成する。次いでシードＣｕ膜をシードとしためっきを行うことにより、溝２４２の中、接続孔２２０ａの中、及び配線層間絶縁膜２４０上にＣｕ膜を形成する。次いで、配線層間絶縁膜２４０上のＣｕ膜、シードＣｕ膜、及びバリアメタル膜をＣＭＰ（Chemical Mechanical Polishing）により除去する。これにより、溝２４２の中に位置する配線３００、及び接続孔２２０ａの中に位置するビア３０２が形成される。   Next, as shown in FIG. 4B, a barrier metal film (not shown) and a sheet Cu film (see FIG. 4) are formed on the side and bottom surfaces of the trench 242, the side and bottom surfaces of the connection holes 220a, and the wiring interlayer insulating film 240. (Not shown). Next, by performing plating using the seed Cu film as a seed, a Cu film is formed in the trench 242, in the connection hole 220 a, and on the wiring interlayer insulating film 240. Next, the Cu film, seed Cu film, and barrier metal film on the wiring interlayer insulating film 240 are removed by CMP (Chemical Mechanical Polishing). Thereby, the wiring 300 located in the groove 242 and the via 302 located in the connection hole 220a are formed.

次に、本発明の作用効果について説明する。エッチングストッパー膜２３０は、第１の膜２３２及び第２の膜２３４により形成されており、第１の膜２３２の低耐性領域２３２ａと第２の膜２３４の低耐性領域２３４ａが重なる可能性は低い。このため、溝２４２及び接続孔２２０ａを形成する工程において、エッチングストッパー膜２３０に意図しない開口が形成されることを抑制できる。従って、ビア層間絶縁膜２２０に意図しないピンホールが形成されることを抑制できる。   Next, the function and effect of the present invention will be described. The etching stopper film 230 is formed by the first film 232 and the second film 234, and the low resistance region 232a of the first film 232 and the low resistance region 234a of the second film 234 are unlikely to overlap. . For this reason, in the process of forming the groove 242 and the connection hole 220a, it is possible to suppress the formation of an unintended opening in the etching stopper film 230. Therefore, it is possible to suppress the formation of unintended pin holes in the via interlayer insulating film 220.

このため、溝２４２及び接続孔２２０ａに配線３００を埋め込んでも、配線３００が意図しない部分と接続することを抑制できる。例えば溝２４２が配線１２０の上方にも位置している場合において、配線３００が配線１２２のみではなく配線１２０にも接続することを抑制できる。従って、半導体装置の歩留まりが向上する。   For this reason, even if the wiring 300 is embedded in the groove 242 and the connection hole 220a, it can be suppressed that the wiring 300 is connected to an unintended portion. For example, when the groove 242 is also located above the wiring 120, the wiring 300 can be prevented from being connected not only to the wiring 122 but also to the wiring 120. Accordingly, the yield of the semiconductor device is improved.

また、エッチングストッパー膜２３０を２回以上に分けて形成する点を除いて、既存のプロセスを変更する必要がないため、プロセスパラメータ等の製造条件を変更する必要がない。また生産性が低下することを抑制できる。   In addition, since it is not necessary to change the existing process except that the etching stopper film 230 is formed twice or more, there is no need to change manufacturing conditions such as process parameters. Moreover, it can suppress that productivity falls.

また、エッチングストッパー膜２３０を構成する第１の膜２３２及び第２の膜２３４は、互いに同一の材料である。このため、エッチングストッパー膜２３０の膜厚及び材料を、エッチングストッパー膜２３０が一層構造の場合と同一にすることにより、エッチングストッパー膜２３０に起因して電気的特性が変化することを抑制できる。   Further, the first film 232 and the second film 234 constituting the etching stopper film 230 are made of the same material. For this reason, by making the film thickness and material of the etching stopper film 230 the same as in the case where the etching stopper film 230 has a single layer structure, it is possible to suppress changes in electrical characteristics due to the etching stopper film 230.

なお、上記した図では、エッチングストッパー膜２３０を２層構造としたが、３層以上としても良い。この場合においても、各層は互いに同一の材料から形成されている。   In the above-described figure, the etching stopper film 230 has a two-layer structure, but may have three or more layers. Even in this case, each layer is formed of the same material.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。   As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

各図は実施形態にかかる半導体装置の製造方法を示す断面図である。Each drawing is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. 各図は実施形態にかかる半導体装置の製造方法を示す断面図である。Each drawing is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. 各図は実施形態にかかる半導体装置の製造方法を示す断面図である。Each drawing is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. 各図は実施形態にかかる半導体装置の製造方法を示す断面図である。Each drawing is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. 各図は本発明の課題を説明するための断面図である。Each drawing is a cross-sectional view for explaining the problem of the present invention. 各図は本発明の課題を説明するための断面図である。Each drawing is a cross-sectional view for explaining the problem of the present invention.

符号の説明Explanation of symbols

１００ 層間絶縁膜
１２０ 配線
１２２ 配線
２１０ エッチングストッパー膜
２２０ ビア層間絶縁膜
２２０ａ 接続孔
２２０ｂ 凹部
２３０ エッチングストッパー膜
２３０ａ 開口パターン
２３２ 膜
２３２ａ 低耐性領域
２３４ 膜
２３４ａ 低耐性領域
２３４ｂ 溝
２４０ 配線層間絶縁膜
２４２ 溝
３００ 配線
３０２ ビア
４００ 絶縁膜
４１０ 配線
４１２ 配線
４２０ エッチングストッパー膜
４３０ ビア層間絶縁膜
４４０ エッチングストッパー膜
４４２ 低耐性領域
４４２ａ ピンホール
４４４ 開口パターン
４４４ａ 接続孔
４５０ 配線層間絶縁膜
４５２ 配線溝
４６０ マスクパターン
４７０ 配線
４７２ ビア
４７４ ビア
５０ マスクパターン
５２ マスクパターン
５２ａ 開口パターン 100 interlayer insulating film 120 wiring 122 wiring 210 etching stopper film 220 via interlayer insulating film 220a connection hole 220b recess 230 etching stopper film 230a opening pattern 232 film 232a low resistance region 234 film 234a low resistance region 234b groove 240 wiring interlayer insulating film 242 groove 300 wiring 302 via 400 insulating film 410 wiring 412 wiring 420 etching stopper film 430 via interlayer insulating film 440 etching stopper film 442 low resistance region 442a pin hole 444 opening pattern 444a connection hole 450 wiring interlayer insulating film 452 wiring groove 460 mask pattern 470 wiring 472 Via 474 Via 50 Mask pattern 52 Mask pattern 52a Opening pattern

Claims (6)

第１の絶縁膜を形成する工程と、
前記第１の絶縁膜の上に、互いに同一の材料からなる少なくとも２つの膜を積層したエッチングストッパー膜を形成する工程と、
前記エッチングストッパー膜に第１の開口パターンを形成する工程と、
前記エッチングストッパー膜上及び前記第１の開口パターン内に、第２の絶縁膜を形成する工程と、
前記第２の絶縁膜の上に、前記第１の開口パターンの上方に位置する第２の開口パターンを有するマスクパターンを形成する工程と、
前記マスクパターンをマスクとして前記第２の絶縁膜をエッチングし、引き続き前記エッチングストッパー膜をマスクとして前記第１の絶縁膜をエッチングすることにより、前記第２の絶縁膜に位置する溝、及び前記第１の絶縁膜に位置していて前記溝の底部から下方に延伸する孔を形成する工程と、
を備える半導体装置の製造方法。 Forming a first insulating film;
Forming an etching stopper film in which at least two films made of the same material are laminated on the first insulating film;
Forming a first opening pattern in the etching stopper film;
Forming a second insulating film on the etching stopper film and in the first opening pattern;
Forming a mask pattern having a second opening pattern located above the first opening pattern on the second insulating film;
The second insulating film is etched using the mask pattern as a mask, and then the first insulating film is etched using the etching stopper film as a mask, whereby the groove located in the second insulating film, and the first Forming a hole located in the insulating film of 1 and extending downward from the bottom of the groove;
A method for manufacturing a semiconductor device comprising: 請求項１に記載の半導体装置の製造方法において、
前記第１の絶縁膜は第１の導電パターンの上に形成され、
前記第１の開口パターンを形成する工程において、前記第１の開口パターンを前記第１の導電パターンの上方に位置させ、
前記溝及び孔を形成する工程において、前記孔を前記溝の底面と前記第１の導電パターンをつなぐように形成し、
前記溝及び孔を形成する工程の後に、前記溝及び前記孔に導電体を埋め込む工程を備える半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The first insulating film is formed on the first conductive pattern;
In the step of forming the first opening pattern, the first opening pattern is positioned above the first conductive pattern,
In the step of forming the groove and the hole, the hole is formed so as to connect the bottom surface of the groove and the first conductive pattern,
A method for manufacturing a semiconductor device comprising a step of embedding a conductor in the groove and the hole after the step of forming the groove and the hole. 請求項２に記載の半導体装置の製造方法において、
前記第１の導電パターンと同一層に位置する第２の導電パターンがあり、
前記第１の絶縁膜を形成する工程において、前記第２の導電パターンの上にも前記第１の絶縁膜を形成し、
前記溝及び前記孔を形成する工程において、前記溝を前記第２の導電パターンの上方にも位置させる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
There is a second conductive pattern located in the same layer as the first conductive pattern,
In the step of forming the first insulating film, the first insulating film is also formed on the second conductive pattern,
A method of manufacturing a semiconductor device, wherein in the step of forming the groove and the hole, the groove is also positioned above the second conductive pattern. 第１の導電パターンと、
前記第１の導電パターンの上に位置する第１の層間絶縁膜と、
前記第１の層間絶縁膜の上に位置しており、同一の材料からなる少なくとも２つの膜を積層したエッチングストッパー膜と、
前記エッチングストッパー膜の上に位置する第２の層間絶縁膜と、
前記第２の層間絶縁膜に形成され、前記第１の導電パターンの上方に位置しており、底面に前記エッチングストッパー膜が露出している配線溝と、
前記第１の層間絶縁膜及び前記エッチングストッパー膜に形成され、前記配線溝の底面と前記第１の導電パターンをつなぐ接続孔と、
前記接続孔内及び前記配線溝に埋め込まれた第２の導電パターンと、
を備える半導体装置。 A first conductive pattern;
A first interlayer insulating film located on the first conductive pattern;
An etching stopper film, which is located on the first interlayer insulating film and in which at least two films made of the same material are laminated;
A second interlayer insulating film located on the etching stopper film;
A wiring groove formed in the second interlayer insulating film, located above the first conductive pattern, and exposing the etching stopper film on a bottom surface;
A connection hole formed in the first interlayer insulating film and the etching stopper film and connecting a bottom surface of the wiring groove and the first conductive pattern;
A second conductive pattern embedded in the connection hole and in the wiring groove;
A semiconductor device comprising: 請求項４に記載の半導体装置において、
前記第１の導電パターンと同一層に位置する第３の導電パターンがあり、
前記第１の層間絶縁膜及び前記第２の導電パターンは前記第３の導電パターンの上方にも形成されている半導体装置。 The semiconductor device according to claim 4,
There is a third conductive pattern located in the same layer as the first conductive pattern,
The semiconductor device in which the first interlayer insulating film and the second conductive pattern are also formed above the third conductive pattern. 請求項５に記載の半導体装置において、
前記第１の導電パターンは、前記第３の導電パターンとは異なる信号が入力される半導体装置。 The semiconductor device according to claim 5,
The first conductive pattern is a semiconductor device to which a signal different from that of the third conductive pattern is input.
JP2008161641A 2008-06-20 2008-06-20 Method for manufacturing semiconductor device, and the semiconductor device Pending JP2010003894A (en)

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