JP4361517B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a low dielectric constant (Low-k) film and a manufacturing method thereof, and more particularly to a semiconductor device for a large scale integrated circuit (LSI) using a Low-k film as an interlayer film and a manufacturing method thereof. It is about.

  Currently, LSIs are widely used in various industrial fields, but in the future, it will be required to process a huge amount of information at high speed. Until now, the miniaturization of transistors has determined the performance of LSIs. However, in recent years, delays in resistance and capacitance (RC: Resistance, Capacitance) in the circuit have become a problem. At present, the resistance of the wiring to be connected and the capacity of the insulating material between the wirings have become problems.

  In order to cope with this problem, the wiring has been changed from aluminum (Al) to copper (Cu), and the insulating material has been changed from a silicon oxide film to a low-k film.

  However, since the low-k film generally has a low film density, the adhesion strength with the lower layer material is weak, and it is easy to peel off when the semiconductor chip is diced or when the resin is cured and contracted during resin sealing. As a result, this interlaminar film peeling breaks the peripheral wiring, causes a wiring defect, and causes a problem of decreasing the yield.

  On the other hand, conventionally, the following two countermeasures have been taken in order to solve the above problems.

  The first countermeasure is a method of preventing film peeling by embedding a high strength material such as a plug in the Low-k film (for example, see Patent Document 1). In fact, this method has no additional steps and is now widely used.

The second countermeasure is a method for preventing film peeling during the manufacturing process by using a material having high adhesion to the Low-k film. This countermeasure is currently under development.
JP 2001-267323 A

  However, the first countermeasure described above has a problem of causing film peeling during CMP. Further, it cannot be added at the final stage of the manufacturing process. In the second countermeasure method, various attempts have been made to develop a material having high adhesion to the low-k film, but at present, it is still in order to prevent film peeling during resin sealing. Has not reached.

  Therefore, in view of the above problems, an object of the present invention is a semiconductor capable of preventing film peeling during dicing of a semiconductor chip and during resin sealing without changing the existing manufacturing apparatus and materials. An apparatus and a method for manufacturing the same are provided.

In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention is stacked on the element formation region at least at a part of a peripheral portion of an element formation region formed by integrating a plurality of semiconductor elements. a plurality of the sacrificial peel pattern formed in a concave shape so as to penetrate the more from the top of at least one of the insulating layer, the sacrificial peel pattern on so as to cover a surface protective film formed on the element forming region The sacrificial peeling pattern includes any one of an assembly of a plurality of contact holes, an assembly of a plurality of perforated grooves arranged in parallel, and a plurality of grooves arranged in parallel. The surface protective film is embedded in the sacrificial release pattern so as to have a hole in the sacrificial release pattern. In this case, as the sacrificial peeling pattern according to the first aspect, a high aspect ratio fine contact or fine line is provided so that the surface protective film does not reach the bottom of the groove.

The semiconductor device according to claim 2, wherein, in at least part of the peripheral portion of the plurality of semiconductor elements element forming region formed by integrating, at least on of the plurality of the insulating film layer laminated on the element forming region a sacrificial peel pattern formed in a concave shape so as to penetrate further from the so as to cover the sacrificial peel pattern, and a said element forming region the surface protective film formed on the sacrificial peel pattern includes a plurality The surface protective film is composed of any one of an aggregate of contact holes, an aggregate of a plurality of perforated grooves arranged in parallel, and a plurality of grooves arranged in parallel. The entire inner wall of the sacrificial release pattern is covered so as to be along the inner surface of the release pattern and not to be embedded in the sacrificial release pattern. In this case, as a sacrificial peeling pattern according to claim 2, a fine contact or fine line having an aspect ratio in which the surface protective film does not reach the bottom of the groove is provided.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the insulating film layer on which the sacrificial peeling pattern is formed is a low-k film.

  A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect, wherein the low-k film has a relative dielectric constant of less than 3.9.

  According to a fifth aspect of the present invention, in the semiconductor device according to the first, second, third, or fourth aspect, the sacrificial release pattern is formed over the entire periphery of the element formation region.

  According to a sixth aspect of the present invention, in the semiconductor device according to the first, second, third, or fourth aspect, the sacrificial peeling pattern is formed at a corner of the peripheral portion of the element formation region and in the vicinity thereof.

The method of manufacturing a semiconductor device according to claim 7 , wherein a plurality of semiconductor elements are integrated and formed on a substrate, a plurality of insulating film layers are stacked, and the plurality of semiconductor elements are integrated and formed. in at least a part of the periphery of the element forming region, and forming a concave sacrificial peel pattern so as to penetrate the more from the top of at least one of said plurality of insulating layers film, so as to cover the sacrificial peel pattern on Forming a surface protective film on the element formation region, and forming the sacrificial release pattern in a concave shape by arranging the sacrificial release pattern in a plurality of parallel arrangements of a plurality of contact holes. Forming the surface protective film as one of an assembly of a plurality of perforated grooves and a plurality of grooves arranged in parallel ; Have Embed urchin said surface protective layer on the sacrificial peel pattern within.

The method of manufacturing a semiconductor device according to claim 8 , wherein a plurality of semiconductor elements are integrated and formed on a substrate, a plurality of insulating film layers are stacked, and the plurality of semiconductor elements are integrated and formed. Forming a sacrificial release pattern in a concave shape so as to penetrate at least one of the plurality of insulating film layers from at least one of the peripheral portions of the element formation region, and covering the sacrificial release pattern Forming a surface protective film on a region formed by integrating the plurality of semiconductor elements, and forming the sacrificial release pattern in a concave shape by using the sacrificial release pattern as a plurality of contact holes. Forming the surface protective film as one of an assembly of the above, an assembly of a plurality of perforated grooves arranged in parallel, and a plurality of grooves arranged in parallel , Surface protective film Wherein along the inner surface of the sacrificial peel pattern, and covers the entire inner wall in the sacrificial peel pattern so as not to fill the sacrificial peel pattern within.

A method for manufacturing a semiconductor device according to a ninth aspect is the method for manufacturing a semiconductor device according to the seventh or eighth aspect , wherein the sacrificial peeling pattern is formed by a chemical etching technique.

  According to the semiconductor device of the first aspect of the present invention, the surface protective film is embedded in the sacrificial peeling pattern so as to have a void portion inside the sacrificial peeling pattern. When stress is applied, the sacrificial peeling pattern is peeled off, so that film peeling to the element formation region can be prevented. For this reason, it becomes possible to prevent film peeling at the time of dicing the semiconductor chip and at the time of resin sealing without changing the existing manufacturing apparatus and materials.

  According to the semiconductor device of the second aspect of the present invention, since the surface protective film covers the inside of the sacrificial release pattern along the inner surface of the sacrificial release pattern, stress is applied during dicing and resin sealing. As the sacrificial peeling pattern peels off, film peeling to the element formation region can be prevented, and the same effect as in claim 1 can be obtained.

  According to the third and fourth aspects, since the insulating film layer on which the sacrificial peeling pattern is formed is a low-k film, the problem of delay in resistance and capacitance in the circuit can be solved. In addition, the low-k film is effective because it has a low film density and has low adhesion strength with the lower layer material, and is easily peeled when the resin is cured and contracted during dicing of the semiconductor chip. The relative dielectric constant of the low-k film is preferably less than 3.9.

  According to the fifth aspect, since the sacrificial peeling pattern is formed on the entire peripheral portion of the element forming region, film peeling due to stress at the time of dicing and resin sealing can be prevented on the entire peripheral portion of the element forming region.

  According to the sixth aspect of the present invention, since the sacrificial peeling pattern is formed at the corner of the peripheral portion of the element forming region and in the vicinity thereof, film peeling due to stress at the time of dicing and resin sealing is performed on the peripheral portion of the element forming region. This can be prevented at and around the corner.

According to the method of manufacturing a semiconductor device according to claim 7 of the present invention, the step of forming the surface protective film embeds the surface protective film in the sacrificial peeling pattern so as to have a void portion inside the sacrificial peeling pattern. When stress is applied at the time of dicing and resin sealing, the sacrificial release pattern is peeled off, so that film peeling to the element formation region can be prevented. For this reason, it becomes possible to prevent film peeling at the time of dicing the semiconductor chip and at the time of resin sealing without changing the existing manufacturing apparatus and materials.

According to the eighth aspect of the present invention , the step of forming the surface protective film covers the inside of the sacrificial release pattern so that the surface protective film is along the inner surface of the sacrificial release pattern. Therefore, when stress is applied during dicing or resin sealing, By peeling the pattern, film peeling to the element formation region can be prevented, and the same effect as in the tenth aspect can be obtained.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh or eighth aspect , the sacrificial peeling pattern is preferably formed by a chemical etching technique.

(First embodiment)
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a plan view showing a sacrificial peeling region forming portion in a semiconductor chip in the first embodiment of the present invention, and FIG. 2 is a plan view showing a sacrificial peeling pattern in each sacrificial peeling region. FIG. 3 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.

  1 and 2, reference numerals 101 and 201 denote element forming regions where semiconductor elements are formed, reference numerals 102 and 202 denote sacrificial peeling regions, and reference numeral 103 denotes a dicing line region.

  As shown in FIG. 1 and FIG. 3, of at least a part of the peripheral portion of the element formation region 101 formed by integrating a plurality of semiconductor elements, out of the plurality of insulating film layers stacked on the element formation region 101. A sacrificial release pattern 313 formed in a concave shape so as to penetrate at least one layer and a surface protection film 314 formed on the element formation region 101 so as to cover the sacrificial release pattern 313 are provided. The surface protective film 314 embeds the sacrificial release pattern 313 so as to have a hole in the sacrificial release pattern 313.

  In this case, in FIG. 1A, on the entire outer periphery of the semiconductor chip, in FIG. 1B, on the corner portion of the semiconductor chip, and in FIG. 1C, on the outer periphery and corner portion of the semiconductor chip, A sacrificial release region 102 is provided for each.

  Further, in each sacrificial peeling region, a plurality of contact-shaped sacrificial peeling patterns 203 as shown in FIG. 2 (b) and a plurality of perforated line-shaped sacrificial shapes as shown in FIG. 2 (c). The peeling pattern 204 or a plurality of line-shaped sacrificial peeling patterns 205 as shown in FIG.

  Each sacrificial release region and each sacrificial release pattern 313 are formed in a groove shape across a plurality of layers 303 and 304 of the semiconductor chip, as can be seen from the cross-sectional view of the semiconductor chip shown in FIG. Further, as shown in FIG. 3C, the surface protective film 314 covers a part of the inner wall of the groove.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings.

In the present embodiment, on a substrate 301 such as Si, low-k interlayer film 303, such as the interlayer film 302, F added SiO _2, such as SiO _2, lines 306 to 308, the contact 309 to 311, PAD 312 , A sacrificial release pattern 313 and a passivation film 314 (surface protective film). The relative dielectric constant of the low-k interlayer film is preferably less than 3.9.

  First, as shown in FIG. 3A, the element formation region up to the uppermost layer before the surface protective film is formed as a semiconductor chip. Next, as shown in FIG. 3B, a plurality of interlayer insulating films 303 and 304 are penetrated into a predetermined region around the semiconductor chip by, for example, a chemical etching method such as dry etching, and low-k A groove is formed to a depth reaching the interlayer film 302 which is not a film, and is used as a sacrificial peeling region. Next, as shown in FIG. 3C, a surface protective film 314 is formed on the entire semiconductor chip including the element formation region. At this time, in the sacrificial peeling region, a high aspect ratio fine contact or fine line is provided as the sacrificial peeling pattern 313 so that the surface protective film does not reach the bottom of the groove. By doing in this way, the surface protective film 314 does not bury the whole inside of the groove | channel of the sacrificial peeling pattern 313, but a fine seam is formed.

  By providing this sacrificial peeling region, when stress is applied during dicing or resin sealing, the opening pattern peels off, thereby preventing film peeling to the element forming region.

  In the present embodiment, the sacrificial separation region is formed by forming a groove portion that penetrates through a plurality of interlayer insulating films 303 and 304 and reaches a depth reaching the interlayer film 302 that is not a low-k film, but is limited to this. However, if a groove that penetrates at least one interlayer insulating film is formed, a function as a sacrificial peeling region can be achieved.

  Note that by providing the surface protective film 314 that partially fills the inside of the groove of the sacrificial peeling pattern 313, the sacrificial peeling region can be formed with a small area while maintaining the moisture-proof effect of the passivation film.

  Further, since the surface protective film 314 does not fill the entire inside of the groove, the opening pattern can be more easily peeled off when stress is applied during dicing or resin sealing.

The present invention is characterized in that the sacrificial release region is intentionally provided to prevent the chip body from being peeled off. The shape of the sacrificial release region and the sacrificial region pattern are limited to the present embodiment. is not.
(Second Embodiment)
The semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention will be described below with reference to FIG.

  The planar shapes of the sacrificial release region and the sacrificial release pattern in this embodiment are the same as those in the first embodiment shown in FIGS.

  Each sacrificial release region and each sacrificial release pattern 414 are formed in a groove shape across a plurality of layers 403 and 404 of the semiconductor chip, as can be seen from the cross-sectional view of the semiconductor chip shown in FIG. Further, as shown in FIG. 4C, a surface protective film 414 covers the inner wall of the groove.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings.

  FIG. 4 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.

In the present embodiment, on a substrate 401 such as Si, low-k interlayer film 403 and 404, such as the interlayer film 402, F added SiO _2, such as SiO _2, lines 406-408, contacts 409 to 411, Pad412 , A sacrificial release pattern 413 and a passivation film (surface protective film) 414. The relative dielectric constant of the low-k interlayer film is preferably less than 3.9.

  First, as shown in FIG. 4A, the element formation region up to the uppermost layer before the surface protective film is formed as a semiconductor chip. Next, as shown in FIG. 4B, a plurality of interlayer insulating films 403 and 404 are penetrated into a predetermined region around the semiconductor chip by, for example, a chemical etching method such as dry etching, and low-k A groove is formed to a depth reaching the interlayer film 402 which is not a film, and is used as a sacrifice peeling region. Next, as shown in FIG. 4C, a surface protective film 414 is formed on the entire semiconductor chip including the element formation region. At this time, in the sacrificial peeling region, as the sacrificial peeling pattern 413, a fine contact or fine line having an aspect ratio that allows the surface protective film 414 to reach the bottom of the groove is provided. By doing in this way, the surface protective film 414 is formed in the shape which covers the whole inner wall of a groove part so that the inside of a groove part may not be embedded so that the wall surface inside the groove | channel of the sacrificial peeling pattern 413 may be followed.

  By providing this sacrificial peeling region, when stress is applied during dicing or resin sealing, the opening pattern peels off, thereby preventing film peeling to the element forming region.

  In the present embodiment, the sacrificial separation region is formed by forming a groove portion that penetrates through the plurality of interlayer insulating films 403 and 404 and reaches the depth reaching the interlayer film 402 that is not a low-k film, but is limited to this. However, if a groove that penetrates at least one interlayer insulating film is formed, a function as a sacrificial peeling region can be achieved.

  In addition, by providing the surface protective film 414 in a shape that covers the entire inner wall of the groove portion so as to be along the wall surface inside the groove of the sacrificial peeling pattern 413 and not to be embedded in the groove portion, the surface protection film 414 has a larger area than the first embodiment. However, as compared with the first embodiment, the moisture-proof effect of the passivation film can be obtained easily and reliably.

  Further, since the surface protective film 414 does not fill the entire inside of the groove, the opening pattern can be more easily peeled off when stress is applied during dicing or resin sealing.

  The present invention is characterized in that the sacrificial release region is intentionally provided to prevent the chip body from being peeled off. The shape of the sacrificial release region and the sacrificial region pattern are limited to the present embodiment. is not.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention can prevent film peeling during dicing and resin sealing, and in particular, a large scale integrated circuit (LSI) using a low-k film as an interlayer film. It is useful for the production of

(A)-(c) is a top view which shows the example of the sacrificial peeling area | region in the 1st and 2nd embodiment of this invention. (A) is a top view which shows the sacrificial peeling area | region in the 1st and 2nd embodiment of this invention, (b)-(d) is a top view which shows the example of the sacrificial peeling pattern. It is process sectional drawing for forming the sacrificial peeling area | region in the 1st Embodiment of this invention. It is process sectional drawing for forming the sacrificial peeling area | region in the 2nd Embodiment of this invention.

Explanation of symbols

101 Element formation region 102 Sacrificial peeling region 103 Dicing line region 201 Element formation region 202 Sacrificial peeling region 301 Substrate 302 Interlayer film 303 Low-k interlayer film 304 Low-k interlayer film 305 Wiring 306 Wiring 307 Wiring 308 Wiring 309 Contact 310 Contact 311 Contact 312 Pad
313 Sacrificial peeling pattern 314 Passivation film 401 Substrate 402 Interlayer film 403 Low-k interlayer film 404 Low-k interlayer film 405 Wiring 406 Wiring 407 Wiring 408 Wiring 409 Contact 410 Contact 411 Contact 412 Pad
413 Sacrificial release pattern 414 Passivation film

Claims (9)

In at least a part of the periphery of the plurality of semiconductor elements element forming region formed by integrating, concave so as to penetrate the more from the top of at least one of the element formation region a plurality of insulating films layers stacked A formed sacrificial release pattern; and
A surface protective film formed on the element formation region so as to cover the sacrificial release pattern;
The sacrificial release pattern comprises any one of an assembly of a plurality of contact holes, an assembly of a plurality of perforated grooves arranged in parallel, and a plurality of grooves arranged in parallel.
The semiconductor device according to claim 1, wherein the surface protective film is embedded in the sacrificial peeling pattern so as to have a hole portion inside the sacrificial peeling pattern. In at least a part of the periphery of the plurality of semiconductor elements element forming region formed by integrating, concave so as to penetrate the more from the top of at least one of the element formation region a plurality of insulating films layers stacked A formed sacrificial release pattern; and
A surface protective film formed on the element formation region so as to cover the sacrificial release pattern;
The sacrificial release pattern comprises any one of an assembly of a plurality of contact holes, an assembly of a plurality of perforated grooves arranged in parallel, and a plurality of grooves arranged in parallel.
The semiconductor device according to claim 1, wherein the surface protective film covers the entire inner wall of the sacrificial release pattern so as to be along the inner surface of the sacrificial release pattern and not to be embedded in the sacrificial release pattern.   3. The semiconductor device according to claim 1, wherein the insulating film layer on which the sacrificial peeling pattern is formed is a low-k film.   The semiconductor device according to claim 3, wherein a dielectric constant of the low-k film is less than 3.9.   5. The semiconductor device according to claim 1, wherein the sacrificial release pattern is formed on the entire periphery of the element formation region.   5. The semiconductor device according to claim 1, wherein the sacrificial release pattern is formed at a corner of the peripheral portion of the element formation region and in the vicinity thereof. Forming a plurality of semiconductor elements on a substrate and stacking a plurality of insulating film layers;
A sacrificial release pattern is formed in a concave shape so as to penetrate at least one of the plurality of insulating layer films from at least a part of a peripheral portion of an element formation region formed by integrating the plurality of semiconductor elements. Process,
Forming a surface protective film on the element formation region so as to cover the sacrificial release pattern,
The step of forming the sacrificial release pattern in a concave shape includes the step of forming the sacrificial release pattern by an aggregate of a plurality of contact holes, an aggregate of a plurality of perforated grooves arranged in parallel, and a plurality of parallel arrays. Formed as one of the grooves of the book,
The step of forming the surface protective film includes embedding the surface protective film in the sacrificial peeling pattern so as to have a void portion inside the sacrificial peeling pattern. Forming a plurality of semiconductor elements on a substrate and stacking a plurality of insulating film layers;
A sacrificial release pattern is formed in a concave shape so as to penetrate at least one of the plurality of insulating film layers from at least a part of a peripheral portion of an element formation region formed by integrating the plurality of semiconductor elements. Process,
Forming a surface protective film on a region formed by integrating the plurality of semiconductor elements so as to cover the sacrificial release pattern,
The step of forming the sacrificial release pattern in a concave shape includes the step of forming the sacrificial release pattern by an aggregate of a plurality of contact holes, an aggregate of a plurality of perforated grooves arranged in parallel, and a plurality of parallel arrays. Formed as one of the grooves of the book,
The step of forming the surface protective film includes covering the entire inner wall of the sacrificial peeling pattern so that the surface protective film is along the inner surface of the sacrificial peeling pattern and is not embedded in the sacrificial peeling pattern. A method of manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the sacrificial release pattern is formed by a chemical etching technique.

Images