JP2006516780A - デバッグの間データ処理システムを制御するための方法および装置 - Google Patents

デバッグの間データ処理システムを制御するための方法および装置 Download PDF

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Publication number
JP2006516780A
JP2006516780A JP2006502871A JP2006502871A JP2006516780A JP 2006516780 A JP2006516780 A JP 2006516780A JP 2006502871 A JP2006502871 A JP 2006502871A JP 2006502871 A JP2006502871 A JP 2006502871A JP 2006516780 A JP2006516780 A JP 2006516780A
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Prior art keywords
subsystem
activation
subsystems
data processing
processing system
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JP2006502871A
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Japanese (ja)
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JP2006516780A5 (enExample
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シー． モイヤー、ウィリアム
ケリー、ジョン
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NXP USA Inc
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NXP USA Inc
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Publication of JP2006516780A publication Critical patent/JP2006516780A/ja
Publication of JP2006516780A5 publication Critical patent/JP2006516780A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3698—Environments for analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Power Sources (AREA)
JP2006502871A 2003-01-24 2004-01-16 デバッグの間データ処理システムを制御するための方法および装置 Pending JP2006516780A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/350,658 US6895530B2 (en) 2003-01-24 2003-01-24 Method and apparatus for controlling a data processing system during debug
PCT/US2004/001224 WO2004068279A2 (en) 2003-01-24 2004-01-16 Method and apparatus for controlling a data processing system during debug

Publications (2)

Publication Number Publication Date
JP2006516780A true JP2006516780A (ja) 2006-07-06
JP2006516780A5 JP2006516780A5 (enExample) 2010-11-11

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JP2006502871A Pending JP2006516780A (ja) 2003-01-24 2004-01-16 デバッグの間データ処理システムを制御するための方法および装置

Country Status (7)

Country Link
US (1) US6895530B2 (enExample)
EP (1) EP1590912A2 (enExample)
JP (1) JP2006516780A (enExample)
KR (1) KR100993134B1 (enExample)
CN (1) CN1742458B (enExample)
TW (1) TWI338835B (enExample)
WO (1) WO2004068279A2 (enExample)

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JP2023509711A (ja) * 2020-01-02 2023-03-09 テキサス インスツルメンツ インコーポレイテッド デバッガ及び仲裁インタフェースを備えた集積回路

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US7870430B2 (en) * 2008-02-29 2011-01-11 Freescale Semiconductor, Inc. Method and apparatus for sharing debug resources
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US9612987B2 (en) * 2009-05-09 2017-04-04 Cypress Semiconductor Corporation Dynamically reconfigurable analog routing circuits and methods for system on a chip
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US8826079B2 (en) * 2011-12-16 2014-09-02 Arm Limited Data processing apparatus and method for identifying debug events
US9213388B2 (en) 2012-09-21 2015-12-15 Atmel Corporation Delaying reset signals in a microcontroller system
US9507406B2 (en) * 2012-09-21 2016-11-29 Atmel Corporation Configuring power domains of a microcontroller system
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KR20150019457A (ko) * 2013-08-14 2015-02-25 삼성전자주식회사 시스템 온 칩, 이의 동작 방법, 및 이를 포함하는 시스템
US9383807B2 (en) 2013-10-01 2016-07-05 Atmel Corporation Configuring power domains of a microcontroller system
US9483373B2 (en) * 2014-02-14 2016-11-01 Freescale Semiconductor, Inc. Debug configuration tool with layered graphical user interface
US9270553B1 (en) 2014-03-26 2016-02-23 Amazon Technologies, Inc. Dynamic service debugging in a virtual environment
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023509711A (ja) * 2020-01-02 2023-03-09 テキサス インスツルメンツ インコーポレイテッド デバッガ及び仲裁インタフェースを備えた集積回路
JP7698650B2 (ja) 2020-01-02 2025-06-25 テキサス インスツルメンツ インコーポレイテッド デバッガ及び仲裁インタフェースを備えた集積回路

Also Published As

Publication number Publication date
WO2004068279B1 (en) 2004-11-25
US20040148548A1 (en) 2004-07-29
KR100993134B1 (ko) 2010-11-10
WO2004068279A3 (en) 2004-09-30
KR20050100639A (ko) 2005-10-19
CN1742458B (zh) 2010-09-29
TW200422819A (en) 2004-11-01
TWI338835B (en) 2011-03-11
CN1742458A (zh) 2006-03-01
EP1590912A2 (en) 2005-11-02
US6895530B2 (en) 2005-05-17
WO2004068279A2 (en) 2004-08-12

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