JP5427775B2 - 低パワーキャッシュアクセスモードを備えたデータ処理デバイス - Google Patents
低パワーキャッシュアクセスモードを備えたデータ処理デバイス Download PDFInfo
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- JP5427775B2 JP5427775B2 JP2010506332A JP2010506332A JP5427775B2 JP 5427775 B2 JP5427775 B2 JP 5427775B2 JP 2010506332 A JP2010506332 A JP 2010506332A JP 2010506332 A JP2010506332 A JP 2010506332A JP 5427775 B2 JP5427775 B2 JP 5427775B2
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- 230000008859 change Effects 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 230000002093 peripheral effect Effects 0.000 description 14
- 230000007704 transition Effects 0.000 description 13
- 230000008569 process Effects 0.000 description 12
- 239000003795 chemical substances by application Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000004044 response Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001427 coherent effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Power Sources (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Microcomputers (AREA)
Description
cache transaction requests)キャッシュメッセージを受け取るように構成されている。キャッシュメッセージは、プロセッサ105および周辺デバイス106,107からのコヒーレンシトランザクションまたはキャッシュアクセス要求を表しうる。コヒーレンシエージェント150は、信号C_CTRL1、C_CTRL2およびC_CTRL3を介して、受信キャッシュメッセージに関する情報を提供する。
Claims (9)
- 第1の期間、プロセッサに第1の動作電圧を供給するステップ(402)と、
前記第1の期間に、前記プロセッサで命令を実行するステップ(404)と、
前記第1の期間にモード変化指標を受け取る(406)と、第2の期間、前記プロセッサに、前記第1の動作電圧よりも低い保持電圧を供給するステップ(408)であって、前記第2の期間、前記プロセッサは保持状態にあるステップと、
前記第2の期間に第1のキャッシュメッセージを受け取る(410)と、第3の期間、前記プロセッサに、前記第1の動作電圧よりも低く、前記保持電圧よりも高い第2の動作電圧を供給するステップ(412)と、
前記第3の期間に、前記第1のキャッシュメッセージを処理するステップ(414)とを含む方法。 - 前記キャッシュメッセージはキャッシュコヒーレンシメッセージである請求項1に記載の方法。
- 前記キャッシュメッセージの処理が完了すると、第4の期間、前記プロセッサに前記保持電圧を供給するステップ(416)を更に含む、請求項1に記載の方法。
- 前記第4の期間に、第2のキャッシュメッセージを受け取るステップ(206)と、
前記第2のキャッシュメッセージを受け取ると、第5の期間、前記第2の動作電圧を供給するステップ(208)とを更に含む、請求項3に記載の方法。 - 前記第1の期間、前記プロセッサに第1の周波数を有するクロック信号を供給する(160)ステップと、
前記第3の期間、前記プロセッサに第2の周波数を有するクロック信号を供給する(160)ステップとを更に含む、請求項1に記載の方法。 - 受け取ったキャッシュメッセージの数を基に前記第2の周波数を決定するステップを更に含む、請求項5に記載の方法。
- 前記第2の周波数を決定するステップは、第1の時間期間に受け取ったキャッシュメッセージの数を基に前記第2の周波数を決定するステップを含む、請求項6に記載の方法。
- プロセッサコアおよびキャッシュを有するプロセッサ(102)と、
前記プロセッサの動作モードを制御するように構成されたモード制御モジュール(140)と、
前記モード制御モジュールが前記プロセッサのアクティブモードを指示すると、前記プロセッサの動作電圧を第1の電圧に設定し、
前記モード制御モジュールが、前記プロセッサがキャッシュメッセージを処理することが可能な前記プロセッサの低処理モードを指示すると、前記プロセッサの前記動作電圧を前記第1の電圧よりも低い第2の電圧に設定し、
前記モード制御モジュールが、前記プロセッサを保持モードにすることを指示すると、前記動作電圧を前記第2の電圧よりも低い第3の電圧に設定するように構成された電圧調整器(130)と、
を備え、
前記モード制御モジュールは、前記プロセッサが前記保持モードのときに前記プロセッサがキャッシュメッセージを受け取ると、前記動作モードを前記低処理モードに設定するように構成されている、
デバイス。 - 前記モード制御モジュールは、前記プロセッサが前記キャッシュメッセージの処理を完了すると、前記動作モードを前記保持モードに設定するように構成されている、請求項8に記載のデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/743,388 | 2007-05-02 | ||
US11/743,388 US7941683B2 (en) | 2007-05-02 | 2007-05-02 | Data processing device with low-power cache access mode |
PCT/US2008/005692 WO2008137079A2 (en) | 2007-05-02 | 2008-05-02 | Data processing device with low-power cache access mode |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010526374A JP2010526374A (ja) | 2010-07-29 |
JP5427775B2 true JP5427775B2 (ja) | 2014-02-26 |
Family
ID=39940497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010506332A Active JP5427775B2 (ja) | 2007-05-02 | 2008-05-02 | 低パワーキャッシュアクセスモードを備えたデータ処理デバイス |
Country Status (8)
Country | Link |
---|---|
US (1) | US7941683B2 (ja) |
JP (1) | JP5427775B2 (ja) |
KR (1) | KR101473907B1 (ja) |
CN (1) | CN101730872A (ja) |
DE (1) | DE112008001223B4 (ja) |
GB (1) | GB2460602B (ja) |
TW (1) | TW200910078A (ja) |
WO (1) | WO2008137079A2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8479028B2 (en) * | 2007-09-17 | 2013-07-02 | Intel Corporation | Techniques for communications based power management |
US8028181B2 (en) * | 2008-09-19 | 2011-09-27 | Intel Corporation | Processor power consumption control and voltage drop via micro-architectural bandwidth throttling |
US8103830B2 (en) | 2008-09-30 | 2012-01-24 | Intel Corporation | Disabling cache portions during low voltage operations |
US9678878B2 (en) | 2008-09-30 | 2017-06-13 | Intel Corporation | Disabling cache portions during low voltage operations |
US8352819B2 (en) * | 2009-04-15 | 2013-01-08 | Arm Limited | State retention using a variable retention voltage |
US20110112798A1 (en) * | 2009-11-06 | 2011-05-12 | Alexander Branover | Controlling performance/power by frequency control of the responding node |
US20120096290A1 (en) * | 2010-10-14 | 2012-04-19 | Keynetik, Inc. | Distributed Architecture for Situation Aware Sensory Application |
US8732499B2 (en) | 2011-05-27 | 2014-05-20 | Arm Limited | State retention circuit adapted to allow its state integrity to be verified |
US8639960B2 (en) | 2011-05-27 | 2014-01-28 | Arm Limited | Verifying state integrity in state retention circuits |
JP2013008270A (ja) * | 2011-06-27 | 2013-01-10 | Renesas Electronics Corp | 並列演算装置及びマイクロコンピュータ |
US20130124891A1 (en) * | 2011-07-15 | 2013-05-16 | Aliphcom | Efficient control of power consumption in portable sensing devices |
US20130117511A1 (en) * | 2011-11-08 | 2013-05-09 | Arm Limited | Data processing apparatus and method |
US9063734B2 (en) * | 2012-09-07 | 2015-06-23 | Atmel Corporation | Microcontroller input/output connector state retention in low-power modes |
US9317100B2 (en) * | 2013-01-10 | 2016-04-19 | Advanced Micro Devices, Inc. | Accelerated cache rinse when preparing a power state transition |
KR101475931B1 (ko) * | 2013-05-24 | 2014-12-23 | 고려대학교 산학협력단 | 캐시 및 그 운영 방법 |
JP6130750B2 (ja) * | 2013-07-16 | 2017-05-17 | 株式会社東芝 | メモリ制御回路およびプロセッサ |
US9965220B2 (en) * | 2016-02-05 | 2018-05-08 | Qualcomm Incorporated | Forced idling of memory subsystems |
US20180024610A1 (en) * | 2016-07-22 | 2018-01-25 | Futurewei Technologies, Inc. | Apparatus and method for setting a clock speed/voltage of cache memory based on memory request information |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6014751A (en) * | 1997-05-05 | 2000-01-11 | Intel Corporation | Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state |
EP0901063A3 (en) * | 1997-09-05 | 2000-05-24 | Texas Instruments Incorporated | Power management methods |
US6118306A (en) * | 1998-12-03 | 2000-09-12 | Intel Corporation | Changing clock frequency |
US6795896B1 (en) * | 2000-09-29 | 2004-09-21 | Intel Corporation | Methods and apparatuses for reducing leakage power consumption in a processor |
US6988211B2 (en) * | 2000-12-29 | 2006-01-17 | Intel Corporation | System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field |
US6920574B2 (en) * | 2002-04-29 | 2005-07-19 | Apple Computer, Inc. | Conserving power by reducing voltage supplied to an instruction-processing portion of a processor |
JP3857661B2 (ja) * | 2003-03-13 | 2006-12-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 情報処理装置、プログラム、及び記録媒体 |
CA2527326C (en) * | 2003-05-27 | 2015-07-28 | International Business Machines Corporation | Method and apparatus for specifying factors that impede power savings of a processor |
US7299370B2 (en) | 2003-06-10 | 2007-11-20 | Intel Corporation | Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states |
GB2403561A (en) * | 2003-07-02 | 2005-01-05 | Advanced Risc Mach Ltd | Power control within a coherent multi-processor system |
US7664970B2 (en) * | 2005-12-30 | 2010-02-16 | Intel Corporation | Method and apparatus for a zero voltage processor sleep state |
US7337335B2 (en) * | 2004-12-21 | 2008-02-26 | Packet Digital | Method and apparatus for on-demand power management |
JP2006318380A (ja) * | 2005-05-16 | 2006-11-24 | Handotai Rikougaku Kenkyu Center:Kk | 回路システム |
-
2007
- 2007-05-02 US US11/743,388 patent/US7941683B2/en active Active
-
2008
- 2008-05-01 TW TW097116042A patent/TW200910078A/zh unknown
- 2008-05-02 CN CN200880014524A patent/CN101730872A/zh active Pending
- 2008-05-02 JP JP2010506332A patent/JP5427775B2/ja active Active
- 2008-05-02 WO PCT/US2008/005692 patent/WO2008137079A2/en active Application Filing
- 2008-05-02 KR KR1020097025205A patent/KR101473907B1/ko active IP Right Grant
- 2008-05-02 GB GB0918043A patent/GB2460602B/en active Active
- 2008-05-02 DE DE112008001223T patent/DE112008001223B4/de active Active
Also Published As
Publication number | Publication date |
---|---|
TW200910078A (en) | 2009-03-01 |
KR101473907B1 (ko) | 2014-12-17 |
WO2008137079A2 (en) | 2008-11-13 |
KR20100017583A (ko) | 2010-02-16 |
DE112008001223T5 (de) | 2010-03-11 |
CN101730872A (zh) | 2010-06-09 |
DE112008001223B4 (de) | 2013-02-07 |
WO2008137079A3 (en) | 2009-07-02 |
GB2460602B (en) | 2011-09-21 |
US7941683B2 (en) | 2011-05-10 |
GB0918043D0 (en) | 2009-12-02 |
US20080276236A1 (en) | 2008-11-06 |
JP2010526374A (ja) | 2010-07-29 |
GB2460602A (en) | 2009-12-09 |
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