JP2006512786A - バイポーラトランジスタの形成方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 110
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 claims description 48
- 230000015572 biosynthetic process Effects 0.000 claims description 47
- 239000012535 impurity Substances 0.000 claims description 32
- 238000000605 extraction Methods 0.000 claims description 29
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000011065 in-situ storage Methods 0.000 claims description 8
- 238000003631 wet chemical etching Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 114
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
Description
例えば非特許文献1(T.F. Meister et al., IEDMTechniucal Digest 1995, pp 739−741)に開示されているDPSA(double polysilicon self−aligned:2重ポリシリコン自己整合)トランジスタは、p+型ポリシリコンベース取り出し部及びn+型エミッタコンタクトとして、これらのベース取り出し部及びエミッタコンタクトのために特別に堆積させるそれぞれp+型ポリシリコン層及びn+型ポリシリコン層を使用する。この場合、エミッタ開口においては、n+型ポリシリコンエミッタ層は、ベース取り出し部のp+型ポリシリコン層からスペーサによって自己整合により絶縁する。トランジスタを横方向及び縦方向に縮小することができ、かつ寄生容量成分及び寄生抵抗成分を小さくする、という観点からすると、DPSAトランジスタ構造は非常に高速な動作を必要とする用途に最も適する。この場合、DPSAトランジスタはイオン注入Siベース及びエピタキシャル成長SiGeベースを含む。
図4では、参照符号1はシリコン半導体基板を指し、10は埋込み層構造のn+型サブコレクタ領域を指し、20はp+型チャネル阻止領域を指し、25はn−型コレクタ領域を指し、30はp型ベース領域を指し、35はCVD絶縁酸化膜層を指し、15はLOCOS絶縁酸化膜層を指し、40はp+型ベース取り出し部を指し、45はn+型コレクタコンタクトを指し、55はシリコン酸化膜/シリコン窒化膜から成る2重スペーサを指し、そして50はn+型エミッタコンタクトを指す。
間の活性トランジスタ領域に形成される。制御するのが極めて難しい前記自然酸化膜層36の厚さは、DPSAトランジスタの電流利得及びエミッタ抵抗の両方に大きく影響する。
この目的は、請求項1によるバイポーラトランジスタの形成方法を用いて実現することができる。
一の好適な実施形態によれば、炭素をエミッタ層に導入する。従って、ベース層に含まれる不純物の外方拡散が後の工程において生じる現象を防止することができる。
更に別の好適な実施形態によれば、第2絶縁領域をコレクタ領域とベース取り出し領域との間に設け、そしてベース領域を選択的にコレクタ領域上のエミッタ開口に形成する前に、第2絶縁領域のエミッタ開口部分をウェット化学エッチングによって開口する。
更に別の好適な実施形態によれば、マスク領域は酸化膜層及び被覆窒化膜層を有し、被覆窒化膜層は開口の形成プロセス中に除去し、第1サイドウォールスペーサは酸化膜層の上の開口に形成し、そして酸化膜層はウェット化学エッチングによって開口する。
更に別の好適な実施形態によれば、露出ベース領域の自然酸化膜の除去は、エピタキシ
ャル成長装置において水素雰囲気の熱処理によって行なわれ、そして続いて、エミッタ層を異なる構造に成長させる操作が、エピタキシャル成長装置において、in−situに不純物がドープされる方法を用いて行なわれる。
法によって大きく下げることができる。更に、同じ厚さのn+型ポリシリコン層と比較すると、エミッタのn+型単結晶シリコン層60a’のシート抵抗は3分の1以下に小さくなる。同じように、この構造は、不所望なアスペクト比を有する、DPSAトランジスタの狭いエミッタ開口Fにおいて可能な限り小さいエミッタ抵抗を実現するために非常に有利である。
選択エピタキシャル成長によるSiGeベースを用いて形成されるDPSAトランジスタの公知の形成方法は、例えば特許文献2(ドイツ特許第199,58,062C2号)に完全な形で記載されている。第2の実施形態を理解するために最も重要な形成工程で、ベースの選択成長から始まる形成工程について以下に説明する。
に設け、これらのサイドウォールは後の工程において、p+型ベース取り出し部40をn+型エミッタ領域から絶縁するように作用する、またはp+型ベース取り出し部40の他の側部エッジをn+型エミッタポリシリコンの成長中に保護するように作用する。
第3の実施形態は、全面エピタキシャル成長を行なって異なるエピタキシャル構造のSiGeエピタキシャル層が形成されるようにすることにより得られるDPSAトランジスタである。
図は、最近発行された刊行物にも示されている(例えば、非特許文献3:B. Jagannathan et al., IEEE Electron Device Letters, Vol. 23, 2002, pp. 258−260を参照されたい)。
。
(参照符号一覧)
25 コレクタ領域
30 ベース領域
35,35’,35’’ 酸化膜層
40,160,160’ ベース取り出し領域
55’,80,180,180’ 酸化膜サイドウォールスペーサ
60a,b 単結晶,多結晶
60a’,b’ エミッタ
F エミッタ開口
1 シリコン基板
10 サブコレクタ領域
70,71 窒化膜層
71a 窒化膜サイドウォールスペーサ
U オーバーハング
32,120 真性ベース層
34,130 ベースキャップ層
90 窒化膜マスク
M フォトマスク
100 層間誘電体
96,97,98 コンタクト
110 配線
95 シリサイド
140 酸化膜層
150 窒化膜層
170 酸化膜層
Claims (10)
- 半導体基板(1)に第1導電型(n)のコレクタ領域(25)をコレクタ領域が基板に埋め込まれる形で設け、及び前記コレクタ領域の上面を露出させる工程と、
第2導電型(p)の単結晶真性ベース領域(30;32;120)及び第1導電型または第2導電型(n,p)の任意選択の単結晶ベースキャップ領域(34;130)をコレクタ領域(25)の上にベース領域(30;32;34;120,130)として設ける工程と、
第2導電型(p)のベース取り出し領域(40;160)をベース領域(30;32;34;120,130)の上に設ける工程と、
第1絶縁領域(35;35’’;170)をベース取り出し領域(40;160)の上に設ける工程と、
第1絶縁領域(35;35’’;170)及びベース取り出し領域(40;160)に開口(F)を設けてベース領域(30;32;34;120,130)を少なくとも一部露出させる工程と、
第1絶縁サイドウォールスペーサ(55’;80;180)を開口に設けてベース取り出し領域(40;160)を絶縁する工程と、
露出ベース領域(30;32;34;120,130)の自然酸化膜を除去する工程と、
エミッタ層(60a,60b)を異なる構造に成長させてパターニングする工程であって、単結晶エミッタ層(60a)がベース領域(30;32;34;120,130)の上に、かつ多結晶エミッタ層(60a)が第1絶縁領域(35;35’’;170)及び第1絶縁サイドウォールスペーサ(55’;80;180)の上に形成される、パターニング工程と、
熱処理工程を実施して単結晶エミッタ層(60a)をベース領域(30;32;34;120,130)にベース領域の一部の深さにまで拡散させ、かつ拡大単結晶エミッタ層(60a’)を形成する工程と、を備える、バイポーラトランジスタの製造方法。 - 炭素をエミッタ層(60a,60b)に含有させることを特徴とする、請求項1記載の方法。
- 熱処理工程は高速アニール処理工程、好適にはランプアニール工程であることを特徴とする、請求項1又は2記載の方法。
- 第2絶縁領域(35’)をコレクタ領域(25)とベース取り出し領域(40;160)との間に設け、そしてベース領域(32,34)を選択的にコレクタ領域(25)上のエミッタ開口(F)に形成する前に、第2絶縁領域のエミッタ開口(F)部分をウェット化学エッチングによって開口することを特徴とする、請求項1〜3のいずれか一項に記載の方法。
- ベース領域(120,130)を、コレクタ領域(25)が埋め込まれ、かつ前記コレクタ領域の上面が露出した状態の半導体基板(1)の全面を覆って成長させ、マスク領域(140,150)をベース領域(120,130)の上方に、後で形成されるエミッタ開口(F)に対応する形で形成し、前記マスク領域はベース取り出し領域(160)及び被覆第1絶縁領域(170)に埋まり、この後、開口(F)が形成されることを特徴とする、請求項1〜4のいずれか一項に記載の方法。
- ベース取り出し領域(40;160)はベース領域(120,130)の上に、in−situに不純物がドープされる選択エピタキシャル成長を用いて成長させることを特徴とする、請求項5に記載の方法。
- マスク領域(140,150)は酸化膜層(140)及び被覆窒化膜層(150)を有し、被覆窒化膜層(150)は開口(F)の形成プロセス中に除去し、第1サイドウォールスペーサ(180)は酸化膜層(140)の上の開口(F)に形成し、そして酸化膜層(140)はウェット化学エッチングによって開口することを特徴とする、請求項5又は6に記載の方法。
- ベース領域(120,130)は下部の相対的に高い不純物濃度の第1真性ベース層(120)及び上部の相対的に低い不純物濃度のベースキャップ層(130)を有し、ベース領域の上にはベース取り出し領域(160)が設けられ、ベースキャップ層(130)は、熱処理工程の間にベース取り出し領域(160)から不純物が拡散することにより不純物濃度が高くなることを特徴とする、請求項5〜7のいずれか一項に記載の方法。
- ベースキャップ層(130)は、マスク領域(140,150)形成の後に薄くすることを特徴とする、請求項7に記載の方法。
- 露出ベース領域(30;32;34;120,130)の自然酸化膜の除去は、エピタキシャル成長装置において水素雰囲気の熱処理によって行なわれ、そして続いて、エミッタ層(60a,60b)を異なる構造に成長させる操作が、エピタキシャル成長装置において、in−situに不純物がドープされる方法を用いて行なわれることを特徴とする、請求項1〜9のいずれか一項に記載の方法。
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DE10317098A DE10317098A1 (de) | 2003-04-14 | 2003-04-14 | Verfahren zur Herstellung eines Bipolartransistors |
PCT/EP2004/003125 WO2004090968A1 (de) | 2003-04-14 | 2004-03-24 | Verfahren zur herstellung eines bipolartransistors |
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ATE475640T1 (de) | 2004-03-12 | 2010-08-15 | Lilly Co Eli | Antagonisten des opioidrezeptors |
DE102005046738A1 (de) * | 2005-09-29 | 2007-03-22 | Infineon Technologies Ag | Bipolartransistor |
DE102006011240A1 (de) * | 2006-03-10 | 2007-09-20 | Infineon Technologies Ag | Bipolartransistor und Verfahren zum Herstellen eines Bipolartransistors |
US7687887B1 (en) * | 2006-12-01 | 2010-03-30 | National Semiconductor Corporation | Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter |
US7910447B1 (en) * | 2007-05-15 | 2011-03-22 | National Semiconductor Corporation | System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter |
US7855119B2 (en) | 2007-06-15 | 2010-12-21 | Sandisk 3D Llc | Method for forming polycrystalline thin film bipolar transistors |
WO2008156694A1 (en) * | 2007-06-15 | 2008-12-24 | Sandik 3D Llc | Polycrystalline thin film bipolar transistors and methods of making the same |
US8004013B2 (en) | 2007-06-15 | 2011-08-23 | Sandisk 3D Llc | Polycrystalline thin film bipolar transistors |
US7947552B2 (en) | 2008-04-21 | 2011-05-24 | Infineon Technologies Ag | Process for the simultaneous deposition of crystalline and amorphous layers with doping |
US9240611B2 (en) * | 2013-01-15 | 2016-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures having a micro-battery and methods for making the same |
US20140291681A1 (en) * | 2013-03-28 | 2014-10-02 | Skyworks Solutions, Inc. | Phase noise reduction in transistor devices |
DE102016216084B8 (de) * | 2016-08-26 | 2021-12-23 | Infineon Technologies Dresden Gmbh | Verfahren zum Herstellen eines Bipolartransistors |
FR3078197B1 (fr) | 2018-02-21 | 2020-03-13 | Stmicroelectronics (Crolles 2) Sas | Dispositif de transistor bipolaire et procede de fabrication correspondant |
US11018247B1 (en) | 2019-12-26 | 2021-05-25 | Nxp Usa, Inc. | Semiconductor device with a base link region and method therefor |
US11855196B2 (en) | 2021-10-25 | 2023-12-26 | Globalfoundries Singapore Pte. Ltd. | Transistor with wrap-around extrinsic base |
US11855195B2 (en) | 2021-10-25 | 2023-12-26 | Globalfoundries Singapore Pte. Ltd. | Transistor with wrap-around extrinsic base |
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US5266504A (en) * | 1992-03-26 | 1993-11-30 | International Business Machines Corporation | Low temperature emitter process for high performance bipolar devices |
JP2551353B2 (ja) * | 1993-10-07 | 1996-11-06 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO1997037377A1 (en) * | 1996-03-29 | 1997-10-09 | Philips Electronics N.V. | Manufacture of a semiconductor device with an epitaxial semiconductor zone |
DE19755979A1 (de) * | 1996-12-09 | 1999-06-10 | Inst Halbleiterphysik Gmbh | Silizium-Germanium-Heterobipolartransistor |
FR2779572B1 (fr) * | 1998-06-05 | 2003-10-17 | St Microelectronics Sa | Transistor bipolaire vertical a faible bruit et procede de fabrication correspondant |
US6180478B1 (en) * | 1999-04-19 | 2001-01-30 | Industrial Technology Research Institute | Fabrication process for a single polysilicon layer, bipolar junction transistor featuring reduced junction capacitance |
DE19940278A1 (de) | 1999-08-26 | 2001-03-08 | Inst Halbleiterphysik Gmbh | Schichtstruktur für bipolare Transistoren und Verfahren zu deren Herstellung |
US6406966B1 (en) * | 2000-11-07 | 2002-06-18 | National Semiconductor Corporation | Uniform emitter formation using selective laser recrystallization |
DE10104776A1 (de) * | 2001-02-02 | 2002-08-22 | Infineon Technologies Ag | Bipolartransistor und Verfahren zu dessen Herstellung |
DE10160511A1 (de) * | 2001-11-30 | 2003-06-12 | Ihp Gmbh | Bipolarer Transistor |
US6541336B1 (en) | 2002-05-15 | 2003-04-01 | International Business Machines Corporation | Method of fabricating a bipolar transistor having a realigned emitter |
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