JP2006345007A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2006345007A
JP2006345007A JP2006263136A JP2006263136A JP2006345007A JP 2006345007 A JP2006345007 A JP 2006345007A JP 2006263136 A JP2006263136 A JP 2006263136A JP 2006263136 A JP2006263136 A JP 2006263136A JP 2006345007 A JP2006345007 A JP 2006345007A
Authority
JP
Japan
Prior art keywords
integrated circuit
electrode
capacitor
semiconductor integrated
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006263136A
Other languages
Japanese (ja)
Other versions
JP4392422B2 (en
Inventor
Shigeo Tanahashi
成夫 棚橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2006263136A priority Critical patent/JP4392422B2/en
Publication of JP2006345007A publication Critical patent/JP2006345007A/en
Application granted granted Critical
Publication of JP4392422B2 publication Critical patent/JP4392422B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stable power supply with low resistance and inductance and a ground potential to a semiconductor integrated circuit element, using a decoupling capacitor. <P>SOLUTION: The semiconductor device 9 includes an insulating base body 1, having a concave portion 1a for housing a capacitor 4 in the upper surface thereof, in which a wiring conductor 2 is formed on the periphery of the opening of the concave portion 1a, and a terminal 3 for providing a power supply is formed on the bottom surface of the concave portion 1a; a capacitor 4, housed in the concave portion 1a whose one terminal electrode is connected to the terminal 3 for providing a power supply; a mounting wiring substrate 6, attached on the insulating base body 1 so as to cover the opening of the concave portion 1a, in which through-hole conductors 7, respectively, connected to the other terminal electrode of the capacitor 4 or to the wiring conductor, are formed; and a semiconductor integrated circuit element 8 mounted on the mounting wiring substrate 6, in which via the through-hole conductors 7, an electrode of the power supply is connected to the other terminal electrode of the capacitor 4, and a signal electrode is connected electrically to the wiring conductor 2 of the insulating base body 1, respectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明はコンピュータ等の情報処理装置に使用される半導体集積回路素子を実装して成る半導体装置に関し、より詳細には、半導体集積回路素子の極めて近傍に電源供給用のデカップリングコンデンサを配置して、半導体集積回路素子を容易かつ安定に高速動作させることができる半導体装置に関するものである。   The present invention relates to a semiconductor device in which a semiconductor integrated circuit element used in an information processing apparatus such as a computer is mounted. More specifically, a decoupling capacitor for supplying power is disposed in the vicinity of the semiconductor integrated circuit element. The present invention relates to a semiconductor device capable of operating a semiconductor integrated circuit element easily and stably at high speed.

従来より、半導体集積回路素子を高速でかつ安定して動作させる目的で、半導体集積回路素子への電源供給および電源ノイズ抑制のためのいわゆるデカップリングコンデンサを半導体集積回路素子の近傍に配置し、素子に対する電源電位およびグランド電位を安定させることが検討されている。   Conventionally, in order to operate a semiconductor integrated circuit element at high speed and stably, a so-called decoupling capacitor for supplying power to the semiconductor integrated circuit element and suppressing power supply noise is disposed in the vicinity of the semiconductor integrated circuit element. It has been studied to stabilize the power supply potential and ground potential with respect to.

例えば、半導体装置を構成する半導体素子収納用パッケージに半導体集積回路素子を実装する目的で形成された凹部、いわゆるキャビティ部の底面に半導体集積回路素子の裏面を金・シリコン等からなる合金ろう材で接合し、この半導体集積回路素子の表面外周部に設けられた信号および電源接続用の端子電極と、半導体素子収納用パッケージのキャビティ部外側に設けられ、配線導体に接続された端子電極とを金やアルミニウム等から成る細線によってワイヤボンディング接続する場合であれば、この半導体集積回路素子に接続されるデカップリングコンデンサは、例えばチップコンデンサを用いて、この半導体素子収納用パッケージが実装される回路基板上に、あるいは半導体素子収納用パッケージの表面の外周部に実装される。   For example, a recess formed for the purpose of mounting a semiconductor integrated circuit element on a package for housing a semiconductor element constituting a semiconductor device, that is, a bottom surface of a so-called cavity portion, and a back surface of the semiconductor integrated circuit element is made of an alloy brazing material made of gold, silicon, The terminal electrode for signal and power supply provided on the outer periphery of the surface of the semiconductor integrated circuit element and the terminal electrode provided on the outer side of the cavity part of the package for housing the semiconductor element and connected to the wiring conductor are joined together. In the case of wire bonding connection using thin wires made of aluminum or aluminum, the decoupling capacitor connected to the semiconductor integrated circuit element is, for example, a chip capacitor on the circuit board on which the semiconductor element storage package is mounted. Alternatively, it is mounted on the outer periphery of the surface of the semiconductor element storage package.

しかしながら、半導体集積回路素子の高速化に伴い、デカップリングコンデンサが半導体素子収納用パッケージの外側に配置された場合は、このデカップリングコンデンサと半導体集積回路素子との距離が長くなるため、その電気的接続を行なうための配線が有する抵抗やインダクタンスにより安定した電源供給あるいはグランド電位の供給が困難となる。そのため、デカップリングコンデンサを半導体集積回路素子の近傍に配置する目的で、例えば、半導体素子収納用パッケージをセラミック積層技術により形成し、誘電体層間に積層された電源配線およびグランド配線を面状に形成することによりそれらの間で容量を形成することによって、半導体素子収納用パッケージ内部にデカップリングコンデンサを形成することが行なわれてきた。   However, as the speed of semiconductor integrated circuit elements increases, when a decoupling capacitor is disposed outside the package for housing a semiconductor element, the distance between the decoupling capacitor and the semiconductor integrated circuit element becomes longer. Stable power supply or ground potential supply becomes difficult due to the resistance and inductance of the wiring for connection. Therefore, for the purpose of placing the decoupling capacitor in the vicinity of the semiconductor integrated circuit element, for example, a package for housing the semiconductor element is formed by a ceramic lamination technique, and the power supply wiring and the ground wiring laminated between the dielectric layers are formed in a planar shape. Thus, a decoupling capacitor has been formed inside a package for housing a semiconductor element by forming a capacitance between them.

また、有機多層技術を用いた半導体素子収納用パッケージの場合であれば、有機樹脂の誘電率が低いことから、セラミック多層技術による場合のように誘電体層を利用してパッケージ内部にデカップリングコンデンサを形成することが困難であるため、半導体集積回路素子が実装された部位の外周部にデカップリングコンデンサとしてのチップコンデンサを実装することが行なわれてきた。   In the case of a package for semiconductor element storage using organic multilayer technology, the dielectric constant of the organic resin is low, so that a decoupling capacitor is used inside the package using a dielectric layer as in the case of ceramic multilayer technology. Since it is difficult to form a chip capacitor, a chip capacitor as a decoupling capacitor has been mounted on the outer periphery of a portion where a semiconductor integrated circuit element is mounted.

しかしながら、近年、半導体集積回路素子の動作が更に高速になったことから、半導体集積回路素子を半導体素子収納用パッケージに搭載してワイヤボンディング接続と、金属細線のインダクタンスの影響が無視できなくなって電源およびグランドの電位を安定して供給することが困難となった。   In recent years, however, the operation of semiconductor integrated circuit elements has become even faster, so that the effects of the wire bonding connection and the inductance of the fine metal wires can no longer be ignored by mounting the semiconductor integrated circuit element on the package for housing the semiconductor element. In addition, it has become difficult to stably supply the ground potential.

そこで、ワイヤボンディング接続に代わって、半導体集積回路素子の端子電極上に半田ボール等の導体バンプを形成し、これを用いて半導体素子収納用パッケージや配線基板上の接続電極に直接搭載し接続する、いわゆるフリップチップ接続法が考案された。   Therefore, instead of wire bonding connection, a conductor bump such as a solder ball is formed on the terminal electrode of the semiconductor integrated circuit element, and this is used to directly mount and connect to the connection electrode on the semiconductor element storage package or wiring board. The so-called flip chip connection method was devised.

しかしながら、半導体集積回路素子をフリップチップ実装する場合は、半導体集積回路素子の表面に形成された端子電極とパッケージや配線基板側の接続電極とを対向させるため、この半導体集積回路素子に接続されるデカップリングコンデンサの配置は、実装される半導体集積回路素子の近傍の外周部に限定されることとなる。   However, when the semiconductor integrated circuit element is flip-chip mounted, the terminal electrode formed on the surface of the semiconductor integrated circuit element is opposed to the connection electrode on the package or wiring board side, so that the semiconductor integrated circuit element is connected to the semiconductor integrated circuit element. The arrangement of the decoupling capacitor is limited to the outer peripheral portion in the vicinity of the semiconductor integrated circuit element to be mounted.

そして、この構成においても、半導体集積回路素子を更に高速で動作させる場合には、デカップリングコンデンサが半導体集積回路素子の近傍の外周部に配置されることから、デカップリングコンデンサからこれが接続される端子電極が形成された半導体集積回路素子の中心部までの配線の有する抵抗およびインダクタンスの影響が無視できないものとなるために半導体集積回路素子への電源およびグランド電位の安定した供給が困難となるという問題点があった。   Even in this configuration, when the semiconductor integrated circuit element is operated at a higher speed, the decoupling capacitor is disposed on the outer peripheral portion in the vicinity of the semiconductor integrated circuit element, and thus the terminal to which the decoupling capacitor is connected. Since the influence of the resistance and inductance of the wiring to the center of the semiconductor integrated circuit element on which the electrode is formed cannot be ignored, it is difficult to stably supply power and ground potential to the semiconductor integrated circuit element. There was a point.

本発明は上記従来技術の問題点に鑑み案出されたものであり、その目的は、高速で動作する半導体集積回路素子に低抵抗かつ低インダクタンスで安定した電源供給およびグランド電位の供給を行なうことができる半導体装置を提供することにある。   The present invention has been devised in view of the above-described problems of the prior art, and an object thereof is to stably supply power and ground potential with low resistance and low inductance to a semiconductor integrated circuit element operating at high speed. It is an object of the present invention to provide a semiconductor device capable of achieving the above.

本発明者は、上記従来技術の問題点に対して種々の検討を行なった結果、半導体集積回路素子を中継基板である実装用配線基板上にフリップチップ接続により実装するとともに、この実装用配線基板を搭載する絶縁基体上面の中央部に凹部を設けてこの凹部にデカップリングコンデンサを実装して収容し、この上に実装用配線基板を載置して半導体集積回路素子とデカップリングコンデンサとを電気的に接続する構成とすることにより、半導体集積回路素子の極めて近傍にデカップリングコンデンサを配置して電源およびグランド電位の供給を極めて低抵抗かつ低インダクタンスで安定して行なえることを見出した。   As a result of various studies on the problems of the above-described prior art, the present inventor has mounted the semiconductor integrated circuit element on the mounting wiring board which is a relay board by flip chip connection, and this mounting wiring board. A recess is formed in the central portion of the upper surface of the insulating substrate, and a decoupling capacitor is mounted and accommodated in the recess, and a mounting wiring board is placed thereon to electrically connect the semiconductor integrated circuit element and the decoupling capacitor. It has been found that the power supply and the ground potential can be stably supplied with a very low resistance and a low inductance by arranging a decoupling capacitor in the very vicinity of the semiconductor integrated circuit element by adopting a configuration in which the connection is made in the same manner.

本発明の半導体装置は、上面にコンデンサを収容する凹部を有し、該凹部の開口周辺に形成された、信号伝送用配線および接地接続用配線を含む配線導体と、前記凹部の底面に形成された電源供給端子と、を有する絶縁基体と、前記凹部内に収容され、前記電源供給端子に一方の端子電極が電気的に接続されたコンデンサと、前記絶縁基体上に前記凹部の開口を覆うように取着され、前記コンデンサの他方の端子電極または前記配線導体にそれぞれ電気的に接続される貫通導体が形成された実装用配線基板と、電源電極と接地電極と信号電極とを有し、前記実装用配線基板上に搭載されてなる半導体集積回路素子であって、前記貫通導体を介して、前記電源電極が前記コンデンサの他方の端子電極に接続され、前記信号電極が前記絶縁基体の前記配線導体の前記信号伝送用配線に接続され、前記接地電極が前記配線導体の前記接地接続用配線にそれぞれ電気的に接続された半導体集積回路素子と、を具備することを特徴とするものである。   The semiconductor device of the present invention has a concave portion for accommodating a capacitor on the upper surface, and is formed on the bottom surface of the concave portion, the wiring conductor including the signal transmission wiring and the ground connection wiring formed around the opening of the concave portion. An insulating base having a power supply terminal, a capacitor housed in the recess, and one terminal electrode electrically connected to the power supply terminal, and an opening of the recess on the insulating base. A mounting wiring board on which a through conductor that is electrically connected to the other terminal electrode of the capacitor or the wiring conductor is formed, a power electrode, a ground electrode, and a signal electrode, A semiconductor integrated circuit element mounted on a wiring board for mounting, wherein the power supply electrode is connected to the other terminal electrode of the capacitor via the through conductor, and the signal electrode is connected to the insulating substrate. A semiconductor integrated circuit element connected to the signal transmission wiring of the wiring conductor, and wherein the ground electrode is electrically connected to the ground connection wiring of the wiring conductor, respectively. is there.

本発明の半導体装置によれば、絶縁基体の凹部内に収容されたデカップリングコンデンサとしてのコンデンサに、凹部を覆うように取着された実装用配線基板に半導体集積回路素子を搭載実装し、実装用配線基板中に形成された貫通導体を介して半導体集積回路素子の電源電極を電気的に接続したことから、従来半導体集積回路素子の近傍の外周部等に配置されていたデカップリングコンデンサを半導体集積回路素子の直近に極めて近接して配置させることができ、半導体集積回路素子の電源電極とデカップリングコンデンサの端子電極との距離を最短に設定することができるため、両者の接続部の抵抗やインダクタンスを最小にすることができる。その結果、高速で動作する半導体集積回路素子を安定して動作させるための素子への電源供給および電源ノイズ抑制を極めて効果的に安定して行なうことができる。   According to the semiconductor device of the present invention, a semiconductor integrated circuit element is mounted and mounted on a mounting wiring board attached so as to cover the concave portion in a capacitor as a decoupling capacitor housed in the concave portion of the insulating base. Since the power supply electrode of the semiconductor integrated circuit element is electrically connected through the through conductor formed in the wiring board for the semiconductor, the decoupling capacitor which has been arranged in the outer peripheral portion in the vicinity of the semiconductor integrated circuit element in the conventional semiconductor It can be placed very close to the integrated circuit element, and the distance between the power supply electrode of the semiconductor integrated circuit element and the terminal electrode of the decoupling capacitor can be set to the shortest. Inductance can be minimized. As a result, the power supply to the element for stably operating the semiconductor integrated circuit element operating at high speed and the suppression of power supply noise can be performed extremely effectively and stably.

以上詳述した通り、本発明の半導体装置によれば、上面にコンデンサを収容する凹部を有し、該凹部の開口周辺に形成された、信号伝送用配線および接地接続用配線を含む配線導体と、前記凹部の底面に形成された電源供給端子と、を有する絶縁基体と、前記凹部内に収容され、前記電源供給端子に一方の端子電極が電気的に接続されたコンデンサと、前記絶縁基体上に前記凹部の開口を覆うように取着され、前記コンデンサの他方の端子電極または前記配線導体にそれぞれ電気的に接続される貫通導体が形成された実装用配線基板と、電源電極と接地電極と信号電極とを有し、前記実装用配線基板上に搭載されてなる半導体集積回路素子であって、前記貫通導体を介して、前記電源電極が前記コンデンサの他方の端子電極に接続され、前記信号電極が前記絶縁基体の前記配線導体の前記信号伝送用配線に接続され、前記接地電極が前記配線導体の前記接地接続用配線にそれぞれ電気的に接続された半導体集積回路素子と、を具備するものとしたことから、従来半導体集積回路素子の近傍の外周部等に配置されていたデカップリングコンデンサを半導体集積回路素子の直近に極めて近接して配置させることができ、半導体集積回路素子の電源電極とデカップリングコンデンサの端子電極との距離を最短に設定することができるため、両者の接続部の抵抗やインダクタンスを最小にすることができる。その結果、高速で動作する半導体集積回路素子を安定して動作させるための素子への電源供給および電源ノイズ抑制を極めて効果的に安定して行なうことができる。   As described above in detail, according to the semiconductor device of the present invention, the wiring conductor including the signal transmission wiring and the ground connection wiring, which has the concave portion for accommodating the capacitor on the upper surface and is formed around the opening of the concave portion, An insulating substrate having a power supply terminal formed on the bottom surface of the recess, a capacitor housed in the recess and having one terminal electrode electrically connected to the power supply terminal, and the insulating substrate A mounting wiring board that is attached to cover the opening of the recess and has a through conductor that is electrically connected to the other terminal electrode of the capacitor or the wiring conductor, a power supply electrode, and a ground electrode, A semiconductor integrated circuit device mounted on the wiring board for mounting, wherein the power supply electrode is connected to the other terminal electrode of the capacitor via the through conductor, A semiconductor integrated circuit element, wherein a signal electrode is connected to the signal transmission wiring of the wiring conductor of the insulating base, and the ground electrode is electrically connected to the ground connection wiring of the wiring conductor, respectively. Therefore, it is possible to dispose the decoupling capacitor, which has been conventionally disposed on the outer peripheral portion in the vicinity of the semiconductor integrated circuit element, in close proximity to the semiconductor integrated circuit element. Since the distance between the terminal electrode of the decoupling capacitor and the terminal electrode of the decoupling capacitor can be set to the shortest, the resistance and inductance of the connecting portion between them can be minimized. As a result, the power supply to the element for stably operating the semiconductor integrated circuit element operating at high speed and the suppression of power supply noise can be performed extremely effectively and stably.

次に、本発明の半導体装置を添付図面に基づき詳細に説明する。   Next, the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

図1は本発明の半導体装置の実施の形態の一例を示す断面図である。同図において、1は絶縁基体、1aは例えばその上面中央部に形成された凹部、2は凹部1aの開口周辺に形成された配線導体、3は凹部1aの底面に形成された電源供給端子である。なお、配線導体2については代表的なもの以外は図示を省略してある。   FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor device of the present invention. In the figure, 1 is an insulating substrate, 1a is a recess formed in the center of the upper surface thereof, 2 is a wiring conductor formed around the opening of the recess 1a, and 3 is a power supply terminal formed on the bottom surface of the recess 1a. is there. The wiring conductor 2 is not shown except for typical ones.

4は凹部1a内に収容され、電源供給端子3に一方の端子電極が電気的に接続された、デカップリングコンデンサとしてのコンデンサ、5はコンデンサ4の一方の端子電極と電源供給端子3とを電気的に接続する導体バンプ、例えば半田バンプである。   A capacitor 4 is housed in the recess 1 a and one terminal electrode is electrically connected to the power supply terminal 3, and serves as a decoupling capacitor. 5, one terminal electrode of the capacitor 4 and the power supply terminal 3 are electrically connected. Conductive bumps, for example, solder bumps.

6は実装用配線基板、7はその内部に形成された貫通導体、8は半導体集積回路素子である。実装用配線基板6は絶縁基体1上に凹部1aの開口を覆うように取着され、半導体集積回路素子8はこの実装用配線基板6上に搭載されている。   Reference numeral 6 denotes a mounting wiring board, 7 denotes a through conductor formed therein, and 8 denotes a semiconductor integrated circuit element. The mounting wiring board 6 is attached on the insulating substrate 1 so as to cover the opening of the recess 1a, and the semiconductor integrated circuit element 8 is mounted on the mounting wiring board 6.

そして、貫通導体7はコンデンサ4の他方の端子電極または配線導体3にそれぞれ電気的に接続されるとともに半導体集積回路素子8の端子電極である電源電極または信号電極に電気的に接続され、この貫通導体7を介して半導体集積回路素子8の電源電極がコンデンサ4の他方の端子電極に、信号電極が絶縁基体1に形成された配線導体2にそれぞれ電気的に接続される。このようにして本発明の半導体装置9が構成されている。   The through conductor 7 is electrically connected to the other terminal electrode or the wiring conductor 3 of the capacitor 4 and is also electrically connected to a power supply electrode or a signal electrode which is a terminal electrode of the semiconductor integrated circuit element 8. The power supply electrode of the semiconductor integrated circuit element 8 is electrically connected to the other terminal electrode of the capacitor 4 and the signal electrode is electrically connected to the wiring conductor 2 formed on the insulating base 1 via the conductor 7. Thus, the semiconductor device 9 of the present invention is configured.

なお、10は半導体装置9が実装される外部電気回路基板、11はその上面に形成された接続用導体、12は半導体装置9の実装用電極と接続用導体11とを電気的に接続する半田等の導電性接続部材である。   Note that 10 is an external electric circuit board on which the semiconductor device 9 is mounted, 11 is a connection conductor formed on the upper surface thereof, and 12 is solder for electrically connecting the mounting electrode of the semiconductor device 9 and the connection conductor 11. Or the like.

また、図2は本発明の半導体装置の実施の形態の他の例を示す、図1と同様の断面図である。図2に示す例の半導体装置9’においては、コンデンサ4と電源供給端子3とを電気的に接続する導体バンプ5に代えて、導電性接着剤または半田等の接続用金属から成る導体層5’を用いている。   FIG. 2 is a sectional view similar to FIG. 1, showing another example of the embodiment of the semiconductor device of the present invention. In the semiconductor device 9 ′ shown in FIG. 2, instead of the conductor bump 5 that electrically connects the capacitor 4 and the power supply terminal 3, a conductor layer 5 made of a connecting metal such as a conductive adhesive or solder. 'Is used.

これらの例において、絶縁基体1は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス等のセラミック材料、もしくはエポキシ・BTレジン・ポリイミド・ベンゾシクロブテン・ポリノルボルネン・フッ素樹脂等の高分子絶縁材料、あるいはセラミック材料から成る無機絶縁物粉末を熱硬化性の高分子絶縁材料で結合して成る複合絶縁材料等から成る、例えば略四角形状の平板状のものである。また、セラミック材料から成る基体の上に高分子絶縁材料から成る層間絶縁層と配線導体とを積層した多層配線部を形成したものであってもよい。その上面中央部には、コンデンサ4を搭載するための凹部1aが形成してある。さらに、その凹部1aの開口周辺には信号伝送用あるいは接地接続用の配線導体2が形成されており、この開口周辺は実装用配線基板6を搭載するための搭載部となっている。   In these examples, the insulating substrate 1 is a ceramic material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a silicon nitride sintered body, or a glass ceramic. Or composite insulation made by bonding polymer insulation material such as epoxy, BT resin, polyimide, benzocyclobutene, polynorbornene, fluororesin, etc., or inorganic insulation powder made of ceramic material with thermosetting polymer insulation material It is made of a material or the like, for example, a substantially rectangular flat plate. Alternatively, a multilayer wiring portion in which an interlayer insulating layer made of a polymer insulating material and a wiring conductor are laminated on a base made of a ceramic material may be formed. A concave portion 1a for mounting the capacitor 4 is formed at the center of the upper surface. Further, a wiring conductor 2 for signal transmission or ground connection is formed around the opening of the recess 1a, and the periphery of the opening is a mounting portion for mounting the mounting wiring board 6.

配線導体2は、例えばタングステンやモリブデン・モリブデン−マンガン・銅・銀・銀−パラジウム等からなる電気配線用導電体であり、絶縁基体1上面の凹部1aの開口周辺から例えば絶縁基体1下面にかけて、金属粉末メタライズ等により複数が被着形成されている。   The wiring conductor 2 is a conductor for electric wiring made of, for example, tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, and the like. From the periphery of the opening of the recess 1a on the upper surface of the insulating base 1 to the lower surface of the insulating base 1, for example. A plurality is formed by metal powder metallization or the like.

また、電源供給端子3は、絶縁基体1の凹部1aの底面に広面積に、あるいは接続パッド形状に配線導体2と同様の材料・方法により形成されており、外部電気回路基板10等からの電源配線が接続されている。   The power supply terminal 3 is formed on the bottom surface of the recess 1a of the insulating base 1 in a wide area or in the shape of a connection pad by the same material and method as the wiring conductor 2, and is supplied with power from the external electric circuit board 10 or the like. Wiring is connected.

絶縁基体1は、例えば酸化アルミニウム質焼結体から成る場合であれば、酸化アルミニウム・酸化珪素・酸化マグネシウム・酸化カルシウム等の原料粉末に適当な有機バインダ・溶剤・可塑剤・分散剤等を添加混合して泥漿状となすとともにこれを従来周知のドクターブレード法を採用してシート状となすことにより複数枚のセラミックグリーンシートを得て、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施すとともに配線導体2および電源供給端子3となる金属ペーストを印刷し、最後にこのセラミックグリーンシートを上下積層するとともに約1600℃の温度で焼成することによって作製される。   If the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder, solvent, plasticizer, dispersant, etc. are added to the raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide. A mixture is made into a mud shape, and a plurality of ceramic green sheets are obtained by adopting a conventionally known doctor blade method to obtain a sheet shape, and then the ceramic green sheet is appropriately punched. At the same time, a metal paste to be used as the wiring conductor 2 and the power supply terminal 3 is printed, and finally, the ceramic green sheets are laminated on top and bottom and fired at a temperature of about 1600 ° C.

なお、配線導体2および電源供給端子3となる金属ペーストは、例えばこれらがタングステンメタライズから成る場合であれば、タングステン粉末に適当な有機バインダ・溶剤・可塑剤等を添加混合してペースト状としたものが用いられ、セラミックグリーンシートへの被着形成はスクリーン印刷法等を採用することによって行なわれる。   The metal paste used as the wiring conductor 2 and the power supply terminal 3 is, for example, a paste made by adding and mixing an appropriate organic binder, solvent, plasticizer, etc. to tungsten powder if these are made of tungsten metallization. The material is used, and the adherence formation to the ceramic green sheet is performed by adopting a screen printing method or the like.

コンデンサ4としては、デカップリングコンデンサとして用いることができる特性を有するものであれば種々のものを用いることができる。例えば、チタン酸バリウム等から成るセラミック誘電体層とニッケル等から成る内部電極層とを交互に多層に積層して成る積層型チップコンデンサや、あるいはセラミック誘電体基体の表面に陽極化成によりタンタルやアルミ等の端子電極を形成したセラミックコンデンサを用いればよい。   Various capacitors 4 can be used as long as they have characteristics that can be used as decoupling capacitors. For example, a multilayer chip capacitor formed by alternately laminating ceramic dielectric layers made of barium titanate or the like and internal electrode layers made of nickel or the like, or tantalum or aluminum by anodizing the surface of a ceramic dielectric substrate. A ceramic capacitor in which terminal electrodes such as those are formed may be used.

また、そのようなコンデンサ4の上面には実装用配線基板6の貫通導体7に対応させた接続用の端子電極が、通常は多数形成されることとなる。例えば、積層型のコンデンサを構成する誘電体層および内部電極層が絶縁基体1と半導体集積回路素子8との間で水平方向の層として垂直方向に積み重ねられている場合には、内部電極層と接続用の端子電極との接続は、誘電体層を貫通して形成された貫通導体等により行なわれる。また、誘電体層および内部電極層が絶縁基体1と半導体集積回路素子8との間で垂直方向の層として水平方向に積層されている場合には、コンデンサ4の上面となる積層断面に導出された内部電極層に接続されるように接続用の端子電極が形成されることとなる。   Further, a large number of terminal electrodes for connection corresponding to the through conductors 7 of the mounting wiring board 6 are usually formed on the upper surface of the capacitor 4. For example, when the dielectric layer and the internal electrode layer constituting the multilayer capacitor are stacked in the vertical direction as a horizontal layer between the insulating substrate 1 and the semiconductor integrated circuit element 8, the internal electrode layer The connection with the terminal electrode for connection is made by a through conductor formed through the dielectric layer. Further, when the dielectric layer and the internal electrode layer are laminated in the horizontal direction as a vertical layer between the insulating substrate 1 and the semiconductor integrated circuit element 8, the dielectric layer and the internal electrode layer are led out to the laminated cross section that becomes the upper surface of the capacitor 4. Thus, a terminal electrode for connection is formed so as to be connected to the internal electrode layer.

このようにコンデンサ4を半導体集積回路素子8への電気的接続のために貫通導体7に対応させた多数の端子電極を有する場合は、一般的に使用されるチップコンデンサのように両端面のそれぞれ1つずつの端子電極のみから電源および接地を接続する場合に比べて、端子電極1つ当たりに流れる電流が少なくなり、また、電流の流れる距離が短くなることとなるため、コンデンサ4全体として、その抵抗やインダクタンスによる電源供給への影響を小さくすることができる。   In this way, when the capacitor 4 has a large number of terminal electrodes corresponding to the through conductors 7 for electrical connection to the semiconductor integrated circuit element 8, each of both end faces is generally used like a chip capacitor generally used. Compared to the case where the power source and the ground are connected only from one terminal electrode at a time, the current flowing per terminal electrode is reduced, and the current flowing distance is shortened. The influence of the resistance and inductance on the power supply can be reduced.

なお、コンデンサ4は単体のものに限られず、絶縁基体1の凹部1a内に収容搭載され、貫通導体7を介して半導体集積回路素子8に電源を供給するデカップリングコンデンサとして使用できるものであれば、複数のコンデンサを収容搭載してそれらによりデカップリングコンデンサとして機能させるようにしたものであってもよい。   Note that the capacitor 4 is not limited to a single capacitor, and may be used as a decoupling capacitor that is housed and mounted in the recess 1 a of the insulating base 1 and supplies power to the semiconductor integrated circuit element 8 through the through conductor 7. Alternatively, a plurality of capacitors may be housed and function as a decoupling capacitor.

このようなコンデンサ4は、絶縁基体1のコンデンサ搭載部である凹部1aに収容され、その一方の端子電極と電源供給端子3とが導体バンプ5あるいは導体層5’により電気的に接続されている。   Such a capacitor 4 is accommodated in a recess 1a which is a capacitor mounting portion of the insulating base 1, and one terminal electrode thereof and the power supply terminal 3 are electrically connected by a conductor bump 5 or a conductor layer 5 '. .

また、絶縁基体1には凹部1aの開口を覆うようにして実装用配線基板6が取着され、その貫通導体7の一部が凹部1a内のコンデンサ4の他方の端子電極に電気的に接続されており、他の貫通導体7は凹部1aの開口周辺において信号電送用あるいは接地用の配線導体2と電気的に接続されている。   A mounting wiring board 6 is attached to the insulating base 1 so as to cover the opening of the recess 1a, and a part of the through conductor 7 is electrically connected to the other terminal electrode of the capacitor 4 in the recess 1a. The other through conductor 7 is electrically connected to the wiring conductor 2 for signal transmission or grounding around the opening of the recess 1a.

そして、実装用配線基板6上には半導体集積回路素子8が半田またはエポキシ樹脂等の接着剤を介して搭載固定されて実装されるとともに、コンデンサ4の他方の端子電極と半導体集積回路素子8の電源電極とが半田等により電気的に接続され、半導体集積回路素子8の外周部に位置する信号電極と絶縁基体1の凹部1aの開口周辺に形成された配線導体2とが同じく半田等により電気的に接続されている。   The semiconductor integrated circuit element 8 is mounted and fixed on the mounting wiring substrate 6 via an adhesive such as solder or epoxy resin, and the other terminal electrode of the capacitor 4 and the semiconductor integrated circuit element 8 are mounted. The power electrode is electrically connected by solder or the like, and the signal electrode located on the outer periphery of the semiconductor integrated circuit element 8 and the wiring conductor 2 formed around the opening of the recess 1a of the insulating substrate 1 are also electrically connected by solder or the like. Connected.

このようにして本発明の半導体装置9・9’が完成することになるが、さらに、絶縁基体1の上面には、半導体集積回路素子8およびその周辺の絶縁基体1の上面を被覆するようにして樹脂製被覆材を被着してもよく、あるいは半導体集積回路素子8を覆うようにして絶縁基体1の上面に蓋体を接合してもよい。   Thus, the semiconductor devices 9 and 9 ′ of the present invention are completed. Further, the upper surface of the insulating substrate 1 is covered with the upper surfaces of the semiconductor integrated circuit element 8 and the surrounding insulating substrate 1. A resin covering material may be applied, or a lid may be bonded to the upper surface of the insulating substrate 1 so as to cover the semiconductor integrated circuit element 8.

そして、このようにして完成された本発明の半導体装置9・9’は、絶縁基体1の下面に導出した配線導体2と外部電気回路基板10の接続用導体11とを導電性接続部材12を介して接続することによって、外部電気回路基板11上に実装されるのと同時に半導体集積回路素子8の各電極が貫通導体7・配線導体2および導電性接続部材12を介して外部電気回路に接続されることになる。   The thus completed semiconductor device 9, 9 ′ of the present invention has the conductive conductor 12 connected to the wiring conductor 2 led to the lower surface of the insulating substrate 1 and the connecting conductor 11 of the external electric circuit board 10. As a result, the electrodes of the semiconductor integrated circuit element 8 are connected to the external electric circuit via the through conductor 7, the wiring conductor 2 and the conductive connection member 12 at the same time as being mounted on the external electric circuit board 11. Will be.

このような本発明の半導体装置9・9’によれば、絶縁基体1の凹部1a内に収容されたデカップリングコンデンサとしてのコンデンサ4に、凹部1aを覆うように取着された実装用配線基板6に半導体集積回路素子8を搭載実装し、実装用配線基板6中に形成された貫通導体7を介して半導体集積回路素子8の電源電極を電気的に接続したことから、従来半導体集積回路素子の近傍の外周部等に配置されていたデカップリングコンデンサを半導体集積回路素子8の直近に極めて近接して配置させることができ、半導体集積回路素子8の電源電極とコンデンサ4の端子電極との距離を最短に設定することができるため、両者の接続部の抵抗やインダクタンスを最小にすることができる。その結果、高速で動作する半導体集積回路素子8を安定して動作させるための素子への電源供給および電源ノイズ抑制を極めて効果的に安定して行なうことができる。   According to such semiconductor devices 9 and 9 ′ of the present invention, the mounting wiring board attached to the capacitor 4 as the decoupling capacitor housed in the recess 1a of the insulating base 1 so as to cover the recess 1a. Since the semiconductor integrated circuit element 8 is mounted and mounted on 6 and the power supply electrode of the semiconductor integrated circuit element 8 is electrically connected through the through conductor 7 formed in the wiring board 6 for mounting, the conventional semiconductor integrated circuit element The decoupling capacitor disposed on the outer peripheral portion in the vicinity of the semiconductor integrated circuit element 8 can be disposed very close to the semiconductor integrated circuit element 8, and the distance between the power supply electrode of the semiconductor integrated circuit element 8 and the terminal electrode of the capacitor 4 Can be set to the shortest, the resistance and inductance of the connecting portion between them can be minimized. As a result, the power supply to the element for stably operating the semiconductor integrated circuit element 8 operating at high speed and the suppression of the power supply noise can be performed extremely effectively and stably.

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の改良・変更を施すことは何ら差し支えない。例えば、上記の半導体装置9・9’に搭載されるデカップリングコンデンサとしてのコンデンサ4は、図1および図2に示したように1つの容量素子で形成してもよい4、複数のコンデンサを搭載してもよい。   It should be noted that the present invention is not limited to the examples of the embodiments described above, and various improvements and modifications can be made without departing from the gist of the present invention. For example, the capacitor 4 as a decoupling capacitor mounted on the semiconductor devices 9 and 9 ′ may be formed by one capacitive element as shown in FIGS. 1 and 2, and a plurality of capacitors are mounted. May be.

本発明の半導体装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the semiconductor device of this invention. 本発明の半導体装置の実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the semiconductor device of this invention.

符号の説明Explanation of symbols

1・・・・・・絶縁基体
1a・・・・・凹部
2・・・・・・配線導体
3・・・・・・電源供給端子
4・・・・・・コンデンサ
6・・・・・・実装用配線基板
7・・・・・・貫通導体
8・・・・・・半導体集積回路素子
9、9’・・・半導体装置
DESCRIPTION OF SYMBOLS 1 ... Insulation substrate 1a ... Recessed part 2 ... Wiring conductor 3 ... Power supply terminal 4 ... Capacitor 6 ... Wiring board for mounting 7 .... Penetration conductor 8 .... Semiconductor integrated circuit element 9, 9 '... Semiconductor device

Claims (1)

上面にコンデンサを収容する凹部を有し、該凹部の開口周辺に形成された、信号伝送用配線および接地接続用配線を含む配線導体と、前記凹部の底面に形成された電源供給端子と、を有する絶縁基体と、
前記凹部内に収容され、前記電源供給端子に一方の端子電極が電気的に接続されたコンデンサと、
前記絶縁基体上に前記凹部の開口を覆うように取着され、前記コンデンサの他方の端子電極または前記配線導体にそれぞれ電気的に接続される貫通導体が形成された実装用配線基板と、
電源電極と接地電極と信号電極とを有し、前記実装用配線基板上に搭載されてなる半導体集積回路素子であって、前記貫通導体を介して、前記電源電極が前記コンデンサの他方の端子電極に接続され、前記信号電極が前記配線導体の前記信号伝送用配線に接続され、前記接地電極が前記配線導体の前記接地接続用配線にそれぞれ電気的に接続された半導体集積回路素子と、を具備することを特徴とする半導体装置。
A wiring conductor including a signal transmission wiring and a ground connection wiring formed around the opening of the concave portion, and a power supply terminal formed on the bottom surface of the concave portion. An insulating substrate having,
A capacitor housed in the recess and electrically connected to one terminal electrode of the power supply terminal;
A mounting wiring board attached on the insulating base so as to cover the opening of the recess, and formed with through conductors electrically connected to the other terminal electrode of the capacitor or the wiring conductor;
A semiconductor integrated circuit device having a power electrode, a ground electrode, and a signal electrode, and mounted on the mounting wiring board, the power electrode being the other terminal electrode of the capacitor via the through conductor A semiconductor integrated circuit element, wherein the signal electrode is connected to the signal transmission wiring of the wiring conductor, and the ground electrode is electrically connected to the ground connection wiring of the wiring conductor, respectively. A semiconductor device comprising:
JP2006263136A 2006-09-27 2006-09-27 Semiconductor device Expired - Fee Related JP4392422B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006263136A JP4392422B2 (en) 2006-09-27 2006-09-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006263136A JP4392422B2 (en) 2006-09-27 2006-09-27 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP20818399A Division JP4012652B2 (en) 1999-07-22 1999-07-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006345007A true JP2006345007A (en) 2006-12-21
JP4392422B2 JP4392422B2 (en) 2010-01-06

Family

ID=37641661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006263136A Expired - Fee Related JP4392422B2 (en) 2006-09-27 2006-09-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4392422B2 (en)

Also Published As

Publication number Publication date
JP4392422B2 (en) 2010-01-06

Similar Documents

Publication Publication Date Title
JP4912992B2 (en) Capacitor-embedded substrate and manufacturing method thereof
JPH098217A (en) Package for housing semiconductor element
JP6140834B2 (en) Wiring board and electronic device
JP2014127678A (en) Wiring board and electronic device
JP4012652B2 (en) Semiconductor device
JP4012655B2 (en) Semiconductor device
JP4041253B2 (en) Integrated circuit device mounting substrate and integrated circuit device
JP2014232851A (en) Electronic element mounting substrate and electronic device
JP2007234663A (en) Wiring board, and electronic device employing it
JP2006270082A (en) Wiring board and electronic device using it
JP6698301B2 (en) Wiring board, electronic device and electronic module
JP4392422B2 (en) Semiconductor device
JP6166194B2 (en) Wiring board, electronic device and electronic module
JP2007027788A (en) Semiconductor device
JP6959785B2 (en) Circuit boards, electronic components and electronic modules
JP4373841B2 (en) Wiring board
JP2008034782A (en) Electronic component housing package, and electronic device
JP2015146383A (en) Wiring board, electronic device, and electronic module
JP2020053578A (en) Circuit board and electronic component
JP4986500B2 (en) Laminated substrate, electronic device and manufacturing method thereof.
JP2004281470A (en) Wiring board
JP4480418B2 (en) Wiring board
JP3878878B2 (en) Wiring board
JP2006185977A (en) Wiring board
JP2001185675A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061012

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080612

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090624

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090822

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090915

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091009

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121016

Year of fee payment: 3

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131016

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees