JP2006337271A - Method for inspecting semiconductor device - Google Patents

Method for inspecting semiconductor device Download PDF

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JP2006337271A
JP2006337271A JP2005164514A JP2005164514A JP2006337271A JP 2006337271 A JP2006337271 A JP 2006337271A JP 2005164514 A JP2005164514 A JP 2005164514A JP 2005164514 A JP2005164514 A JP 2005164514A JP 2006337271 A JP2006337271 A JP 2006337271A
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semiconductor device
power supply
inspection
voltage
signal
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Hideaki Mizumura
秀明 水村
Makoto Saito
誠 齊藤
Daisuke Chiba
大介 千葉
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To shorten inspection time while reducing inspection costs by dispensing with a waiting time till stabilizing of voltage when inspecting a semiconductor device by changing voltage level. <P>SOLUTION: This device comprises a power supply control part 121 which linearly varies an internal power supply voltage applied to an internal cell 122 of the semiconductor device according to a control counter signal 101 which is provided from outside on a board on which the semiconductor device 131 or the semiconductor device 132 is mounted, and the device controls the power supply control part 121 using the control counter signal 101 so that the power supply voltage applied to the semiconductor device varies synchronizing with a signal for inspection applied to the semiconductor device. Accordingly, the waiting time till stabilizing of voltage become unnecessary and the inspection time can be shortened, and thus the inspection costs can be reduced. Furthermore, inspection efficiency can be higher by changing the voltage level of a clock or data applied to the semiconductor device in the power supply control part 121. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置の電源電圧レベルを変化させて実施する検査方法に関するものである。   The present invention relates to an inspection method performed by changing a power supply voltage level of a semiconductor device.

従来、半導体装置の検査においては、電源電圧を単一レベルにして検査を行っており、製品の最高電圧や最低電圧などで検査を行う場合であっても、それぞれに応じた特定の電圧で検査を行っていた。また、1チップ上にさまざまな電圧のコアや回路ブロックが存在する場合は、各コアや回路ブロックを個別に検査できる回路構成にして検査を行っていた。   Conventionally, in the inspection of semiconductor devices, the power supply voltage is inspected at a single level, and even when inspecting at the highest voltage or the lowest voltage of the product, the inspection is performed at a specific voltage corresponding to each. Had gone. In addition, when cores and circuit blocks of various voltages exist on one chip, the inspection is performed with a circuit configuration in which each core or circuit block can be individually inspected.

このように半導体装置の電源電圧レベルを変化させて検査を実施する際に、内部電源電圧の安定を図ることは重要な課題であるが、半導体装置そのものとして、過渡応答を抑え高周波応答特性に優れた内部電源電圧発生回路を提供する技術が開示されている(例えば、特許文献1参照)。
特開平8−190437号公報
As described above, it is important to stabilize the internal power supply voltage when performing inspection by changing the power supply voltage level of the semiconductor device. However, as a semiconductor device itself, the transient response is suppressed and the high frequency response characteristics are excellent. Further, a technique for providing an internal power supply voltage generation circuit is disclosed (for example, see Patent Document 1).
JP-A-8-190437

しかしながら、従来の半導体装置の検査では、電圧レベルを変更して検査を行う場合は、電圧を変更するときに電圧が安定するまでの待ち時間が必要となり、テスト時間が増して検査コストが増大するという問題があった。   However, in the conventional semiconductor device inspection, when the voltage level is changed and the inspection is performed, when changing the voltage, a waiting time until the voltage becomes stable is required, and the test time increases and the inspection cost increases. There was a problem.

また、テスタ装置による電圧レベル変化は、パターン発生部と電圧設定部とが別設定で行われるため、両者の電圧レベルを完全に同期させて変化させることができないという問題があった。   In addition, the voltage level change by the tester device has a problem in that the voltage generation unit and the voltage setting unit are separately set, so that the voltage levels of both cannot be changed completely in synchronization.

さらに、スキャンテストなどではテストを簡略化するために回路ブロックをまとめて検査することが望ましいが、1チップ上にさまざまな内部電源のコアや回路ブロックが存在する場合は異なる電圧レベルで個別の検査が必要となり、テスト時間が増して検査コストが増大するという問題があった。   In addition, it is desirable to inspect circuit blocks collectively in order to simplify the test in scan tests, etc., but if there are various internal power supply cores and circuit blocks on one chip, individual inspections at different voltage levels There is a problem that the test time increases and the inspection cost increases.

本発明は、電圧レベルを変化させて半導体装置の検査を行う場合に、電圧が安定するまでの待ち時間を不要にし、検査時間の短縮と検査コストの削減を図ることができる半導体装置の検査方法を提供することを目的とする。   The present invention eliminates the waiting time until the voltage stabilizes when the semiconductor device is inspected by changing the voltage level, and can reduce the inspection time and the inspection cost. The purpose is to provide.

本発明の半導体装置の検査方法は、半導体装置に与える電源電圧を外部から与えられる制御信号に応じて線形的に可変する電源制御部を、前記半導体装置に与える電源電圧が前記半導体装置に与えられる検査用の信号と同期して可変するように前記制御信号を用いて制御する。   According to the method for inspecting a semiconductor device of the present invention, a power supply control unit that linearly varies a power supply voltage applied to the semiconductor device according to a control signal applied from the outside is provided, and the power supply voltage applied to the semiconductor device is applied to the semiconductor device. Control is performed using the control signal so as to vary in synchronization with the inspection signal.

上記構成によれば、半導体装置に与える電源電圧を半導体装置に与えられる検査用の信号と同期して線形的に変化させることで、電圧が安定するまでの待ち時間が不要となり、検査時間を短縮して検査コストを削減することができる。また、電圧レベルを線形的に変化させることはIRドロップを抑制する効果も期待できる。   According to the above configuration, the power supply voltage applied to the semiconductor device is linearly changed in synchronization with the inspection signal applied to the semiconductor device, thereby eliminating the waiting time until the voltage stabilizes and reducing the inspection time. Thus, the inspection cost can be reduced. Further, linearly changing the voltage level can be expected to suppress IR drops.

本発明において、前記半導体装置に与える電源電圧に加えて前記半導体装置に与えられるクロック信号やデータ信号の電圧レベルも前記制御信号に応じて可変するものであり、前記電源制御部を前記半導体装置に与える電源電圧とクロック信号やデータ信号の電圧レベルが同期して可変するように前記制御信号を用いて制御する。   In the present invention, in addition to the power supply voltage applied to the semiconductor device, the voltage levels of the clock signal and the data signal applied to the semiconductor device are also variable according to the control signal, and the power supply control unit is provided in the semiconductor device. Control is performed using the control signal so that the applied power supply voltage and the voltage level of the clock signal or data signal can be varied in synchronization.

上記構成によれば、半導体装置の検査において電源電圧レベルだけでなくクロックやデータの電圧を任意に変化させることで、複数の電圧レベルを保証する半導体装置の検査が可能となる。   According to the above-described configuration, it is possible to inspect a semiconductor device that guarantees a plurality of voltage levels by arbitrarily changing not only the power supply voltage level but also the clock and data voltages in the inspection of the semiconductor device.

本発明において、前記半導体装置は異なる内部電源電圧を有する複数のIPコアや回路ブロックで構成され、前記電源制御部は前記複数のIPコアや回路ブロックのそれぞれに対して与える電源電圧を外部から与えられる制御信号に応じて線形的に可変する。   In the present invention, the semiconductor device includes a plurality of IP cores and circuit blocks having different internal power supply voltages, and the power supply control unit externally supplies a power supply voltage to each of the plurality of IP cores and circuit blocks. It varies linearly according to the control signal to be applied.

上記構成によれば、内部コアや回路ブロックが互いに異なる電源で構成された半導体装置においても、それぞれに与える内部電源の電圧レベルを外部から与える信号値に応じて線形的に変化させることで、全体を同期させて変化させることが可能となり、内部電源の電圧レベルを変化させながら短時間に半導体装置の検査を行うことが可能となる。   According to the above configuration, even in a semiconductor device in which the internal core and the circuit block are configured with different power supplies, the voltage level of the internal power supply given to each is linearly changed according to the signal value given from the outside, Thus, the semiconductor device can be inspected in a short time while changing the voltage level of the internal power supply.

本発明において、前記半導体装置は複数の電源電圧範囲を保証する製品であり、前記制御信号を用いて前記電源制御部を制御することにより、前記複数の電源電圧範囲の検査を連続して実施する。   In the present invention, the semiconductor device is a product that guarantees a plurality of power supply voltage ranges, and the inspection of the plurality of power supply voltage ranges is continuously performed by controlling the power supply control unit using the control signal. .

上記構成によれば、複数の電圧レベルを保証する半導体装置の検査において、電圧レベルを変更する度に検査を止めて半導体検査装置の安定を待つことが不要になり、ファンクション検査や電流および電圧の測定検査などの連続した検査が可能になる。   According to the above configuration, in the inspection of a semiconductor device that guarantees a plurality of voltage levels, it is not necessary to stop the inspection every time the voltage level is changed and wait for the stability of the semiconductor inspection device. Continuous inspection such as measurement inspection becomes possible.

本発明によれば、半導体装置の検査において電圧が安定するまでの待ち時間が不要となり、検査時間を短縮して検査コストを削減することができる。また、内部コアや回路ブロックが互いに異なる電源電圧で構成された半導体装置においても、全体を同期させて電圧レベルを変化させながら短時間に半導体装置の検査を行うことが可能となる。   According to the present invention, it is not necessary to wait for the voltage to stabilize in the inspection of the semiconductor device, and the inspection time can be shortened and the inspection cost can be reduced. Even in a semiconductor device in which the internal core and the circuit block are configured with different power supply voltages, the semiconductor device can be inspected in a short time while changing the voltage level in synchronization with the whole.

(実施の形態1)
図1は本発明の実施の形態1に係る半導体装置の検査方法を実施するための装置構成を示す図である。図1において、101は半導体検査装置などから入力される制御カウンタ信号、102は半導体検査装置などから与えられる内部電源、103はデバイス端子124に端子部電圧を供給するデバイス端子電源、121は内部電源102の電圧レベルを制御カウンタ信号101によって変化させる電源制御部、122は電圧が変化して動作する内部セル、123はデバイス端子124の電圧を内部セル122に適した電圧に変換するレベルシフタである。
(Embodiment 1)
FIG. 1 is a diagram showing an apparatus configuration for carrying out a semiconductor device inspection method according to the first embodiment of the present invention. In FIG. 1, 101 is a control counter signal input from a semiconductor inspection apparatus, 102 is an internal power supply provided from the semiconductor inspection apparatus, 103 is a device terminal power supply for supplying terminal voltage to the device terminal 124, and 121 is an internal power supply. A power supply control unit that changes the voltage level of 102 by the control counter signal 101, 122 is an internal cell that operates by changing the voltage, and 123 is a level shifter that converts the voltage of the device terminal 124 into a voltage suitable for the internal cell 122.

また、131は電源制御部121をデバイス内に搭載した場合のデバイスを示し、132は電源制御部121をボード上に搭載した場合のデバイスを示している。   Reference numeral 131 denotes a device when the power control unit 121 is mounted in the device, and 132 denotes a device when the power control unit 121 is mounted on the board.

図2は本実施の形態における電源制御部121の動作を説明するタイミング図である。図2において、内部セル122に供給される内部電源102のレベルは制御カウンタ信号105のカウント値に従って線形的に変化している。   FIG. 2 is a timing chart for explaining the operation of the power control unit 121 in the present embodiment. In FIG. 2, the level of the internal power supply 102 supplied to the internal cell 122 changes linearly according to the count value of the control counter signal 105.

このように、内部電源のレベルを外部から与える制御カウンタ信号の値に応じて線形的に変化させることで、デバイス端子124に与えられる端子部電圧と同期させて変化させることが可能となり、内部電源の電圧レベルを変化させながらの半導体装置の検査が可能になる。   In this way, by changing the level of the internal power supply linearly in accordance with the value of the control counter signal given from the outside, it becomes possible to change it in synchronization with the terminal voltage applied to the device terminal 124. The semiconductor device can be inspected while changing the voltage level.

(実施の形態2)
図3は本発明の実施の形態2に係る半導体装置の検査方法を実施するための装置構成を示す図である。図3において、101は半導体検査装置などから入力される制御カウンタ信号、102は半導体検査装置などから与えられる内部電源、105はクロック、106はデータ、125は電源制御を行う場合と行わない場合とを切り替えるスイッチ、121は電源制御部である。また、131および132については図1と同様である。
(Embodiment 2)
FIG. 3 is a diagram showing an apparatus configuration for carrying out the semiconductor device inspection method according to the second embodiment of the present invention. In FIG. 3, 101 is a control counter signal input from a semiconductor inspection apparatus, 102 is an internal power supply provided from the semiconductor inspection apparatus, 105 is a clock, 106 is data, and 125 is or is not performing power control. A switch 121 for switching the power is a power control unit. 131 and 132 are the same as those in FIG.

本実施の形態においては、半導体検査装置などから入力される制御カウンタ信号101により、電源制御部121において内部電源102の電圧レベルの変化と合わせてクロックおよびデータの電圧レベルも変化させる。このように、電源電圧レベルだけでなくクロックやデータの電圧を任意に変化させることで、複数の電圧レベルを保証する半導体装置の検査が可能となる。   In the present embodiment, the control counter signal 101 input from a semiconductor inspection apparatus or the like causes the power supply control unit 121 to change the voltage level of the clock and data in accordance with the change of the voltage level of the internal power supply 102. As described above, it is possible to inspect a semiconductor device that guarantees a plurality of voltage levels by arbitrarily changing not only the power supply voltage level but also the clock and data voltages.

図4は本実施の形態における電源制御部121の回路構成例を示す図である。図4において、201は半導体検査装置などから入力されるカウンタ制御信号、202はカウンタクロック、203はカウンタ制御信号201とカウンタクロック202から電圧レベルを制御する信号を生成する制御カウンタ、204は可変抵抗器である。なお、実施の形態1における電源制御部も同様の回路構成である。   FIG. 4 is a diagram illustrating a circuit configuration example of the power supply control unit 121 in the present embodiment. In FIG. 4, 201 is a counter control signal input from a semiconductor inspection apparatus, 202 is a counter clock, 203 is a control counter that generates a signal for controlling a voltage level from the counter control signal 201 and the counter clock 202, and 204 is a variable resistor. It is a vessel. Note that the power supply controller in the first embodiment also has a similar circuit configuration.

このような回路構成により、可変抵抗器204を制御することで半導体検査装置などから入力される内部電源102、クロック105、データ106の電圧レベルを必要に応じた電圧レベルに線形的に変化させることができる。   With such a circuit configuration, by controlling the variable resistor 204, the voltage levels of the internal power supply 102, the clock 105, and the data 106 input from the semiconductor inspection apparatus or the like are linearly changed to voltage levels as necessary. Can do.

図5は複数の検査電圧に対して連続して半導体装置の検査を行う場合のタイミング図である。本実施の形態の電源制御部を用いることで、保証する電圧レベルA、B、Cが異なる場合に、電圧レベルを変更する度に検査を止めて半導体検査装置の安定を待つことが不要になり、ファンクション検査や電流および電圧の測定検査などの連続した検査が可能になる。   FIG. 5 is a timing chart when a semiconductor device is inspected continuously for a plurality of inspection voltages. By using the power supply control unit of the present embodiment, when the guaranteed voltage levels A, B, and C are different, it is not necessary to stop the inspection and wait for the stability of the semiconductor inspection apparatus every time the voltage level is changed. Continuous inspection such as function inspection and current and voltage measurement inspection becomes possible.

(実施の形態3)
図6は本発明の実施の形態3に係る半導体装置の検査方法を実施するための装置構成を示す図であり、図1に示した実施の形態1の構成に対して、内部セル122をそれぞれ電源電圧の異なる内部コアA126、内部コアB127、内部コアC128で置き換え、内部電源102をそれぞれの内部コアに電源電圧を供給する内部電源A107、内部電源B108、内部電源C109で置き換えた構成となっている。
(Embodiment 3)
FIG. 6 is a diagram showing a device configuration for carrying out the method for inspecting a semiconductor device according to the third embodiment of the present invention. In contrast to the configuration of the first embodiment shown in FIG. The internal power supply voltage is replaced by an internal core A126, an internal core B127, and an internal core C128, and the internal power supply 102 is replaced by an internal power supply A107, an internal power supply B108, and an internal power supply C109 that supply the power supply voltage to each internal core. Yes.

内部コアA126、内部コアB127、内部コアC128はこの順にスキャンチェーンを構成し、110はスキャン入力データ、111はスキャン出力データである。電源制御部121は内部電源A107、内部電源B108、内部電源C109、スキャン入力データ110の電圧レベルを制御カウンタ信号101によって変化させる。   The internal core A126, the internal core B127, and the internal core C128 constitute a scan chain in this order, 110 is scan input data, and 111 is scan output data. The power supply control unit 121 changes the voltage levels of the internal power supply A 107, the internal power supply B 108, the internal power supply C 109, and the scan input data 110 according to the control counter signal 101.

このように、内部コアが互いに異なる電源で構成された半導体装置においても、それぞれの内部コアに与える内部電源の電圧レベルを外部から与える信号値に応じて線形的に変化させることで、全体を同期させて変化させることが可能となり、内部電源の電圧レベルを変化させながら短時間に半導体装置の検査を行うことが可能となる。   In this way, even in a semiconductor device in which the internal cores are configured with different power supplies, the voltage level of the internal power supply given to each internal core is linearly changed according to the signal value given from the outside, thereby synchronizing the whole. The semiconductor device can be inspected in a short time while changing the voltage level of the internal power supply.

以上のように、本発明の電圧レベルを線形的に変化させながら行う半導体装置の検査方法は、携帯端末などの待ち受け時の低消費電力化に伴い半導体装置そのものが低電力化されている状況において、これらの半導体装置を動作させながら電圧を下げて検査を行う場合に好適である。また、複数の異なる電源電圧で動作するコアや回路ブロックを有する半導体装置のスキャンテストなどにも好適である。   As described above, the method for inspecting a semiconductor device while linearly changing the voltage level according to the present invention is in a situation where the power of the semiconductor device itself is reduced with the reduction in power consumption during standby of a portable terminal or the like. It is suitable for the case where the inspection is performed by lowering the voltage while operating these semiconductor devices. It is also suitable for a scan test of a semiconductor device having a core or circuit block that operates with a plurality of different power supply voltages.

本発明の半導体装置の検査方法は、半導体装置の検査において電圧が安定するまでの待ち時間が不要となり、検査時間を短縮して検査コストを削減することができるという効果を有し、半導体装置の電源電圧レベルを変化させて実施する検査方法等として有用である。   The method for inspecting a semiconductor device of the present invention eliminates the need for a waiting time until the voltage is stabilized in the inspection of the semiconductor device, and has an effect that the inspection time can be shortened and the inspection cost can be reduced. This is useful as an inspection method to be performed by changing the power supply voltage level.

本発明の実施の形態1に係る半導体装置の検査方法における装置構成図。The apparatus block diagram in the test | inspection method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体装置の検査方法における電源制御部の動作を説明するタイミング図。FIG. 3 is a timing chart for explaining the operation of the power supply control unit in the semiconductor device inspection method according to the first embodiment of the present invention; 本発明の実施の形態2に係る半導体装置の検査方法における装置構成図。The apparatus block diagram in the test | inspection method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体装置の検査方法における電源制御部の回路構成例を示す図。The figure which shows the circuit structural example of the power supply control part in the test | inspection method of the semiconductor device which concerns on Embodiment 2 of this invention. 複数の検査電圧に対して連続して本発明の半導体装置の検査方法を実施する場合のタイミング図。The timing diagram in the case of enforcing the inspection method of the semiconductor device of the present invention continuously to a plurality of inspection voltages. 本発明の実施の形態3に係る半導体装置の検査方法における装置構成図。The apparatus block diagram in the test | inspection method of the semiconductor device which concerns on Embodiment 3 of this invention.

符号の説明Explanation of symbols

101 制御カウンタ信号
102、107、108、109 内部電源
103 デバイス端子電源
105 クロック
106 データ
110 スキャン入力データ
111 スキャン出力データ
121 電源制御部
122 内部セル
123 レベルシフタ
124 デバイス端子
125 切り替えスイッチ、
126、127、128 内部コア
131 電源制御部をデバイス内に搭載した場合のデバイス
132 電源制御部をボード上に搭載した場合のデバイス
201 カウンタ制御信号
202 カウンタクロック
203 制御カウンタ
204 可変抵抗器
101 Control counter signal 102, 107, 108, 109 Internal power supply 103 Device terminal power supply 105 Clock 106 Data 110 Scan input data 111 Scan output data 121 Power supply control unit 122 Internal cell 123 Level shifter 124 Device terminal 125 Changeover switch,
126, 127, 128 Internal core 131 Device when power supply control unit is mounted in device 132 Device when power supply control unit is mounted on board 201 Counter control signal 202 Counter clock 203 Control counter 204 Variable resistor

Claims (4)

半導体装置に与える電源電圧を外部から与えられる制御信号に応じて線形的に可変する電源制御部を、前記半導体装置に与える電源電圧が前記半導体装置に与えられる検査用の信号と同期して可変するように前記制御信号を用いて制御する半導体装置の検査方法。   A power supply control unit that linearly varies a power supply voltage applied to the semiconductor device according to a control signal applied from the outside, and varies a power supply voltage applied to the semiconductor device in synchronization with an inspection signal applied to the semiconductor device. Thus, a method for inspecting a semiconductor device controlled using the control signal. 前記半導体装置に与える電源電圧に加えて前記半導体装置に与えられるクロック信号やデータ信号の電圧レベルも前記制御信号に応じて可変するものであり、前記電源制御部を前記半導体装置に与える電源電圧とクロック信号やデータ信号の電圧レベルが同期して可変するように前記制御信号を用いて制御する請求項1記載の半導体装置の検査方法。   A voltage level of a clock signal or a data signal applied to the semiconductor device in addition to a power supply voltage applied to the semiconductor device is variable according to the control signal, and the power supply voltage applied to the semiconductor device 2. The method for inspecting a semiconductor device according to claim 1, wherein the control signal is used to control the voltage level of the clock signal and the data signal so as to vary in synchronization. 前記半導体装置は異なる内部電源電圧を有する複数のIPコアや回路ブロックで構成され、前記電源制御部は前記複数のIPコアや回路ブロックのそれぞれに対して与える電源電圧を外部から与えられる制御信号に応じて線形的に可変する請求項1記載の半導体装置の検査方法。   The semiconductor device includes a plurality of IP cores and circuit blocks having different internal power supply voltages, and the power supply control unit applies a power supply voltage applied to each of the plurality of IP cores and circuit blocks to a control signal supplied from the outside. 2. The method for inspecting a semiconductor device according to claim 1, wherein the inspection method varies linearly in response. 前記半導体装置は複数の電源電圧範囲を保証する製品であり、前記制御信号を用いて前記電源制御部を制御することにより、前記複数の電源電圧範囲の検査を連続して実施する請求項1記載の半導体装置の検査方法。   The semiconductor device is a product that guarantees a plurality of power supply voltage ranges, and the inspection of the plurality of power supply voltage ranges is continuously performed by controlling the power supply control unit using the control signal. Inspection method for semiconductor devices.
JP2005164514A 2005-06-03 2005-06-03 Method for inspecting semiconductor device Withdrawn JP2006337271A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100994669B1 (en) 2008-05-19 2010-11-16 프롬써어티 주식회사 Apparatus for controlling measurement wait-time of test parameter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100994669B1 (en) 2008-05-19 2010-11-16 프롬써어티 주식회사 Apparatus for controlling measurement wait-time of test parameter

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